MT6589 pdf - DroidDevice.ru

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[email protected],time=2012-11-23 14:49:04,ip=218.75.87.37,doctitle=MT6589_Technical_Brief_v0.2.docx,company=Bird_WCX
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MT6589 HSPA+ Smartphone
Application Processor
Technical Brief
Version:
Release date:
0.2
2012-09-26
© 2011 - 2012 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Specifications are subject to change without notice.
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MT6589
HSPA+ Smartphone Application Processor
Technical Brief
Confidential A
Document Revision History
Date
Author
Description
0.1
2012-09-14
YC Lai
First created by YC Lai
0.2
2012-09-26
YC Lai
Document revised.
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Revision
MediaTek Confidential
© 2012 MediaTek Inc.
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MT6589
Technical Brief
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Table of Contents
Document Revision History .................................................................................................................. 2
Table of Contents ................................................................................................................................... 3
1
System Overview .......................................................................................................................... 6
1.1
1.2
1.3
1.4
2
Platform Features ................................................................................................................. 7
MODEM Features ................................................................................................................. 8
Multimedia Features ............................................................................................................. 9
General Descriptions .......................................................................................................... 10
Product Description ................................................................................................................... 12
2.1
2.2
2.3
2.4
2.5
2.6
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2.7
Pin Description.................................................................................................................... 12
2.1.1
Ball Map View ..................................................................................................... 12
2.1.2
Pin Coordinate .................................................................................................... 13
2.1.3
Detailed Pin Description ..................................................................................... 17
Electrical Characteristic ...................................................................................................... 29
2.2.1
Absolute Maximum Ratings ............................................................................... 29
2.2.2
Recommended Operating Conditions ................................................................ 30
2.2.3
Storage Condition............................................................................................... 31
2.2.4
AC Electrical Characteristics and Timing Diagram ............................................ 31
System Configuration ......................................................................................................... 34
2.3.1
Mode Selection ................................................................................................... 34
2.3.1
Constant Tie Pins ............................................................................................... 34
Power-on Sequence ........................................................................................................... 35
Analog Baseband ............................................................................................................... 36
2.5.1
BBRX .................................................................................................................. 37
2.5.2
BBTX .................................................................................................................. 39
2.5.3
2GBBTX ............................................................................................................. 41
2.5.4
APC-DAC ........................................................................................................... 42
2.5.5
VBIAS-DAC ........................................................................................................ 43
2.5.6
AUXADC ............................................................................................................ 44
2.5.7
Clock Squarer ..................................................................................................... 46
2.5.8
Phase Locked Loop............................................................................................ 46
2.5.9
Temperature Sensor .......................................................................................... 51
Package Information ........................................................................................................... 52
2.6.1
Package Outlines ............................................................................................... 52
2.6.2
Thermal Operating Specifications ...................................................................... 52
2.6.3
Lead-free Packaging .......................................................................................... 52
Ordering Information ........................................................................................................... 53
2.7.1
Top Marking Definition ....................................................................................... 53
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Technical Brief
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List of Figures
Figure 1-1: Block diagram of MT6589 ................................................................................................... 11
Figure 2-1 : Ball map view of MT6589 .................................................................................................. 12
Figure 2-2: Basic timing parameter for LPDDR2 commands ................................................................ 32
Figure 2-3: Basic timing parameter for LPDDR2 write .......................................................................... 32
Figure 2-4: Basic timing parameter for LPDDR2 read .......................................................................... 33
Figure 2-8: Power on/off sequence with XTAL ...................................................................................... 35
Figure 2-9: Power on/off sequence without XTAL ................................................................................. 36
Figure 2-10: Block diagram of BBRX-ADC ........................................................................................... 38
Figure 2-11: Block diagram of 2GBBTX ................................................................................................ 41
Figure 2-12: Block diagram of APC-DAC .............................................................................................. 42
Figure 2-13: Block diagram of VBIAS-DAC .......................................................................................... 43
Figure 2-14: Block diagram of AUXADC ............................................................................................... 44
Figure 2-15: Block diagram of PLL ....................................................................................................... 47
Figure 2-16: Outlines and dimensions of FCCSP 11.8mm*11.8mm, 515-ball, 0.4mm pitch package.. 52
Figure 2-17: Top mark of MT6589 ......................................................................................................... 53
List of Tables
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Table 2-1: Pin coordinate ...................................................................................................................... 13
Table 2-2: Acronym for pin type ............................................................................................................ 17
Table 2-3: Detailed pin description ........................................................................................................ 17
Table 2-4: Absolute maximum ratings for power supply ....................................................................... 29
Table 2-5: Recommended operating conditions for power supply ........................................................ 30
Table 2-6: LPDDR2 AC timing parameter table of external memory interfaces .................................... 33
Table 2-8: Mode selection of chip (PMU 6320 pin) ............................................................................... 34
Table 2-9: Constant tied pins of MT6589 .............................................................................................. 34
Table 2-10: Baseband downlink specifications ..................................................................................... 38
Table 2-11: Baseband uplink transmitter specifications ........................................................................ 40
Table 2-12: Baseband uplink transmitter specifications ........................................................................ 41
Table 2-13: APC-DAC specifications ..................................................................................................... 42
Table 2-14: VBIAS-DAC specifications ................................................................................................. 43
Table 2-15: Definitions of AUXADC channels ....................................................................................... 44
Table 2-16: AUXADC specifications ...................................................................................................... 45
Table 2-17: Clock squarer 1 & 2 specifications ..................................................................................... 46
Table 2-18: ARMPLL specifications ....................................................................................................... 47
Table 2-19: MAINPLL specifications ..................................................................................................... 48
Table 2-20: MMPLL specifications ........................................................................................................ 48
Table 2-21: ISPPLL specifications ......................................................................................................... 48
Table 2-22: UNIVPLL specifications ...................................................................................................... 49
Table 2-23: MSDCPLL specifications .................................................................................................... 49
Table 2-24: TVDPLL specifications ....................................................................................................... 49
Table 2-25: LVDSPLL specifications ..................................................................................................... 50
Table 2-26: MDPLL1 & MDPLL2 specifications .................................................................................... 50
Table 2-27: WPLL specifications ........................................................................................................... 50
Table 2-28: WHPLL specifications ........................................................................................................ 50
Table 2-29: MCUPLL1 & MCUPLL2 specifications ............................................................................... 51
Table 2-30: Temperature sensor specifications ..................................................................................... 51
Table 2-31: Thermal operating specifications ....................................................................................... 52
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Technical Brief
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1
System Overview
MT6589 is a highly integrated baseband platform incorporating both modem and application
processing subsystems to enable 3G smart phone applications. The chip integrates a Quad-core
TM
ARM® Cortex-A7 MPCore operating up to 1.2GHz, an ARM® Cortex-R4 MCU and a powerful multistandard video accelerator. The MT6589 interfaces to NAND flash memory, 32-bit LPDDR2 for
optimal performance and also supports booting from SLC NAND or eMMC to minimize the overall
BOM cost. In addition, an extensive set of interfaces and connectivity peripherals are included to
interface to cameras, touch-screen displays, MMC/SD cards and external Bluetooth, WiLAN and GPS
modules.
TM
The application processor, a Quad-core ARM® Cortex-A7 MPCore which includes a NEON
multimedia processing engine, offers processing power necessary to support the latest OpenOS
along with its demanding applications such as web browsing, email, GPS navigation and games. All
are viewed on a high resolution touch screen display with graphics enhanced by the 2D and 3D
graphics acceleration. The multi-standard video accelerator and an advanced audio subsystem are
also included to provide advanced multimedia applications and services such as streaming audio and
video, a multitude of decoders and encoders such as H.264 and MPEG-4. Audio supports include FR,
HR, EFR, AMR FR, AMR HR and Wide-Band AMR vocoders, polyphonic ringtones and advanced
audio functions such as echo cancellation, hands-free speakerphone operation and noise cancellation.
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An ARM® Cortex-R4, DSP, and 2G and 3G coprocessors provide a powerful modem subsystem
capable of supporting Category 24 (42.2 Mbps) HSDPA downlink and Category 7 (11.5 Mbps) HSUPA
uplink data rates, as well as Class 12 GPRS and EDGE.
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1.1


Platform Features
General
 Supports LPDDR2 up to 2GB
 Smartphone two MCU subsystems
architecture
 32-bit data bus width
 SLC NAND flash and eMMC bootloader
 Supports self-refresh/partial self-refresh
mode
AP MCU subsystem
 Low-power operation
 Quad-core ARM® Cortex-A7 MPCore
operating at 1.2GHz
 Memory clock up to 533MHz
TM
 Programmable slew rate for memory
controller’s IO pads
 NEON multimedia processing engine
with SIMDv2/VFPv4 ISA support
 Supports dual rank memory device
 Advanced bandwidth arbitration control
 32KB L1 I-cache and 32KB L1 D-cache
 1MB unified L2 cache

 DVFS technology with adaptive
operating voltage from 0.95V to 1.26V
 ARM® TrustZone® Security


Connectivity
 USB2.0 high-speed OTG supporting 15
Tx and 15 Rx endpoints
MD MCU subsystem
 ARM® Cortex-R4 processor with
maximum 480MHz operation frequency
 USB2.0 full-speed host
 64KB I-cache, 32KB D-cache
 NAND flash controller supporting NAND
bootable, iNAND2® and MoviNAND®
 256KB TCM (tightly-coupled memory)

Security
 DSP for running modem/voice tasks,
with maximum 240MHz operation
frequency
 4 UART for GPS, BT, FM-RDS, modem
and debugging interfaces
 High-performance AXI and AHB bus
 SPI for external device
 General DMA engine and dedicated
DMA channels for peripheral data
transfer
 7 I2C to control peripheral devices, e.g.
CMOS image sensor, LCM or FM
receiver module
 Watchdog timer for system error
recovery
 I2S for connection with optional external
hi-end audio codec
 Power management for clock gating
control
 GPIOs
 IrDA FIR/MIR/SIR
 4 sets of memory card controllers
supporting SD/SDHC/MS/MSPRO/MMC
and SDIO2.0/3.0 protocols
MD external interfaces
 Supports dual SIM/USIM interface
 Interface pins with RF and radio-related
peripherals (antenna tuner, PA, …)
Operating conditions
 Core voltage: 1.05V
 UART for modem logging/debugging
purpose
 Processor DVFS voltage: 0.95V ~ 1.26V
(Typ. 1.05V; sleep mode 0.85V)
External memory interface
 Processor SRAM voltage: 1.05V ~
1.26V (Typ. 1.05V; sleep mode 0.85V)
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

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Technical Brief
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 GPU voltage: 1.05V
 Type: FCCSP
 I/O voltage: 1.8V/2.8V/3.3V
 11.8mm x 11.8mm
 Memory: 1.2V/1.8V/1.35V/1.5V/1.25V
 Height: 1.0mm maximum
 NAND: 1.8V/2.8V
 Ball count: 515 ballsc
 LCM interface: 1.8V
 Ball pitch: 0.4mm
 Clock source: 26MHz, 32.768kHz

Package
1.2

MODEM Features
 High dynamic range delta-sigma ADC
converts the downlink analog I and Q
signals to digital baseband
3G UMTS FDD supported features (with
MT6167)
 3G modem supports most main features
in 3GPP Release 7 and Release 8
 10-bit D/A converter for Automatic
Power Control (APC)
 CPC (DTX in CELL_DCH, UL DRX DL
DRX), HS-SCCH-less, HS-DSCH
 Dual cell operation
 Programmable radio Rx filter with
adaptive gain control
 MAC-ehs
 Dedicated Rx filter for FB acquisition
 Two DRX (receiver diversity) schemes
in URA_PCH and CELL_PCH
 Baseband Parallel Interface (BPI) with
programmable driving strength (shared
by 2G & 3G modem)
 Uplink Cat. 7 (16QAM), throughput up to
11.5Mbps
 Downlink Cat. 24 (64QAM, dual-cell
HSDPA), throughput up to 42.2Mbps
 Supports multi-band

GSM modem and voice CODEC
 Fast dormancy
 Dial tone generation
 ETWS
 Noise reduction
 Network selection enhancements
 Echo suppression
 Advanced sidetone oscillation reduction

3G TDD supported features (with
MT6168)
 Digital sidetone generator with
programmable gain
 TD-SCDMA/HSDPA/HSUPA baseband
 Two programmable acoustic
compensation filters
 Supports TD-SCDMA Bands 34, 39 &
40 and Quad band GSM/EDGE
 Circuit-switched voice and data, and
packet-switched data
 GSM quad vocoders for adaptive
multirate (AMR), enhanced full rate
(EFR), full rate (FR) and half rate (HR)
 384/384Kbps class in UL/DL for TDSCDMA
 GSM channel coding, equalization and
A5/1, A5/2 and A5/3 ciphering
 TD-HSDPA: 2.8Mbps DL (Cat.14)
 GPRS GEA1, GEA2 and GEA3
ciphering
 TD-HSUPA: 2.2Mbps UL (Cat.6)
 F8/F9 ciphering/integrity protection
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
Radio interface and baseband front-end
 Programmable GSM/GPRS/EDGE
modem
 Packet switched data with
CS1/CS2/CS3/CS4 coding schemes
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MT6589
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 GSM circuit switch data
 GPRS/EDGE Class 12
 Supports SAIC (single antenna
interference cancellation) technology
 Supports VAMOS (Voice services over
Adaptive Multi-user channels on One
Slot) technology in R9 spec
1.3

Multimedia Features
Display
 Supports landscape or portrait panel
resolution up to WXGA (1280x800)
 Supports 8/9/16/18/24-bit host interface
(MIPI DBI)
Image
 Integrated image signal processor
supports 13 MP up to 15fps
 Supports electronic image stabilization
 Supports 8/9/16/24/32-bit serial
interfaces
 Supports video stabilization
 Supports 16/18/24-bit RGB interfaces
(MIPI DPI)
 Supports preference color adjustment
 MIPI DSI interface (4 data lanes)
 Embedded LCD gamma correction
 Supports multiple frame noise reduction
for video recording
 Supports true colors
 Supports lens shading correction
 4 overlay layers with per-pixel alpha
channel and gamma table
 Supports auto sensor defect pixel
correction
 Supports spatial and temporal dithering
 Supports AE/AWB/AF
 Supports side-by-side format output to
stereo 3D panel in both portrait and
landscape modes
 Supports edge enhancement
(sharpness)
 Supports local contrast enhancement
 Supports external HDMI/MHL Tx bridge
with 720p video output


 Supports noise reduction
 Supports face detection and visual
tracking
 Supports color enhancement
 Supports multiple frame blending for
multi-motion special effect
 Supports adaptive contrast
enhancement
 Supports zero shutter delay image
capture
 Supports image/video/graphic
sharpness enhancement
 Supports capturing full size image when
recording video (up to 8M sensor)
 Supports dynamic backlight scaling
 Supports capturing stereo image without
bridge IC
Graphics
 Supports stereo video recording without
bridge IC
 OpenGL ES 1.1/2.0 3D graphic
accelerator capable of processing 50M
tri/sec and 572M pixel/sec @ 286MHz
(effective pixel rate: 1,430M pixel/sec.)
 2D graphics hardware accelerator
 Supports Xenon flash
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 OpenVG1.1 vector graphics accelerator
 Supports MIPI CSI-2 high-speed
camera serial interface with 4 data lane
(for main) + 2 data lane (for stereo) + 2
data lane (for sub)
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
 Hardware JPEG decoder: Baseline
decoding with 42M pixel/sec,
progressive format decoding support
 Sample formats supported: 8-bit/16-bit,
Mono/Stereo
 Hardware JPEG encoder: Baseline
encoding with 90M pixel/sec
 4-band IIR compensation filter to
enhance loudspeaker responses
 Supports YUV422/YUV420 color format
and EXIF/JFIF format
 Hardware WebP decoder
 Proprietary audio post-processing
technologies: BesLoudness, Android
built-in post processing
Video
 Audio encode: AMR-NB, AMR-WB, AAC,
OGG
 Interfaces supported: DAI, I2S, PCM
 H.264 decoder: Baseline 1080p @
30fps/40Mbps
 Audio decode: WAV, MP3, MP2,
AAC, AMR-NB, AMR-WB, MIDI, Vorbis,
APE, AAC-plus v1, AAC-plus v2, FLAC,
WMA
 H.264 decoder: Main/high profile
1080p@30fps/40Mbps
 Sorenson H.263/H.263 decoder: 1080p
@ 30fps/40Mbps

Speech
 MPEG-4 SP/ASP decoder: 1080p @
30fps/40Mbps
 Speech codec (FR, HR, EFR, AMR FR,
AMR HR and Wide-Band AMR)
 DIVX3/DIVX4/DIVX5/DIVX6/DIVX
HD/XVID decoder: 1080p @
30fps/40Mbps
 CTM
 VP8 decoder: 1080p @ 30fps/40Mbps
 Noise cancellation
 VC-1 decoder: 1080p @ 30fps/40Mbps
 Dual-MIC noise cancellation
 MPEG-4 encoder: Simple profile 1080p
@ 30fps
 Echo cancellation
 H.263 encoder: 1080p @ 30fps
 Dual-MIC input
 H.264 encoder: High profile 720p @
30fps
 Digital MIC input
 Noise reduction
 Noise suppression
 Echo suppression
 VP8 encoder: 720p@ 30fps

Audio
 Sampling rates supported: 6kHz to
96kHz
1.4
General Descriptions
MediaTek MT6589 is a highly integrated 3G System-on-chip (SoC) which incorporates advanced
TM
features e.g. HSPA R8 modem, Quad-core ARM® Cortex-A7 MPCore operating at 1.2 GHz, 3D
graphics (OpenGL|ES 2.0), 13M camera ISP, LPDDR2 533MHz and high-definition 1080p video
decoder. MT6589 helps phone manufacturers build high-performance 3G smart phones with PC-like
browser, 3D gaming and cinema class home entertainment experiences.
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World-leading technology
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Based on MediaTek’s world-leading mobile chip SoC architecture with advanced 28nm process,
MT6589 is the brand-new generation smart phone SoC integrating MediaTek HSPA R8 modem,
TM
1.2GHz Quad-core ARM® Cortex-A7 MPCore , 3D graphics and high-definition 1080p video
decoder.
Rich in features, high-valued product
To enrich the camera features, MT6589 equips a 13M camera ISP with advanced features e.g. auto
focus, anti-handshake, auto sensor defect pixel correction, continuous video AF, face detection, burst
shot, optical zoom and panorama view.
Incredible browser experience
TM
The 1.2GHz Quad-core ARM® Cortex-A7 MPCore with NEON multimedia processing engine brings
PC-like browser experiences and helps accelerate OpenGL|ES 2.0 3D Adobe Flash 10 rendering
performance to an unbeatable level.
NAND
Flash
USB2.0
HOST
USB2.0
OTG
JTAG
MMC/SD/SDIO
MT6589
LPDDR2
External
Memory
Interface
Modem Analog
RX
ADC
TX
ADC
APC
AP MCU
AFC
ARM®
Cortex-A7
MPCoreTM
ARM®
Cortex-A7
MPCoreTM
ARM®
Cortex-A7
MPCoreTM
ARM®
Cortex-A7
MPCoreTM
BT/FM
WIFI/GPS
MT6628
Modem
EDGE
RF
WCDMA
RF
HSPA+
MT6167
For
WCDMA
DSP
Internal
Memory
TCM
Cache
ARM®
Cortex-R4
Qwerty
Keypad
SIM
NEON
Modem MCU
GP Timer
I2C
GSM/GPRS/
EDGE
L2 Cache
JTAG
DMA
SIM
PowerVR™
SGX544
Graphics
accelerator
Analog
Speaker
PLL
MT6320
Multimedia
EDGE
RF
TDSCDMA
RF
MT6168
For
Video
Codec
TDSCDMA
JPEG
Codec
Image Post-process
Camera
ISP
LCD Control
ARM®
TrustZone®
DAC
Power
ADC
Battery
Headset
Management
MIC1
MIC2
GPIO
13MP
Camera
LCD
UART
Touch Panel
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Figure 1-1: Block diagram of MT6589
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2
Product Description
2.1
Pin Description
2.1.1
Ball Map View
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Figure 2-1 : Ball map view of MT6589
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2.1.2
Pin Coordinate
Table 2-1: Pin coordinate
Ball name
Ball
Loc.
Ball name
Ball
Loc.
Ball name
A1
A2
NC
SCL2
K12
K13
GND
DVDD18_EMI
W19
W20
GND
DVDD
A4
A5
MSDC3_DAT0
RDQ9
K15
K16
DVDD18_EMI
GND
W24
W25
GND
URXD4
A8
A9
RDQM0
RDQ5
K17
K18
GND
GND
W26
W27
URXD2
PWM1
A12
A13
RDQ15
RA6
K20
K25
DVDD18_EMI
ADC_CLK
W28
Y1
URTS2
DVDD33_MC2
A15
A17
RA4
RDQ30
K26
K28
ADC_WS
ADC_DAT_IN
Y2
Y3
MSDC1_INSI
MSDC2_INSI
A20
A21
RDQ21
RDQM2
L1
L2
RDP0
RDN1_A
Y4
Y5
MSDC2_DAT1
DPIB4
A24
A25
RDQ26
MSDC0_DAT4
L3
L4
RDP0_A
RCP_A
Y24
Y25
DVDD28_NML2
URTS1
A27
A28
MSDC0_DAT5
MSDC0_CMD
L7
L24
DVDD18_MIPIRX
GND
Y26
Y27
URXD1
UTXD1
A29
B1
NC
SDA2
L25
L26
TESTMODE
DAC_WS
Y28
Y29
UTXD4
UCTS1
B2
B3
MRG_I2S_PCM_CLK
URXD3
L27
L28
DAC_DAT_OUT
PWRAP_EVENT
AA1
AA2
DPIB7
DPIG7
B4
B5
MSDC3_DAT1
RDQ8
L29
M1
PWRAP_SPI0_CSN
RDN0
AA5
AA6
DPIG5
GND
B7
B8
RDQ0
RDQ3
M2
M3
RDP2
RDN1
AA25
AA26
CHD_DM_P0
PWM3
B9
B11
RDQ4
RDQ12
M4
M6
RCP
DVSS18_MIPIRX
AA28
AA29
PWM4
PWM2
B12
B13
RDQ14
RA12
M15
M16
AVSS18_MEMPLL
AVDD18_MEMPLL
AB2
AB4
DPIR2
DPIB3
B14
B15
RBA0
RCAS_
M24
M25
SIM2_SCLK
SIM1_SIO
AB5
AB11
DPIG1
VPROC_FB
B17
B18
RDQ31
RDQ28
M26
M27
PWRAP_SPI0_MI
DAC_CLK
AB25
AB26
CHD_DP_P0
AVSS33_USB_P0
B20
B21
RDQ20
RDQ18
M28
M29
PWRAP_SPI0_MO
PWRAP_SPI0_CLK
AB27
AB28
USB_DM_P0
AVDD33_USB_P0
B22
B24
B25
RDQ16
RDQ25
MSDC0_DAT2
N2
N3
N4
RDN2
RDP1
RCN
AC1
AC2
AC3
DPIG0
DPIHSYNC
DPIB0
B26
B27
MSDC0_DAT0
MSDC0_DAT6
N10
N11
DVDD
DVDD
AC4
AC5
DPIR6
DPIB1
B28
B29
NLD4
NRNB
N12
N13
DVDD
DVDD
AC26
AC27
AVDD18_USB_P1
USB_DP_P0
FO
R
Ball
Loc.
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Technical Brief
Confidential A
Ball name
Ball
Loc.
Ball name
Ball
Loc.
Ball name
C1
SDA1
N14
DVDD
AD1
DPIVSYNC
C2
C3
MRG_I2S_PCM_RX
MRG_I2S_PCM_SYNC
N15
N16
DVDD
DVDD
AD2
AD3
DPIR5
DPIG3
C4
C5
MSDC3_CLK
GND
N17
N18
DVDD
TN_MEMPLL
AD4
AD5
DPIB6
DPIR3
C6
C7
RDQ11
RDQ10
N19
N24
TP_MEMPLL
SIM2_SIO
AD6
AD8
DPIG4
I2S_DATA_OUT
C8
C9
GND
RDQM1
N25
N28
SIM1_SCLK
SIM2_SRST
AD10
AD11
EINT10_AUXIN2
GND_VPROC_FB
C10
C11
RDQ6
RDQ13
P1
P2
RDN3
RDP3
AD12
AD16
AVSS18_AP
AVSS18_MD
C12
C14
RBA1
RRAS_
P3
P4
TDN0
TDP1
AD20
AD24
GND
GND
C15
C16
RODT
RA3
P6
P7
TDN3
TDP3
AD27
AD28
AVDD18_USB_P0
USB_VRT
C17
C18
RA5
RDQM3
P8
P10
TCP
DVDD
AD29
AE2
USB_DM_P1
DPIB5
C19
C20
RDQ22
RDQ23
P11
P12
GND
GND
AE5
AE6
DPIR0
LSA0
C21
C22
GND
RDQ24
P13
P14
GND
GND
AE7
AE8
DISP_PWM
EINT5
C23
C24
RDQ27
GND
P15
P16
GND
GND
AE9
AE10
SDA0
EINT11_AUXIN3
C26
C27
MSDC0_DAT1
MSDC0_CLK
P17
P18
DVDD
DVDD
AE11
AE12
AUX_XM
AUX_YP
C28
C29
NLD0
NLD7
P19
P20
DVDD
DVDD
AE13
AE17
AVSS18_AP
AVSS18_MD
D2
D3
SCL1
MSDC3_DAT3
P25
P26
RTC32K_CK
SRCLKENA
AE20
AE21
BSI1A_CS0
BSI1A_DATA1
D4
D5
MSDC3_DAT2
MSDC3_CMD
P28
P29
SIM1_SRST
SRCVOLTEN
AE22
AE23
BSI1B_DATA
BSI1B_CS0
D6
D7
D8
RDQ1
GND
RDQ2
R1
R2
R3
TDP2
TDN2
TDP0
AE24
AE25
AE26
BPI1_BUS18
DVDD28_BPI
BPI1_BUS16
D9
D10
GND
RDQ7
R4
R6
TDN1
VRT
AE27
AE28
USB_VBUS
AVSS33_USB_P1
D11
D12
GND
RA14
R7
R10
TCN
GND
AE29
AF1
USB_DP_P1
DVDD18_NML3
D13
D14
RA1
RA10
R11
R12
GND
DVDD_DVFS
AF2
AF4
DPIR4
DPIDE
D17
D18
RA13
GND
R13
R14
GND
GND
AF5
AF6
SPI1_MO
LPCE1B
D19
D20
RDQ29
GND
R15
R16
DVDD_DVFS
GND
AF8
AF9
EINT9
SCL0
FO
R
Ball
Loc.
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Technical Brief
Confidential A
Ball name
Ball
Loc.
Ball name
Ball
Loc.
Ball name
D21
RDQ19
R17
DVDD
AF10
EINT16_AUXIN4
D22
D23
GND
RDQ17
R18
R19
GND
DVDD
AF12
AF13
AUX_XP
UL_Q_N2
D24
D25
FSOURCE_P
MSDC0_DAT3
R20
R24
GND
DVDD18_MC0
AF14
AF15
UL_Q_P2
DL_Q_P2
D26
D27
MSDC0_DAT7
NCLE
R25
R26
EINT4
IDDIG
AF16
AF17
DL_Q_N2
UL_I_N1
D28
E1
NLD14
DAI_RSTB
R27
R28
EINT3
WATCHDOG
AF18
AF19
UL_I_P1
UL_Q_P1
E2
E5
MRG_I2S_PCM_TX
SRCLKENAI
R29
T2
SYSRSTB
DVSS18_MIPITX
AF20
AF21
UL_Q_N1
BSI1C_CLK
E6
E9
RDQS0
RDQS1_
T3
T4
DVDD18_MIPITX
MSDC1_DAT1
AF22
AF23
SRCLKENA2
BSI1B_CLK
E11
E12
RA8
RA11
T5
T8
MSDC1_DAT3
GND
AF24
AF26
BPI1_BUS11
BPI1_BUS6
E13
E14
RCKE
RCS_
T9
T10
GND
DVDD_GPU
AF27
AF28
BPI1_BUS4
VM0
E15
E16
REXTDN
RWE_
T11
T12
GND
DVDD_DVFS
AF29
AG1
AVDD33_USB_P1
DPIB2
E17
E18
DDR3RSTB
RA0
T13
T14
GND
GND
AG2
AG3
DPIR7
DPIR1
E20
E23
RDQS3
RDQS2_
T15
T16
DVDD_DVFS
GND
AG4
AG5
LSCK
SPI1_CLK
E25
E26
MSDC0_RSTB
NLD11
T17
T18
DVDD
GND
AG8
AG9
EINT7
I2S_CLK
E28
E29
NLD8
NCEB0
T19
T20
DVDD
GND
AG12
AG13
AUX_YM
UL_I_P2
F1
F2
DVDD18_NML4
CMPDN
T25
T26
JTRST_B
EINT2
AG14
AG15
UL_I_N2
DL_I_P2
F4
F6
UTXD3
RDQS0_
T27
T28
EINT1
EINT0
AG16
AG17
DL_I_N2
DVDD18_MD
F9
F12
F16
RDQS1
RCS1_
RA2
U1
U2
U5
DVDD33_MC1
MSDC1_CLK
MSDC1_CMD
AG18
AG19
AG20
VBIAS
APC2
APC1
F17
F18
RA7
RA9
U6
U8
MSDC1_SDWPI
GND
AG22
AG23
BSI1A_DATA2
DVDD28_BSI
F20
F23
RDQS3_
RDQS2
U9
U10
DVDD_GPU
DVDD_GPU
AG26
AG27
BPI1_BUS1
BPI1_BUS8
F25
F28
NLD12
NLD13
U11
U12
GND
DVDD_DVFS
AG28
AH1
BPI1_BUS5
DPIG2
F29
G2
NWEB
CMFLASH
U13
U14
DVDD_DVFS
DVDD_DVFS
AH2
AH3
DPIG6
LSDA
G3
G4
CMMCLK
CMPCLK
U15
U16
DVDD_DVFS
GND
AH4
AH5
LPCE0B
SPI1_MI
FO
R
Ball
Loc.
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Technical Brief
Confidential A
Ball name
Ball
Loc.
Ball name
Ball
Loc.
Ball name
G25
NLD15
U17
DVDD
AH6
LRSTB
G26
G27
NLD1
NLD3
U18
U19
GND
DVDD
AH7
AH8
LPTE
EINT6
G28
H1
NLD6
DVDD18_MIPIIO
U20
U24
DVDD
JTCK
AH9
AH10
I2S_WS
AUXIN1
H2
H3
CMRST
RDN0_B
U25
U28
JRTCK
JTDO
AH11
AH12
AUXIN0
REFP
H4
H10
RCN_B
DVDD18_EMI
U29
V1
JTDI
MSDC1_DAT0
AH13
AH14
REFN
AVDD18_MD
H12
H13
RCLK1
RCLK1_
V2
V4
MSDC1_DAT2
MSDC2_DAT0
AH16
AH17
DL_I_N1
DL_Q_N1
H14
H15
VREF
RCLK0_
V5
V6
MSDC2_SDWPI
GND
AH18
AH19
DL_Q_P1
AVDD28_DAC
H16
H18
RCLK0
VREF
V7
V8
GND
GND
AH20
AH21
TXBPI1
BSI1A_DATA0
H19
H20
DVDD18_EMI
DVDD18_EMI
V9
V10
DVDD_GPU
DVDD_GPU
AH22
AH23
BSI1A_CLK
BSI1C_DATA
H25
H26
NLD10
NALE
V11
V12
GND
DVDD_DVFS
AH24
AH25
BPI1_BUS10
BPI1_BUS13
H27
H28
NLD2
NLD5
V13
V14
DVDD_DVFS
DVDD_DVFS
AH26
AH27
BPI1_BUS9
BPI1_BUS17
H29
J1
NCEB1
RDN1_B
V15
V16
DVDD_DVFS
GND
AH28
AH29
BPI1_BUS3
VM1
J2
J3
RDP1_B
RDP0_B
V17
V18
DVDD
GND
AJ1
AJ2
NC
DPICK
J4
J6
RCP_B
GND
V19
V20
GND
DVDD
AJ3
AJ5
LSCE0B
LSCE1B
J10
J11
DVDD18_EMI
DVDD18_EMI
V24
V25
UTXD2
UCTS2
AJ6
AJ8
SPI1_CSN
EINT8
J14
J17
GND
DVDD18_EMI
V26
V28
JTMS
SDA3
AJ9
AJ11
I2S_DATA_IN
DVDD18_PLLGP
J18
J19
J20
DVDD18_EMI
DVDD18_EMI
DVDD18_EMI
V29
W2
W3
SCL3
MSDC2_DAT2
MSDC2_CLK
AJ12
AJ14
AJ16
AVDD18_AP
CLK26M2
DL_I_P1
J25
J28
NREB
NLD9
W4
W5
MSDC2_CMD
MSDC2_DAT3
AJ19
AJ21
CLK26M1
EXT_CLK_EN
J29
K2
DVDD18_NML1
RDP1_A
W8
W11
DVDD18_MC12
GND
AJ22
AJ24
DVDD18_BSI
BPI1_BUS0
K3
K4
RDN0_A
RCN_A
W12
W13
DVDD_DVFS
DVDD_SRAM
AJ25
AJ27
BPI1_BUS7
BPI1_BUS2
K6
K10
DVSS18_MIPIIO
GND
W14
W15
DVDD_SRAM
DVDD_DVFS
AJ28
AJ29
BPI1_BUS12
NC
K11
GND
W16
GND
FO
R
Ball
Loc.
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Technical Brief
Confidential A
2.1.3
Detailed Pin Description
Table 2-2: Acronym for pin type
Abbreviation
AI
AO
AIO
DI
DO
DIO
P
G
Description
Analog input
Analog output
Analog bi-direction
Digital input
Digital output
Digital bi-direction
Power
Ground
Table 2-3: Detailed pin description
Pin name
Type
Description
Power domain
SYSTEM
DIO
System reset input
DVDD18_NML1
WATCHDOG
DO
DVDD18_NML1
SRCVOLTEN
DIO
Watchdog reset output
Wakeup signal to external
PMIC
TESTMODE
RTC32K_CK
DIO
DIO
Test mode
32K clock intput
DVDD18_NML1
DVDD18_NML1
SRCLKENAI
SRCLKENA
PMIC
DIO
DIO
26MHz co-clock enable input
26MHz co-clock enable output
DVDD18_NML4
DVDD18_NML1
PWRAP_SPI0_MO
DIO
PMIC SPI control interface
DVDD18_NML1
PWRAP_SPI0_MI
PWRAP_SPI0_CSN
DIO
DIO
DVDD18_NML1
DVDD18_NML1
PWRAP_SPI0_CLK
PWRAP_EVENT
DIO
DIO
DVDD18_NML1
DVDD18_NML1
ADC_CLK
ADC_WS
DIO
DIO
PMIC audio input interface
DVDD18_NML1
DVDD18_NML1
ADC_DAT_IN
DAC_CLK
DIO
DIO
PMIC audio output interface
DVDD18_NML1
DVDD18_NML1
DAC_WS
DAC_DAT_OUT
SIM
DIO
DIO
DVDD18_NML1
DVDD18_NML1
SIM1_SIO
DIO
SIM1 data, PMIC interface
DVDD18_NML1
SIM1_SRST
SIM1_SCLK
DIO
DIO
SIM1 reset, PMIC interface
SIM1 clock, PMIC interface
DVDD18_NML1
DVDD18_NML1
SIM2_SIO
SIM2_SRST
DIO
DIO
SIM2 data, PMIC interface
SIM2 reset, PMIC interface
DVDD18_NML1
DVDD18_NML1
SIM2_SCLK
JTAG
DIO
SIM2 clock, PMIC interface
DVDD18_NML1
JTCK
DIO
JTCK
DVDD18_NML1
FO
R
SYSRSTB
DVDD18_NML1
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Technical Brief
Confidential A
Pin name
Type
Description
Power domain
JTDO
DIO
JTDO
DVDD18_NML1
JTRST_B
JTDI
DIO
DIO
JTRST_B
JTDI
DVDD18_NML1
DVDD18_NML1
JRTCK
JTMS
LCD
DIO
DIO
JRTCK
JTMS
DVDD18_NML1
DVDD18_NML1
DISP_PWM
DIO
Display PWM output
DVDD18_NML3
Parallel display interface chip
select 1 output
Parallel display interface chip
select 0 output
Parallel display interface tearing
effect
LPCE1B
DIO
DVDD18_NML3
LPCE0B
DIO
LPTE
DIO
LRSTB
DIO
Parallel display interface Reset
Signal
DVDD18_NML3
DPIDE
DIO
Data enable signal of DPI
DVDD18_NML3
DPICK
DIO
DVDD18_NML3
DPIVSYNC
DIO
Clock pin of DPI
Vertical synchronization signal
of DPI
DPIHSYNC
DIO
Horizontal synchronization
signal of DPI
DVDD18_NML3
DPIR7
DIO
Data pin 7 of DPI Rchannel/Data 23 for DBI parallel
LCD interface
DVDD18_NML3
DPIR6
DIO
LCD interface
DVDD18_NML3
DPIR5
DIO
LCD interface
DVDD18_NML3
DPIR4
DIO
LCD interface
DVDD18_NML3
DPIR3
DIO
DPIR2
DIO
DPIR1
DIO
DPIR0
DIO
DPIG7
DIO
DPIG6
DIO
DVDD18_NML3
DVDD18_NML3
FO
R
DPI
LCD interface
LCD interface
LCD interface
LCD interface
Data pin 7 of DPI Gchannel/Data 15 for DBI parallel
LCD interface
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
Page 18 of 53
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
LCD interface
Power domain
DPIG5
DIO
LCD interface
DVDD18_NML3
DPIG4
DIO
LCD interface
DVDD18_NML3
DPIG3
DIO
LCD interface
DVDD18_NML3
DPIG2
DIO
LCD interface
DVDD18_NML3
DPIG1
DIO
LCD interface
DVDD18_NML3
DPIG0
DIO
LCD interface
DVDD18_NML3
DPIB7
DIO
Data pin 7 of DPI Bchannel/Data 7 for DBI parallel
LCD interface
DVDD18_NML3
DPIB6
DIO
LCD interface
DVDD18_NML3
DPIB5
DIO
LCD interface
DVDD18_NML3
DPIB4
DIO
LCD interface
DVDD18_NML3
DPIB3
DIO
LCD interface
DVDD18_NML3
DPIB2
DIO
DPIB1
DIO
DPIB0
DIO
LCD interface
LCD interface
LCD interface
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
SLCD
Serial display interface chip
select 0 output
DIO
LSCK
DIO
LSCE1B
DIO
LSDA
DIO
Serial display interface clock
output
Serial display interface chip
select 1 output
Serial display interface data
LSA0
DIO
Serial display interface address
FO
R
LSCE0B
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
DVDD18_NML3
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
Power domain
output
I2S
I2S_DATA_IN
DIO
I2S data input pin
DVDD18_NML3
I2S_DATA_OUT
I2S_WS
DIO
DIO
I2S data output pin
I2S word select
DVDD18_NML3
DVDD18_NML3
I2S_CK
PCM/I2S merge interface
DIO
I2S clock
DVDD18_NML3
MRG_I2S_PCM_TX
DIO
MRG_I2S_PCM_CLK
DIO
MRG_I2S_PCM_RX
DIO
MRG_I2S_PCM_SYN
C
DIO
PCM/I2S/merge audio interface
to MT6628
DVDD18_NML4
DAI_RSTB
DIO
to MT6628
DVDD18_NML4
EINT0
EINT1
DIO
DIO
External interrupt 0
DVDD18_NML1
DVDD18_NML1
EINT2
EINT3
DIO
DIO
DVDD18_NML1
DVDD18_NML1
EINT4
EINT5
DIO
DIO
DVDD18_NML1
DVDD18_NML3
EINT6
EINT7
DIO
DIO
DVDD18_NML3
DVDD18_NML3
EINT8
EINT9
DIO
DIO
DVDD18_NML3
DVDD18_NML3
External interrupt 10/Aux ADC
external channel 2
DVDD18_NML3
to MT6628
to MT6628
to MT6628
DVDD18_NML4
DVDD18_NML4
DVDD18_NML4
EINT
EINT10_AUX_IN2
DIO/AIO
EINT11_AUX_IN3
DIO/AIO
EINT16_AUX_IN4
DIO/AIO
external channel 3
external channel 4
DVDD18_NML3
DVDD18_NML3
PWM
DIO
PWM1
DVDD28_NML2
PWM2
PWM3
DIO
DIO
PWM2
PWM3
DVDD28_NML2
DVDD28_NML2
PWM4
UART1
DIO
PWM4
DVDD28_NML2
URXD1
URTS1
DIO
DIO
UART1 RX
UART1 RTS
DVDD28_NML2
DVDD28_NML2
UCTS1
UTXD1
UART2
DIO
DIO
UART1 CTS
UART1 TX
DVDD28_NML2
DVDD28_NML2
UTXD2
DIO
UART2 TX
DVDD18_NML1
URXD2
DIO
UART2 RX
DVDD18_NML1
FO
R
PWM1
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
Power domain
DIO
UART2 CTS
DVDD18_NML1
URTS2
UART3
DIO
UART2 RTS
DVDD18_NML1
UTXD3
URXD3
UART4
DIO
DIO
UART3 TX
UART3 RX
DVDD18_NML4
DVDD18_NML4
UTXD4
DIO
UART4 TX
DVDD28_NML2
URXD4
SPI
DIO
UART4 RX
DVDD28_NML2
SPI1_CSN
SPI1_MI
DIO
DIO
SPI1 chip select
SPI1 data in
DVDD18_NML3
DVDD18_NML3
SPI1_MO
SPI1_CLK
BPI
DIO
DIO
SPI1 data out
SPI1 clock
DVDD18_NML3
DVDD18_NML3
BPI_BUS0
DIO
BPI BUS0
DVDD28_BPI
BPI_BUS1
BPI_BUS2
DIO
DIO
BPI BUS1
BPI BUS2
DVDD28_BPI
DVDD28_BPI
BPI_BUS3
BPI_BUS4
DIO
DIO
BPI BUS3
BPI BUS4
DVDD28_BPI
DVDD28_BPI
BPI_BUS5
BPI_BUS6
DIO
DIO
BPI BUS5
BPI BUS6
DVDD28_BPI
DVDD28_BPI
BPI_BUS7
BPI_BUS8
DIO
DIO
BPI BUS7
BPI BUS8
DVDD28_BPI
DVDD28_BPI
BPI_BUS9
BPI_BUS10
DIO
DIO
BPI BUS9
BPI BUS10
DVDD28_BPI
DVDD28_BPI
BPI_BUS11
BPI_BUS12
DIO
DIO
BPI BUS11
BPI BUS12
DVDD28_BPI
DVDD28_BPI
BPI_BUS13
BPI_BUS16
DIO
DIO
BPI BUS13
BPI BUS16
DVDD28_BPI
DVDD28_BPI
BPI_BUS17
BPI_BUS18
VM
DIO
DIO
BPI BUS17
BPI BUS18
DVDD28_BPI
DVDD28_BPI
VM1
VM0
BSI
DIO
DIO
PA mode selection
PA mode selection
DVDD28_BPI
DVDD28_BPI
BSI1A_CS0
DIO
BSI1A CS0
DVDD18_BSI
BSI1A_CLK
BSI1A_DATA0
DIO
DIO
BSI1A CLK
BSI1A DATA0
DVDD18_BSI
DVDD18_BSI
BSI1A_DATA1
BSI1A_DATA2
DIO
DIO
BSI1A DATA1
BSI1A DATA2
DVDD18_BSI
DVDD18_BSI
BSI1B_CS0
BSI1B_CLK
DIO
DIO
BSI1B CS0
BSI1B CLK
DVDD28_BSI
DVDD28_BSI
BSI1B_DATA
BSI1C_CLK
DIO
DIO
BSI1B DATA
BSI1C CLK
DVDD28_BSI
DVDD18_BSI
BSI1C_DATA
DIO
BSI1C DATA
DVDD18_BSI
FO
R
UCTS2
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
Power domain
DIO
RF MT6167 TXBPI1
DVDD18_BSI
EXT_CLK_EN
SRCLKENA2
MSDC0
DIO
DIO
Co-clock control pin
Co-clock control pin
DVDD18_BSI
DVDD18_BSI
MSDC0_DAT6
DIO
MSDC0 data6 pin
DVDD18_MC0
MSDC0_DAT7
MSDC0_DAT5
DIO
DIO
MSDC0 data7 pin
MSDC0 data5 pin
DVDD18_MC0
DVDD18_MC0
MSDC0_RSTB
MSDC0_DAT4
DIO
DIO
MSDC0 reset output
MSDC0 data4 pin
DVDD18_MC0
DVDD18_MC0
MSDC0_DAT2
MSDC0_DAT3
DIO
DIO
MSDC0 data2 pin
MSDC0 data3 pin
DVDD18_MC0
DVDD18_MC0
MSDC0_CMD
MSDC0_CLK
DIO
DIO
MSDC0 command pin
MSDC0 clock output
DVDD18_MC0
DVDD18_MC0
MSDC0_DAT1
MSDC0_DAT0
MSDC1
DIO
DIO
MSDC0 data1 pin
MSDC0 data0 pin
DVDD18_MC0
DVDD18_MC0
MSDC1_CLK
DIO
MSDC1 clock output
DVDD33_MC1/DVDD18_MC12
MSDC1_CMD
MSDC1_DAT0
DIO
DIO
MSDC1 command pin
MSDC1 data0 pin
MSDC1_DAT1
MSDC1_DAT2
DIO
DIO
MSDC1 data1 pin
MSDC1 data2 pin
MSDC1_DAT3
MSDC1_SDWPI
DIO
DIO
MSDC1 data3 pin
MSDC1 WP pin
MSDC1_INSI
MSDC2
DIO
MSDC1 card insertion
DVDD18_NML3
MSDC2_CLK
MSDC2_CMD
DIO
DIO
MSDC2 clock output
MSDC2 command pin
MSDC2_DAT0
MSDC2_DAT1
DIO
DIO
MSDC2 data0 pin
MSDC2 data1 pin
MSDC2_DAT2
MSDC2_DAT3
DIO
DIO
MSDC2 data2 pin
MSDC2 data3 pin
MSDC2_SDWPI
MSDC2_INSI
MSDC3
DIO
DIO
MSDC2 WP pin
MSDC2 card insertion
MSDC3_CLK
MSDC3_CMD
DIO
DIO
MSDC3 clock output
MSDC3 command pin
DVDD18_NML4
DVDD18_NML4
MSDC3_DAT0
MSDC3_DAT1
DIO
DIO
MSDC3 data0 pin
MSDC3 data1 pin
DVDD18_NML4
DVDD18_NML4
MSDC3_DAT2
MSDC3_DAT3
NFI
DIO
DIO
MSDC3 data2 pin
MSDC3 data3 pin
DVDD18_NML4
DVDD18_NML4
NCEB0
DIO
NCEB1
DIO
FO
R
TXBPI1
Parallel NAND interface chip
select 0 output
select 1 output
DVDD18_NML1
DVDD18_NML1
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
ready input
Parallel NAND interface
command latch enable output
Power domain
DIO
NCLE
DIO
NALE
DIO
NREB
DIO
NWEB
DIO
NLD0
NLD1
DIO
DIO
Nand-Flash Data 0
Nand-Flash Data 1
DVDD18_NML1
DVDD18_NML1
NLD2
NLD3
DIO
DIO
Nand-Flash Data 2
Nand-Flash Data 3
DVDD18_NML1
DVDD18_NML1
NLD4
NLD5
DIO
DIO
Nand-Flash Data 4
Nand-Flash Data 5
DVDD18_NML1
DVDD18_NML1
NLD6
NLD7
DIO
DIO
Nand-Flash Data 6
Nand-Flash Data 7
DVDD18_NML1
DVDD18_NML1
NLD8
NLD9
DIO
DIO
Nand-Flash Data 8
Nand-Flash Data 9
DVDD18_NML1
DVDD18_NML1
NLD10
NLD11
DIO
DIO
Nand-Flash Data 10
Nand-Flash Data 11
DVDD18_NML1
DVDD18_NML1
NLD12
NLD13
DIO
DIO
Nand-Flash Data 12
Nand-Flash Data 13
DVDD18_NML1
DVDD18_NML1
NLD14
NLD15
EFUSE
DIO
DIO
Nand-Flash Data 14
Nand-Flash Data 15
DVDD18_NML1
DVDD18_NML1
FSOURCE_P
EMI
DIO
E-FUSE blowing power control
FSOURCE_P
DDR3RSTB
DIO
DDR3 reset output #
DVDD18_EMI
RCLK0
RCLK0_
DIO
DIO
DRAM clock 0 output
DRAM clock 0 output #
DVDD18_EMI
DVDD18_EMI
RCLK1
RCLK1_
DIO
DIO
DRAM clock 1 output
DRAM clock 1 output #
DVDD18_EMI
DVDD18_EMI
RCKE
RCS_
DIO
DIO
DRAM command output CKE
DRAM chip select 0 #
DVDD18_EMI
DVDD18_EMI
RCS1_
RCAS_
DIO
DIO
DRAM chip select 1 #
DRAM command output CAS#
DVDD18_EMI
DVDD18_EMI
RRAS_
RWE_
DIO
DIO
DRAM command output RAS#
DRAM command output WR#
DVDD18_EMI
DVDD18_EMI
RBA0
RBA1
DIO
DIO
DRAM bank address output 0
DRAM bank address output 1
DVDD18_EMI
DVDD18_EMI
RA0
RA1
DIO
DIO
DRAM address output 0
DVDD18_EMI
DVDD18_EMI
RA2
RA3
DIO
DIO
DVDD18_EMI
DVDD18_EMI
FO
R
NRNB
Parallel NAND interface
address latch enable output
Parallel NAND interface read
strobe output
Parallel NAND interface write
strobe output
DVDD18_NML1
DVDD18_NML1
DVDD18_NML1
DVDD18_NML1
DVDD18_NML1
Page 23 of 53
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
Power domain
DIO
DVDD18_EMI
RA5
RA6
DIO
DIO
DVDD18_EMI
DVDD18_EMI
RA7
RA8
DIO
DIO
DVDD18_EMI
DVDD18_EMI
RA9
RA10
DIO
DIO
DVDD18_EMI
DVDD18_EMI
RA11
RA12
DIO
DIO
DVDD18_EMI
DVDD18_EMI
RA13
RA14
DIO
DIO
DVDD18_EMI
DVDD18_EMI
RDQM0
RDQM1
DIO
DIO
DRAM DQM 0
DRAM DQM 1
DVDD18_EMI
DVDD18_EMI
RDQM2
RDQM3
DIO
DIO
DRAM DQM 2
DRAM DQM 3
DVDD18_EMI
DVDD18_EMI
RDQS0
RDQS0_
DIO
DIO
DRAM DQS 0
DRAM DQS 0 #
DVDD18_EMI
DVDD18_EMI
RDQS1
RDQS1_
DIO
DIO
DRAM DQS 1
DRAM DQS 1 #
DVDD18_EMI
DVDD18_EMI
RDQS2
RDQS2_
DIO
DIO
DRAM DQS 2
DRAM DQS 2 #
DVDD18_EMI
DVDD18_EMI
RDQS3
RDQS3_
DIO
DIO
DRAM DQS 3
DRAM DQS 3 #
DVDD18_EMI
DVDD18_EMI
RDQ0
RDQ1
DIO
DIO
DRAM data pin 0
DRAM data pin 1
DVDD18_EMI
DVDD18_EMI
RDQ2
RDQ3
DIO
DIO
DRAM data pin 2
DRAM data pin 3
DVDD18_EMI
DVDD18_EMI
RDQ4
RDQ5
DIO
DIO
DRAM data pin 4
DRAM data pin 5
DVDD18_EMI
DVDD18_EMI
RDQ6
RDQ7
DIO
DIO
DRAM data pin 6
DRAM data pin 7
DVDD18_EMI
DVDD18_EMI
RDQ8
RDQ9
RDQ10
DIO
DIO
DIO
DRAM data pin 8
DRAM data pin 9
DRAM data pin 10
DVDD18_EMI
DVDD18_EMI
DVDD18_EMI
RDQ11
RDQ12
DIO
DIO
DRAM data pin 11
DRAM data pin 12
DVDD18_EMI
DVDD18_EMI
RDQ13
RDQ14
DIO
DIO
DRAM data pin 13
DRAM data pin 14
DVDD18_EMI
DVDD18_EMI
RDQ15
RDQ16
DIO
DIO
DRAM data pin 15
DRAM data pin 16
DVDD18_EMI
DVDD18_EMI
RDQ17
RDQ18
DIO
DIO
DRAM data pin 17
DRAM data pin 18
DVDD18_EMI
DVDD18_EMI
RDQ19
RDQ20
DIO
DIO
DRAM data pin 19
DRAM data pin 20
DVDD18_EMI
DVDD18_EMI
RDQ21
DIO
DRAM data pin 21
DVDD18_EMI
FO
R
RA4
Page 24 of 53
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
Power domain
RDQ22
DIO
DRAM data pin 22
DVDD18_EMI
RDQ23
RDQ24
DIO
DIO
DRAM data pin 23
DRAM data pin 24
DVDD18_EMI
DVDD18_EMI
RDQ25
RDQ26
DIO
DIO
DRAM data pin 25
DRAM data pin 26
DVDD18_EMI
DVDD18_EMI
RDQ27
RDQ28
DIO
DIO
DRAM data pin 27
DRAM data pin 28
DVDD18_EMI
DVDD18_EMI
RDQ29
RDQ30
DIO
DIO
DRAM data pin 29
DRAM data pin 30
DVDD18_EMI
DVDD18_EMI
RDQ31
DIO
DVDD18_EMI
RODT(/RBA2)
DIO
DRAM data pin 31
DRAM ODT pin(/DRAM bank
address output 2)
REXTDN
CAM
DIO
DRAM REXTDN pin
DVDD18_EMI
CMPCLK
CMMCLK
DIO
DIO
Pixel clock from sensor
Master clock to sensor
DVDD18_NML4
DVDD18_NML4
CMRST
CMPDN
DIO
DIO
Reset control to sensor
Power down to sensor
DVDD18_NML4
DVDD18_NML4
CMFLASH
I2C0
DIO
Camera flash control signal
DVDD18_NML4
SCL0
SDA0
I2C1
DIO
DIO
I2C0 clock
I2C0 data
DVDD18_NML3
DVDD18_NML3
SCL1
DIO
I2C1 clock
DVDD18_NML4
SDA1
I2C2
DIO
I2C1 data
DVDD18_NML4
SCL2
SDA2
I2C3
DIO
DIO
I2C2 clock
I2C2 data
DVDD18_NML4
DVDD18_NML4
SCL3
DIO
I2C3 clock
DVDD18_NML1
SDA3
ABB
DIO
I2C3 data
DVDD18_NML1
UL_Q_N1
UL_Q_P1
AIO
AIO
UMTS uplink for UMTSTX_QN
UMTS uplink for UMTSTX_QP
DVDD18_MD
DVDD18_MD
UL_I_P1
UL_I_N1
AIO
AIO
UMTS uplink for UMTSTX_IP
UMTS uplink for UMTSTX_IN
DVDD18_MD
DVDD18_MD
VBIAS
AIO
AVDD28_DAC
APC1
AIO
3G PA analog control
st
Automatic power control for 1
modem
APC2
AIO
Automatic power control for 2
modem
DVDD18_EMI
AVDD28_DAC
nd
AVDD28_DAC
st
AIO
26MHz clock input for AP & 1
modem
UMTS uplink for UMTSRX_QP
DVDD18_MD
AIO
AIO
UMTS uplink for UMTSRX_QN
UMTS uplink for UMTSRX_IN
DVDD18_MD
DVDD18_MD
AIO
DL_Q_P1
DL_Q_N1
DL_I_N1
FO
R
CLK26M1
AVDD18_MD
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MT6589
Technical Brief
Confidential A
Pin name
Type
DL_I_P1
AIO
Description
Power domain
UMTS uplink for UMTSRX_IP
DVDD18_MD
nd
AIO
UMTS uplink for 2
UMTSRX_QP or WCDMA
diversity path
AIO
UMTS uplink for 2
UMTSRX_QN or WCDMA
diversity path
AIO
UMTS uplink for 2
UMTSRX_IN or WCDMA
diversity path
DL_I_P2
AIO
UMTS uplink for 2
UMTSRX_IP or WCDMA
diversity path
CLK26M2
AIO
UL_Q_N2
AIO
UL_Q_P2
AIO
UL_I_P2
AIO
UL_I_N2
AIO
REFN
AIO
REFP
AIO
AUX_IN0
AIO
AUX_IN1
AIO
AUX_XP
AIO
AUX_YP
AIO
AUX_XM
AIO
AUX_YM
AIO
DL_Q_P2
DVDD18_MD
nd
DL_Q_N2
DVDD18_MD
nd
DL_I_N2
DVDD18_MD
nd
26MHz clock input for AP & 2
modem
nd
UMTS uplink for 2
UMTSTX_QN
nd
UMTS uplink for 2
UMTSTX_QP
UMTS uplink for 2
UMTSTX_IP
DVDD18_MD
nd
AVDD18_MD
AVDD18_MD
AVDD18_MD
nd
AVDD18_MD
nd
UMTS uplink for 2
UMTSTX_IN
Negative reference port for
internal circuit
Positive reference port for
internal circuit
AuxADC external input channel
0
AuxADC external input channel
1
AuxADC channel for touch
screen TP_X+
screen TP_Y+
screen TP_XAuxADC channel for touch
screen TP_Y-
AVDD18_MD
AVDD18_AP
AVDD18_AP
AVDD18_AP
AVDD18_AP
AVDD18_AP
AVDD18_AP
AVDD18_AP
AVDD18_AP
MIPI
AIO
AIO
DSI0 lane3 N
DSI0 lane3 P
DVDD18_MIPITX
DVDD18_MIPITX
TDN2
TDP2
AIO
AIO
DSI0 lane2 N
DSI0 lane2 P
DVDD18_MIPITX
DVDD18_MIPITX
TCN
TCP
AIO
AIO
DSI0 CK lane N
DSI0 CK lane P
DVDD18_MIPITX
DVDD18_MIPITX
TDN1
TDP1
AIO
AIO
DSI0 lane1 N
DSI0 lane1 P
DVDD18_MIPITX
DVDD18_MIPITX
TDN0
TDP0
AIO
AIO
DSI0 lane0 N
DSI0 lane0 P
DVDD18_MIPITX
DVDD18_MIPITX
FO
R
TDN3
TDP3
Page 26 of 53
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MT6589
Technical Brief
Confidential A
Pin name
Type
Description
Power domain
VRT
AO
RDN3
AIO
External resistor for DSI bias
Connect 1.5K ohm 1% resistor
to ground.
CSI0 lane3 N
RDP3
RDN2
AIO
AIO
CSI0 lane3 P
CSI0 lane2 N
DVDD18_MIPIRX
DVDD18_MIPIRX
RDP2
RCN
AIO
AIO
CSI0 lane2 P
CSI0 CK lane N
DVDD18_MIPIRX
DVDD18_MIPIRX
RCP
RDN1
AIO
AIO
CSI0 CK lane P
CSI0 lane1 N
DVDD18_MIPIRX
DVDD18_MIPIRX
RDP1
RDN0
AIO
AIO
CSI0 lane1 P
CSI0 lane0 N
DVDD18_MIPIRX
DVDD18_MIPIRX
RDP0
AIO
DVDD18_MIPIRX
RDN1_A
AIO
CSI0 lane0 P
CSI1 lane1 N/Pixel data [6]
from sensor
RDP1_A
AIO
RCN_A
AIO
RCP_A
AIO
RDN0_A
AIO
RDP0_A
AIO
RDN1_B
AIO
RDP1_B
AIO
RCN_B
AIO
RCP_B
AIO
RDN0_B
AIO
RDP0_B
AIO
CSI1 lane1 P/Pixel data [7]
from sensor
CSI1 CK lane N/Pixel data [8]
from sensor
CSI1 CK lane P/Pixel data [9]
from sensor
CSI1 lane0 N/VREF from
sensor
CSI1 lane0 P/HREF from
sensor
CSI1 sub-cam lane1 N/Pixel
data [2] from sensor
CSI1 sub-cam lane1 P/Pixel
CSI1 sub-cam CK lane N/Pixel
CSI1 sub-cam CK lane P/Pixel
CSI1 sub-cam lane0 N/Pixel
CSI1 sub-cam lane0 P/Pixel
DVDD18_MIPITX
DVDD18_MIPIRX
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
DVDD18_MIPIIO
USB
USB port0 D+ differential data
line
USB port0 D- differential data
line
AIO
USB_DM_P0
AIO
CHD_DP_P0
CHD_DM_P0
AIO
AIO
BC1.1 Charger DP
BC1.1 Charger DM
AVDD33_USB_P0
AVDD33_USB_P0
USB_VRT
AO
USB output for bias current;
connect with 5.11K 1% Ohm to
GND
AVDD18_USB_P0
USB_VBUS
AI
Power for connected device
+3.3V
AVDD18_USB_P0
FO
R
USB_DP_P0
AVDD33_USB_P0
AVDD33_USB_P0
Page 27 of 53
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MT6589
Technical Brief
Confidential A
Pin name
Type
USB_DP_P1
AIO
USB_DM_P1
AIO
IDDIG
MEMPLL
DIO
TP_MEMPLL
AIO
TN_MEMPLL
AIO
Description
USB port1 D+ differential data
line
USB port1 D- differential data
line
USB OTG ID pin
MEMPLL differential output P
for debug
MEMPLL differential output N
for debug
Power domain
AVDD33_USB_P1
AVDD33_USB_P1
DVDD18_NML1
AVDD18_MEMPLL
AVDD18_MEMPLL
Analog power
Analog power input 1.8V for
PLL
AuxADC, TSENSE
BBTX, BBRX, 2GBBTX
P
AVDD18_AP
P
AVDD18_MD
P
DVDD18_MD
P
AVDD28_DAC
P
DVDD18_MIPITX
P
DVDD18_MIPIRX
P
DVDD18_MIPIIO
P
AVDD33_USB_P0
P
AVDD33_USB_P1
P
AVDD18_USB_P0
P
AVDD18_USB_P1
P
AVDD18_MEMPLL
Digital power
P
Analog power 1.8V for USB
port 0
port 1
Analog power for MEMPLL
DVDD18_NML1
DVDD28_NML2
P
P
Digital power input for NML1
-
DVDD18_NML3
DVDD18_NML4
P
P
-
DVDD28_BPI
P
Digital power input for 2.8V BPI
IO
-
DVDD28_BSI
P
DVDD18_BSI
P
DVDD18_EMI
P
DVDD18_MC0
P
DVDD33_MC1
P
FO
R
DVDD18_PLLGP
Alternative analog power input
1.8V for BBTX, BBRX, 2GBBTX
APC
Analog power for MIPI DSI
Analog power for MIPI CSI0
Analog power for MIPI CSI1 &
GPI
port 0
port 1
Digital power input for 2.8V BSI
IO
Digital power input for 1.8V BSI
IO
Digital power input for EMI
Digital power input for MSDC0
transmitter
-
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Pin name
Type
Description
Power domain
transmitter
Digital power input for
MSDC1/MSDC2 receiver
DVDD33_MC2
P
-
DVDD18_MC12
P
DVDD_GPU
P
DVDD
P
DVDD_DVFS
P
processor
-
DVDD_SRAM
P
processor memory
-
-
Digital power input for graphic
processor
Digital power input for core
-
Analog ground
AVSS18_AP
AVSS18_MD
G
G
DVSS18_MIPITX
DVSS18_MIPIRX
G
G
DVSS18_MIPIIO
AVSS33_USB_P0
G
G
AVSS33_USB_P1
AVSS18_MEMPLL
Digital ground
G
G
GND
G
-
2.2
Electrical Characteristic
2.2.1
Absolute Maximum Ratings
Table 2-4: Absolute maximum ratings for power supply
Symbol or pin
name
Description
Min.
Max.
Unit
Analog power input 1.8V for PLL
1.7
1.9
V
AVDD18_AP
AVDD18_MD
Analog power input 1.8V for AuxADC, TSENSE
Analog power input 1.8V for BBTX, BBRX, 2GBBTX
1.7
1.7
1.9
1.9
V
V
DVDD18_MD
Alternative analog power input 1.8V for BBTX, BBRX,
2GBBTX
1.7
1.9
V
AVDD28_DAC
DVDD18_MIPITX
Analog power input 2.8V for APC
2.66
1.7
2.94
1.9
V
V
DVDD18_MIPIRX
DVDD18_MIPIIO
AVDD33_USB_P0
Analog power for MIPI CSI1 & GPI
Analog power 3.3V for USB port 0
1.7
1.7
3.135
1.9
1.9
3.465
V
V
V
AVDD33_USB_P1
AVDD18_USB_P0
3.135
1.7
3.465
1.9
V
V
AVDD18_USB_P1
AVDD18_MEMPLL
1.7
1.7
1.9
1.9
V
V
DVDD18_NML1
1.62
1.98
V
FO
R
DVDD18_PLLGP
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Symbol or pin
name
Description
Min.
Max.
Unit
DVDD28_NML2
1.7
3.6
V
DVDD18_NML3
DVDD18_NML4
1.62
1.62
1.98
1.98
V
V
DVDD28_BPI
DVDD28_BSI
Digital power input for BPI
Digital power input for BSI
1.7
1.7
3.6
3.6
V
V
DVDD18_BSI
DVDD18_MC0
1.62
1.62
1.98
1.98
V
V
DVDD18_MC12
DVDD33_MC1
Digital power input for MSDC1/MSDC2
1.62
1.7
1.98
3.6
V
V
DVDD33_MC2
DVDD18_EMI
Digital power input for EMI
1.7
1.08
3.6
1.98
V
V
DVDD
DVDD_GPU
Digital power input for GPU
0.95
0.95
1.15
1.26
V
V
DVDD_DVFS
DVDD_SRAM
Digital power input for processor
Digital power input for processor memory
0.77
0.95
1.26
1.26
V
V
Warning: Stressing the device beyond the absolute maximum ratings may cause permanent damage.
These are stress ratings only.
2.2.2
Recommended Operating Conditions
Table 2-5: Recommended operating conditions for power supply
Symbol or pin
name
DVDD18_PLLGP
AVDD18_AP
AVDD18_MD
Description
Analog power input 1.8V for PLL
Analog power input 1.8V for AuxADC,
TSENSE
Analog power input 1.8V for BBTX, BBRX,
2GBBTX
Min.
Typ.
Max.
Unit
1.7
1.8
1.89
V
1.71
1.8
1.89
V
1.71
1.8
1.89
V
Alternative analog power input 1.8V for BBTX,
BBRX, 2GBBTX
1.71
1.8
1.89
V
AVDD28_DAC
DVDD18_MIPITX
Analog power input 2.8V for APC
2.66
1.71
2.8
1.8
2.94
1.89
V
V
DVDD18_MIPIRX
DVDD18_MIPIIO
Analog power for MIPI CSI1 & GPI
1.71
1.71
1.8
1.8
1.89
1.89
V
V
AVDD33_USB_P0
AVDD33_USB_P1
3.135
3.135
3.3
3.3
3.465
3.465
V
V
AVDD18_USB_P0
AVDD18_USB_P1
1.71
1.71
1.8
1.8
1.89
1.89
V
V
AVDD18_MEMPLL
DVDD18_NML1
1.71
1.62
1.8
1.8
1.89
1.98
V
V
DVDD28_NML2
1.7
2.7
1.8
3.3
1.95
3.6
V
DVDD18_NML3
1.62
1.8
1.98
V
FO
R
DVDD18_MD
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Symbol or pin
name
Min.
Typ.
Max.
Unit
1.62
1.8
1.98
V
DVDD28_BPI
Digital power input for BPI
1.7
2.7
1.8
3.3
1.95
3.6
V
DVDD28_BSI
1.7
2.7
1.8
3.3
1.95
3.6
V
DVDD18_BSI
DVDD18_MC0
1.62
1.62
1.8
1.8
1.98
1.98
V
V
DVDD18_MC12
Digital power input for MSDC1/MSDC2
1.8
1.8
1.98
1.95
V
DVDD33_MC1
1.62
1.7
DVDD33_MC2
2.7
1.7
3.3
1.8
3.6
1.95
Digital power input for EMI (LPDDR2)
2.7
1.08
3.3
1.2
3.6
1.32
Digital power input for EMI (UVDDR3)
Digital power input for EMI (LVDDR3)
1.125
1.215
1.25
1.35
1.375
1.485
DVDD
Digital power input for EMI (DDR3)
1.35
1.00
1.5
1.05
1.65
1.10
V
DVDD_GPU
DVDD_DVFS
Digital power input for GPU
Digital power input for processor
1.00
0.81
1.05
1.15
1.20
1.20
V
V
DVDD_SRAM
Digital power input for processor memory
1.00
1.15
1.20
V
DVDD18_NML4
DVDD18_EMI
2.2.3
Description
V
V
V
Storage Condition
1. Shelf life in sealed bag: 12 months at < 40°C and < 90% relative humidity (RH).
2. After bag opened, devices subjected to infrared reflow, vapor-phase reflow, or equivalent
processing must be:

Mounted within 168 hours at factory conditions of 30°C/60% RH, or
 Stored at 20% RH.
3. Devices require baking before mounting, if:

192 hours at 40°C +5°C/-0°C and < 5% RH for low temperature device containers, or

24 hours at 125°C +5°C/-0°C for high temperature device containers.
2.2.4
AC Electrical Characteristics and Timing Diagram
2.2.4.1
External Memory Interface for LPDDR2
FO
R
The external memory interface, shown in Figure 2-4, Figure 2-5 and Figure 2-6, is used to connect
LPDDR2 device for MT6589. It includes pins ED_CLK, ED_CLK_B, ECKE, ECS#, EBA[2:0],
EDQS[3:0], EDQS#[3:0], EA[9:0] and ED[31:0]. Table 2-5 summarizes the symbol definition and the
related timing specifications.
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ED_CLK_B
ED_CLK
ECS_B
ECA0-9
[CMD]
Figure 2-2: Basic timing parameter for LPDDR2 commands
ED_CLK_B
ED_CLK
ECA0-9
[CMD]
EDQS
/EDQS_B
EDQs
EDQS
/EDQS_B
EDQs
FO
R
Figure 2-3: Basic timing parameter for LPDDR2 write
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Figure 2-4: Basic timing parameter for LPDDR2 read
Table 2-6: LPDDR2 AC timing parameter table of external memory interfaces
Symbol
tCK
tDQSCK
Description
Min.
Typ.
Max.
Unit
Clock cycle time
DQS output access time from CK/CK’
3.75
2.5
8
5.5
ns
ns
tCH
tCL
Clock high level width
Clock low level width
0.45
0.45
0.55
0.55
tCK
tCK
tHP
tDS
Clock half period
DQ & DM input setup time
0.45
0.43
0.55
tCK
ns
DQ & DM input hold time
st
Write command to 1 DQS latching transition
0.43
0.75
DQS falling edge to CK setup time
DQS falling edge hold time from CK
0.2
0.2
tCK
tCK
tIS
Address & control input setup time
0.46
ns
tIH
Address & control input hold time
0.46
ns
tDQSCK (Min.) –
300
ns
tDH
tDQSS
tDSS
tDSH
tLZ(DQS)
DQS low-impedance time from CK/CK’
tHZ(DQS)
DQS high-impedance time from CK/CK’
DQ low-impedance time from CK/CK’
tHZ(DQ)
DQ high-impedance time from CK/CK’
FO
R
tLZ(DQ)
tDQSCK (Max.) –
100
tDQSCK (Min.) –
(1.4×tQHS (Max.))
tDQSCK (Max.) +
1.25
ns
tCK
ns
ns
ns
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Symbol
tDQSQ
tQHP
tQHS
tQH
Description
Min.
(1.4×tDQSQ
(Max.))
DQS-DQ skew
Data half period
Data hold skew factor
DQ/DQS output hold time from DQS
Typ.
Max.
Unit
0.34
Min. (tQSH, tQSL)
ns
tCK
0.4
tQHP – tQHS
ns
ns
tDQSH
DQS input high-level width
0.4
tCK
tDQSL
DQS input low-level width
0.4
tCK
tQSH
tQSL
DQS output high pulse width
DQS output low pulse width
tCH – 0.05
tCL – 0.05
tCK
tCK
tMRW
tMRR
MODE register Write command period
MODE register Read command period
5
2
tCK
tCK
tRPRE
tRPST
Read preamble
Read postamble
tRAS
tRC
tRFC
tRCD
0.9
tCL – 0.05
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
AUTO REFRESH to ACTIVE/AUTO REFRESH
command period
ACTIVE to READ or WRITE delay
1.1
tCK
tCK
3
6
tCK
tCK
56
tCK
3
tCK
PRECHARGE command period
3
tCK
tRRD
ACTIVE bank A to ACTIVE bank B delay
2
tCK
tWR
WRITE recovery time
3
tCK
Internal write to READ command time
SELF REFRESH exit to the next valid command
2
40
tCK
tCK
tXP
EXIT power-down to the next valid command
delay
2
tCK
tCKE
CKE min. pulse width (high & low pulse width)
2
tCK
tRP
tWTR
tXSR
2.3
System Configuration
2.3.1
Mode Selection
Table 2-7: Mode selection of chip (PMU 6320 pin)
Pin name
KP_COL0
KP_ROW0
2.3.1
Description
0: Trigger USB download without battery
1: NA
0: Trigger USB download without battery
1: NA
Constant Tie Pins
Table 2-8: Constant tied pins of MT6589
FO
R
Pin name
Description
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Pin name
TESTMODE
FSOURCE_P
2.4
Description
Test mode (tie to GND)
EFUSE burning (tie to GND)
Power-on Sequence
The power-on/off sequence with XTAL is shown in the following figure:
VBAT
DDLO
UVLO
PWRKEY
De-bounce
time = 50ms
BBWAKEUP
2ms
VCORE
2ms
8ms
VIO18
2ms
2ms
VA/VA28/VIO28
2ms
VAST
2ms
VPROC
2ms
VSRAM
2ms
VM
2ms
VUSB/VEMC3V3/VEMC1V8
2ms
VMC/VMCH
2ms
VTCXO
20ms
2ms
RESETB
Figure 2-5: Power on/off sequence with XTAL
Note that the above figure only shows one power-on/off condition with XTAL. The external PMIC
MT6320 for application processor MT6589 handles the power ON and OFF of the handset. The
following three different methods switch on the handset (when VBAT ≥ 3.2V):
1. Pulling PWRKEY low (The user presses PWRKEY.)
2. Pulling BBWAKEUP high
3. Valid charger plug-in
FO
R
Pulling PWRKEY low is a normal way to turn on the handset, which turns on regulators as long as the
PWRKEY is kept low. MT6320 outputs reset signal RESETB to MT6589 SYSRSTB input. After
SYSRSTB is de-asserted, the microprocessor starts and pulls BBWAKEUP high. After that PWRKEY
can be released, pulling BBWAKEUP high will also turn on the handset. This is the case when the
alarm in the RTC expires.
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Besides, applying a valid external supply on CHRIN will also turn on the handset. However, if the
battery is in the UV state (VBAT < 3.2V), the handset cannot be turned on in any way.
The UVLO function in MT6320 prevents system startup when initial voltage of the main battery is
below the 3.2V threshold. When the battery voltage is bigger than 3.2V, the UVLO comparator
switches and threshold are reduced to 2.9V, which allows the handset to start smoothly unless the
battery decays to 2.9V and below.
Once MT6320 enters the UVLO state, it draws very low quiescent current. The VRTC LDO will still be
active until the DDLO disables it.
VBAT
DDLO
UVLO
PWRKEY
De-bounce
time = 50ms
BBWAKEUP
2ms
VCORE
2ms
8ms
VIO18
2ms
2ms
VA/VA28/VIO28
2ms
VAST
2ms
VPROC
2ms
VSRAM
2ms
VM
2ms
VUSB/VEMC3V3/VEMC1V8
2ms
VMC/VMCH
VTCXO
22ms
2ms
RESETB
Figure 2-6: Power on/off sequence without XTAL
The figure above shows the power-on/off sequence without XTAL. VTCXO is always turned on when
VBAT is above the DDLO threshold.
2.5
Analog Baseband
FO
R
To communicate with analog blocks, a common control interface for all analog blocks is implemented.
In addition, there are some dedicated interfaces for data transfer. The common control interface
translates the APB bus write and read cycle for specific addresses related to analog front-end control.
During the writing or reading of any of these control registers, there is a latency associated with the
transfer of data to or from the analog front-end. Dedicated data interface of each analog block is
implemented in the corresponding digital block. An analog block includes the following analog
functions for the complete GSM/GPRS/WCDMA base-band signal processing:
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





Base-band Rx: For I/Q channels base-band A/D conversion
Base-band Tx: For I/Q channels base-band D/A conversion and smoothing filtering.
nd
2G base-band Tx: For the 2 I/Q channels base-band D/A conversion and smoothing filtering.
RF control: Two DACs for automatic power control (APC) are included. Their outputs are provided
to the external RF power amplifier respectively, according to the system dual-talk configuration.
One more DAC for voltage bias control (VBIAS) is included for WCDMA system, and the output is
provided to the external RF power amplifier.
Auxiliary ADC: Provides an ADC for the battery and other auxiliary analog functions monitoring.
Clock generation: Includes two clock-squarers for shaping the dual-talk system clock and 14 PLLs
providing clock signals to base-band TRx, DSP, MCUUSB, MSDC, LVDS and HDMI units.
The analog blocks include the following analog functions for complete GSM/GPRS/WCDMA baseband signal processing:







BBRX
BBTX
2GBBTX
APC-DAC
VBIAS-DAC
AUXADC
Phase locked loop
2.5.1
2.5.1.1
BBRX
Block Descriptions
FO
R
The receiver (Rx) performs baseband I/Q channels downlink analog-to-digital conversion:
1. Analog input multiplexer: For each channel, a 2-input multiplexer is included.
2. A/D converter: 4 high performance sigma-delta ADCs perform I/Q digitization for further digital
signal processing.
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Thermometer
(fS)
DL_I_P1
DL_I_N1
VCM1
VCM1
MUX
8
ΔΣ
Modulator
2's complement
(fS)
Encoder
Main path
DOUT_I1[3:0]
CKOUT_416M_IQ1
INT_SEL_VIN_IQ1
DL_Q_P1
DL_Q_N1
VCM1
VCM1
MUX
8
ΔΣ
Modulator
Encoder
DOUT_Q1[3:0]
Diversity path (or 2nd modem)
DL_I_P2
DL_I_N2
VCM2
VCM2
MUX
8
ΔΣ
Modulator
Encoder
DOUT_I2[3:0]
CKOUT_416M_IQ2
INT_SEL_VIN_IQ2
DL_Q_P2
DL_Q_N2
VCM2
VCM2
MUX
MT6589
Technical Brief
Confidential A
8
ΔΣ
Modulator
Encoder
DOUT_Q2[3:0]
Figure 2-7: Block diagram of BBRX-ADC
2.5.1.2
Function Specifications
See the table below for the function specifications of the base-band downlink receiver.
Table 2-9: Baseband downlink specifications
Symbol
Parameter
VIN
Differential analog input voltage (peak-to-peak)
ICM
Common mode input current magnitude
VCM
Common mode input voltage
FC
0.65
Input clock frequency
 Clock rate (DC mode)
 Clock rate (SC mode & GSM mode)
Input clock duty cycle
Typ.
0.7
Max.
2.4
V
1
uA
0.75
V
416
208
Input clock period jitter, DC mode
0.14
% (rms)
Input clock period jitter, SC mode & GSM mode
0.61
% (rms)
10.4
20.8
kΩ
kΩ
FS
Output sampling rate
5.6
11.2
8
16
416/208
VOS
Differential input referred offset
SIN
Signal to in-band noise
 DC mode, 2.4Vpp (5.2MHz) sinewave, 400kHz ~
4.6MHz band
50
MHz
MHz
%
Differential input resistance
 DC mode
 SC mode & GSM mode
49.5
Unit
50.5
RIN
FO
R
Min.
MSPS
10
72
75
mV
dB
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Symbol
Parameter
 SC mode, 2.4Vpp (2.7MHz) sinewave, 1kHz ~
Min.
72
Typ.
75
Max.
Unit
dB
84
87
1.7
1.8
1.9
1.8
1.9
V
80
°C
3
1
mA
uA
2.1MHz band
 GSM mode: 2.4Vpp(570kHz) sinewave, 70kHz ~
dB
270kHz band
DVDD18
Digital power supply
AVDD18
Analog power supply
1.7
Operating temperature
−20
T
Current consumption (per channel)
 Power-up
 Power-down
2.5.2
2.5.2.1
V
BBTX
Block Descriptions
st
BBTX includes two channel DACs with the 1 order low pass filter. The DACs are PMOS currentsteering topology with NMOS constant sinking current and the active RC filter performs current to
voltage buffer.
The bitwidth of DACs is 10-bit which is encoded into 7 bits of thermometer code and 7 binary code by
mixedsys hardware. The encoded bits are timing synchronized by D-type flip-flop which is toggled by
the analog local clock. The MD-PLL delivers 832MHz differential clock to BBTX. A clock divider
translates the 832MHz to 416MHz for DACs and AFIFO inside mixedsys.
FO
R
The IO power, DVDD18_MD is regulated to a voltage around 1.55V to supply analog component. The
required bias currents are generated by BBRX.
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MT6589
Technical Brief
Confidential A
2.5.2.2
Table 2-10: Baseband uplink transmitter specifications
Symbol
Vocm
IK
Parameter
DC output common mode voltage
HF leakage current @ supply,
Irms @416*2 = 832MHz
Min.
Typ.
Max.
Unit
0.615
0.65
0.685
V
3.5
uA
Vfs
N
DAC output swing
DAC resolution
2100
10.0
Fs
Imis
Sampling clock
1-sgma DAC unit cell mismatch
416
Gmis
Vos_T
3-sigma I/Q gain mismatch
3-sigma output differential DC offset over temp.
Vos
F3dB
3-sigma output differential DC offset
3dB corner freq.
SLPF
NOOB
LPF selectivity @832MHz
Output noise level @45MHz
CN
IM3
FO
R
T
MHz
%
0.2
4
dB
mV
25
10
30
mV
MHz
15.1
30.1.
dB
nVrms/sqrt(Hz)
-146
-140
dBc/Hz
-60
-56
dBc
80
°C
28
Signal to noise ratio@45MHz
In-band two-tone test swing V1=V2=290/sqrt(2)
mV
Current consumption
 Power-up
 Power-down
1
-0.2
20
mV
bit
-20
4.1
10
mA
uA
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2.5.3
2GBBTX
2.5.3.1
Block Descriptions
The 2G transmitter (2GTx) performs 2G baseband I/Q channels up-link digital-to-analog conversion
for dual-talk application. Each channel includes:
1. 11-bit D/A converter: Converts digital modulated signals to analog domain. The input to the DAC
is sampled at 26 MHz rate with the 11-bit resolution.
2. Smoothing filter: The low-pass filter performs smoothing function for DAC output signals with a
nd
1.8MHz 2 -order Butterworth frequency response.
UL_I_Data[10:0]
ULIP
DAC
LPF
ULIN
RG_UL_Analog_PwdB
RG_UL_LPF_Vcm[1:0]
RG_UL_LPF_BiasAdj[1:0]
RG_UL_LPF_FcAdj[7:0]
LPF BW
CAL
UL_Q_Data[10:0]
ULQP
LPF
DAC
ULQN
UL_Analog_CK
Bias Gen
Figure 2-8: Block diagram of 2GBBTX
2.5.3.2
See the table below for the function specifications of the 2G base-band uplink transmitter.
Table 2-11: Baseband uplink transmitter specifications
Symbol
N
FS
SINAD
THD
VOCM
Parameter
Min.
Typ.
Max.
Unit
Resolution
11
Bit
Sampling rate
Signal to noise and distortion ratio (in-band)
26
80
MSPS
dB
Total harmonic distortion
Output swing (full Swing)
0.9
-60
1.0
1.05
1.1
Output CM voltage
Output capacitance (single-ended)
1.1
dB
Vppd
1.15
20
V
PF
Output resistance (differential)
Differential nonlinearity
-0.5
+0.5
KΩ
LSB
INL
Integral nonlinearity
-1.0
+1.0
LSB
FO
R
DNL
1.5
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Symbol
OE
FCUT
Parameter
Min.
Typ.
Offset error (after calibration)
DVDD
Filter -3dB cutoff frequency (calibrated)
I/Q gain mismatch
0.95
AVDD
T
Analog power supply
1.7
-20
2.5.4.1
Unit
LSB
1.8
+/- 0.2
1.05
1.15
MHz
dB
V
1.9
80
V
°C
1.8
Current consumption
 Power-up
 Power-down
2.5.4
Max.
+/- 1
3.6
10
mA
uA
APC-DAC
Block Descriptions
See the figure below. APC-DAC is designed to produce a single-ended output signal at APC pin.
VBG
Reference buffer
& bias gen.
(from bandgap)
RG_APCBUF_TRIM[3:0]
APC_EN
APC_BUS[9:0]
APC_RSTB
APC_TG
10- bit DFF
R-string DAC core
RG_APC_TGSEL
PAD_APC
Output
Buffer
PA
APC-DAC
Figure 2-9: Block diagram of APC-DAC
2.5.4.2
See the table below for the function specifications of the APC-DAC.
Table 2-12: APC-DAC specifications
Symbol
N
FS
SNDR
TS
VO,max
Parameter
Min.
Resolution
Typ.
1.0833
Output loading capacitance
1,000
Differential nonlinearity (code 30 ~ 970)
1.0
INL
Integral nonlinearity (code 30 ~ 970)
FO
R
2.1666
MS/s
Bit
50
Maximum output
Analog power supply
Unit
10
Clock rate
Signal-to-noise-and-distortion ratio
(10kHz sine wave with 1.0V swing)
Settling time (99% full-swing settling)
CL
DNL
DVDD
AVDD
Max.
dB
5
us
AVDD  0.2
V
2,200
2.0
0.9
2.6
1.0
2.8
pF
LSB
LSB
1.1
3.0
V
V
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Symbol
T
Parameter
Min.
ION
Current consumption (power-on state)
IOFF
Current consumption (power-down state)
2.5.5
Typ.
20
Max.
Unit
85
C
300
uA
1
uA
VBIAS-DAC
2.5.5.1
Block Descriptions
VBG
Reference buffer
& bias gen.
(from bandgap)
RG_VBIASBUF_TRIM[3:0]
VBIAS_EN
VBIAS_BUS[9:0]
VBIAS_RSTB
VBIAS_TG
10- bit DFF
RG_VBIAS_TGSEL
R-string DAC core
PAD_VBIAS
Output
Buffer
PA
VBIAS-DAC
Figure 2-10: Block diagram of VBIAS-DAC
2.5.5.2
The functional specifications of the VBIAS-DAC are listed in the following table.
Table 2-13: VBIAS-DAC specifications
Symbol
N
FS
SNDR
TS
VO,max
CL
Parameter
Min.
Resolution
Clock rate
Typ.
Max.
Unit
2.1666
Bit
MS/s
10
1.0833
Signal-to-noise-and-distortion ratio
(10KHz sine wave with 1.0V swing)
50
Settling time (99% full-swing settling)
dB
5
AVDD  0.2
Maximum output
us
V
Output loading capacitance
1000
pF
DNL
Differential nonlinearity (code 20 ~ 970)
1.0
LSB
INL
Integral nonlinearity (code 20 ~ 970)
2.0
LSB
DVDD
0.9
1.0
1.1
V
AVDD
T
Analog power supply
2.6
2.8
20
3.0
85
C
Current consumption (power-on state)
Current consumption (power-down state)
FO
R
ION
IOFF
300
V
uA
1
uA
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2.5.6
2.5.6.1
AUXADC
Block Descriptions
Auxiliary ADC measures ADC and is the resistive touch panel controller. The auxiliary ADC includes
the following functional blocks:
1.
2.
Analog multiplexer: Selects signal from one of the auxiliary input channels. There are 16 input
channels of AUXADC. Some are for internal voltage measuring and some for external voltage
measuring. Environmental messages to be monitored, e.g. temperature, should be transferred to
the voltage domain.
12-bit A/D converter: Converts the multiplexed input signal to 12-bit digital data.
The touch screen controller drives the external touch panel via Pads XP, XM, YP and YM, and
AUXADC as a voltage meter, obtains the X/Y-position of the touched point on the external touch
screen. The touch screen interface contains 3 main blocks, which are touch screen pads control logic,
ADC interface logic and interrupt generation logic. The touch screen interface supports 2 conversion
modes, separate X/Y position conversion mode and auto (sequential) X/Y position conversion mode.
See
Table 2-14: Definitions of AUXADC channels for brief descriptions of AUXADC input channels.
AVDD
AVDD
Pen Interrupt
PAD_XP
PAD_YP
S/H
PAD_XM
PAD_YM
VRB
5
MUX
PAD_AUXIN<4:0>
ADC
VRT
DO<11:0>
Digital
Controller
Figure 2-11: Block diagram of AUXADC
Table 2-14: Definitions of AUXADC channels
FO
R
AUXADC channel ID
Channel 0
Channel 1
Channel 2
Description
External use (AUX_IN0)
External use (AUX_IN1)
Optional external use (AUX_IN2)
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AUXADC channel ID
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
Description
NA
NA
NA
NA
NA
NA
NA
XM (touch panel)
XP (touch panel)
YP (touch panel)
YM (touch panel)
2.5.6.2 Function Specifications
See the table below for the function specifications of auxiliary ADC.
Table 2-15: AUXADC specifications
Symbol
Parameter
N
FC
Resolution
Clock rate
FS
Sampling rate @ N-Bit
Input swing
CIN
Input capacitance
Unselected channel
Selected channel
RIN
Input resistance
Unselected channel
Min.
Typ.
Max.
12
4
Bit
MHz
4/(N+4)
0
Unit
AVDD
50
4
MSPS
V
fF
pF
MΩ
400
DNL
Clock latency
Differential nonlinearity
N+4
+1.0/-1.0
1/FC
LSB
INL
OE
Integral nonlinearity
Offset error
+1.0/-1.0
+/- 5
LSB
mV
FSE
Full swing error
Signal to noise and distortion ratio (10kHz full
swing input & 1.0833MHz clock rate)
+/- 5
mV
62
68
dB
Analog power supply
1.0
1.75
1.1
1.8
Current consumption
 Power-up
 Power-down
-20
Supports touch panel impedance
200
SINAD
DVDD
AVDD
T
FO
R
Ztp
1.2
1.85
V
V
80
°C
250
1
uA
uA
2K
Ω
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2.5.7
Clock Squarer
2.5.7.1
Block Descriptions
For most VCXO, the output clock waveform is sinusoidal with too small amplitude (about several
hundred mV) to make MT6589 digital circuits function well. Clock squarer is designed to convert such
a small signal to a rail-to-rail clock signal with excellent duty-cycle.
See the table below for the function specifications of clock squarer.
Table 2-16: Clock squarer 1 & 2 specifications
Symbol
Parameter
Min.
Typ.
Fin
Fout
Output clock frequency
13
13
26
26
Vin
DcycIN
Input signal amplitude
Input signal duty cycle
350
500
50
DcycOUT
TR
Output signal duty cycle
Rise time on pin CLKSQOUT
DcycIN-5
TF
DVDD
Fall time on pin CLKSQOUT
1.0
1.1
AVDD
T
Analog power supply
1.7
-20
1.8
Current consumption
2.5.8
2.5.8.1
Max.
Unit
MHz
MHz
1,000
mVpp
%
DcycIN+5
5
%
ns/pF
5
1.2
1.9
ns/pF
V
80
℃
500
V
uA
Phase Locked Loop
Block Descriptions
FO
R
There are total 14 PLLs in PLL macro, providing several clocks for CPU, BUS, modem, analog
modem, MSDC, LVDS, HDMI and image-sensor. ARMPLL provides around 1.2GHz clock for ARM
Cortex-A15. MAINPLL provides around 806MHz clock for bus and most of the function modules.
MMPLL provides around 286MHz clock for VENC and MFG. ISPPLL is the clock source of image
sense processing, which ranges from 104 to 208MHz for supporting various image sensors. UNIVPLL
provides 48MHz for USBPHY. MSDCPLL provides around 208MHz as the clock source of MSDC
module. TVDPLL provides 27/54/148.5MHz clock for the TV encoder and HDMI bridge. LVDSPLL
provides 20 ~ 75MHz clock for LVDS bridge and DPI interface. MDPLL1 and MDPLL2 are the main
clock source of dual-talk modem, providing a fixed 416MHz from different clock squarers for further
clock division. WPLL is a fractional PLL which multiplies clock 26MHz to 245.76MHz for HSPA.
WHPLL provides a fixed 250.25MHz for 3G HSPA. MCUPLL1 and MCUPLL2 provide around 481MHz
for ARM Cortex-R4, FD216 and bus.
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/M
/M
External
of PLL
Internal
of PLL
/M
Analog Special
Divider
MT6589 MDPLL1
MT6589 MDPLL2
CLKSQ1
CLKSQ2
AD_SYS_26M_CK
PAD_CLK26M_1
CLKSQ
26MHz
PAD_CLK26M_2
AD_MDSYS1_26M_CK
CLKSQ
26MHz
AD_MDSYS2_26M_CK
AD_MEM_26M_CK
RG_CLKSQ1_EN
AD_MIPI_26M_CK
MDPLL1
Bias / LDO
Bias / LDO
MD_PLL
/2
(832MHz)
MT6589 PLLGP
MDPLL2
MD_PLL
AD_MDPLL1_416M_CK
/2
(832MHz)
To BBTRX
To BBTRX
NS_MD832M_CKP
NS_MD832M_CKN
QS_MD832M_VSS
NS_MD832M_CKP
NS_MD832M_CKN
QS_MD832M_VSS
MODEM
WPLL
Bias / LDO
RG_CLKSQ2_EN
SDM_PLL
(1966.08MHz)
/4
/2
MODEM
MCUPLL2
SDM_PLL
AD_WPLL_245P76M_CK
(Hop 1924MHz)
AD_MDPLL2_416M_CK
/4
/2
AD_MCU2_H481M_CK
WHPLL
Test CKT
/4
LC_INT_PLL
(1001MHz)
/4
AD_WHPLL_250P25M_CK
/4
AD_MCU1_H481M_CK
+
-
MT6589
Technical Brief
Confidential A
MCUPLL1
SDM_PLL
(Hop 1924MHz)
DA_CPU_CK_MON
UNIVPLL
/2
/3
/5
/7
LC_INT_PLL
(1248MHz)
/26
MAINPLL
SDM_PLL
(Hop 1612MHz)
/1
/2
/3
/5
/7
AD_UNIV_624M_CK
AD_UNIV_416M_CK
AD_UNIV_249P6M_CK
AD_UNIV_178P3M_CK
AD_UNIV_48M_CK
AD_USB_48M_CK
AD_MAIN_H806M_CK
AD_MAIN_H537P3M_CK
AD_MAIN_H322P4M_CK
AD_MAIN_H230P3M_CK
ARMPLL
SDM_PLL
(Hop 1300MHz)
/1
AD_ARM_H1300M_CK
MMPLL
/2
/3
/5
/7
AD_MM_DIV2_CK
AD_MM_DIV3_CK
AD_MM_DIV5_CK
/4
/2
AD_MSDC_H208M_CK
/4
/2
/4
/8
/16
AD_TVD_H148P5M_CK
/4
/2
AD_LVDS_H180M_CK
/4
/2
LC_INT_PLL
(1430MHz)
AD_MM_DIV7_CK
MSDCPLL
SDM_PLL
(Hop 1664MHz)
TVDPLL
SDM_PLL
(Hop 2376MHz)
LVDSPLL
SDM_PLL
(Hop 1440MHz)
ISPPLL
LC_INT_PLL
(1664MHz)
125MHz ~ 312.5MHz
AD_ISP_208M_CK
Back-up for special sensor
Figure 2-12: Block diagram of PLL
See the table below for the function specifications of PLL.
Table 2-17: ARMPLL specifications
Symbol
Fin
Fout
Parameter
Settling time
Output clock duty cycle
FO
R
DVDD
Output clock jitter (period jitter)
Min.
Typ.
Max.
Unit
1,508
MHz
MHz
53
us
%
1.15
ps
V
26
754
47
20
50
0.95
30
1.05
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Symbol
AVDD
Parameter
Analog power supply
Min.
Typ.
1.7
1.8
Max.
Unit
V
1.9
T
Current consumption
-20
80
°C
mA
1
uA
1.2
Power-down current consumption
Table 2-18: MAINPLL specifications
Symbol
Fin
Fout
Parameter
Min.
Typ.
Max.
26
Unit
MHz
Settling time
500
806
20
884
MHz
us
47
0.95
50
60
1.05
53
DVDD
1.15
%
ps
V
AVDD
T
Analog power supply
1.7
-20
1.9
80
V
°C
1
mA
uA
Typ.
Max.
Unit
26
286
338
MHz
MHz
Settling time
53
us
%
1.15
ps
V
1.9
80
V
°C
1
mA
uA
Max.
Unit
Current consumption
1.8
0.8
Table 2-19: MMPLL specifications
Symbol
Fin
Fout
Parameter
Min.
47
20
50
DVDD
0.95
60
1.05
AVDD
T
Analog power supply
1.7
-20
Current consumption
1.8
0.8
Table 2-20: ISPPLL specifications
Symbol
Fin
Fout
DVDD
AVDD
FO
R
T
Parameter
Min.
26
Settling time
104
47
Analog power supply
0.95
1.7
-20
Typ.
MHz
208
MHz
us
50
60
53
%
ps
1.05
1.8
1.15
1.9
V
V
80
°C
20
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Symbol
Parameter
Min.
Current consumption
Typ.
Max.
0.8
Unit
mA
1
uA
Table 2-21: UNIVPLL specifications
Symbol
Fin
Fout
Parameter
Settling time
Min.
Typ.
Max.
Unit
N/A
26
624
N/A
MHz
MHz
55
us
%
1.15
ps
V
1.9
80
V
°C
1
mA
uA
Max.
Unit
45
20
50
DVDD
0.95
60
1.05
AVDD
T
Analog power supply
1.7
-20
Current consumption
1.8
0.8
Table 2-22: MSDCPLL specifications
Symbol
Fin
Fout
DVDD
AVDD
T
Parameter
Min.
Typ.
26
208
MHz
MHz
Settling time
45
20
50
60
55
us
%
ps
Analog power supply
0.95
1.7
1.05
1.8
1.15
1.9
V
V
Current consumption
-20
80
°C
mA
1
uA
0.8
Table 2-23: TVDPLL specifications
Symbol
Fin
Fout
Parameter
Min.
Settling time
DVDD
AVDD
T
Max.
Unit
26
MHz
148.5
20
MHz
us
45
50
60
55
%
ps
Analog power supply
0.95
1.7
1.05
1.8
1.15
1.9
V
V
Current consumption
-20
80
°C
mA
1
uA
0.8
FO
R
Typ.
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Table 2-24: LVDSPLL specifications
Symbol
Fin
Fout
Parameter
Min.
Typ.
Max.
26
75
Settling time
Unit
MHz
MHz
45
20
50
55
us
%
60
1.05
1.15
ps
V
1.9
80
V
°C
1
mA
uA
Max.
Unit
DVDD
0.95
AVDD
T
Analog power supply
1.7
-20
Current consumption
1.8
0.8
Table 2-25: MDPLL1 & MDPLL2 specifications
Symbol
Fin
Fout
DVDD
AVDD
T
Parameter
Min.
Typ.
Settling time
N/A
416
100
N/A
MHz
us
47
50
30
53
%
ps
Analog power supply
0.95
1.7
1.05
1.8
1.15
1.9
V
V
Current consumption
-20
80
°C
mA
1
uA
Max.
Unit
26
MHz
2.5
Table 2-26: WPLL specifications
Symbol
Fin
Fout
DVDD
AVDD
T
Parameter
Min.
Typ.
Settling time
N/A
245.76
20
N/A
MHz
us
47
50
60
53
%
ps
Analog power supply
0.95
1.7
1.05
1.8
1.15
1.9
V
V
Current consumption
-20
80
1
°C
mA
uA
Max.
Unit
26
MHz
0.8
Table 2-27: WHPLL specifications
Symbol
FO
R
Fin
Parameter
Min.
Typ.
26
MHz
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Symbol
Fout
DVDD
AVDD
T
Min.
Typ.
Max.
Unit
Parameter
N/A
250.25
N/A
MHz
Settling time
47
20
50
60
53
us
%
ps
Analog power supply
0.95
1.7
1.05
1.8
1.15
1.9
V
V
Current consumption
-20
80
°C
mA
1
uA
0.8
Table 2-28: MCUPLL1 & MCUPLL2 specifications
Symbol
Fin
Fout
Parameter
Min.
T
Unit
MHz
Settling time
481
20
MHz
us
47
50
60
53
%
ps
Analog power supply
0.95
1.7
1.05
1.8
1.15
1.9
V
V
Current consumption
-20
80
°C
mA
1
uA
2
2.5.9
Max.
26
DVDD
AVDD
Typ.
Temperature Sensor
2.5.9.1
Block Descriptions
In order to monitor the temperature of CPUs, several temperature sensors are provided. The
temperature sensor is made of substrate BJT in the CMOS process. The voltage output of
temperature sensor is measured by AUXADC.
2.5.9.2
See the table below for the function specifications of temperature sensor.
Table 2-29: Temperature sensor specifications
Symbol
Parameter
Min.
Resolution
Temperature range
Accuracy
FO
R
Max.
0.15
0
-5
Active current
Quiescent current
Typ.
Unit
°C
85
5
300
3
°C
°C
uA
uA
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MT6589
Technical Brief
Confidential A
2.6
Package Information
2.6.1
Package Outlines
Figure 2-13: Outlines and dimensions of FCCSP 11.8mm*11.8mm, 515-ball, 0.4mm pitch
package
2.6.2
Thermal Operating Specifications
Table 2-30: Thermal operating specifications
Symbol
Description
Maximum operating junction temperature
Package thermal resistances in nature convection
2.6.3
Value
Unit
125
29.55
°C
°C/Watt
Notes
Lead-free Packaging
FO
R
MT6589 is provided in a lead-free package and meets RoHS requirements.
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Technical Brief
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2.7
Ordering Information
2.7.1
Top Marking Definition
MTXXXXXX
%:
MT6589 %K
DDDD - ####
LLLLL
DDDD:
####:
LLLLL:
S:
Part No.
W : WCDMA
T : TD-SCDMA
E : Edge
Date Code
Subcontractor Code
Die Lot No.
Special Code
FO
R
Figure 2-14: Top mark of MT6589
Page 53 of 53

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