iMX6 Rex Module - Schematic

Transcription

1
2
3
4
5
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iMX6 Rex Module
A
7
8
27. 9. 2013
V1I1
Variant: Prototype
A
RELEASED 27-SEP-2013
B
B
Page
C
Index
Page
Index
Page
Index
Page
Index
1
COVER PAGE
11
CPU - POWER
21
............................................
31
............................................
2
BLOCK DIAGRAM
12
CPU - UNUSED
22
............................................
32
............................................
3
CONNECTORS
13
ETHERNET PHY
23
............................................
33
............................................
4
CPU - DDR3, DDR3 MEM
14
SPI FLASH, LEDS
24
............................................
34
............................................
5
CPU - SATA, PCIe
15
PWR 3V3, 1V375, 3V0_ALWAYS
25
............................................
35
............................................
6
CPU - HDMI, LVDS
16
PWR 2V5, 1V5
26
............................................
36
............................................
7
CPU - USB, ETHERNET
17
MECH
27
............................................
37
............................................
8
CPU - SPI, I2C, SD, MMC
18
POWER SEQUENCING
28
............................................
38
............................................
9
CPU - UART, AUDIO
19
DOC REVISION HISTORY
29
............................................
39
............................................
CPU - JTAG, CONTROL
20
............................................
30
............................................
40
............................................
10
C
DESIGN NOTE:
Example text for debug notes.
TOP VIEW
DESIGN CONSIDERATIONS
DESIGN NOTE:
Example text for informational
design notes .
BOTTOM VIEW
DESIGN NOTE:
Example text for critical
design notes.
Hardware design courses
http://www.fedevel.com/academy/
(c) 2013 FEDEVEL www.fedevel.com
D
DESIGN NOTE:
Example text for cautionary
design notes.
LAYOUT NOTE:
Example text for critical
layout guidelines.
CONFIDENTAL. Do not distribute.
Variant:
Title:
iMX6 Rex Module
Page Contents:
[01] - COVER PAGE.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
Size:
DWG NO
Date:
27. 9. 2013
7
V1I1
Sheet
of
1
8
20
D
1
2
3
4
5
6
7
8
iMX6 Rex Module
(Block Diagram)
A
A
Input Voltage: 7~24V (DC)
POWERS
Page 15
Pages 4 - 12
Page 13
Page 3
ETHERNET PHY
RGMII
Page 15
Ethernet PHY, LEDs
BOARD CONNECTOR 1
PMIC 1
(10/100/1000 Mbps)
1x HDMI
PMIC 2
1x SD card (SD3)
1x SPI2
Page 16
B
1x USB OTG
PMIC 3
1x full UART1 (or 2x RX, TX, RTS, CTS UART1 and UART3)
1x I2C4
B
ON/OFF, RESET_IN, RESET_OUT
Page 4
DDR3 MEMORIES
DDR3
(DDR3-1066 / Up to 4GB)
CPU
Page 3
(Freescale iMX6)
C
SPI3
1x LVDS0
(Up to 32MB)
1x MMC card (SD2)
1x SATA
1x PCIE
USER LED
1x USB HOST
(ORANGE)
1x UART2
JTAG
POWER LED
C
(Optional)
SPI FLASH
BOARD CONNECTOR 2
Digital audio
Page 14
http://www.iMX6Rex.com
(GREEN)
D
FREE for non-commercial use
Contact FEDEVEL for commercial use
Variant:
Title:
iMX6 Rex Module
Page Contents:
[02] - BLOCK DIAGRAM.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
Size:
DWG NO
Date:
27. 9. 2013
7
V1I1
Sheet
of
2
8
20
D
1
2
3
4
5
6
7
8
CONNECTORS
A
A
DESIGN NOTE:
Input voltage range (VIN) is: from +6 to +24V (DC)
+VIN
PIJ1063 PIJ1064
COC2
C2
10uF
35V
*1
PORSTOUTn
PORSTOUTN
10
RSTOUTn
POUART10DSR
9 UART1_DSR
POUART10CTS
9 UART1_CTS
POUART10RTS
9 UART1_RTS
POUART10DTR
9 UART1_DTR
POCSPI20CLK
8 CSPI2_CLK
POCSPI20CS0
8 CSPI2_CS0
POCSPI20MISO
8 CSPI2_MISO
POCSPI20MOSI
8 CSPI2_MOSI
POSD30WP
8 SD3_WP
POSD30CLK
8 SD3_CLK
POSD30DATA0
8 SD3_DATA0
POSD30DATA2
8 SD3_DATA2
POSD30CMD
8 SD3_CMD
POI2C40SCL
8 I2C4_SCL
POI2C40SDA
8 I2C4_SDA
POHDMI0D00N
6 HDMI_D0_N
POHDMI0D00P
6 HDMI_D0_P
POHDMI0HPD
6 HDMI_HPD
POHDMI0CLK0N
6 HDMI_CLK_N
POHDMI0CLK0P
6 HDMI_CLK_P
POTRD10N
13
TRD1_N
POTRD10P
13
TRD1_P
POENET0LED0RX
13
ENET_LED_RX
POTRD00N
13
TRD0_N
POTRD00P
13
TRD0_P
1
3
PIJ103
5
PIJ105
7
PIJ107
9
PIJ109
11
PIJ1011
13
PIJ1013
15
PIJ1015
17
PIJ1017
19
PIJ1019
21
PIJ1021
23
PIJ1023
25
PIJ1025
27
PIJ1027
29
PIJ1029
31
PIJ1031
33
PIJ1033
35
PIJ1035
37
PIJ1037
39
PIJ1039
41
PIJ1041
43
PIJ1043
45
PIJ1045
47
PIJ1047
49
PIJ1049
51
PIJ1051
53
PIJ1053
55
PIJ1055
57
PIJ1057
59
PIJ101
PIJ1059
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
62
PIJ106 PIJ1062
PIJ2064 PIJ2063
64
63
PIC201
PIC202
COJ1
J1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
PIJ104
6
!ALWAYS POWERED!
PIJ106
POON0OFF
ON_OFF 10
8
NLRSTINn
RSTINn
PIJ108
PORSTINn
PORSTINN
RSTINn 10
10
PIJ1010
POUART10RI
UART1_RI 9
12
PIJ1012
POUART10TXD
UART1_TXD 9
DESIGN NOTE:
14
PIJ1014
POUART10RXD
UART1_RXD 9
I2C1 is used with AUDIO
16
+5V_USB_VBUS
PIJ1016
POUART10DCD
UART1_DCD 9
18
PIJ1018
20
PIC24201
PIJ1020
POUSB00ID
USB0_ID 7
COC242
C242
22
PIJ1022
POUSB00N
USB0_N 7
100n
24
PIC24202
PIJ1024
POUSB00P
USB0_P 7
26
PIJ1026
POUSB00PWR0EN
USB0_PWR_EN 7
28
PIJ1028
POUSB0OC
USB_OC 7
30
PIJ1030
POSD30DATA1
SD3_DATA1 8
32
PIJ1032
POSD30DATA3
SD3_DATA3 8
34
PIJ1034
POSD30CD
SD3_CD 8
DESIGN NOTE:
36
PIJ1036
POI2C20SCL
I2C2_SCL 6
BOOT MODE: !ALWAYS POWERED!
38
PIJ1038
POI2C20SDA
I2C2_SDA 6
connect to ground to boot from serial downloader,
40
PIJ1040
POHDMI0D20N
HDMI_D2_N 6
left unconnected to boot from e-fuses.
42
PIJ1042
POHDMI0D20P
HDMI_D2_P 6
44
PIJ1044
POHDMI0CEC0IN
HDMI_CEC_IN 6
46
+3V3(Output)
PIJ1046
POHDMI0D10N
HDMI_D1_N 6
48
PIJ1048
POHDMI0D10P
HDMI_D1_P 6
DESIGN NOTE:
50
*1
PIJ1050
POBOOT0MODE
BOOT_MODE 10
Test function of BOOT MODE.
52
PIJ1052
POTRD30N
TRD3_N 13
54
PIC101
PIJ1054
POTRD30P
TRD3_P 13
C1
COC1
56
PIJ1056
POENET0LED0LINK
ENET_LED_LINK 13
1u
58
PIC102
PIJ1058
POTRD20N
TRD2_N 13
60
PIJ1060
POTRD20P
TRD2_P 13
PIJ102
6POLVDS00TX00N
LVDS0_TX0_N
6POLVDS00TX00P
LVDS0_TX0_P
6POLVDS00CABC
LVDS0_CABC
6POLVDS00TX10N
LVDS0_TX1_N
6POLVDS00TX10P
LVDS0_TX1_P
9POI2C10SDA
I2C1_SDA
9POI2C10SCL
I2C1_SCL
9POAUD30TXC
AUD3_TXC
9POAUD30TXD
AUD3_TXD
9POAUD30CLK
AUD3_CLK
9POAUD30RXD
AUD3_RXD
9POAUD30TXFS
AUD3_TXFS
8POSD20DATA0
SD2_DATA0
8POSD20DATA2
SD2_DATA2
8POSD20DATA4
SD2_DATA4
8POSD20DATA6
SD2_DATA6
8POSD20WP
SD2_WP
8POSD20CLK
SD2_CLK
8POSD20CD
SD2_CD
7POUSB10N
USB1_N
7POUSB10P
USB1_P
7POUSB10PWR0EN
USB1_PWR_EN
5POCLK10N
CLK1_N
5POCLK10P
CLK1_P
5POPCIE0RX0N
PCIE_RX_N
5POPCIE0RX0P
PCIE_RX_P
5POSATA0RX0N
SATA_RX_N
5POSATA0RX0P
SATA_RX_P
2
4
PIJ204
6
PIJ206
8
PIJ208
10
PIJ2010
12
PIJ2012
14
PIJ2014
16
PIJ2016
18
PIJ2018
20
PIJ2020
22
PIJ2022
24
PIJ2024
26
PIJ2026
28
PIJ2028
30
PIJ2030
32
PIJ2032
34
PIJ2034
36
PIJ2036
38
PIJ2038
40
PIJ2040
42
PIJ2042
44
PIJ2044
46
PIJ2046
48
PIJ2048
50
PIJ2050
52
PIJ2052
54
PIJ2054
56
PIJ2056
58
PIJ2058
60
PIJ202
PIJ2060
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
GND
GND
COC241
C241
10uF
35V
63
64
PIC24101
PIC24102
GND
GND
COC240
C240
100n
GND
GND
DESIGN NOTE:
*1 Be careful during
debugging phase - this pin is
connected to +3V0_ALWAYS.
PIC240 1
PIC240 2
PIJ206 PIJ2061
QSH-030-01-L-D-A
62
61
DESIGN NOTE:
UART1 signals DSR, DTR, DCD and
RI can be used as UART3.
B
COC239
C239
100n
GND
GND
PIC23901
PIC23902
+VIN
COJ2
J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1
3
PIJ203
5
PIJ205
7
PIJ207
9
PIJ209
11
PIJ2011
13
PIJ2013
15
PIJ2015
17
PIJ2017
19
PIJ2019
21
PIJ2021
23
PIJ2023
25
PIJ2025
27
PIJ2027
29
PIJ2029
31
PIJ2031
33
PIJ2033
35
PIJ2035
37
PIJ2037
39
PIJ2039
41
PIJ2041
43
PIJ2043
45
PIJ2045
47
PIJ2047
49
PIJ2049
51
PIJ2051
53
PIJ2053
55
PIJ2055
57
PIJ2057
59
PIJ201
PIJ2059
POLVDS00TX20N
LVDS0_TX2_N 6
POLVDS00TX20P
LVDS0_TX2_P 6
POLVDS00PWM
LVDS0_PWM 6
POLVDS00TX30N
LVDS0_TX3_N 6
POLVDS00TX30P
LVDS0_TX3_P 6
POSD20ACT
SD2_ACT 8
POLVDS00CLK0N
LVDS0_CLK_N 6
POLVDS00CLK0P
LVDS0_CLK_P 6
POI2C30SDA
I2C3_SDA 6, 8
POI2C30SCL
I2C3_SCL 6, 8
POSD20CMD
SD2_CMD 8
POSD20DATA1
SD2_DATA1 8
POSD20DATA3
SD2_DATA3 8
POSD20DATA5
SD2_DATA5 8
POSD20DATA7
SD2_DATA7 8
POUART20CTS
UART2_CTS 9
POUART20RTS
UART2_RTS 9
POUART20RXD
UART2_RXD 9
POUART20TXD
UART2_TXD 9
POPCIE0WAKE
PCIE_WAKE 5
POJTAG0nTRST
POJTAG0NTRST
JTAG_nTRST 10
POJTAG0TCK
JTAG_TCK 10
POJTAG0TDO
JTAG_TDO 10
POJTAG0TDI
JTAG_TDI 10
POJTAG0TMS
JTAG_TMS 10
POPCIE0TX0N
PCIE_TX_N 5
POPCIE0TX0P
PCIE_TX_P 5
B
DESIGN NOTE:
I2C3 is used with LVDS
DESIGN NOTE:
In reference design I2C3 uses
LVDS1. Software changes
may be required.
POSATA0TX0N
SATA_TX_N 5
POSATA0TX0P
SATA_TX_P 5
QSH-030-01-L-D-A
DESIGN NOTE:
Connector:
1.0A per contact, 7.8A ground plane
DESIGN NOTE:
Mating connector: QTH-030-02-L-D-A
http://www.digikey.com/product-detail/en/QT
H-030-02-L-D-A/SAM8186-ND/1106530
DESIGN NOTE:
3V3 output. Max. 1A (Can be used on Base
board)
C
C
DESIGN NOTE:
If required, use Pin 49 on Connector 1 for
Ethernet Tap Voltage.
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[03] - CONNECTORS.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
3
of
20
D
1
2
3
4
5
6
7
8
CPU - DDR3, DDR3 MEM
Clock terminators: Place at end of route at each DDR pair
C
ClassName: DRAM_BANK6
Net Class i
Net Class i
AC22
PIU10AC22
AE22
PIU10AE22
AE24
PIU10AE24
AC24
PIU10AC24
AB22
PIU10AB22
AC23
PIU10AC23
AD25
PIU10AD25
AC25
PIU10AC25
DIFF100 AD23
PIU10AD23
DIFF100 AE23
PIU10AE23
AD24
DRAM_D56
NLDRAM0D56
DRAM_D57
NLDRAM0D57
DRAM_D58
NLDRAM0D58
DRAM_D59
NLDRAM0D59
DRAM_D60
NLDRAM0D60
DRAM_D61
NLDRAM0D61
DRAM_D62
NLDRAM0D62
DRAM_D63
NLDRAM0D63
DRAM_DQS7_P
NLDRAM0DQS70P
DRAM_DQS7_N
NLDRAM0DQS70N
DRAM_DQM7
NLDRAM0DQM7
AB25
PIU10AB25
AA21
PIU10AA21
Y25
PIU10Y25
Y22
PIU10Y22
AB23
PIU10AB23
AA23
PIU10AA23
Y23
PIU10Y23
W25
PIU10W25
DIFF100 AA25
PIU10AA25
DIFF100 AA24
PIU10AA24
Y21
PIU10AD24
PIU10Y21
DRAM_D56
DRAM_D57
DRAM_D58
DRAM_D59
DRAM_D60
DRAM_D61
DRAM_D62
DRAM_D63
DRAM_SDQS7
DRAM_SDQS7
DRAM_DQM7
M8
VREFCA
H1
PIU20H1 VREFDQ
PIC301
PIC302
Y11
DRAM_SDCKE0 PIU10Y11
AA11
DRAM_SDCKE1 PIU10AA11
NLDRAM0SDCKE0
DRAM_SDCKE0
AC16
DRAM_SDODT0 PIU10AC16
AB17
DRAM_SDODT1 PIU10AB17
NLDRAM0SDODT0
DRAM_SDODT0
PIR602
PIC401
PIC402
COC3
C3
220n
COC4
C4
220n
DRAM_DQM1
DRAM_DQM0
E7
LDM
D3
PIU20D3 UDM
PIU20E7
NLDRAM10ZQ
DRAM1_ZQ
DRAM_SDODT0
+DDR_VREF
PIU20M8
PIC501
PIC502
DRAM_A15
DRAM_A14
PIU30J1
M8
VREFCA
H1
PIU30H1 VREFDQ
PIU30M8
PIC601
PIC602
COC5
C5
220n
DRAM_DQM2
DRAM_DQM3
COC6
C6
220n
E7
LDM
D3
PIU30D3 UDM
PIU30E7
PIU20A9 PIU20B3 PIU20E1 PIU20G8 PIU20J PIU20J8 PIU20M1 PIU20M9 PIU20P1 PIU20P9 PIU20T1 PIU20T9 PIU20B1 PIU20B9 PIU20D1 PIU20D8 PIU20E PIU20E8 PIU20F9 PIU20G1 PIU20G9
COR6
R6
10k
A1
A8
C1
C9
D2
E9
F1
H2
H9
L8
ZQ
K1
PIU30K1 ODT
PIU30L8
J1
J9
PIU30J9
L1
PIU30L1
L9
PIU30L9
M7
PIU30M7
T7
PIU30T7
NC_J1
NC_J9
NC_L1
NC_L9
NC_M7
NC_T7
PIU30J7
B
PIU30A9 PIU30B PIU30E1 PIU30G8 PIU30J2 PIU30J8 PIU30M1 PIU30M9 PIU30P1 PIU30P9 PIU30T1 PIU30T9 PIU30B1 PIU30B9 PIU30D1 PIU30D8 PIU30E2 PIU30E8 PIU30F9 PIU30G1 PIU30G9
PIR601
DRAM_RESET
Y6
NLDRAM0RESET0B
DRAM_RESET_B
PIU10Y6
COR7
R7
10k
PIR702
DRAM_SDCLK_0
DRAM_SDCLK_0
DRAM_SDCLK_1
DRAM_SDCLK_1
AD15
AE15
PIU10AE15
DIFF100
DIFF100
PIU10AD15
AD14
AE14
DIFF100
DIFF100
PIU10AD14
PIU10AE14
DRAM_D[63..0]
PIU40B2 PIU40D9 PIU40G7 PIU40K2 PIU40K8 PIU40N1 PIU40N9 PIU40R1 PIU40R9 PIU40A1 PIU40A8 PIU40C1 PIU40C9 PIU40D2 PIU40E9 PIU40F1 PIU40H2 PIU40H9
DRAM_CLK0_P
DRAM_CLK0_N
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_CLK1_P
DRAM_CLK1_N
ClassName: DRAM_SDCLK
+DDR_VREF
DRAM_VREF
C7
COC7
100n
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
AC2
PIU10AC2
R10
COR10
PIR1001
ZQPAD
AE17
+1V5_DDR
NVCC_DRAM_1
NVCC_DRAM_2
NVCC_DRAM_3
NVCC_DRAM_4
NVCC_DRAM_5
NVCC_DRAM_6
NVCC_DRAM_7
NVCC_DRAM_8
NVCC_DRAM_9
NVCC_DRAM_10
NVCC_DRAM_11
NVCC_DRAM_12
NVCC_DRAM_13
R18
PIU10R18
T18
PIU10T18
U18
PIU10U18
V10
PIU10V10
V11
PIU10V11
V12
PIU10V12
V13
PIU10V13
V14
PIU10V14
V15
PIU10V15
V16
PIU10V16
V17
PIU10V17
V18
PIU10V18
V9
PIU10V9
R8
COR8
PIR1002
PIR801
240R
ZQPAD
NLZQPAD
PIU10AE17
DRAM_D[63..0]
+1V5_DDR
i
Net Class
PIC701
PIC702
+1V5_DDR
DRAM_A[15..0]
PIR701
DRAM_A[15..0]
DRAM_D40
DRAM_D41
DRAM_D42
DRAM_D43
DRAM_D44
DRAM_D45
DRAM_D46
DRAM_D47
DRAM_SDQS5
DRAM_SDQS5
DRAM_DQM5
DRAM_D48
DRAM_D49
DRAM_D50
DRAM_D51
DRAM_D52
DRAM_D53
DRAM_D54
DRAM_D55
DRAM_SDQS6
DRAM_SDQS6
DRAM_DQM6
DRAM_A15
DRAM_A14
DRAM_DQS3_P
DRAM_DQS3_N
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
DRAM_D48
NLDRAM0D48
DRAM_D49
NLDRAM0D49
DRAM_D50
NLDRAM0D50
DRAM_D51
NLDRAM0D51
DRAM_D52
NLDRAM0D52
DRAM_D53
NLDRAM0D53
DRAM_D54
NLDRAM0D54
DRAM_D55
NLDRAM0D55
DRAM_DQS6_P
NLDRAM0DQS60P
DRAM_DQS6_N
NLDRAM0DQS60N
DRAM_DQM6
NLDRAM0DQM6
PIU10AC20
240R
J7
CK
K7
PIU30K7 CK
K9
PIU30K9 CKE
T2
PIU30T2 RESET
C7
B7
PIU30B7
DRAM_CLK0_P
DRAM_CLK0_N
DRAM_SDCKE0
DRAM_RESET_B
PIR802
240R
i
Net Class
DRAM2_ZQ
NLDRAM20ZQ
DRAM_SDODT0
+DDR_VREF
ClassName: DRAM_OTHERS
N3
P7
PIU40P7
P3
PIU40P3
N2
PIU40N2
P8
PIU40P8
P2
PIU40P2
R8
PIU40R8
R2
PIU40R2
T8
PIU40T8
R3
PIU40R3
L7
PIU40L7
R7
PIU40R7
N7
PIU40N7
T3
PIU40T3
M2
PIU40M2
N8
PIU40N8
M3
PIU40N3
PIU40M3
PIC901
PIC902
C8
COC8
220n
DRAM_DQM7
DRAM_DQM6
LDQS
LDQS
E3
F7
PIU40F7
F2
PIU40F2
F8
PIU40F8
H3
PIU40H3
H8
PIU40H8
G2
PIU40G2
H7
PIU40H7
D7
PIU40D7
C3
PIU40C3
C8
PIU40C8
C2
PIU40C2
A7
PIU40A7
A2
PIU40A2
B8
PIU40B8
A3
PIU40E3
PIU40A3
F3
PIU40F3
G3
PIU40G3
C7
UDQS PIU40C7
B7
UDQS PIU40B7
Top left
DRAM_D56
DRAM_D59
DRAM_D61
DRAM_D62
DRAM_D60
DRAM_D63
DRAM_D57
DRAM_D58
DRAM_D48
DRAM_D50
DRAM_D53
DRAM_D49
DRAM_D52
DRAM_D55
DRAM_D51
DRAM_D54
L8
PIU40L8
K1
PIU40K1
CK
CK
CKE
RESET
NC_J1
NC_J9
NC_L1
NC_L9
NC_M7
NC_T7
ZQ
ODT
J1
PIU40J1
J9
PIU40J9
L1
PIU40L1
L9
PIU40L9
M7
PIU40M7
T7
DRAM_DQS7_P
DRAM_DQS7_N
PIU40T7
PIR901
PIU50M3
DRAM3_ZQ
NLDRAM30ZQ
DRAM_SDODT0
+DDR_VREF
J7
PIU50J7
K7
PIU50K7
K9
PIU50K9
T2
PIU50T2
L8
PIU50L8
K1
PIU50K1
M8
PIC10 1
PIC10 2
PIC1 01
PIC1 02
C10
COC10
220n
PIU50M8
H1
PIU50H1
C11
COC11
220n
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
E7
DRAM_DQM4
DRAM_DQM5
PIU50E7
D3
PIU50D3
COU5
U5
MT41J128M16HA-15E:D TR
PIU50E3
LDQS
LDQS
PIU50F3
G3
PIU50G3
UDQS
UDQS
PIU50C7
B7
PIU50B7
NC_J1
NC_J9
NC_L1
NC_L9
NC_M7
NC_T7
PIU50J1
J9
PIU50J9
L1
PIU50L1
L9
PIU50L9
M7
PIU50M7
T7
PIU50T7
Bottom left
CK
CK
CKE
RESET
ZQ
ODT
E3
F7
PIU50F7
F2
PIU50F2
F8
PIU50F8
H3
PIU50H3
H8
PIU50H8
G2
PIU50G2
H7
PIU50H7
D7
PIU50D7
C3
PIU50C3
C8
PIU50C8
C2
PIU50C2
A7
PIU50A7
A2
PIU50A2
B8
PIU50B8
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2G_DDR3_SDRAM_128MX16
L2
PIU50L2 CS
J3
PIU50J3 RAS
K3
PIU50K3 CAS
L3
PIU50L3 WE
DRAM_CLK0_P
DRAM_CLK0_N
DRAM_SDCKE0
DRAM_RESET_B
PIR902
240R
VREFCA
VREFDQ
E7
PIU40E7 LDM
D3
PIU40D3 UDM
PIU50N3
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
DRAM_DQS6_P
DRAM_DQS6_N
DRAM_A15
DRAM_A14
N3
P7
PIU50P7
P3
PIU50P3
N2
PIU50N2
P8
PIU50P8
P2
PIU50P2
R8
PIU50R8
R2
PIU50R2
T8
PIU50T8
R3
PIU50R3
L7
PIU50L7
R7
PIU50R7
N7
PIU50N7
T3
PIU50T3
M2
PIU50M2
N8
PIU50N8
M3
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
R9
COR9
J7
PIU40J7
K7
PIU40K7
K9
PIU40K9
T2
PIU40T2
PIU40M8
H1
PIU40H1
C9
COC9
220n
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
L2
PIU40L2 CS
J3
PIU40J3 RAS
K3
PIU40K3 CAS
L3
PIU40L3 WE
M8
PIC801
PIC802
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
COU4
U4
A1
A8
C1
C9
D2
E9
F1
H2
H9
Y19
AB20
PIU10AB20
AB21
PIU10AB21
AD21
PIU10AD21
Y20
PIU10Y20
AA20
PIU10AA20
AE21
PIU10AE21
AC21
PIU10AC21
DIFF100 AD20
PIU10AD20
DIFF100 AE20
PIU10AE20
AC20
PIU10Y19
L8
ZQ
K1
PIU20K1 ODT
PIU20L8
DRAM_CLK1_P
DRAM_CLK1_N
DRAM_SDCKE0
DRAM_RESET_B
PIR502
DRAM_DQS2_P
DRAM_DQS2_N
PIU30C7
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
DRAM_D40
NLDRAM0D40
DRAM_D41
NLDRAM0D41
DRAM_D42
NLDRAM0D42
DRAM_D43
NLDRAM0D43
DRAM_D44
NLDRAM0D44
DRAM_D45
NLDRAM0D45
DRAM_D46
NLDRAM0D46
DRAM_D47
NLDRAM0D47
DRAM_DQS5_P
NLDRAM0DQS50P
DRAM_DQS5_N
NLDRAM0DQS50N
DRAM_DQM5
NLDRAM0DQM5
PIU10AB18
DRAM_D32
DRAM_D33
DRAM_D34
DRAM_D35
DRAM_D36
DRAM_D37
DRAM_D38
DRAM_D39
DRAM_SDQS4
DRAM_SDQS4
DRAM_DQM4
NC_J1
NC_J9
NC_L1
NC_L9
NC_M7
NC_T7
J1
PIU20J1
J9
PIU20J9
L1
PIU20L1
L9
PIU20L9
M7
PIU20M7
T7
PIU20T7
PIR501
F3
G3
PIU30G3
UDQS
UDQS
Bottom right
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
AA17
AA18
PIU10AA18
AC18
PIU10AC18
AE19
PIU10AE19
Y17
PIU10Y17
Y18
PIU10Y18
AB19
PIU10AB19
AC19
PIU10AC19
DIFF100 AD18
PIU10AD18
DIFF100 AE18
PIU10AE18
AB18
PIU10AA17
NLDRAM0RAS0B
DRAM_RAS_B
NLDRAM0CAS0B
DRAM_CAS_B
NLDRAM0WE0B
DRAM_WE_B
COR5
R5
J7
CK
K7
PIU20K7 CK
K9
PIU20K9 CKE
T2
PIU20T2 RESET
PIU20J7
PIU30F3
LDQS
LDQS
PIU50A3
DRAM_D32
DRAM_D39
DRAM_D37
DRAM_D34
DRAM_D36
DRAM_D38
DRAM_D33
DRAM_D35
DRAM_D40
DRAM_D47
DRAM_D45
DRAM_D42
DRAM_D43
DRAM_D44
DRAM_D41
DRAM_D46
F3
DRAM_DQS4_P
DRAM_DQS4_N
C7
DRAM_DQS5_P
DRAM_DQS5_N
C
J1
DRAM_A15
DRAM_A14
VREFCA
VREFDQ
LDM
UDM
PIU40A9 PIU40B3 PIU40E1 PIU40G8 PIU40J2 PIU40J8 PIU40M1 PIU40M9 PIU40P1 PIU40P9 PIU40T1 PIU40T9 PIU40B1 PIU40B9 PIU40D1 PIU40D8 PIU40E2 PIU40E8 PIU40F9 PIU40G1 PIU40G9
+1V5_DDR
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
Net Class i
DRAM_D32
NLDRAM0D32
DRAM_D33
NLDRAM0D33
DRAM_D34
NLDRAM0D34
DRAM_D35
NLDRAM0D35
DRAM_D36
NLDRAM0D36
DRAM_D37
NLDRAM0D37
DRAM_D38
NLDRAM0D38
DRAM_D39
NLDRAM0D39
DRAM_DQS4_P
NLDRAM0DQS40P
DRAM_DQS4_N
NLDRAM0DQS40N
DRAM_DQM4
NLDRAM0DQM4
DRAM_D24
DRAM_D25
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
DRAM_D30
DRAM_D31
DRAM_SDQS3
DRAM_SDQS3
DRAM_DQM3
AB15
DRAM_RAS PIU10AB15
AE16
DRAM_CAS PIU10AE16
AB16
DRAM_SDWE PIU10AB16
NLDRAM00ZQ
DRAM0_ZQ
DRAM_SDODT0
+DDR_VREF
DRAM_DQS0_P
DRAM_DQS0_N
PIU20C7
DRAM_D16
DRAM_D22
DRAM_D23
DRAM_D17
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D18
DRAM_D24
DRAM_D26
DRAM_D28
DRAM_D27
DRAM_D25
DRAM_D30
DRAM_D29
DRAM_D31
PIU30E3
L2
PIU30L2 CS
J3
PIU30J3 RAS
K3
PIU30K3 CAS
L3
PIU30L3 WE
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
E3
F7
PIU30F7
F2
PIU30F2
F8
PIU30F8
H3
PIU30H3
H8
PIU30H8
G2
PIU30G2
H7
PIU30H7
D7
PIU30D7
C3
PIU30C3
C8
PIU30C8
C2
PIU30C2
A7
PIU30A7
A2
PIU30A2
B8
PIU30B8
A3
PIU30A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
PIR1 02
PIU50A9 PIU50B3 PIU50E1 PIU50G8 PIU50J2 PIU50J8 PIU50M1 PIU50M9 PIU50P1 PIU50P9 PIU50T1 PIU50T9 PIU50B1 PIU50B9 PIU50D1 PIU50D8 PIU50E2 PIU50E8 PIU50F9 PIU50G1 PIU50G9
B1
B9
D1
D8
E2
E8
F9
G1
G9
AE9
PIU10AE9
Y10
PIU10Y10
AE11
PIU10AE11
AB11
PIU10AB11
AC9
PIU10AC9
AD9
PIU10AD9
AD11
PIU10AD11
AC11
PIU10AC11
DIFF100 AC10
PIU10AC10
DIFF100 AB10
PIU10AB10
AE10
PIU10AE10
NLDRAM0CS00B
DRAM_CS0_B
PIU10Y16
DRAM_CLK1_P
DRAM_CLK1_N
DRAM_SDCKE0
DRAM_RESET_B
C7
B7
PIU20B7
UDQS
UDQS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
Net Class i
NLDRAM0D24
DRAM_D24
NLDRAM0D25
DRAM_D25
NLDRAM0D26
DRAM_D26
NLDRAM0D27
DRAM_D27
NLDRAM0D28
DRAM_D28
NLDRAM0D29
DRAM_D29
NLDRAM0D30
DRAM_D30
NLDRAM0D31
DRAM_D31
NLDRAM0DQS30P
DRAM_DQS3_P
NLDRAM0DQS30N
DRAM_DQS3_N
DRAM_DQM3
NLDRAM0DQM3
Y16
AD17
PIU10AD17
DRAM_CS0
DRAM_CS1
PIR402
240R
DRAM_DQS1_P
DRAM_DQS1_N
PIU20F3
PIU30N3
B2
D9
G7
K2
K8
N1
N9
R1
R9
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_SDQS2
DRAM_SDQS2
DRAM_DQM2
COR4
R4
PIR401
Top right
F3
G3
PIU20G3
LDQS
LDQS
N3
P7
PIU30P7
P3
PIU30P3
N2
PIU30N2
P8
PIU30P8
P2
PIU30P2
R8
PIU30R8
R2
PIU30R2
T8
PIU30T8
R3
PIU30R3
L7
PIU30L7
R7
PIU30R7
N7
PIU30N7
T3
PIU30T3
M2
PIU30M2
N8
PIU30N8
M3
PIU30M3
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
Net Class i
AB7
AA8
PIU10AA8
AB9
PIU10AB9
Y9
PIU10Y9
Y7
PIU10Y7
Y8
PIU10Y8
AC8
PIU10AC8
AA9
PIU10AA9
DIFF100 AD8
PIU10AD8
DIFF100 AE8
PIU10AE8
AB8
PIU10AB8
PIU10AB7
NLDRAM0SDBA0
DRAM_SDBA0
NLDRAM0SDBA1
DRAM_SDBA1
NLDRAM0SDBA2
DRAM_SDBA2
L2
PIU20L2 CS
J3
PIU20J3 RAS
K3
PIU20K3 CAS
L3
PIU20L3 WE
DRAM_D8
DRAM_D9
DRAM_D13
DRAM_D14
DRAM_D12
DRAM_D15
DRAM_D10
DRAM_D11
DRAM_D0
DRAM_D5
DRAM_D2
DRAM_D4
DRAM_D7
DRAM_D6
DRAM_D1
DRAM_D3
PIU20E3
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
NLDRAM0D16
DRAM_D16
NLDRAM0D17
DRAM_D17
NLDRAM0D18
DRAM_D18
NLDRAM0D19
DRAM_D19
NLDRAM0D20
DRAM_D20
NLDRAM0D21
DRAM_D21
NLDRAM0D22
DRAM_D22
NLDRAM0D23
DRAM_D23
NLDRAM0DQS20P
DRAM_DQS2_P
NLDRAM0DQS20N
DRAM_DQS2_N
NLDRAM0DQM2
DRAM_DQM2
AC15
DRAM_SDBA0 PIU10AC15
Y15
DRAM_SDBA1 PIU10Y15
AB12
DRAM_SDBA2 PIU10AB12
DRAM_CS0_B
DRAM_RAS_B
DRAM_CAS_B
DRAM_WE_B
E3
F7
PIU20F7
F2
PIU20F2
F8
PIU20F8
H3
PIU20H3
H8
PIU20H8
G2
PIU20G2
H7
PIU20H7
D7
PIU20D7
C3
PIU20C3
C8
PIU20C8
C2
PIU20C2
A7
PIU20A7
A2
PIU20A2
B8
PIU20B8
A3
PIU20A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
B
DRAM_D8
DRAM_D9
DRAM_D10
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_SDQS1
DRAM_SDQS1
DRAM_DQM1
NLDRAM0A0
DRAM_A0
NLDRAM0A1
DRAM_A1
NLDRAM0A2
DRAM_A2
NLDRAM0A3
DRAM_A3
NLDRAM0A4
DRAM_A4
NLDRAM0A5
DRAM_A5
NLDRAM0A6
DRAM_A6
NLDRAM0A7
DRAM_A7
NLDRAM0A8
DRAM_A8
NLDRAM0A9
DRAM_A9
NLDRAM0A10
DRAM_A10
NLDRAM0A11
DRAM_A11
NLDRAM0A12
DRAM_A12
NLDRAM0A13
DRAM_A13
NLDRAM0A14
DRAM_A14
NLDRAM0A15
DRAM_A15
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
Net Class i
AD5
PIU10AD5
AE5
PIU10AE5
AA6
PIU10AA6
AE7
PIU10AE7
AB5
PIU10AB5
AC5
PIU10AC5
AB6
PIU10AB6
AC7
PIU10AC7
AD6
DIFF100 PIU10AD6
AE6
DIFF100 PIU10AE6
AC6
PIU10AC6
AC14
AB14
PIU10AB14
AA14
PIU10AA14
Y14
PIU10Y14
W14
PIU10W14
AE13
PIU10AE13
AC13
PIU10AC13
Y13
PIU10Y13
AB13
PIU10AB13
AE12
PIU10AE12
AA15
PIU10AA15
AC12
PIU10AC12
AD12
PIU10AD12
AC17
PIU10AC17
AA12
PIU10AA12
Y12
PIU10Y12
PIU10AC14
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
NLDRAM0D8
DRAM_D8
NLDRAM0D9
DRAM_D9
NLDRAM0D10
DRAM_D10
NLDRAM0D11
DRAM_D11
NLDRAM0D12
DRAM_D12
NLDRAM0D13
DRAM_D13
NLDRAM0D14
DRAM_D14
NLDRAM0D15
DRAM_D15
NLDRAM0DQS10P
DRAM_DQS1_P
NLDRAM0DQS10N
DRAM_DQS1_N
NLDRAM0DQM1
DRAM_DQM1
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
Net Class i
DRAM_D0
DRAM_D1
DRAM_D2
DRAM_D3
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_SDQS0
DRAM_SDQS0
DRAM_DQM0
B2
D9
G7
K2
K8
N1
N9
R1
R9
AD2
AE2
PIU10AE2
AC4
PIU10AC4
AA5
PIU10AA5
AC1
PIU10AC1
AD1
PIU10AD1
AB4
PIU10AB4
AE4
PIU10AE4
AE3
DIFF100 PIU10AE3
AD3
DIFF100 PIU10AD3
AC3
PIU10AC3
PIU10AD2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
Net Class i
NLDRAM0D0
DRAM_D0
NLDRAM0D1
DRAM_D1
NLDRAM0D2
DRAM_D2
NLDRAM0D3
DRAM_D3
NLDRAM0D4
DRAM_D4
NLDRAM0D5
DRAM_D5
NLDRAM0D6
DRAM_D6
NLDRAM0D7
DRAM_D7
NLDRAM0DQS00P
DRAM_DQS0_P
NLDRAM0DQS00N
DRAM_DQS0_N
NLDRAM0DQM0
DRAM_DQM0
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
B1
B9
D1
D8
E2
E8
F9
G1
G9
i.MX6Q - DDR
N3
P7
PIU20P7
P3
PIU20P3
N2
PIU20N2
P8
PIU20P8
P2
PIU20P2
R8
PIU20R8
R2
PIU20R2
T8
PIU20T8
R3
PIU20R3
L7
PIU20L7
R7
PIU20R7
N7
PIU20N7
T3
PIU20T3
M2
PIU20M2
N8
PIU20N8
M3
PIU20M3
PIU20N3
A
COU3
U3
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_SDBA0
DRAM_SDBA1
DRAM_SDBA2
DRAM_A[15..0]
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
COU1C
U1C
DRAM_D[63..0]
COU2
U2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
Net Class
i
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
ClassName: DRAM_ADDR_CTRL
B2
D9
G7
K2
K8
N1
N9
R1
R9
PIU20B PIU20D9 PIU20G7 PIU20K PIU20K8 PIU20N1 PIU20N9 PIU20R1 PIU20R9 PIU20A1 PIU20A8 PIU20C1 PIU20C9 PIU20D PIU20E9 PIU20F1 PIU20H PIU20H9
PIR301
NLDRAM0CLK10N
DRAM_CLK1_N
NLDRAM0D0630000
DRAM_D[63..0]
DRAM_D[63..0]
B1
B9
D1
D8
E2
E8
F9
G1
G9
PIR201
DRAM_A[15..0]
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
NLDRAM0CLK00N
DRAM_CLK0_N
A
COR3
R3
200R
B1
B9
D1
D8
E2
E8
F9
G1
G9
200R
A1
A8
C1
C9
D2
E9
F1
H2
H9
COR2
R2
+1V5_DDR
NLDRAM0A0150000
DRAM_A[15..0]
+1V5_DDR
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
PIR302
A1
A8
C1
C9
D2
E9
F1
H2
H9
NLDRAM0CLK10P
DRAM_CLK1_P
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
PIR202
B2
D9
G7
K2
K8
N1
N9
R1
R9
NLDRAM0CLK00P
DRAM_CLK0_P
+DDR_VREF
PIC1801
PIC1802
R11
COR11
240R
C18
COC18
100n
+1V5_DDR
PIR1 01
PIC1201
PIC1202
MCIMX6Q5EYM10AC
C12
COC12
22u
PIC1301
PIC1302
C13
COC13
22u
PIC1401
PIC1402
C14
COC14
22u
PIC1501
PIC1502
C15
COC15
22u
PIC1601
PIC1602
PIC1701
PIC1702
C16
COC16
22u
PIR1202
C17
COC17
22u
PIC20 1
PIC20 2
R12
COR12
240R
+1V5_DDR
DESIGN NOTE:
Recommended resistor values R11
and R12 are 768 Ohm 1% (Hardware
development guide).
+1V5_DDR
PIC1901
PIC1902
C19
COC19
10u
C20
COC20
100n
PIR1201
DESIGN NOTE:
Pull down resistor RX3 is added to trace SDCKE0 in Rev B4 by soldering to an existing
open via. Change will be made permanent in layout with the Rev C board.
PIC2101
PIC2102
D
C21
COC21
220n
PIC2 01
PIC2 02
C22
COC22
220n
PIC2301
C23
COC23
220n
PIC2302
PIC2401
PIC2402
C24
COC24
220n
PIC2501
PIC2502
C25
COC25
220n
PIC2601
PIC2602
C26
COC26
220n
PIC2701
PIC2702
PIC2801
C27
COC27
220n
PIC2802
C28
COC28
220n
PIC2901
PIC2902
C29
COC29
220n
PIC30 1
PIC30 2
C30
COC30
220n
PIC3101
PIC3102
C31
COC31
220n
PIC3201
PIC3202
C32
COC32
220n
PIC3 01
PIC3 02
C33
COC33
220n
PIC3401
PIC3402
C34
COC34
220n
PIC3501
PIC3502
C35
COC35
220n
PIC3601
PIC3602
C36
COC36
220n
PIC3701
PIC3702
C37
COC37
220n
PIC3801
PIC3802
C38
COC38
220n
PIC3901
PIC3902
C39
COC39
220n
PIC40 1
PIC40 2
C40
COC40
220n
DESIGN NOTE:
Using bit swapping for DATA bus to allow easy pcb routing.
+1V5_DDR
DESIGN NOTE:
When using data bit swapping the low order bit of eachbyte must reside at bit 0 of the
byte. The remaining 7 data bits can be swapped freely. This restriction is for write
leveling calibration. Example D0 to D0 or D0 to D8, and D1-7 can be swapped.
+1V5_DDR
PIC4101
PIC4102
C41
COC41
220n
PIC4201
PIC4202
C42
COC42
220n
PIC4301
PIC4302
C43
COC43
220n
PIC4 01
PIC4 02
C44
COC44
220n
PIC4501
PIC4502
C45
COC45
220n
PIC4601
PIC4602
C46
COC46
220n
PIC4701
PIC4702
PIC4801
PIC4802
C47
COC47
220n
C48
COC48
220n
PIC4901
PIC4902
C49
COC49
220n
PIC50 1
PIC50 2
C50
COC50
220n
PIC5101
PIC5102
C51
COC51
220n
PIC5201
PIC5202
C52
COC52
220n
PIC5301
PIC5302
C53
COC53
220n
PIC5401
PIC5402
C54
COC54
220n
PIC5 01
PIC5 02
C55
COC55
220n
PIC5601
PIC5602
C56
COC56
220n
PIC5701
PIC5702
C57
COC57
220n
PIC5801
PIC5802
C58
COC58
220n
PIC5901
PIC5902
C59
COC59
220n
PIC60 1
PIC60 2
Variant:
C60
COC60
220n
DESIGN NOTE:
When swapping byte lanes on 16-bit memories, remember to move the DQMx,
DQSx, and DQSx_B signals for that byte lane.
1
Title:
iMX6 Rex Module
Page Contents:
[04] - CPU - DDR3, DDR3 MEM.SchDoc
Prototype
Checked by
Revision:
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
4
of
20
D
1
2
3
4
5
6
7
8
CPU - SATA, PCIe
+1V1_VDDSOC_CAP
COR13
R13
PIR1301
A
PIC7801
PIC7802
0R
40mA
PIR1302
PIC6101
PIC6102
COC78
C78
A
PCIe
COC61
C61
220n
4u7
ClassName: PCIE
COFB1
FB1
1
PIFB101
COU1I
U1I
2
PIFB102
20mA
PIC6201
PIC6202
220R, 2.5A
Net Class
i
i.MX6Q - PCIe
COC62
C62
H7
NL0PCIE0VP
+PCIE_VP
PIU10H7
220n
NL0PCIE0VPTX
+PCIE_VPTX
+2V5
PCIE_VP
PCIE_RX_N
PCIE_RX_P
G8
PIU10G8
B1
B2
PIU10B2
PIU10B1
NLPCIE0RX0N
PCIE_RX_N
NLPCIE0RX0P
PCIE_RX_P
DIFF90
DIFF90
POPCIE0RX0N
PCIE_RX_N 3
POPCIE0RX0P
PCIE_RX_P 3
NLPCIE0TX0N
PCIE_TX_N
NLPCIE0TX0P
PCIE_TX_P
DIFF90
DIFF90
POPCIE0TX0N
PCIE_TX_N 3
POPCIE0TX0P
PCIE_TX_P 3
NLCLK10N
CLK1_N
NLCLK10P
CLK1_P
DIFF100
DIFF100
POCLK10N
CLK1_N 3
POCLK10P
CLK1_P 3
PCIE_VPTX
i Net Class
COR14
R14
PIR1401
PIC24 01
PIC24 02
COC244
C244
4u7
0R
25mA
PIR1402
PIC6401
PIC6402
NL0PCIE0VPH
+PCIE_VPH
COC64
C64
NLPCIe0REXT
PCIe_REXT
220n
PIR1502
ClassName: PCIE
G7
PIU10G7
PCIE_VPH
PCIE_TX_N
PCIE_TX_P
A2
PIU10A2
A3
B3
PIU10B3
PIU10A3
NLPCIE0C0TX0N
PCIE_C_TX_N
NLPCIE0C0TX0P
PCIE_C_TX_P
DIFF90
DIFF90
PCIE_REXT
COR15
R15
200R
XTALOSC_CLK1_N
XTALOSC_CLK1_P
C7
D7
PIU10D7
PIU10C7
NLCLK10C0N
CLK1_C_N
NLCLK10C0P
CLK1_C_P
DIFF100
DIFF100
PIR1501
IPU1_CSI0_DATA_EN / EIM_DATA00 / <GPIO5_IO20> / ARM_TRACE_CLK
DESIGN NOTE:
Close to pins +PCIE_VP, +PCIE_VPTX and
+PCIE_VPH should be placed additional bigger
capacitors. Near these pins are located 4u7 capacitors.
COC63
C63
PIC6301
PIC6302
COC65
C65
PIC6501
PIC6502
COC66
C66
PIC6601
PIC6602
COC67
C67
PIC6701
PIC6702
100n
100n
100n
100n
P3
NLPCIE0WAKE
PCIE_WAKE
PIU10P3
MCIMX6Q5EYM10AC
PIR1602
PIR1702
PIR1601
PIR1701
COR16
R16
49R9
POPCIE0WAKE
PCIE_WAKE 3
COR17
R17
49R9
B
B
SATA
+1V1_VDDSOC_CAP
COR18
R18
PIR1801
0R
COU1D
U1D
11mA
PIR1802
PIC6801
PIC6802
ClassName: SATA
i.MX6Q - SATA
COC68
C68
220n
+SATA_VP
NL0SATA0VP
G13
PIU10G13
SATA_VP
+2V5
COR19
R19
PIC24501
PIC24502
PIR1901
C245
COC245
4u7
0R
13mA
PIR1902
PIC7301
PIC7302
+SATA_VPH
NL0SATA0VPH
G12
PIU10G12
SATA_VPH
Net Class
i
A14
B14
SATA_C_RX_N
NLSATA0C0RX0N
SATA_C_RX_P
NLSATA0C0RX0P
DIFF100
DIFF100
COC69
C69
PIC6901
B12
A12
SATA_C_TX_N
NLSATA0C0TX0N
SATA_C_TX_P
NLSATA0C0TX0P
DIFF100
DIFF100
COC71
C71
C14
SATA_REXT
NLSATA0REXT
SATA_PHY_RX_N
SATA_PHY_RX_P
PIU10A14
SATA_PHY_TX_N
SATA_PHY_TX_P
PIU10B12
SATA_REXT
PIU10C14
C73
COC73
220n
ClassName: SATA
Net Class
i
PIU10B14
PIU10A12
10n
PIC6902
COC70
C70
PIC7001
PIC7101
10n
SATA_RX_N
NLSATA0RX0N
SATA_RX_P
NLSATA0RX0P
DIFF100
DIFF100
POSATA0RX0N
SATA_RX_N 3
POSATA0RX0P
SATA_RX_P 3
10n
SATA_TX_N
NLSATA0TX0N
SATA_TX_P
NLSATA0TX0P
DIFF100
DIFF100
POSATA0TX0N
SATA_TX_N 3
POSATA0TX0P
SATA_TX_P 3
PIC7002
10n
PIC7102
COC72
C72
PIC7201
PIC7202
PIR20 2
MCIMX6Q5EYM10AC
R20
COR20
191R
PIR20 1
DESIGN NOTE:
Close to pins +SATA_VP and +SATA_VPH should be
placed additional bigger capacitors. Near these pins
are located 4u7 capacitors.
DESIGN NOTE:
SATA supported only by iMX6
dual and quad processors
C
C
D
Variant:
CLOCKS (CPU & PCIE)
Title:
iMX6 Rex Module
Page Contents:
[05] - CPU - PCIE, SATA.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
5
of
20
D
1
2
3
4
5
6
7
8
CPU - HDMI, LVDS
+3V3
A
A
HDMI
+1V1_VDDSOC_CAP
PIC24601
PIC24602
0R
22mA
PIR2302
PIC7501
PIC7502
COC246
C246
4u7
i.MX6Q - HDMI
COC75
C75
220n
L7
NL0HDMI0VP
+HDMI_VP
PIU10L7
+2V5
COR27
R27
PIR2701
PIC24701
PIC24702
0R
19mA
PIR2702
PIC7601
PIC7602
COC247
C247
4u7
PIU10M7
PIU10K1
NLHDMI0HPD
HDMI_HPD
ECSPI1_SS2 / ENET_TX_DATA2 / FLEXCAN1_RX / KEY_ROW2 / SD2_VSELECT / <GPIO4_IO11> / HDMI_TX_CEC_LINE
HDMI_TX_DDC_CEC
PIU10W4
W4
K2
PIU10K2
NLHDMI0CEC
HDMI_CEC
NLHDMI0DDC
HDMI_DDC
HDMI_VP
HDMI_VPH
COC76
C76
220n
J1
PIU10J1
NLHDMI0RESREF
HDMI_RESREF
PIR30 2
K1
HDMI_TX_HPD
HDMI_REF
J5
J6
PIU10J6
COR25
R25
PIR2501
COR24
R24
PIR2401
PIR2101
0R
0R
PIR2402
PIR2502
NF
NLHDMI0CEC0IN
HDMI_CEC_IN
DIFF100
DIFF100
K5
HDMI_TX_DATA0_N PIU10K5
K6
HDMI_TX_DATA0_P PIU10K6
NLHDMI0D00N
HDMI_D0_N
NLHDMI0D00P
HDMI_D0_P
DIFF100
DIFF100
POHDMI0D00N
HDMI_D0_N 3
POHDMI0D00P
HDMI_D0_P 3
PIU10J3
J3
J4
PIU10J4
NLHDMI0D10N
HDMI_D1_N
NLHDMI0D10P
HDMI_D1_P
DIFF100
DIFF100
POHDMI0D10N
HDMI_D1_N 3
POHDMI0D10P
HDMI_D1_P 3
K3
HDMI_TX_DATA2_N PIU10K3
K4
HDMI_TX_DATA2_P PIU10K4
NLHDMI0D20N
HDMI_D2_N
NLHDMI0D20P
HDMI_D2_P
DIFF100
DIFF100
HDMI_TX_DATA1_N
HDMI_TX_DATA1_P
COR30
R30
1k6
PIU10J5
POHDMI0CLK0N
HDMI_CLK_N 3
POHDMI0CLK0P
HDMI_CLK_P 3
POHDMI0CEC0IN
HDMI_CEC_IN 3
i
Net Class
ECSPI1_SS3 / ENET_CRS / HDMI_TX_DDC_SCL / KEY_COL3 / I2C2_SCL / <GPIO4_IO12> / SPDIF_IN
ASRC_EXT_CLK / HDMI_TX_DDC_SDA / KEY_ROW3 / I2C2_SDA / <GPIO4_IO13> / SD1_VSELECT
U5
T7
PIU10T7
PIC7402
PIC7401
ClassName: HDMI
+3V3
PIR2802
PIR2902
PIR2801
PIR2901
COR28
R28
4k99
POHDMI0D20N
HDMI_D2_N 3
POHDMI0D20P
HDMI_D2_P 3
PIR30 1
DESIGN NOTE:
Close to pins +HDMI_VP and +HDMI_VPH should be
placed additional bigger capacitors. Near these pins
are located 4u7 capacitors.
PIR2 01
COR21
R21
47k
POHDMI0HPD
HDMI_HPD 3
NLHDMI0CLK0N
HDMI_CLK_N
NLHDMI0CLK0P
HDMI_CLK_P
HDMI_TX_CLK_N
HDMI_TX_CLK_P
M7
NL0HDMI0VPH
+HDMI_VPH
PIR2102
COR22
R22
47k
Net Class
i
COU1G
U1G
COR23
R23
PIR2301
PIR2 02
ClassName: HDMI
COR29
R29
4k99
NLI2C20SCL
I2C2_SCL
NLI2C20SDA
I2C2_SDA
PIU10U5
COC74
C74
100n
POI2C20SCL
I2C2_SCL 3
POI2C20SDA
I2C2_SDA 3
PIR2602
MCIMX6Q5EYM10AC
PIR2601
COR26
R26
0R
DESIGN NOTE:
from Design Guide: if HDMI_DDCEC is
unused, recommended conditions is float
B
B
LVDS
ClassName: LVDS
Net Class
i
COU1F
U1F
NVCC_LVDS2P5
i.MX6Q - LVDS
+2V5
R34
COR34
PIR3401
0R
+LVDS_2V5
NL0LVDS02V5 V7
PIR3402
PIU10V7
PIC24301
PIC24302
C243
COC243
4u7
PIC7 01
PIC7 02
LVDS0_DATA0_N
LVDS0_DATA0_P
PIU10U2
U2
U1
PIU10U1
NLLVDS00TX00N
LVDS0_TX0_N
LVDS0_TX0_P
NLLVDS00TX00P
DIFF100
DIFF100
POLVDS00TX00N
LVDS0_TX0_N 3
POLVDS00TX00P
LVDS0_TX0_P 3
LVDS0_DATA1_N
LVDS0_DATA1_P
PIU10U4
U4
U3
PIU10U3
LVDS0_TX1_N
NLLVDS00TX10N
LVDS0_TX1_P
NLLVDS00TX10P
DIFF100
DIFF100
POLVDS00TX10N
LVDS0_TX1_N 3
POLVDS00TX10P
LVDS0_TX1_P 3
LVDS0_DATA2_N
LVDS0_DATA2_P
PIU10V2
V2
V1
PIU10V1
LVDS0_TX2_N
NLLVDS00TX20N
LVDS0_TX2_P
NLLVDS00TX20P
DIFF100
DIFF100
POLVDS00TX20N
LVDS0_TX2_N 3
POLVDS00TX20P
LVDS0_TX2_P 3
LVDS0_DATA3_N
LVDS0_DATA3_P
PIU10W2
W2
W1
LVDS0_TX3_N
NLLVDS00TX30N
LVDS0_TX3_P
NLLVDS00TX30P
DIFF100
DIFF100
POLVDS00TX30N
LVDS0_TX3_N 3
POLVDS00TX30P
LVDS0_TX3_P 3
LVDS0_CLK_N
LVDS0_CLK_P
PIU10V4
V4
V3
LVDS0_CLK_N
NLLVDS00CLK0N
LVDS0_CLK_P
NLLVDS00CLK0P
DIFF100
DIFF100
POLVDS00CLK0N
LVDS0_CLK_N 3
LVDS0_CLK_P 3
POLVDS00CLK0P
PIU10W1
PIU10V3
NVCC_LVDS2P5
C77
COC77
220n
PIR3102
PIR3202
PIR3 02
PIR3101
PIR3201
PIR3 01
R31
COR31
4k99
R32
COR32
4k99
R33
COR33
10k
F21
I2C3_SCL
NLI2C30SCL
I2C3_SDA
NLI2C30SDA
I2C3_SCL 3, 8
POI2C30SCL
I2C3_SDA 3, 8
POI2C30SDA
A17
LVDS0_CABC
NLLVDS00CABC
LVDS0_PWM
NLLVDS00PWM
LVDS0_CABC 3
POLVDS00CABC
LVDS0_PWM 3
POLVDS00PWM
EIM_DATA17 / ECSPI1_MISO / IPU1_DI0_PIN06 / IPU2_CSI1_PIXCLK / DCIC1_OUT / <GPIO3_IO17> / I2C3_SCL
EIM_DATA18 / ECSPI1_MOSI / IPU1_DI0_PIN07 / IPU2_CSI1_DATA17 / IPU1_DI1_D0_CS / <GPIO3_IO18> / I2C3_SDA
PIU10F21
D24
PIU10D24
NAND_CE2_B / IPU1_SISG0 / ESAI_TX0 / EIM_CRE / CCM_CLKO2 / <GPIO6_IO15> / IPU2_SISG0
SD1_DATA3 / ECSPI5_SS2 / GPT_COMPARE3 / PWM1_OUT / WDOG2_B / <GPIO1_IO21> / WDOG2_RESET_B_DEB
PIU10A17
F18
PIU10F18
C
NVCC_LVDS2P5
+3V3
Y1
LVDS1_DATA0_N
LVDS1_DATA0_P
PIU10Y1
Y2
PIU10Y2
LVDS1_DATA1_N
LVDS1_DATA1_P
PIU10AA2
AA1
PIU10AA1
LVDS1_DATA2_N
LVDS1_DATA2_P
PIU10AB1
AB2
PIU10AB2
LVDS1_DATA3_N
LVDS1_DATA3_P
PIU10AA3
AA4
PIU10AA4
LVDS1_CLK_N
LVDS1_CLK_P
PIU10Y3
Y4
PIU10Y4
C
DESIGN NOTE:
I2C3 has been moved to another pad. This
change requires an update in software.
AA2
AB1
AA3
Y3
MCIMX6Q5EYM10AC
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[06] - CPU - HDMI, LVDS.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
6
of
20
D
1
2
3
4
5
6
7
8
CPU - USB, ETHERNET
A
A
ETHERNET
ClassName: RGMII_TXD
ClassName: RGMII_TXD
Net Class
i
COU1H
U1H
Net Class
i
i.MX6Q - RGMII
D21
COR35
R35
PIR3501
PORGMII0TXCLK
RGMII_TXCLK 13
C22
F20
PIU10F20
E21
PIU10E21
A24
PIU10A24
NLRGMII0TXD0
RGMII_TXD0
NLRGMII0TXD1
RGMII_TXD1
NLRGMII0TXD2
RGMII_TXD2
NLRGMII0TXD3
RGMII_TXD3
PORGMII0TXD0
RGMII_TXD0 13
PORGMII0TXD1
RGMII_TXD1 13
PORGMII0TXD2
RGMII_TXD2 13
PORGMII0TXD3
RGMII_TXD3 13
C23
NLRGMII0TXEN
RGMII_TXEN
PORGMII0TXEN
RGMII_TXEN 13
PIU10D21
HSI_TX_READY / RGMII_TD0 / <GPIO6_IO20>
HSI_RX_FLAG / RGMII_TD1 / <GPIO6_IO21>
HSI_RX_DATA / RGMII_TD2 / <GPIO6_IO22>
HSI_RX_WAKE / RGMII_TD3 / <GPIO6_IO23>
PIU10C22
USB_H2_STROBE / RGMII_TX_CTL / <GPIO6_IO26> / ENET_REF_CLK
PIU10C23
NLRGMII0R0TXCLK
RGMII_R_TXCLK
22R
NLRGMII0TXCLK
RGMII_TXCLK
USB_H2_DATA / RGMII_TXC / SPDIF_EXT_CLK / <GPIO6_IO19> / XTALOSC_REF_CLK_24M
PIR3502
ClassName: RGMII_RXD
B
Net Class i
B25
USB_H3_STROBE / RGMII_RXC / <GPIO6_IO30>
PIU10B25
NLRGMII0RXCLK
RGMII_RXCLK
PORGMII0RXCLK
RGMII_RXCLK 13
HSI_RX_READY / RGMII_RD0 / <GPIO6_IO25>
HSI_TX_FLAG / RGMII_RD1 / <GPIO6_IO27>
HSI_TX_DATA / RGMII_RD2 / <GPIO6_IO28>
HSI_TX_WAKE / RGMII_RD3 / <GPIO6_IO29>
PIU10C24
C24
B23
PIU10B23
B24
PIU10B24
D23
PIU10D23
NLRGMII0RXD0
RGMII_RXD0
NLRGMII0RXD1
RGMII_RXD1
NLRGMII0RXD2
RGMII_RXD2
NLRGMII0RXD3
RGMII_RXD3
PORGMII0RXD0
RGMII_RXD0 13
PORGMII0RXD1
RGMII_RXD1 13
PORGMII0RXD2
RGMII_RXD2 13
PORGMII0RXD3
RGMII_RXD3 13
USB_H3_DATA / RGMII_RX_CTL / <GPIO6_IO24>
PIU10D22
D22
NLRGMII0RXDV
RGMII_RXDV
PORGMII0RXDV
RGMII_RXDV 13
MLB_DATA / ENET_MDC / ESAI_TX5_RX0 / ENET_1588_EVENT1_IN / <GPIO1_IO31>
ENET_MDIO / ESAI_RX_CLK / ENET_1588_EVENT1_OUT / <GPIO1_IO22> / SPDIF_LOCK
PIU10V20
ENET_TX_CLK / ESAI_RX_FS / <GPIO1_IO23> / SPDIF_SR_CLK
ENET_TX_EN / ESAI_TX3_RX2 / <GPIO1_IO28>
MLB_SIG / ENET_RX_DATA1 / ESAI_TX_FS / ENET_1588_EVENT3_OUT / <GPIO1_IO26>
PIU10V22
V20
V23
PIU10V23
NLRGMII0MDC
RGMII_MDC
NLRGMII0MDIO
RGMII_MDIO
V22
V21
PIU10V21
W22
PIU10W22
PORGMII0MDC
RGMII_MDC 13
PORGMII0MDIO
RGMII_MDIO 13
NLENET0REF0CLK
ENET_REF_CLK
COR88
R88
PIR8801
NLRGMII0INT0R
RGMII_INT_R
POENET0REF0CLK
ENET_REF_CLK 13
0R
PIR8802
NLRGMII0INT
RGMII_INT
i
Net Class
MCIMX6Q5EYM10AC
B
PORGMII0INT
RGMII_INT 13
i
Net Class
ClassName: RGMII_MISC
DESIGN NOTE:
Resistor R88 fitted, if problem
occur unfit this resistor.
DESIGN NOTE:
+5V_USB_VBUS must be
provided by baseboard.
USB
U1E
COU1E
+5V_USB_VBUS
F9
PIC80 1
PIC80 2
C80
COC80
10u
PIC8101
PIC8102
B8
USB_OTG_CHD
PIU10B8
USB_OTG_VBUS
USB_OTG_DN
USB_OTG_DP
PIU10E9
B6
PIU10B6
A6
PIU10A6
EIM_DATA21 / ECSPI4_SCLK / IPU1_DI0_PIN17 / IPU2_CSI1_DATA11 / USB_OTG_OC / <GPIO3_IO21> / I2C1_SCL / SPDIF_IN
EIM_DATA22 / ECSPI4_MISO / IPU1_DI0_PIN01 / IPU2_CSI1_DATA10 / USB_OTG_PWR / <GPIO3_IO22> / SPDIF_OUT
VDDUSB_CAP
ESAI_RX_CLK / WDOG2_B / KEY_ROW5 / USB_OTG_ID / PWM2_OUT / <GPIO1_IO01> / SD1_CD_B
PIU10H20
E23
PIU10E23
USB_H1_VBUS
USB_H1_DN
USB_H1_DP
PIU10D10
F10
PIU10F10
E10
PIU10E10
C
PIU10F9
+3V3
ClassName: USB0
i.MX6Q - USB
+VDDUSB
NL0VDDUSB
DESIGN NOTE:
+5V_USB_VBUS should be enabled
after +3V3 or after USB0_PWR_EN
(USB1_PWR_EN).
PIR10 02
Net Class
i
R100
COR100
10k
PIR10 01
E9
USB0_N
NLUSB00N
USB0_P
NLUSB00P
DIFF90
DIFF90
C
USB0_N 3
POUSB00N
USB0_P 3
POUSB00P
H20
USB_OC
NLUSB0OC
USB0_PWR_EN
NLUSB00PWR0EN
USB_OC 3
POUSB0OC
USB0_PWR_EN 3
POUSB00PWR0EN
T4
USB0_ID
NLUSB00ID
USB0_ID 3
POUSB00ID
PIU10T4
C81
COC81
220n
EIM_DATA30 / IPU1_DISP1_DATA21 / IPU1_DI0_PIN11 / IPU1_CSI0_DATA03 / UART3_CTS_B / <GPIO3_IO30> / USB_H1_OC
EIM_DATA31 / IPU1_DISP1_DATA20 / IPU1_DI0_PIN12 / IPU1_CSI0_DATA02 / UART3_RTS_B / <GPIO3_IO31> / USB_H1_PWR
MCIMX6Q5EYM10AC
DESIGN NOTE:
USB_ID: low - HOST
high - DEVICE
D10
USB1_N
NLUSB10N
USB1_P
NLUSB10P
DIFF90
DIFF90
USB1_N 3
POUSB10N
USB1_P 3
POUSB10P
J20
PIU10J20
H21
PIU10H21
USB1_PWR_EN
NLUSB10PWR0EN
USB1_PWR_EN 3
POUSB10PWR0EN
PIC8201
PIC8202
i
Net Class
C82
COC82
220n
PIC7901
PIC7902
C79
COC79
220n
ClassName: USB1
DESIGN NOTE:
CPU pins for signals USB1_PWR_EN,
USB0_ID has been moved to another
pad, software change will be required.
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[07] - CPU - USB, ETHERNET.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
7
of
20
D
1
2
3
4
5
6
7
8
CPU - SPI, I2C, SD, MMC
A
A
DESIGN NOTE:
Card detection pin:
If not used,tie to low to indicate
there is a card attached.
SD-CARD
MMC-CARD
ClassName: SD_CARD
COU1K
U1K
i.MX6Q - SD3
B
ClassName: MMC_CARD
DESIGN NOTE:
Card write protect detect
If not used, tie to low to indicate it's
not write protected.
Net Class
i
E14
F14
PIU10F14
A15
PIU10A15
B15
PIU10B15
D13
PIU10D13
C13
PIU10C13
E13
PIU10E13
F13
PIU10F13
NLSD30DATA0
SD3_DATA0
NLSD30DATA1
SD3_DATA1
NLSD30DATA2
SD3_DATA2
NLSD30DATA3
SD3_DATA3
B13
D14
PIU10D14
A18
PIU10A18
C17
PIU10C17
NLSD30CMD0R
SD3_CMD_R
NLSD30CLK0R
SD3_CLK_R
NLSD30CD
SD3_CD
NLSD30WP
SD3_WP
SD3_DATA0 / UART1_CTS_B / FLEXCAN2_TX / <GPIO7_IO04>
SD3_DATA1 / UART1_RTS_B / FLEXCAN2_RX / <GPIO7_IO05>
SD3_DATA2 / <GPIO7_IO06>
SD3_DATA3 / UART3_CTS_B / <GPIO7_IO07>
SD3_DATA4 / UART2_RX_DATA / <GPIO7_IO01>
SD3_DATA5 / UART2_TX_DATA / <GPIO7_IO00>
PIU10E14
SD3_CMD / UART2_CTS_B / FLEXCAN1_TX / <GPIO7_IO02>
SD3_CLK / UART2_RTS_B / FLEXCAN1_RX / <GPIO7_IO03>
NAND_DATA00 / SD1_DATA4 / <GPIO2_IO00>
PIU10B13
POSD30DATA0
SD3_DATA0 3
POSD30DATA1
SD3_DATA1 3
POSD30DATA2
SD3_DATA2 3
POSD30DATA3
SD3_DATA3 3
PIR3802
COR38
R38
10k
COR1
R1
COR50
R50
PIR5002
PIR102
PIR3902
PIR3901
COR39
R39
10k
DESIGN NOTE:
Resistor R40 for SD3_WP pull up. On
base board make variant with NF 0R
resistor pull down.
PIR40 2
COR40
R40
10k
PIR40 1
NLSD30CMD
SD3_CMD
NLSD30CLK
SD3_CLK
MCIMX6Q5EYM10AC
DESIGN NOTE:
The maximum image size to load
in SD/MMC boot is 32MB. (iMX6
reference manual)
ClassName: SD_CARD
ClassName: SPI3
SPINOR
i.MX6Q - SPI, I2C
ECSPI2
PIU10P22
P23
PIU10P23
IPU1_DISP0_DATA00 / IPU2_DISP0_DATA00 / ECSPI3_SCLK / <GPIO4_IO21>
PIU10P24
P24
CSPI3_CLK_R
NLCSPI30CLK0R
ESAI_TX_CLK / I2C3_SDA / <GPIO1_IO06> / SD2_LCTL / MLB_SIG
PIU10T3
PIU10P21
P20
PIU10P20
R25
PIU10R25
R23
PIU10R23
IPU1_DISP0_DATA16 / IPU2_DISP0_DATA16 / ECSPI2_MOSI / AUD5_TXC / SDMA_EXT_EVENT0 / <GPIO5_IO10>
IPU1_DISP0_DATA17 / IPU2_DISP0_DATA17 / ECSPI2_MISO / AUD5_TXD / SDMA_EXT_EVENT1 / <GPIO5_IO11>
PIU10T21
U24
PIU10U24
IPU1_DISP0_DATA19 / IPU2_DISP0_DATA19 / ECSPI2_SCLK / AUD5_RXD / AUD4_RXC / <GPIO5_IO13> / EIM_CS3
PIU10U23
T3
COR52
R52
COR66
R66
PIR6602
PIR5202
COR112
R112
PIR11201
PIR11202
T21
U23
CSPI2_CLK_R
NLCSPI20CLK0R
R159
COR159
PIR15901
22R
V25
PIU10V25
D16
PIU10D16
E15
PIU10E15
COR41
R41
10k
PIR4202
COR42
R42
10k
PIR4302
COR43
R43
10k
B
PIR4101
PIR4201
PIR4301
NLSD20CMD
SD2_CMD
NLSD20CLK
SD2_CLK
POSD20CMD
SD2_CMD 3
POSD20CLK
SD2_CLK 3
POSD20CD
SD2_CD 3
POSD20WP
SD2_WP 3
NLSD20ACT
SD2_ACT
POSD20ACT
SD2_ACT 3
i
Net Class
MCIMX6Q5EYM10AC
ClassName: MMC_CARD
CSPI3_MOSI
NLCSPI30MOSI
CSPI3_MISO
NLCSPI30MISO
CSPI3_MOSI 14
POCSPI30MOSI
CSPI3_MISO 14
POCSPI30MISO
DESIGN NOTE:
SD2_ACT is not used in
reference design. Configure in
software first.
CSPI3_CLK
NLCSPI30CLK
CSPI3_CLK 14
POCSPI30CLK
CSPI3_CS2
NLCSPI30CS2
CSPI3_CS2 14
POCSPI30CS2
DESIGN NOTE:
CSPI2_MOSI needs to be
configured in software first.
i
Net Class
ClassName: SPI2
PIR15902
CSPI2_MOSI
NLCSPI20MOSI
CSPI2_MISO
NLCSPI20MISO
CSPI2_MOSI 3
POCSPI20MOSI
CSPI2_MISO 3
POCSPI20MISO
CSPI2_CLK
NLCSPI20CLK
CSPI2_CLK 3
POCSPI20CLK
CSPI2_CS0
NLCSPI20CS0
CSPI2_CS0 3
POCSPI20CS0
i
Net Class
DESIGN NOTE:
iMX6 Quad doesn't support I2C4 therefore: emulate
I2C4 by software or connect to I2C3.
If connected to I2C3 do not populate pullups R44, R45.
+3V3
PIR4 02
R44
COR44
4k99
PIR4 01
DESIGN NOTE:
I2C4 is not used in reference
design. Configure in software
first.
C
PIR4502
R45
COR45
4k99
R156
COR156
PIR15601
R157
COR157
NF
NF
PIR15701
0R
PIR15602
0R
PIR15702
I2C3_SDA 3, 6
POI2C30SDA
I2C3_SCL 3, 6
POI2C30SCL
PIR4501
ClassName: SPI2
I2C4_SDA
NLI2C40SDA
I2C4_SCL
NLI2C40SCL
MCIMX6Q5EYM10AC
22R
PIR5201
22R
PIR6601
PIR4102
DESIGN NOTE:
Resistor R43 FOR SD3_WP pull up.
On base board make variant with NF
0R resistor pull down.
22R
P21
IPU1_DISP0_DATA03 / IPU2_DISP0_DATA03 / ECSPI3_SS0 / <GPIO4_IO24>
IPU1_DISP0_DATA04 / IPU2_DISP0_DATA04 / ECSPI3_SS1 / <GPIO4_IO25>
IPU1_DISP0_DATA05 / IPU2_DISP0_DATA05 / ECSPI3_SS2 / AUD6_RXFS / <GPIO4_IO26>
IPU1_DISP0_DATA06 / IPU2_DISP0_DATA06 / ECSPI3_SS3 / AUD6_RXC / <GPIO4_IO27>
I2C4
Net Class
i
P22
IPU1_DISP0_DATA01 / IPU2_DISP0_DATA01 / ECSPI3_MOSI / <GPIO4_IO22>
IPU1_DISP0_DATA02 / IPU2_DISP0_DATA02 / ECSPI3_MISO / <GPIO4_IO23>
NAND_CE3_B / IPU1_SISG1 / ESAI_TX1 / EIM_ADDR26 / <GPIO6_IO16> / IPU2_SISG1
NAND_WP_B / IPU2_SISG5 / <GPIO6_IO09>
NLSD20CMD0R
SD2_CMD_R
NLSD20CLK0R
SD2_CLK_R
NLSD20CD
SD2_CD
NLSD20WP
SD2_WP
PIU10F19
+3V3
DESIGN NOTE:
CSPI3 needs to be configured
in software first.
ClassName: SPI3
Net Class
i
IPU1_DISP0_DATA18 / IPU2_DISP0_DATA18 / ECSPI2_SS0 / AUD5_TXFS / AUD4_RXFS / <GPIO5_IO12> / EIM_CS2
F19
C21
PIU10C21
F16
PIU10F16
D17
PIU10D17
SD2_CMD / ECSPI5_MOSI / KEY_ROW5 / AUD4_RXC / <GPIO1_IO11>
SD2_CLK / ECSPI5_SCLK / KEY_COL5 / AUD4_RXFS / <GPIO1_IO10>
POSD20DATA0
SD2_DATA0 3
POSD20DATA1
SD2_DATA1 3
POSD20DATA2
SD2_DATA2 3
POSD20DATA3
SD2_DATA3 3
POSD20DATA4
SD2_DATA4 3
POSD20DATA5
SD2_DATA5 3
POSD20DATA6
SD2_DATA6 3
POSD20DATA7
SD2_DATA7 3
DESIGN NOTE:
In reference design SD2 uses 4
bit data bus. Check software
settings.
SPI FLASH, I2C
C
NLSD20DATA0
SD2_DATA0
NLSD20DATA1
SD2_DATA1
NLSD20DATA2
SD2_DATA2
NLSD20DATA3
SD2_DATA3
NLSD20DATA4
SD2_DATA4
NLSD20DATA5
SD2_DATA5
NLSD20DATA6
SD2_DATA6
NLSD20DATA7
SD2_DATA7
PIU10A22
DESIGN NOTE:
In reference design SD3 uses 8
bit data bus. Check software
settings.
COU1L
U1L
A22
E20
PIU10E20
A23
PIU10A23
B22
PIU10B22
A19
PIU10A19
B18
PIU10B18
E17
PIU10E17
C18
PIU10C18
SD2_DATA0 / ECSPI5_MISO / AUD4_RXD / KEY_ROW7 / <GPIO1_IO15> / DCIC2_OUT
SD2_DATA1 / ECSPI5_SS0 / EIM_CS2 / AUD4_TXFS / KEY_COL7 / <GPIO1_IO14>
SD2_DATA2 / ECSPI5_SS1 / EIM_CS3 / AUD4_TXD / KEY_ROW6 / <GPIO1_IO13>
SD2_DATA3 / ECSPI5_SS3 / KEY_COL6 / AUD4_TXC / <GPIO1_IO12>
POSD30CMD
SD3_CMD 3
POSD30CLK
SD3_CLK 3
POSD30CD
SD3_CD 3
POSD30WP
SD3_WP 3
i
Net Class
Net Class
i
i.MX6Q - SD2
+3V3
PIR3801
22R
PIR101
22R
PIR5001
COU1J
U1J
I2C4_SDA 3
POI2C40SDA
I2C4_SCL 3
POI2C40SCL
i
Net Class
ClassName: I2C
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[08] - CPU - SPI, I2C, SD, MMC.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
8
of
20
D
1
2
3
4
5
6
7
8
CPU - UART, AUDIO
A
A
UART
ClassName: UART1
COU1M
U1M
Net Class
i
NVCC_UART1
i.MX6Q - UART
PIU10M1
M1
M3
PIU10M3
NLUART10TXD
UART1_TXD
NLUART10RXD
UART1_RXD
POUART10TXD
UART1_TXD 3
POUART10RXD
UART1_RXD 3
EIM_DATA20 / ECSPI4_SS0 / IPU1_DI0_PIN16 / IPU2_CSI1_DATA15 / UART1_RTS_B / <GPIO3_IO20> / EPIT2_OUT
EIM_DATA19 / ECSPI1_SS1 / IPU1_DI0_PIN08 / IPU2_CSI1_DATA16 / UART1_CTS_B / <GPIO3_IO19> / EPIT1_OUT
PIU10G20
G20
G21
PIU10G21
NLUART10RTS
UART1_RTS
NLUART10CTS
UART1_CTS
POUART10RTS
UART1_RTS 3
POUART10CTS
UART1_CTS 3
EIM_DATA25 / ECSPI4_SS3 / UART3_RX_DATA / ECSPI1_SS3 / ECSPI2_SS3 / <GPIO3_IO25> / AUD5_RXC / UART1_DSR_B
EIM_DATA24 / ECSPI4_SS2 / UART3_TX_DATA / ECSPI1_SS2 / ECSPI2_SS2 / <GPIO3_IO24> / AUD5_RXFS / UART1_DTR_B
PIU10G22
G22
F22
PIU10F22
NLUART10DSR
UART1_DSR
NLUART10DTR
UART1_DTR
POUART10DSR
UART1_DSR 3
POUART10DTR
UART1_DTR 3
EIM_DATA23 / IPU1_DI0_D0_CS / UART3_CTS_B / UART1_DCD_B / IPU2_CSI1_DATA_EN / <GPIO3_IO23> / IPU1_DI1_PIN02 / IPU1_DI1_PIN14
EIM_EB3 / ECSPI4_RDY / UART3_RTS_B / UART1_RI_B / IPU2_CSI1_HSYNC / <GPIO2_IO31> / IPU1_DI1_PIN03 / SRC_BOOT_CFG31
PIU10D25
D25
F23
PIU10F23
NLUART10DCD
UART1_DCD
NLUART10RI
UART1_RI
POUART10DCD
UART1_DCD 3
POUART10RI
UART1_RI 3
NVCC_UART2
B
IPU1_CSI0_DATA10 / AUD3_RXC / ECSPI2_MISO / UART1_TX_DATA / <GPIO5_IO28> / ARM_TRACE07
IPU1_CSI0_DATA11 / AUD3_RXFS / ECSPI2_SS0 / UART1_RX_DATA / <GPIO5_IO29> / ARM_TRACE08
PIU10D19
D19
E18
PIU10E18
NLUART20TXD
UART2_TXD
NLUART20RXD
UART2_RXD
POUART20TXD
UART2_TXD 3
POUART20RXD
UART2_RXD 3
SD4_DATA5 / UART2_RTS_B / <GPIO2_IO13>
SD4_DATA6 / UART2_CTS_B / <GPIO2_IO14>
PIU10C19
C19
B20
PIU10B20
NLUART20RTS
UART2_RTS
NLUART20CTS
UART2_CTS
POUART20RTS
UART2_RTS 3
POUART20CTS
UART2_CTS 3
DESIGN NOTE:
All UART signal should be configured
in software except UART1_RXD and
UART1_TXD.
B
i
Net Class
MCIMX6Q5EYM10AC
ClassName: UART2
+3V3
AUDIO
PIR4602
ClassName: Audio
Net Class
i
U1N
COU1N
i.MX6Q - AUDIO
IPU1_CSI0_DATA04 / EIM_DATA02 / ECSPI1_SCLK / KEY_COL5 / AUD3_TXC / <GPIO5_IO22> / ARM_TRACE01
IPU1_CSI0_DATA05 / EIM_DATA03 / ECSPI1_MOSI / KEY_ROW5 / AUD3_TXD / <GPIO5_IO23> / ARM_TRACE02
IPU1_CSI0_DATA06 / EIM_DATA04 / ECSPI1_MISO / KEY_COL6 / AUD3_TXFS / <GPIO5_IO24> / ARM_TRACE03
IPU1_CSI0_DATA07 / EIM_DATA05 / ECSPI1_SS0 / KEY_ROW6 / AUD3_RXD / <GPIO5_IO25> / ARM_TRACE04
C
IPU1_CSI0_DATA08 / EIM_DATA06 / ECSPI2_SCLK / KEY_COL7 / I2C1_SDA / <GPIO5_IO26> / ARM_TRACE05
IPU1_CSI0_DATA09 / EIM_DATA07 / ECSPI2_MOSI / KEY_ROW7 / I2C1_SCL / <GPIO5_IO27> / ARM_TRACE06
CCM_CLKO1 / KEY_COL5 / ASRC_EXT_CLK / EPIT1_OUT / <GPIO1_IO00> / USB_H1_PWR / SNVS_VIO_5
PIR4702
R46
COR46
4k99
R47
COR47
4k99
PIR4601
PIR4701
ClassName: Audio
Net Class
i
R72
COR72
22R
N1
PIU10N1
P2
PIU10P2
N4
PIU10N4
N3
PIU10N3
N6
PIU10N6
N5
PIU10N5
T5
PIU10T5
AUD3_TXC_R
NLAUD30TXC0R
AUD3_TXD
NLAUD30TXD
AUD3_TXFS
NLAUD30TXFS
AUD3_RXD
NLAUD30RXD
PIR7201
PIR7202
AUD3_TXC
NLAUD30TXC
I2C1_SDA
NLI2C10SDA
I2C1_SCL
NLI2C10SCL
AUD3_CLK_R
NLAUD30CLK0R
AUD3_TXC 3
POAUD30TXC
AUD3_TXD 3
POAUD30TXD
AUD3_TXFS 3
POAUD30TXFS
AUD3_RXD 3
POAUD30RXD
I2C1_SDA 3
POI2C10SDA
I2C1_SCL 3
POI2C10SCL
R160
COR160
PIR16001
PIR16002
AUD3_CLK
NLAUD30CLK
DESIGN NOTE:
In reference schematic I2C1 used by Audio has 1V8 level
intefrace. IMX6 Rex Module has whole Audio intefrace on 3V3.
C
AUD3_CLK 3
POAUD30CLK
22R
MCIMX6Q5EYM10AC
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[09] - CPU - UART, AUDIO.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
9
of
20
D
1
2
3
4
5
6
7
8
CPU - JTAG, CONTROL
DESIGN NOTE:
from Design Guide: pullup not required
(ON / OFF).
+3V0_ALWAYS
PIR4802
CONTROL
COR48
R48
10k
PIR4801
3POON0OFF
ON_OFF
DESIGN NOTE:
PMIC_ON_REQ:
1 or high Z = ON
0 = OFF
COU1A
U1A
NLON0OFF
ON_OFF
POR_Bn
D12
PIU10D12 SRC_ONOFF
C11
PIU10C11 SRC_POR
NLBOOT0MODE0
BOOT_MODE0
NLBOOT0MODE1
BOOT_MODE1
PIU10C12
POPMIC0ON0REQ
15
PMIC_ON_REQ
COR73
R73
100k
PIR7301
COTP3 TP_25MILC
TP3
PITP301
E12
NLTEST0MODE
TEST_MODE
PIU10E12
NLTAMPER
TAMPER
PIU10E11
TCU_TEST_MODE
E11
ClassName: JTAG
i.MX6Q - CONTROL
C12
SRC_BOOT_MODE0
F12
PIU10F12 SRC_BOOT_MODE1
+3V0_ALWAYS
PIR7302
A
Net Class
i
NVCC_JTAG
SNVS_TAMPER
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRSTB
JTAG_MOD
H5
C3
PIU10C3
G5
PIU10G5
G6
PIU10G6
C2
PIU10C2
H6
PIU10H6
PIU10H5
PIU10F11
+3V3
WD_OUT
R22
PIU10R22
NLCPU0XTALI
CPU_XTALI
NLCPU0XTALO
CPU_XTALO
PIU10A7
NF
10M
PIR5401
ESAI_TX_FS / KEY_ROW6 / <GPIO1_IO02> / SD2_WP / MLB_DATA
D9
PIU10D9 XTALOSC_RTC_XTALI
C9
PIU10C9 XTALOSC_RTC_XTALO
PIR3702
PIC8301
PIC8302
PIR14302
PIR14 02
PIR14301
PIR14 01
COR143
R143
100k
C5
XTALOSC_CLK2_N PIU10C5
D5
XTALOSC_CLK2_P PIU10D5
COR144
R144
100k
MCIMX6Q5EYM10AC
COY2
Y2
PIY102
PIY201
24MHz
COR37
R37
2M2
NLBOARD0VARIANT00
BOARD_VARIANT_0
NLBOARD0VARIANT01
BOARD_VARIANT_1
B
PIY202
+3V0_ALWAYS
32.768kHz
PIC8401
PIC8402
COC83
C83
18p
PIC8501
PIC8502
COC84
C84
18p
PIC8601
PIC8602
COC85
C85
18p
DESIGN NOTE:
Resistor R37 from CPU_XTALO to GND is required to correct a
known 24MHz slow starting issue present on some iMX6 part.
Please refer to the i.MX 6 Processor Errata, issue # ERR005777
for more details.
COC86
C86
18p
+3V0_ALWAYS
PIR5 02
PIR10302
COR55
R55
4k99
COR103
R103
10k
PIR10301
PIR5702
R56
COR56
4k99
R57
COR57
10k
PIR5601
+1V5_DDR
PIR5902
+3V0_ALWAYS
U6
COU6
SENSE_1V5
NLSENSE01V5
+3V3
PIR6702
10k
R71
COR71
PIR7101
NF
0R
PIU701
WD_OUT_R
NLWD0OUT0R
PIR7102
100n
5
PIU605
4
R67
COR67
10k
PIR6701
C89
COC89
PIU604
PIC8 01
PIC8 02
3
C88
COC88
100n
PIU603
C87
COC87
100n
PIR60 2
R60
COR60
10k
PIR60 1
SENSE1
PIR4902
R49
COR49
10k
4
PIR5801
POBOOT0MODE
BOOT_MODE 3
2N7002BKW,115
PIQ902
PIU606
CT
RESET
PIU601
MR
GND
PIU602
JTAG
ClassName: JTAG
Net Class
i
1
+3V3
POR_Bn
NLPOR0Bn
PIR70 1
2
R70
COR70
0R
TPS3808G09DBVRG4
JTAG_MOD
NLJTAG0MOD
R51
COR51
NF
PIR5101
0R
RSTOUTn
NLRSTOUTn
PIR5102
PID101
POK_3V3
NLPOK03V3
PIU703
PIR6102
PIR6202
PIR6302
PIR6402
PIR6101
PIR6201
PIR6301
PIR6401
R61
COR61
1k
PIR70 2
RSTOUTn_R
NLRSTOUTn0R
PIU702
AND
PIR5701
1
PIQ901
C
PIR4901
6
VDD
U7
COU7
SN74AHC1G09DBVR
PIU704
2
NF
NF
RSTOUTn 3
PORSTOUTn
PORSTOUTN
D1
COD1
RB751V-40-TP
R62
COR62
10k
R63
COR63
10k
R64
COR64
10k
DESIGN NOTE:
from Design Guide: pullup not required
JTAG_TDO: no use of external PU/PD
3
WD_OUT
NLWD0OUT
PIU705
PIR6901
R58
COR58
10k
COQ9
Q9
DESIGN NOTE:
Default boot mode: 00 (eFuses).
Tamper will not be used. Test mode only for factory use.
DESIGN NOTE:
from Design Guide: JTAG_MOD use
pulldown 1k or tie to GND
Reset Threhold 0.84 Volts
1
RSTINn
NLRSTINn
3PORSTINN
RSTINn
PORSTINn
10k
5
PIR6801
PIC8901
PIC8902
R69
COR69
PIR5802
PIQ903
DESIGN NOTE:
Do not fit R58 and fit R104 to
use BOOT MODE signal from
connector J1.
+3V0_ALWAYS +3V3
PIC8701
PIC8702
R59
COR59
4k99
PIR5901
C
PIR6902
PIR16501
BOOT MODE[1:0]:
00 Boot from fuses
01 Serial downloader
10 Boot from board settings
11 Reserved
RESET
R68
COR68
PIR10401
COR165
R165
10k
3
PIR5602
DESIGN NOTE:
from Design Guide: TEST_MODE pull
down internally - externall not required
PIR6802
PIR16502
BOOT_MODE0
BOOT_MODE1
TAMPER
TEST_MODE
DESIGN NOTE:
Per bulletin EB830, the i.MX6 processor may drive the 24 MHz
crystal up to 250 uW. Freescale recommends following the
guidelines contained in the bulletin.
+3V3
PIR10402
COR104
R104
10k
NF
PIR5 01
+3V3
DESIGN NOTE:
USER_LED configure in software first.
POUSER0LED
USER_LED 14
G
PIR3701
G24
H25
PIU10H25
PIU10G24
PIR13701
D
PIY101
NLUSER0LED
USER_LED
S
COY1
Y1
PIR5402
COR137
R137
NF
100k
PIR1 101
T1
PIU10T1
COR54
R54
PIR5302
PIR13702
NF
IPU1_DISP0_DATA08 / IPU2_DISP0_DATA08 / PWM1_OUT / WDOG1_B / <GPIO4_IO29>
A7
XTALOSC_XTALI
B7
PIU10B7 XTALOSC_XTALO
NLRTC0XTALI
RTC_XTALI
NLRTC0XTALO
RTC_XTALO
B
DESIGN NOTE:
Pins GPIO2_IO21 and 22 used to recognize version of
the board. V1I1 - both pins pull down (00)
RGMII_RSTn_R
RSTOUTn_R
COR111
R111
100k
<EIM_ADDR17> / IPU1_DISP1_DATA12 / IPU2_CSI1_DATA12 / GPIO2_IO21 / SRC_BOOT_CFG17
<EIM_ADDR16> / IPU1_DI1_DISP_CLK / IPU2_CSI1_PIXCLK / GPIO2_IO22 / SRC_BOOT_CFG16
NF
10M
JTAG_MOD
PIR1 102
DESIGN NOTE:
WD_OUT configure in software first.
COR53
R53
22R
PIR16102
F11
CCM_PMIC_STBY_REQ
D11
PIU10D11 SNVS_PMIC_ON_REQ
NLPMIC0STBY0REQ
PMIC_STBY_REQ
NLPMIC0ON0REQ
PMIC_ON_REQ
U21
ENET_RX_EN / ESAI_TX_CLK / SPDIF_EXT_CLK / <GPIO1_IO25> PIU10U21
H19
<EIM_ADDR25> / ECSPI4_SS1 / ECSPI2_RDY / IPU1_DI1_PIN12 / IPU1_DI0_D1_CS / GPIO5_IO02 / HDMI_TX_CEC_LINE PIU10H19
PIR5301
COR161
NLJTAG0TDO0R R161
JTAG_TDO_R
PIR16101
NLJTAG0TCK0R
JTAG_TCK_R
NLJTAG0TMS
JTAG_TMS
NLJTAG0TDI0R
JTAG_TDI_R
NLJTAG0TDO
JTAG_TDO
NLJTAG0nTRST
JTAG_nTRST
2
A
VDD_SNVS_IN
DESIGN NOTE:
Power ON / OFF control needs to be tested first.
RGMII_RSTn_R
NLRGMII0RSTn0R
JTAG_nTRST
JTAG_TDI_R
JTAG_TMS
JTAG_TCK_R
JTAG_TDO
PID102
R65
COR65
NF
0R
PIR6501
PIR6502
RGMII_RSTn
NLRGMII0RSTn
RGMII_RSTn 13
PORGMII0RSTn
PORGMII0RSTN
R90
COR90
PIR9001
R92
COR92
PIR9201
22R
JTAG_TDI
NLJTAG0TDI
22R
JTAG_TCK
NLJTAG0TCK
PIR9002
PIR9202
JTAG_nTRST 3
POJTAG0NTRST
POJTAG0nTRST
JTAG_TDI 3
POJTAG0TDI
JTAG_TMS 3
POJTAG0TMS
JTAG_TCK 3
POJTAG0TCK
JTAG_TDO 3
POJTAG0TDO
13, 14, 15 POK_3V3
POPOK03V3
i
Net Class
DESIGN NOTE:
The proper peripheral RESET (RSTOUTn) should be controlled
by processor GPIO, but has to be supported by software first.
Temporarily we use the POR to reset peripherals.
ClassName: JTAG
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[10] - CPU - JTAG, CONTROL.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
10
of
20
D
1
2
3
DESIGN NOTE:
Disable LDOs for VDDARM_IN, VDDARM23_IN and
VDDSOC_IN.
4
7
H14
J14
PIU10J14
K14
PIU10K14
L14
PIU10L14
M14
PIU10M14
N14
PIU10N14
P14
PIU10P14
R14
PIU10R14
PIU10H14
PIC90 1
PIC90 2
A
PIC9101
PIC9102
COC90
C90
220n
PIC9201
PIC9202
COC91
C91
220n
COC92
C92
220n
PIC9301
PIC9302
COC93
C93
220n
PIC9401
PIC9402
COC94
C94
220n
PIC9501
PIC9502
PIC9601
PIC9602
COC95
C95
220n
COC96
C96
22u
K9
L9
PIU10L9
M9
PIU10M9
N9
PIU10N9
P9
PIU10P9
R9
PIU10R9
T9
PIU10T9
U9
PIU10U9
PIU10K9
COC107
C107
220n
PIC10801
PIC10802
COC108
C108
220n
PIC10901
PIC10902
COC109
C109
220n
PIC1 0 1
PIC1 0 2
PIC1 101
PIC1 102
COC110
C110
220n
COC111
C111
22u
2
PIC10701
PIC10702
COFB2
FB2
VDDARM23_IN_1
VDDARM23_IN_2
VDDARM23_IN_3
VDDARM23_IN_4
VDDARM23_IN_5
VDDARM23_IN_6
VDDARM23_IN_7
VDDARM23_IN_8
1750mA (max 1890mA)
COC119
C119
220n
PIC120 1
PIC120 2
COC120
C120
220n
NL01V3750VDDSOC0IN
+1V375_VDDSOC_IN
PIC12101
PIC12102
COC121
C121
220n
PIC12 01
PIC12 02
COC122
C122
220n
PIC12301
PIC12302
PIC12401
PIC12402
COC123
C123
220n
PIC12501
PIC12502
COC124
C124
220n
COC125
C125
220n
PIC12601
PIC12602
COC126
C126
220n
PIC12701
PIC12702
COC127
C127
22u
PIC12801
PIC12802
PIC12901
PIC12902
COC128
C128
22u
COC129
C129
22u
+3V0_ALWAYS
100mA (max 125mA)
PIC13601
PIC13602
B
PIC13701
PIC13702
COC136
C136
220n
H16
J16
PIU10J16
K16
PIU10K16
L16
PIU10L16
M16
PIU10M16
N16
PIU10N16
P16
PIU10P16
R16
PIU10R16
T16
PIU10T16
U16
PIU10U16
PIU10H16
C
PIC16701
PIC16702
220n
C167
COC167
220n
PIC16801
PIC16802
C158
COC158
220n
C168
COC168
220n
PIC15901
PIC15902
PIC16901
PIC16902
C159
COC159
220n
C169
COC169
220n
VDDARM23_CAP_1
VDDARM23_CAP_2
VDDARM23_CAP_3
VDDARM23_CAP_4
VDDARM23_CAP_5
VDDARM23_CAP_6
VDDARM23_CAP_7
VDDARM23_CAP_8
PIU10H11
NL01V20VDD0ARM0CAP
+1V2_VDD_ARM_CAP
PIC9701
PIC9702
COC97
C97
220n
H11
J11
PIU10J11
K11
PIU10K11
L11
PIU10L11
M11
PIU10M11
N11
PIU10N11
P11
PIU10P11
R11
PIU10R11
PIC9801
PIC9802
COC98
C98
220n
PIC9 01
PIC9 02
COC99
C99
220n
PIC10 01
PIC10 02
COC100
C100
220n
PIC10101
PIC10102
COC101
C101
22u
PIC10201
PIC10202
COC102
C102
220n
PIC10301
PIC10302
COC103
C103
220n
PIC10401
PIC10402
COC104
C104
220n
PIC10501
PIC10502
COC105
C105
220n
A
PIC10601
PIC10602
COC106
C106
22u
R10
T10
PIU10T10
T13
PIU10T13
T14
PIU10T14
U10
PIU10U10
U13
PIU10U13
U14
PIU10U14
VDDSOC_CAP_1
VDDSOC_CAP_2
VDDSOC_CAP_3
VDDSOC_CAP_4
VDDSOC_CAP_5
VDDSOC_CAP_6
VDDSOC_CAP_7
PIU10R10
VDDPU_CAP_1
VDDPU_CAP_2
VDDPU_CAP_3
VDDPU_CAP_4
VDDPU_CAP_5
VDDPU_CAP_6
VDDPU_CAP_7
PIU10H17
VDD_CACHE_CAP
PIU10N12
H17
J17
PIU10J17
K17
PIU10K17
L17
PIU10L17
M17
PIU10M17
N17
PIU10N17
P17
PIU10P17
N12
PIC1 201
PIC1 202
PIC1 301
PIC1 302
COC112
C112
220n
PIC1 401
PIC1 402
COC113
C113
220n
PIC1 501
PIC1 502
COC114
C114
220n
PIC1 601
PIC1 602
COC115
C115
220n
PIC1 701
PIC1 702
COC116
C116
220n
PIC1 801
PIC1 802
COC117
C117
220n
COC118
C118
22u
LAYOUT NOTE:
It is critical that the bulk and decoupling capacitors placed on the VDDARM_CAP,
VDDARM23_CAP, VDDSOC_CAP and VDDPU rails be placed directly underneath the
processors. Development testing has shown that proper placement of the capacitors can
reduce ripple on the voltage rails by as much as 50% compared to placing capacitors outside
the physical boundaries of the processor. These will result in more stable processor operations.
NL0VDDPU
+VDDPU
PIC130 1
PIC130 2
PIC13101
PIC13102
COC130
C130
220n
PIC13201
PIC13202
COC131
C131
220n
PIC13 01
PIC13 02
COC132
C132
220n
PIC13401
PIC13402
COC133
C133
220n
PIC13501
PIC13502
COC134
C134
220n
COC135
C135
22u
{NVCC_CACHE POWER}
PIC13801
PIC13802
COC137
C137
22u
MX6 power domains under-BGA decoupling (belongs
to CPU pins on page 4)
PIC15801
PIC15802
VDDSOC_IN_1
VDDSOC_IN_2
VDDSOC_IN_3
VDDSOC_IN_4
VDDSOC_IN_5
VDDSOC_IN_6
VDDSOC_IN_7
VDDSOC_IN_8
VDDSOC_IN_9
VDDSOC_IN_10
H9
VDDHIGH_IN_1
J9
PIU10J9 VDDHIGH_IN_2
PIC14201
PIC14202
C157
COC157
PIU10H13
PIU10H9
G11
PIU10G11
PIC15701
PIC15702
H13
J13
PIU10J13
K13
PIU10K13
L13
PIU10L13
M13
PIU10M13
N13
PIU10N13
P13
PIU10P13
R13
PIU10R13
VDDARM_CAP_1
VDDARM_CAP_2
VDDARM_CAP_3
VDDARM_CAP_4
VDDARM_CAP_5
VDDARM_CAP_6
VDDARM_CAP_7
VDDARM_CAP_8
+1V1_VDDSOC_CAP
1
220R, 2.5A
i.MX6Q - POWER
VDDARM_IN_1
VDDARM_IN_2
VDDARM_IN_3
VDDARM_IN_4
VDDARM_IN_5
VDDARM_IN_6
VDDARM_IN_7
VDDARM_IN_8
PIC160 1
PIC160 2
PIC170 1
PIC170 2
C160
COC160
220n
C170
COC170
220n
PIC16101
PIC16102
PIC17101
PIC17102
C161
COC161
220n
C171
COC171
220n
COC142
C142
220n
+1V5_DDR
PIC16201
PIC16202
PIC17201
PIC17202
C162
COC162
220n
C172
COC172
22u
PIC17301
PIC17302
C173
COC173
22u
D
H10
VDDHIGH_CAP_1 PIU10H10
J10
VDDHIGH_CAP_2 PIU10J10
PIU10T11
NL02V50VDDHIGH0VPH
+2V5_VDDHIGH_VPH
PIC13902
PIC13901
VDD_SNVS_IN
VDD_SNVS_CAP
A13
PIU10A13
A25
PIU10A25
A4
PIU10A4
A8
PIU10A8
AA10
PIU10AA10
AA13
PIU10AA13
AA16
PIU10AA16
AA19
PIU10AA19
AA22
PIU10AA22
AA7
PIU10AA7
AB24
PIU10AB24
AB3
PIU10AB3
AD10
PIU10AD10
AD13
PIU10AD13
AD16
PIU10AD16
AD19
PIU10AD19
AD22
PIU10AD22
AD4
PIU10AD4
AD7
PIU10AD7
AE1
PIU10AE1
AE25
PIU10AE25
B4
PIU10B4
C1
PIU10C1
C10
PIU10C10
C4
PIU10C4
C6
PIU10C6
D3
PIU10D3
D6
PIU10D6
D8
PIU10D8
E5
PIU10E5
E6
PIU10E6
E7
PIU10E7
F5
PIU10F5
F6
PIU10F6
F7
PIU10F7
F8
PIU10F8
G10
PIU10G10
G19
PIU10G19
G3
PIU10G3
H12
PIU10H12
H15
PIU10H15
H18
PIU10H18
H8
PIU10H8
J12
PIU10J12
J15
PIU10J15
J18
PIU10J18
J2
PIU10J2
J8
PIU10J8
K10
PIU10K10
K12
PIU10K12
K15
PIU10K15
K18
PIU10K18
K8
PIU10K8
L10
PIU10L10
L12
PIU10L12
L15
PIU10L15
L18
PIU10L18
L2
PIU10L2
L5
PIU10L5
L8
PIU10L8
M10
PIU10M10
M12
PIU10M12
M15
PIU10M15
M18
PIU10M18
M8
PIU10M8
N10
PIU10N10
N15
PIU10N15
N18
PIU10N18
N8
PIU10N8
P10
PIU10P10
P12
PIU10P12
P15
PIU10P15
P18
PIU10P18
P8
PIU10P8
R12
PIU10R12
R15
PIU10R15
R17
PIU10R17
R8
PIU10R8
T11
8
DESIGN NOTE:
The VDDARM_CAP and VDDARM23_CAP rails have been optimized for use with the i.MX 6 Quad and i.MX 6 DualLite processors. To achieve the
lowest power mode (preventing internal leakage) when using the i.MX 6 Dual and the i.MX 6 SoloLite processors, VDDARM_CAP should be split
from VDDARM23_CAP and the VDDARM23_CAP pins should be connected to ground. This can be done on a single board configured for use with
all four processors by placing a Zero Ohm resistor between the VDDARM_CAP and VDDARM23_CAP rails (in place of the straight net connection).
To use the board with different processors, populate the resistor when using Quad and DualLite processors and depopulate resistor when using Dual
and SoloLite processors. When using Dual and SoloLite processors, depopulate the capacitors attached to VDDARM23_CAP pins and replace one
of the capacitors with a zero Ohm resistor to short pins to ground. The configuration in this schematic will work with all four processors, but will not
result in the most power optimized configuration for the i.MX 6 Dual and Solo processors.
COU1B
U1B
2500mA (max 3920mA)
PIC1 901
PIC1 902
6
CPU - POWER
DESIGN NOTE:
For testing purpuse only: Set +1V375 to +1.24V
(when LDO VDDARM, VDDARM23 and VDDSOC
are disabled) to lower power dissipation.
+1V375
PIFB20
PIFB201
5
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
G9
PIU10G9
+3V3
NL0VDD0SNVS0CAP
+VDD_SNVS_CAP
PIC14 01
PIC14 02
P19
NVCC_LCD
PIU10P19
NVCC_CSI
PIU10N7
NVCC_MIPI
PIU10K7
NVCC_EIM0
K19
PIU10K19
NVCC_EIM1
L19
PIU10L19
NVCC_EIM2
PIU10M19
N7
NL0NVCC0CSI
+NVCC_CSI
K7
+NVCC_MIPI
NL0NVCC0MIPI
PIC14301
PIC14302
COC139
C139
10n
PIC140 1
PIC140 2
PIC14101
PIC14102
COC140
C140
220n
COC138
C138
220n
B
COC141
C141
22u
COC143
C143
220n
COC144
C144
220n
+3V3
+3V3
+1V2_ETH
+1V375
COR76
R76
PIR7601
+NVCC_CSI
NVCC_ENET
M19
R19
PIU10R19
PIC16 01
PIC16 02
PIC14601
PIC14602
C166
COC166
220n
C146
COC146
220n
PIC14701
PIC14702
C147
COC147
22u
PIC14801
PIC14802
C148
COC148
22u
PIR10502
PIR7 01
NF
NF
PIR10501
PIR7 02
R105
COR105
0R
PIC14501
PIC14502
R77
COR77
2R2
C145
COC145
220n
+2V5
+NVCC_ENET
NL0NVCC0ENET
COR78
R78
+NVCC_MIPI
P7
R80
COR80
NVCC_PLL_OUT
NVCC_RGMII
E8
PIU10G18
PIU10G16
NVCC_SD2
PIU10G17
NVCC_SD3
NVCC_NANDF
NVCC_JTAG
PIC15401
PIC15402
PIC150 1
0R
PIR8002
PIC15301
PIC15302
C152
COC152
220n
C153
COC153
220n
PIC150 2
C150
COC150
220n
PIC15101
PIC15102
PIR7902
R79
COR79
10R
NF
C151
COC151
22u
PIR7901
C154
COC154
220n
PIC16301
PIC16302
G14
PIU10G14
+3V3
PIC16401
PIC16402
G15
PIU10G15
+3V3
PIC16501
PIC16502
J7
PIU10J7
PIC17401
PIC17402
C149
COC149
220n
R74
COR74
+NVCC_ENET
PIR7401
PIC15 01
PIC15 02
DESIGN NOTE:
+1V1_NVCC_PLL_OUT: R77, R79,
R105 for testing only.
+3V3
PIR7802
+2V5
DESIGN NOTE:
Measure +1V1_NVCC_PLL_OUT, if
needed fit R77, R79.
+3V3
G17
C8
GPANAIO PIU10C8
A5
FA_ANA PIU10A5
B5
VDD_FA PIU10B5
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
PIC15201
PIC15202
+NVCC_RGMII
NL0NVCC0RGMII
G16
NVCC_SD1
PIR8001
+3V3
PIU10E8
G18
PIC14901
PIC14902
+2V5
PIU10P7
0R
PIR7801
+1V1_NVCC_PLL_OUT
NL01V10NVCC0PLL0OUT
NVCC_GPIO
0R
PIR7602
C155
COC155
220n
PIC15601
PIC15602
0R
PIR7402
C156
COC156
22u
C
C163
COC163
220n
C164
COC164
220n
DESIGN NOTE:
+NVCC_RGMII connected to 2V5
for RGMII 2V5 operation.
C165
COC165
220n
DESIGN NOTE:
+NVCC_ENET connected to 2V5 to be
able to easy connect cpu with ethernet
phy (which is supplied from 2V5).
C174
COC174
220n
T12
PIU10T12
T15
PIU10T15
T17
PIU10T17
T19
PIU10T19
T8
PIU10T8
U11
PIU10U11
U12
PIU10U12
U15
PIU10U15
U17
PIU10U17
U8
PIU10U8
U19
PIU10U19
V8
PIU10V8
V19
PIU10V19
W3
PIU10W3
W7
PIU10W7
W8
PIU10W8
W9
PIU10W9
W10
PIU10W10
DESIGN NOTE:
design guide: GPANAIO must be a no
connect. VDD_FA and FA_ANA should
be tied to GND.
W11
W12
PIU10W12
W13
PIU10W13
W15
PIU10W15
W16
PIU10W16
W17
PIU10W17
W18
PIU10W18
W19
PIU10W19
Y5
PIU10Y5
Y24
PIU10W11
PIU10Y24
Variant:
Title:
iMX6 Rex Module
Page Contents:
[11] - CPU - POWER.SchDoc
Prototype
Checked by
MCIMX6Q5EYM10AC
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
11
of
20
D
1
2
3
4
5
6
7
8
CPU - UNUSED PINS
A
A
COU1O
U1O
i.MX6Q - UNUSED
A21
SD1_DATA0 / ECSPI5_MISO / GPT_CAPTURE1 / <GPIO1_IO16>
C20
PIU10C20 SD1_DATA1 / ECSPI5_SS0 / PWM3_OUT / GPT_CAPTURE2 / <GPIO1_IO17>
E19
PIU10E19 SD1_DATA2 / ECSPI5_SS1 / GPT_COMPARE2 / PWM2_OUT / WDOG1_B / <GPIO1_IO19> / WDOG1_RESET_B_DEB
PIU10N25
IPU1_CSI0_DATA12 / EIM_DATA08 / UART4_TX_DATA / <GPIO5_IO30> / ARM_TRACE09
IPU1_CSI0_DATA13 / EIM_DATA09 / UART4_RX_DATA / <GPIO5_IO31> / ARM_TRACE10
IPU1_CSI0_DATA14 / EIM_DATA10 / UART5_TX_DATA / <GPIO6_IO00> / ARM_TRACE11
IPU1_CSI0_DATA15 / EIM_DATA11 / UART5_RX_DATA / <GPIO6_IO01> / ARM_TRACE12
IPU1_CSI0_DATA16 / EIM_DATA12 / UART4_RTS_B / <GPIO6_IO02> / ARM_TRACE13
IPU1_CSI0_DATA17 / EIM_DATA13 / UART4_CTS_B / <GPIO6_IO03> / ARM_TRACE14
IPU1_CSI0_DATA18 / EIM_DATA14 / UART5_RTS_B / <GPIO6_IO04> / ARM_TRACE15
IPU1_CSI0_DATA19 / EIM_DATA15 / UART5_CTS_B / <GPIO6_IO05>
PIU10M2
IPU1_CSI0_VSYNC / EIM_DATA01 / <GPIO5_IO21> / ARM_TRACE00
IPU1_CSI0_HSYNC / CCM_CLKO1 / <GPIO5_IO19> / ARM_TRACE_CTL
IPU1_CSI0_PIXCLK / <GPIO5_IO18> / ARM_EVENTO
PIU10N2
ECSPI1_MOSI / ENET_TX_DATA3 / AUD5_TXD / KEY_ROW0 / UART4_RX_DATA / <GPIO4_IO07> / DCIC2_OUT
ECSPI1_MISO / ENET_MDIO / AUD5_TXFS / KEY_COL1 / UART5_TX_DATA / <GPIO4_IO08> / SD1_VSELECT
PIU10V6
ECSPI1_SCLK / ENET_RX_DATA3 / AUD5_TXC / KEY_COL0 / UART4_TX_DATA / <GPIO4_IO06> / DCIC1_OUT
PIU10W5
ECSPI1_SS0 / ENET_COL / AUD5_RXD / KEY_ROW1 / UART5_RX_DATA / <GPIO4_IO09> / SD2_VSELECT
U6
PIU10U6
IPU1_DISP0_DATA07 / IPU2_DISP0_DATA07 / ECSPI3_RDY / <GPIO4_IO28>
PIU10R24
IPU1_DISP0_DATA09 / IPU2_DISP0_DATA09 / PWM2_OUT / WDOG2_B / <GPIO4_IO30>
IPU1_DISP0_DATA10 / IPU2_DISP0_DATA10 / <GPIO4_IO31>
IPU1_DISP0_DATA13 / IPU2_DISP0_DATA13 / AUD5_RXFS / <GPIO5_IO07>
IPU1_DISP0_DATA14 / IPU2_DISP0_DATA14 / AUD5_RXC / <GPIO5_IO08>
IPU1_DISP0_DATA15 / IPU2_DISP0_DATA15 / ECSPI1_SS1 / ECSPI2_SS1 / <GPIO5_IO09>
PIU10T25
IPU1_DISP0_DATA20 / IPU2_DISP0_DATA20 / ECSPI1_SCLK / AUD4_TXC / <GPIO5_IO14>
IPU1_DISP0_DATA21 / IPU2_DISP0_DATA21 / ECSPI1_MOSI / AUD4_TXD / <GPIO5_IO15>
IPU1_DISP0_DATA22 / IPU2_DISP0_DATA22 / ECSPI1_MISO / AUD4_TXFS / <GPIO5_IO16>
IPU1_DISP0_DATA23 / IPU2_DISP0_DATA23 / ECSPI1_SS0 / AUD4_RXD / <GPIO5_IO17>
<EIM_ADDR23> / IPU1_DISP1_DATA18 / IPU2_CSI1_DATA18 / IPU2_SISG3 / IPU1_SISG3 / GPIO6_IO06 / SRC_BOOT_CFG23
<EIM_ADDR24> / IPU1_DISP1_DATA19 / IPU2_CSI1_DATA19 / IPU2_SISG2 / IPU1_SISG2 / GPIO5_IO04 / SRC_BOOT_CFG24
NAND_CE0_B / <GPIO6_IO11>
NAND_CE1_B / SD4_VSELECT / SD3_VSELECT / <GPIO6_IO14>
PIU10U22
EIM_DATA16 / ECSPI1_SCLK / IPU1_DI0_PIN05 / IPU2_CSI1_DATA18 / HDMI_TX_DDC_SDA / <GPIO3_IO16> / I2C2_SDA
NAND_ALE / SD4_RESET / <GPIO6_IO08>
NAND_CLE / IPU2_SISG4 / <GPIO6_IO07>
NAND_READY / IPU2_DI0_PIN01 / <GPIO6_IO10>
PIU10A16
MLB_SIG_N
MLB_SIG_P
PIU10A9
<EIM_BCLK> / IPU1_DI1_PIN16 / GPIO6_IO31
<EIM_LBA> / IPU1_DI1_PIN17 / ECSPI2_SS1 / GPIO2_IO27 / SRC_BOOT_CFG26
<EIM_OE> / IPU1_DI1_PIN07 / ECSPI2_MISO / GPIO2_IO25
<EIM_RW> / IPU1_DI1_PIN08 / ECSPI2_SS0 / GPIO2_IO26 / SRC_BOOT_CFG29
<EIM_WAIT> / EIM_DTACK_B / GPIO5_IO00 / SRC_BOOT_CFG25
MLB_DATA_N
MLB_DATA_P
PIU10B10
A10
PIU10A10
MLB_CLK_N
MLB_CLK_P
PIU10A11
B11
PIU10B11
<EIM_EB0> / IPU1_DISP1_DATA11 / IPU2_CSI1_DATA11 / CCM_PMIC_READY / GPIO2_IO28 / SRC_BOOT_CFG27
<EIM_EB1> / IPU1_DISP1_DATA10 / IPU2_CSI1_DATA10 / GPIO2_IO29 / SRC_BOOT_CFG28
EIM_EB2 / ECSPI1_SS0 / IPU2_CSI1_DATA19 / HDMI_TX_DDC_SCL / <GPIO2_IO30> / I2C2_SCL / SRC_BOOT_CFG30
CSI_DATA0_N
CSI_DATA0_P
PIU10E4
E3
PIU10E3
CSI_DATA1_N
CSI_DATA1_P
PIU10D1
D2
PIU10D2
CSI_DATA2_N
CSI_DATA2_P
PIU10E1
E2
PIU10E2
CSI_DATA3_N
CSI_DATA3_P
PIU10F2
F1
PIU10F1
CSI_CLK0_N
CSI_CLK0_P
PIU10F4
F3
PIU10F3
CSI_REXT
PIU10D4
DSI_DATA0_N
DSI_DATA0_P
PIU10G2
G1
PIU10G1
DSI_DATA1_N
DSI_DATA1_P
PIU10H2
H1
PIU10H1
DSI_CLK0_N
DSI_CLK0_P
PIU10H3
H4
PIU10H4
DSI_REXT
PIU10G4
B21
SD1_CMD / ECSPI5_MOSI / PWM4_OUT / GPT_COMPARE1 / <GPIO1_IO18>
D20
PIU10D20 SD1_CLK / ECSPI5_SCLK / GPT_CLKIN / <GPIO1_IO20>
PIU10B21
D18
PIU10D18 SD4_DATA0 / NAND_DQS / <GPIO2_IO08>
B19
PIU10B19 SD4_DATA1 / PWM3_OUT / <GPIO2_IO09>
F17
PIU10F17 SD4_DATA2 / PWM4_OUT / <GPIO2_IO10>
A20
PIU10A20 SD4_DATA3 / <GPIO2_IO11>
B17
SD4_CMD / NAND_RE_B / UART3_TX_DATA / <GPIO7_IO09>
E16
PIU10E16 SD4_CLK / NAND_WE_B / UART3_RX_DATA / <GPIO7_IO10>
PIU10B17
D15
PIU10D15
SD3_RESET / UART3_RTS_B / <GPIO7_IO08>
L20
J25
PIU10J25
L21
PIU10L21
K24
PIU10K24
L22
PIU10L22
L23
PIU10L23
K25
PIU10K25
L25
PIU10L25
<EIM_AD00> / IPU1_DISP1_DATA09 / IPU2_CSI1_DATA09 / GPIO3_IO00 / SRC_BOOT_CFG00
L24
M21
PIU10M21
M22
PIU10M22
M20
PIU10M20
M24
PIU10M24
M23
PIU10M23
N23
PIU10N23
N24
PIU10N24
<EIM_AD10> / IPU1_DI1_PIN15 / IPU2_CSI1_DATA_EN / GPIO3_IO10 / SRC_BOOT_CFG10
<EIM_AD11> / IPU1_DI1_PIN02 / IPU2_CSI1_HSYNC / GPIO3_IO11 / SRC_BOOT_CFG11
<EIM_AD12> / IPU1_DI1_PIN03 / IPU2_CSI1_VSYNC / GPIO3_IO12 / SRC_BOOT_CFG12
<EIM_AD13> / IPU1_DI1_D0_CS / GPIO3_IO13 / SRC_BOOT_CFG13
<EIM_AD14> / IPU1_DI1_D1_CS / GPIO3_IO14 / SRC_BOOT_CFG14
<EIM_AD15> / IPU1_DI1_PIN01 / IPU1_DI1_PIN04 / GPIO3_IO15 / SRC_BOOT_CFG15
PIU10L20
B
PIU10L24
J22
G25
PIU10G25
H22
PIU10H22
H23
PIU10H23
F24
PIU10F24
J21
PIU10J21
F25
PIU10J22
PIU10F25
C25
PIU10C25
E24
EIM_DATA26 / IPU1_DI1_PIN11 / IPU1_CSI0_DATA01 / IPU2_CSI1_DATA14 / UART2_TX_DATA / <GPIO3_IO26> / IPU1_SISG2 / IPU1_DISP1_DATA22
E25
PIU10E25 EIM_DATA27 / IPU1_DI1_PIN13 / IPU1_CSI0_DATA00 / IPU2_CSI1_DATA13 / UART2_RX_DATA / <GPIO3_IO27> / IPU1_SISG3 / IPU1_DISP1_DATA23
G23
PIU10G23 EIM_DATA28 / I2C1_SDA / ECSPI4_MOSI / IPU2_CSI1_DATA12 / UART2_CTS_B / <GPIO3_IO28> / IPU1_EXT_TRIG / IPU1_DI0_PIN13
J19
PIU10J19 EIM_DATA29 / IPU1_DI1_PIN15 / ECSPI4_SS0 / UART2_RTS_B / <GPIO3_IO29> / IPU2_CSI1_VSYNC / IPU1_DI0_PIN14
PIU10E24
N22
PIU10N22
K22
PIU10K22
J24
PIU10J24
K20
PIU10K20
M25
PIU10M25
K21
PIU10K21
K23
PIU10K23
E22
PIU10E22
C
H24
PIU10H24
J23
PIU10J23
W20
PIU10W20
R1
PIU10R1
P6
PIU10P6
R4
PIU10R4
R2
PIU10R2
R3
PIU10R3
R5
PIU10R5
R6
PIU10R6
T2
PIU10T2
R7
PIU10R7
W23
PIU10W23
P5
PIU10P5
W6
PIU10W6
U20
PIU10U20
W21
PIU10W21
T6
PIU10T6
V5
PIU10V5
N25
N20
PIU10N20
P25
PIU10P25
N21
PIU10N21
N19
PIU10N19
IPU1_DI0_PIN02 / IPU2_DI0_PIN02 / AUD6_TXD / <GPIO4_IO18>
IPU1_DI0_PIN03 / IPU2_DI0_PIN03 / AUD6_TXFS / <GPIO4_IO19>
IPU1_DI0_PIN04 / IPU2_DI0_PIN04 / AUD6_RXD / SD1_WP / <GPIO4_IO20>
IPU1_DI0_PIN15 / IPU2_DI0_PIN15 / AUD6_TXC / <GPIO4_IO17>
IPU1_DI0_DISP_CLK / IPU2_DI0_DISP_CLK / <GPIO4_IO16>
PIU10A21
<EIM_CS0> / IPU1_DI1_PIN05 / ECSPI2_SCLK / GPIO2_IO23
<EIM_CS1> / IPU1_DI1_PIN06 / ECSPI2_MOSI / GPIO2_IO24
MLB_CLK / ENET_TX_DATA1 / ESAI_TX2_RX3 / ENET_1588_EVENT0_IN / <GPIO1_IO29>
ESAI_TX0 / ENET_1588_EVENT3_IN / CCM_PMIC_READY / SDMA_EXT_EVENT0 / SPDIF_OUT / <GPIO7_IO12>
ESAI_TX1 / ENET_RX_CLK / SD3_VSELECT / SDMA_EXT_EVENT1 / ASRC_EXT_CLK / <GPIO7_IO13> / SNVS_VIO_5_CTL
ESAI_TX2_RX3 / KEY_ROW7 / CCM_CLKO1 / <GPIO1_IO05> / I2C3_SCL / ARM_EVENTI
ESAI_TX3_RX2 / ENET_1588_EVENT2_IN / ENET_REF_CLK / SD1_LCTL / SPDIF_IN / <GPIO7_IO11> / I2C3_SDA / JTAG_DE_B
ESAI_TX4_RX1 / ECSPI5_RDY / EPIT1_OUT / FLEXCAN1_TX / UART2_TX_DATA / <GPIO1_IO07> / SPDIF_LOCK / USB_OTG_HOST_MODE
ESAI_TX5_RX0 / XTALOSC_REF_CLK_32K / EPIT2_OUT / FLEXCAN1_RX / UART2_RX_DATA / <GPIO1_IO08> / SPDIF_SR_CLK / USB_OTG_PWR_CTL_WAKE
ESAI_TX_HF_CLK / KEY_COL7 / <GPIO1_IO04> / SD2_CD_B
ESAI_RX_FS / WDOG1_B / KEY_COL6 / CCM_REF_EN_B / PWM1_OUT / <GPIO1_IO09> / SD1_WP
ESAI_RX_HF_CLK / I2C3_SCL / XTALOSC_REF_CLK_24M / CCM_CLKO2 / <GPIO1_IO03> / USB_H1_OC / MLB_CLK
USB_OTG_ID / ENET_RX_ER / ESAI_RX_HF_CLK / SPDIF_IN / ENET_1588_EVENT2_OUT / <GPIO1_IO24>
KEY_COL5 / ENET_1588_EVENT0_OUT / SPDIF_OUT / CCM_CLKO1 / ECSPI1_RDY / <GPIO4_IO05> / ENET_TX_ER
ECSPI1_SS1 / ENET_RX_DATA2 / FLEXCAN1_TX / KEY_COL2 / ENET_MDC / <GPIO4_IO10> / USB_H1_PWR_CTL_WAKE
ENET_TX_DATA0 / ESAI_TX4_RX1 / <GPIO1_IO30>
ENET_RX_DATA0 / ESAI_TX_HF_CLK / SPDIF_OUT / <GPIO1_IO27>
FLEXCAN2_TX / IPU1_SISG4 / USB_OTG_OC / KEY_COL4 / UART5_RTS_B / <GPIO4_IO14>
FLEXCAN2_RX / IPU1_SISG5 / USB_OTG_PWR / KEY_ROW4 / UART5_CTS_B / <GPIO4_IO15>
M2
L1
PIU10L1
M4
PIU10M4
M5
PIU10M5
L4
PIU10L4
L3
PIU10L3
M6
PIU10M6
L6
PIU10L6
N2
P4
PIU10P4
P1
PIU10P1
V6
U7
PIU10U7
W5
B
R24
T25
R21
PIU10R21
T23
PIU10T23
T24
PIU10T24
R20
PIU10R20
U25
PIU10U25
T22
PIU10T22
U22
T20
PIU10T20
V24
PIU10V24
W24
PIU10W24
F15
C16
PIU10F15
PIU10C16
A16
C15
PIU10C15
B16
PIU10B16
A9
B9
PIU10B9
B10
A11
E4
C
D1
E1
F2
F4
D4
G2
H2
H3
G4
MCIMX6Q5EYM10AC
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[12] - CPU - UNUSED.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
12
of
20
D
1
2
3
4
5
6
7
8
ETHERNET PHY
A
A
COC175
C175
NLETH0OSCI025MHz
ETH_OSCI_25MHz
PIC17501
PIY302
PIC17502
22pF
COY3
Y3
25MHz
PIY301
COC176
C176
NLETH0OSCO025MHz
ETH_OSCO_25MHz
PIC17601
PIC17602
22pF
COU8
U8
15
LED2 / PHYAD1 PIU8015
17
LED1 / PHYAD0 PIU8017
ClassName: RGMII_RXD
Net Class
i
B
COR83
R83
PIR8301
NLRGMII0RXCLK
RGMII_RXCLK
RGMII_RXDV
PORGMII0RXCLK
7 RGMII_RXCLK
PORGMII0RXDV
7 RGMII_RXDV
22R
RGMII_R_RXCLK
PIR8302
+2V5_ETH_DVDDH
COR87
R87
PIR16202
NF
4k99
PIR8701
7PORGMII0MDC
RGMII_MDC
7PORGMII0MDIO
RGMII_MDIO
7PORGMII0INT
RGMII_INT
35
RX_CLK / PHYAD2
33
PIU8033 RX_DV / CLK125_EN
PIU8035
27
PIU8027 RXD3 / MODE3
28
31
32
RGMII_RXD3
RGMII_RXD2
NLRGMII0RXD1
RGMII_RXD1
NLRGMII0RXD0
RGMII_RXD0
PORGMII0RXD3
7 RGMII_RXD3
PORGMII0RXD2
7 RGMII_RXD2
PORGMII0RXD1
7 RGMII_RXD1
PORGMII0RXD0
7 RGMII_RXD0
PIR8702
CLK125_NDO / LED_MODE
PIR8902
COR162
R162
1k
PIR16201
COR89
R89
4k99
PIR8901
PIR7502
Net Class
i
COR85
R85
PIR8501
COR86
R86
PIR8601
22R
PIR8502
22R
PIR8602
36
PIU8036 MDC
37
PIU8037 MDIO
38
PIU8038 INT_N
NLRGMII0R0MDC
RGMII_R_MDC
RGMII_R_MDIO
NLRGMII0R0MDIO
COR75
R75
10k
42
PIU8042
PIR7501
RGMII_MDC
NLRGMII0MDC
RGMII_MDIO
NLRGMII0MDIO
RGMII_INT
NLRGMII0INT
13
29
PIU8013
PIU8029
49
PIU8049
10 RGMII_RSTn
PORGMII0RSTn
PORGMII0RSTN
RESET_N
VSS_PS
VSS
P_GND
41
PIU8041
i Net Class
2
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
DIFF100
PIU8043
ISET
PIU8048
48
POTRD00N
TRD0_N 3
POTRD00P
TRD0_P 3
POTRD10N
TRD1_N 3
POTRD10P
TRD1_P 3
POTRD20N
TRD2_N 3
POTRD20P
TRD2_P 3
POTRD30N
TRD3_N 3
POTRD30P
TRD3_P 3
LED2
LED1
COR81
R81
PIR8101
COR82
R82
PIR8201
220R
PIR8102
220R
PIR8202
NLENET0LED0LINK
ENET_LED_LINK
NLENET0LED0RX
ENET_LED_RX
POENET0LED0LINK
ENET_LED_LINK 3
POENET0LED0RX
ENET_LED_RX
3
ENET_REF_CLK_R
COR36
R36
PIR3601
PIR3602
22R
NLENET0REF0CLK
ENET_REF_CLK
POENET0REF0CLK
ENET_REF_CLK 7
NLETH0ISET
ETH_ISET
COR84
R84
PIR8401
4k99
PIR8402
COU9
U9
+3V3
PIC17 01
PIC17 02
1
PIU901
9
PIU909
3
PIU903
4
PIU904
5
PIU905
6
PIU906
14
PIU9014
COC177
C177
10u
NLSW0EP
16
34
PIU8034
40
PIU8040
PIU8016
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
PIU8014
+1V2_ETH_DVDDL
14
18
PIU8018
23
PIU8023
26
PIU8026
30
PIU8030
39
PIU8039
AVDDL
AVDDL
AVDDL_PLL
PIU809
+1V2_ETH_AVDDL_PLL
DESIGN NOTE:
Supply voltages range for KSZ9021RN chip:
DVDDL, AVDDL, AVDDL_PLL: min 1.14V max 1.26V
AVDDH: min 3.135V max 3.465V
DVDDH (2V5 operation): min 2.375V max 2.625V
+1V2_ETH
44
PIU8044
FB4
COFB4
PIFB401
COC180
C180
10u
PIC18101
PIC18102
COC181
C181
100n
PIC18201
PIC18202
COC182
C182
10n
PIC18301
PIC18302
COC183
C183
10n
PIC18401
PIC18402
C187
COC187
100n
PIC18 01
PIC18 02
C188
COC188
10n
PIC18901
PIC18902
C189
COC189
10n
C192
COC192
100n
PIC19301
PIC19302
C193
COC193
10n
C195
COC195
100n
PIC19601
PIC19602
C196
COC196
10n
PIC19701
PIC19702
C197
COC197
10n
PIC19801
PIC19802
C198
COC198
10n
C190
COC190
100n
PIC20 01
PIC20 02
C200
COC200
10n
PIC20101
PIC20102
C201
COC201
10n
PIC20201
PIC20202
C202
COC202
10n
COC184
C184
10n
PIC18501
PIC18502
COC185
C185
10n
PIC24801
PIC24802
PIC24901
PIC24902
COC248
C248
10n
COC249
C249
10n
2
BLM18KG101TN1D
PIC18601
PIC18602
C186
COC186
10u
PIC18701
PIC18702
+1V2_ETH_AVDDL_PLL
1
COFB5
FB5
PIFB501
DESIGN NOTE:
Measure signals RGMII_MDC, RGMII_MDIO,
RGMII_INT (if they are 2V5).
PIC180 1
PIC180 2
PIFB402
+1V2_ETH
2
PIFB502
BLM15AX601SN1D
+2V5
PIC19101
PIC19102
C191
COC191
10u
PIC19201
PIC19202
C
+2V5_ETH_DVDDH
1
FB6
COFB6
PIFB601
2
PIFB602
BLM18KG101TN1D
+2V5_ETH_DVDDH
PIC19401
PIC19402
C194
COC194
10u
PIC19501
PIC19502
MODE3
MODE1
PHYAD0
MODE2
MODE0
CLK125_EN
+3V3
PIR9102
B
+1V2_ETH_AVDDL
1
KSZ9021RN
DESIGN NOTE:
Default Ethernet strapping options:
PHYAD2-0: PHY address 0x1
MODE3-0: RGMII mode (10/100/1000 half/full duplex)
CLK125_EM: ref. clock enable
LED_MODE: tri-color dual mode
COC178
C178
10u
2
BLM18KG101TN1D
4
9
COC179
C179
560pF
TP_25MILC
PIFB302
+3V3_ETH_AVDDH
PIU804
PIC17901
PIC17902
PIC17801
PIC17802
+1V2_ETH_DVDDL
FB3
COFB3
1
PIFB301
+1V2_ETH_AVDDL
COTP5
TP5
PITP501
DESIGN NOTE:
DVDH connected to 2V5 for RGMII
2V5 operation
+1V2_ETH
1
AVDDH PIU801
12
AVDDH PIU8012
47
AVDDH PIU8047
+1V2_ETH
PIU902 PIU9013 PIU9012
POPOK03V3
10,
14, 15
POK_3V3
DESIGN NOTE:
All RGMII signal from cpu are 2V5 level, therefore
used pull up to 2V5.
C
MIC33050-4YHL TR
15
OUT_EP PIU9015
8
VIN
OUT PIU908
7
EN
OUT PIU907
SW
10
SW
SNS PIU9010
SW
11 CFF
NLCFF
SW
CFF PIU9011
SW_EP
+2V5_ETH_DVDDH
DVDDH
DVDDH
DVDDH
PIFB801
220R, 2.5A
i
Net Class
ClassName: ENET
DESIGN NOTE:
Bead for opportunity to connect together +1V2_ETH
and +1V375. Beware: Fit bead FB8 only when
supply +1V375 is set to +1V24 and chip
MIC33050-4YHL TR is not fitted.
NF 1
PIFB802
NLTRD00N
TRD0_N
NLTRD00P
TRD0_P
NLTRD10N
TRD1_N
NLTRD10P
TRD1_P
NLTRD20N
TRD2_N
NLTRD20P
TRD2_P
NLTRD30N
TRD3_N
NLTRD30P
TRD3_P
43
LDO_O
+1V2_ETH
COFB8
FB8
PGND
EPAD
AGND
PIU8022
3
PIU803
2
PIU802
6
PIU806
5
PIU805
8
PIU808
7
PIU807
11
PIU8011
10
PIU8010
+1V375
ClassName: ENET
2
13
12
22
TXD3
21
PIU8021 TXD2
20
PIU8020 TXD1
19
PIU8019 TXD0
NLRGMII0TXD3
RGMII_TXD3
NLRGMII0TXD2
RGMII_TXD2
NLRGMII0TXD1
RGMII_TXD1
NLRGMII0TXD0
RGMII_TXD0
PORGMII0TXD3
7 RGMII_TXD3
PORGMII0TXD2
7 RGMII_TXD2
PORGMII0TXD1
7 RGMII_TXD1
PORGMII0TXD0
7 RGMII_TXD0
TXRXM_A
TXRXP_A
TXRXM_B
TXRXP_B
TXRXM_C
TXRXP_C
TXRXM_D
TXRXP_D
46
45
PIU8045
PIU8046
SW_EP
PORGMII0TXCLK
7 RGMII_TXCLK
PORGMII0TXEN
7 RGMII_TXEN
XI
XO
24
PIU8024 GTX_CLK
25
PIU8025 TX_EN
NLRGMII0TXCLK
RGMII_TXCLK
NLRGMII0TXEN
RGMII_TXEN
PIR9402
R91
COR91
10k
R94
COR94
10k
PIR9502
R95
COR95
10k
PIR9602
R96
COR96
10k
PIR9702
R97
COR97
10k
PIR9802
R98
COR98
10k
+3V3_ETH_AVDDH
1
FB7
COFB7
PIFB701
2
PIFB702
BLM18KG101TN1D
PIR9101
PIR9401
PIR9501
PIR9601
PIR9701
PIR9801
ENET_REF_CLK_R
NLENET0REF0CLK0R
RGMII_RXDV
NLRGMII0RXDV
RGMII_R_RXCLK
NLRGMII0R0RXCLK
LED2
NLLED2
LED1
NLLED1
RGMII_RXD3
NLRGMII0RXD3
RGMII_RXD2
NLRGMII0RXD2
PIC19 01
PIC19 02
C199
COC199
10u
PIC190 1
PIC190 2
RGMII_RXD1
RGMII_RXD0
LAYOUT NOTE:
Be sure you place R99 directly on
the net to minimize stubs.
PIR9 02
R99
COR99
1k
PIR9 01
D
LED_MODE
PIR10102
PIR10101
R101
COR101
1k
PIR10202
R102
COR102
1k
PIR10201
PHYAD2
PHYAD1
Variant:
Title:
iMX6 Rex Module
Page Contents:
[13] - ETHERNET PHY.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
13
of
20
D
1
2
3
4
5
6
7
8
SPI FLASH, LED
A
A
SPI NOR FLASH
6
PIU1006 SCK
5
PIU1005 SI
2
PIU1002 SO
1
PIU1001 CE
8POCSPI30CLK
CSPI3_CLK
8POCSPI30MOSI
CSPI3_MOSI
8POCSPI30MISO
CSPI3_MISO
8POCSPI30CS2
CSPI3_CS2
EP
COU10
U10
SST25VF016B-75-4I-QAF-ND
8
VDD PIU1008COR109
7
R109
10k
PIR10902
PIR10901
HOLD PIU1007COR110
3
R110
10k
PIR11002
WP PIU1003 PIR11001
4
VSS PIU1004
+3V3
PIC20301
PIC20302
COC203
C203
100n
9
PIU109
B
B
POWER LED
USER DEFINED LED
+3V3
PIR1 302
+3V3
PIR1 402
R113
COR113
220R
R114
COR114
220R
PIR1 502
Green
COD2
C
D
10
USER_LED
POUSER0LED
1
PIQ201
Q2
COQ2
2N7002BKW,115
S
PIQ101
Q1
COQ1
2N7002BKW,115
G
G
D
3
PID301
PIQ203
S
10,
13, 15 POK_3V3
POPOK03V3
1
D3
COD3
Orange
PIR1 501
3
PID201
PIQ103
PIR1 401
PID302
R115
COR115
10k
D2
PIR1 301
PID202
C
+3V3
2
PIQ202
2
PIQ102
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[14] - SPI FLASH, LEDS.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
14
of
20
D
1
2
3
4
5
6
7
8
POWER +3.3V, +1.375V, +3.0_ALWAYS CON
A
A
+VIN
+5V_LDO1
Note:
LDORFIN TIED TO GND = LDO 5V
LDORFIN TIED TO VCC = LDO 3.3V
COR116
R116
PIR11601
PIR11602
0R
+5V_PVCC1
+5V_VCC1
C213
C214
C215
PIC2COC213
1301
PIC2COC214
1401
PIC2COC215
1501
PIC2100µF
1302
PIC2100µF
1402
PIC2100µF
1502
7
D2/S1_3
6
PIQ306 D2/S1_2
5
PIQ305 D2/S1_1
PIC21101
G1
B
100n
1R
PIR12202
NLUGATE103V3
UGATE1_3V3
4
PIQ304
17
PIU11017
15
PIU11015
16
NLPHASE103V3
PHASE1_3V3
PIU11016
NLLGATE103V3
LGATE1_3V3
18
PIU11018
10
PIU11010
14
POPOK02V5
16
POK_2V5
PIU11014
2
PIQ30 PIQ302
3
SI4816BDY-T1-GE3
COR122PIR12201
R122
A/S2_1
A/S2_2
G2
1
PIQ301
PIC21102
9
PIU1109
PIR12302
11
NLFB103V3
FB1_3V3
PIU11011
COR123
R123
39k
SET OUT1
VOTLAGE
TO 3.3V
21
PIU11021
PIR12301
COR125PIR12501
R125
200k PIU11012
12
PIR12502
29
PIR12602
PIU11029
COR126
R126
10k5
ON_5V_LDO
+5V_VCC1
4
PIU1104
20
PIU11020
PIR12601
2
PIU1102
PIR12702
+5V_LDO1
PIR13102
R127
COR127
10k
+5V_LDO1
PIR13202
R131
COR131
10k
NF
PIR12701
PIR13101
R132
COR132
10k
BOOT2
PIU11024
PIR12101
ON_5V_LDO
NLON05V0LDO
PHASE1
PHASE2
LGATE1
23
NLLGATE201V375
LGATE2 PIU11023 LGATE2_1V375
25
PGND
PIU11022
EN1
OUT2
PIU11030
BYP
EN2
PIU11027
FB1
REFIN2
PIU11032
ILIM2
31
PIU11031
ILIM1
VREF3
5
PIU1105
SKIP#
REF
PIU1101
EN LDO
POK1
PIU11013
SECFB
POK2
PIU11028
TON
D
3
NF
PIU103
10 PMIC_ON_REQ
POPMIC0ON0REQ
NF
DESIGN NOTE:
+1.375V / max 5.8A
(Required 4.25A)
PIL202
3u3
COC216
C216
PIC21601
PIC21602
PIC217
C21COC217
701
PIC232
C23COC232
201
PI100µF
C21702
PI100µF
C23202
G2
B
EN_1V375
PIQ402 PIQ403
32
REFIN2_1V375
COR124
R124
PIR12401
200k
PIR12402
COC218
NL0VREF103V301V375 C218
+VREF1_3V3_1V375
PIC21801
NL0VREF102V01V375
+VREF1_2V_1V375
10n
PIC21802
COC219
C219
100n
PIC21901 PIC21902
13
28
ISL6236AIRZ
+3V3
+3V0_ALWAYS
PIR12902
PIR130 2
R129
COR129
10k
R130
COR130
10k
POK
HIGH: POWER IS OK
PIR130 1
0R
0R
R107
COR107
R108
COR108
PIR10702
PIR10701
PIR10802
PIR10801
POK_3V3
10, 13, 14
POPOK03V3
POK_1V375
16
POPOK01V375
PIR13 01
Q5
COQ5
2N7002BKW,115
Q8
COQ8
2N7002BKW,115
S
PIQ801
COL2
L2
PIL201
SI4816BDY-T1-GE3
27
1
PITP701
COTP7
TP7
TP_25MILC
TON
GND:400kHz/500kHz
NC:400kHz/300kHz
VCC:200kHz/300kHz
2
3
1
D
C
R133
COR133
10k
G1
30
PIR12901
PIQ502
G
PIQ803
4
PIQ404
S
PIQ501
1
PIQ401
7
6
PIQ406
5
PIQ405
PIQ407
+1V375
100µF
R128
COR128
0R
NF
G
1
100n
POK_3V3_R
NLPOK03V30R
POK_1V375_R
NLPOK01V3750R
PIR13 02
D2/S1_3
D2/S1_2
D2/S1_1
PIC21202
22
OUT1
GND
PIC21201
COC210
C210
10uF
35V
NLPHASE201V375
PHASE2_1V375
EN_1V375
NLEN01V375
PIQ503
PIR12102
UGATE1
PIR12801
PIR13201
COC212
C212
COR121
R121
24
PIU11025
8
LDOREFIN
8
PIU1108
COQ4
Q4
1R
26
NLUGATE201V375
UGATE2 PIU11026 UGATE2_1V375
+5V_VCC1
PIR12802
3
BOOT1
PIU1107
33
+5V_VCC1
VIN
PIQ408
7
LDO
PIC210 1
PIC210 2
D1
COC211
C211
PIQ307
PIU103
A/S2_2
4µ7
6
PIU1106
+VIN
A/S2_1
PIL102
PIU109
COC207
C207
1u
2
COL1
L1
PIL101
DESIGN NOTE:
+3.3V / max 5A
(Required 2A)
COQ3
Q3
D1
+3V3
COU11
U11
VCC
PIQ308
PIC20701
PIC20702
COC206
C206
1u
COC205
C205
100n
EP
COC209
C209
10uF
35V
8
PITP601
TP_25MILC
COC208
C208
1uF
50V
PIR11802
10R
PVCC
PIC20901
PIC20902
COTP6
TP6
PIR11801
PIC20601
PIC20602
+VIN
PIC20801
PIC20802
NF
PIR11702
0R
19
NF
PIR11701
COR118
R118
PIC20501
PIC20502
COC204
C204
10u
3
COR117
R117
PIC20401
PIC20402
PIQ802
SET OUT2
VOTLAGE
TO 1V375
R119
COR119
REFIN2_1V375
NLREFIN201V375
R120
COR120
PIR11901
R136
COR136
2
NF
PIR12002
PIR13602
14K
+VREF1_3V3_1V375
4k99
+VREF1_2V_1V375
PIR11902
PIR12001
DESIGN NOTE:
voltage created by voltage divider
connected to 3V3
REFIN2=3V3*10K/(10K+14K)=1.375V
C
10k
PIR13601
+VIN
+3V0_ALWAYS
PIC2 0 1
PIC2 0 2
SW_3V0_SNVS
NLSW03V00SNVS
10uF
35V
1
2
PIL301
PIL302
VLCF4020T-100MR85
PIR13802
U12
COU12
2
PIU1202
3
PIU1203
+3V0_ALWAYS
R106
COR106
PIR10602
0R
PIR10601
8
PIU1208
VIN
4
NC
6
PIU1206 AGND
1
PIU1201 PGND
11
PIU12011 EP
PIU1204
9
SW PIU1209
10
VOS PIU12010
EN
SLEEP
DESIGN NOTE:
+3.0V / max 500mA
(Required 10mA)
PITP1 01
L3
COL3
C220
COC220
TP11
COTP11
TP_25MILC
R138
COR138
330k
PIC2 101
PIC2 102
C221
COC221
10u
PIC2 201
PIC2 202
C222
COC222
10u
PIR13801
7
POK_3V0_SNVS
NLPOK03V00SNVS
5
FB_3V0_SNVS
NLFB03V00SNVS
PG
PIU1207
FB
PIU1205
R93
COR93
PIR9301
PIR13902
0R
PIR9302
EN_1V375
R139
COR139
120k
TPS62175DQCT
D
PIR13901
DESIGN NOTE:
Voltage treeshold on FB pin Vref = 800mv
DESIGN NOTE:
resistor values for output voltage 3V0:
R138=R139*(Vout/Vref-1)=120k*(3.0/0.8-1)=330k
backward control:
Vout=Vref*(R138+R139)/R139=0.8*(330k+120k)/120k=3V
Variant:
Title:
iMX6 Rex Module
Page Contents:
[15] - PWR 3V3, 1V375.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
15
of
20
D
1
2
3
4
5
6
7
8
POWER +2.5V, +1.5V CON
A
A
Note:
VARIANT: PVCC pin connected from LDO
+VIN
+5V_LDO2
Note:
LDORFIN TIED TO GND = LDO 5V
LDORFIN TIED TO VCC = LDO 3.3V
COR140
R140
PIR14001
PIR14002
0R
+5V_PVCC2
+5V_VCC2
C233
C234
PIC2COC233
3 01
PIC2COC234
3401
PIC2100µF
3 02
PIC2100µF
3402
PIL402
7
D2/S1_3
6
PIQ606 D2/S1_2
5
PIQ605 D2/S1_1
PIQ607
PIC23001
G1
1
PIC23002
COR145
R145
PIR14501
PIR14502
1R
100n
PIQ601
6
PIU1306
NLUGATE102V5
UGATE1_2V5
NLPHASE102V5
PHASE1_2V5
4
NLLGATE102V5
LGATE1_2V5
PIQ604
A/S2_1
A/S2_2
G2
16
PIU13016
18
PIU13018
10
2
PIQ603 PIQ602
3
SI4816BDY-T1-GE3
15
PIU13015
PIU13010
NLPOK01V5
POK_1V5
B
17
PIU13017
14
PIU13014
9
PIU1309
PIR14702
11
NLFB102V5
FB1_2V5
PIU13011
COR147
R147
27k
SET OUT1
VOTLAGE
TO 2.5V
21
PIU13021
COR149
R149
PIR14701
PIR14901
PIR14902
200k
PIR150 2
12
PIU13012
29
PIU13029
COR150
R150
10k5
ON_5V_LDO_2
+5V_VCC2
4
PIU1304
20
PIU13020
PIR150 1
2
PIU1302
BOOT1
PIR15202
PIR15101
BOOT2
26
PHASE2
PIU13025
LGATE1
LGATE2
PIU13023
OUT1
PGND
PIU13022
EN1
OUT2
PIU13030
BYP
EN2
27
PIU13027
FB1
REFIN2
PIU13032
ILIM2
31
PIU13031
ILIM1
VREF3
5
PIU1305
SKIP#
REF
PIU1301
EN LDO
POK1
PIU13013
SECFB
POK2
PIU13028
TON
25
23
COC231
C231
COR146
R146
24
PHASE1
GND
COQ7
Q7
PIU13024
PIU13026
PIR14601
PIR14602
PIC23101
1R
1
PIQ701
4
NLLGATE201V5
LGATE2_1V5
PIQ704
30
1
DESIGN NOTE:
+1.5V / max 5A
(Required 2.5A)
+1V5_DDR
COL5
L5
PIL501
COTP9
TP9
TP_25MILC
PIL502
3u3
COC235
C235
PIC23501
PIC23502
PIC23601
PIC23602
COC236
C236
100µF
G2
22
32
PITP901
100µF
B
PIQ702 PIQ703
SI4816BDY-T1-GE3
POPOK01V375
POK_1V375
15
REFIN2_1V5
COR148
R148
PIR14801
200k
PIR14802
NL0VREF103V301V5
+VREF1_3V3_1V5
COC237
C237
10n
PIC23701 PIC23702
NL0VREF102V01V5
+VREF1_2V_1V5
COC238
C238
100n
PIC23801 PIC23802
13
28
PIU130
ISL6236AIRZ
33
+3V0_ALWAYS +3V0_ALWAYS
PIR15302
PIR15201
R153
COR153
10k
PIR15301
PIR15402
R154
COR154
10k
POK
HIGH: POWER IS OK
PIR15401
POK_2V5_R
NLPOK02V50R
POK_1V5_R
NLPOK01V50R
NF
G1
7
6
PIQ706
5
PIQ705
PIQ707
COC229
C229
10uF
35V
NLPHASE201V5
PHASE2_1V5
R152
COR152
0R
R155
COR155
10k
D2/S1_3
D2/S1_2
D2/S1_1
PIC23102
100n
NLUGATE201V5
UGATE2_1V5
ON_5V_LDO_2
NLON05V0LDO02
PIR15 02
8
LDOREFIN
8
PIU1308
UGATE2
+5V_VCC2
R151
COR151
10k
PIU1307
UGATE1
+5V_VCC2
PIR15102
3
VIN
PIQ708
7
LDO
PIC2 901
PIC2 902
A/S2_2
DESIGN NOTE:
+2.5V / max 5A
(Required 350mA)
3u3
COC230
C230
PIU130
D1
COL4
L4
PIL401
COQ6
Q6
D1
+2V5
PIU1309
+VIN
3
PIQ608
COU13
U13
COC226
C226
1u
A/S2_1
TP_25MILC
COC227
C227
1uF
50V
PIC2 601
PIC2 602
COC225
C225
1u
COC224
C224
100n
EP
PITP801
COC228
C228
10uF
35V
PIC2 501
PIC2 502
PIR14202
10R
PVCC
COTP8
TP8
8
PIC2 801
PIC2 802
PIR14201
VCC
+VIN
PIC2 701
PIC2 702
NF
PIR14102
0R
19
NF
PIR14101
COR142
R142
PIC2 401
PIC2 402
COC223
C223
10u
2
COR141
R141
PIC2 301
PIC2 302
0R
0R
R163
COR163
R164
COR164
PIR16302
PIR16301
PIR16402
PIR16401
POK_1V5
POK_2V5
15
POPOK02V5
TON
GND:400kHz/500kHz
NC:400kHz/300kHz
VCC:200kHz/300kHz
PIR15 01
SET OUT2
VOTLAGE
TO 1V5
C
REFIN2_1V5
NLREFIN201V5
R134
COR134
PIR13401
R135
COR135
NF
PIR13501
R158
COR158
PIR15802
12k
+VREF1_3V3_1V5
3k3
+VREF1_2V_1V5
PIR13402
PIR13502
DESIGN NOTE:
voltage created by voltage divider
connected to 3V3
REFIN2=3V3*10K/(10K+12K)=1.5V
C
10k
PIR15801
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[16] - PWR 2V5, 1V5.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
16
of
20
D
1
2
3
4
5
6
7
8
MECHANICAL
A
A
TESTPOINT
PITP10 1
MOUNTING HOLES
COTP10
TP10
TP_25MILC
COMH1
MH1
COMH2
MH2
COMH3
MH3
COMH4
MH4
PIMH10
PIMH201
PIMH301
PIMH401
FIDUCIALS
COFID1
FID1
COFID2
FID2
COFID3
FID3
COFID4
FID4
Mounting holes 5mm pad 2.2mm drill
BOARD MOUNTING HOLES - ONE IN EACH CORNER
PCB
FIRMWARE
COPCB1
PCB1
COFIRMWARE0FOR0U10
FIRMWARE_FOR_U10
B
B
FIRMWARE
uBOOT
PCB
iMX6 Rex V1I1 PCB
iMX6_REX_uBOOT 1.0
LICENCE
ORIGINAL AUTHOR: FEDEVEL 2013
WEBSITE: http://www.iMX6Rex.com
****************
This is a human-readable summary of the Legal Code (read full licence at:
http://creativecommons.org/licenses/by-nc-nd/3.0/deed.en_GB).
You are free:
---------------to copy, distribute, display, and perform the work
C
C
Under the following conditions:
---------------Attribution ? You must give the original author credit.
Non-Commercial ? You may not use this work for commercial purposes.
No Derivative Works ? You may not alter, transform, or build upon this work.
With the understanding that:
---------------Waiver ? Any of the above conditions can be waived if you get permission from the copyright holder.
Public Domain ?
the licence.
Where the work or any of its elements is in the public domain under applicable law, that status is in no way affected by
Other Rights ? In no way are any of the following rights affected by the licence:
- Your fair dealing or fair use rights, or other applicable copyright exceptions and limitations;
- The author's moral rights;
- Rights other persons may have either in the work itself or in how the work is used, such as publicity or privacy rights.
D
Notice ?
For any reuse or distribution, you must make clear to others the licence terms of this work.
Variant:
Title:
iMX6 Rex Module
Page Contents:
[17] - MECH.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
17
of
20
D
1
2
3
4
5
6
7
8
CPU - POWER SEQUENCING
A
A
OTHER POWERS
LEVEL
FROM
USED BY
+USB_VBUS
5V
connector
+DDR_VREF
0V75
+1V5_DDR
+1V2_VDD_ARM_CAP
1V2
iMX
cpu, core caps
+1V1_VDDSOC_CAP
1V1
iMX
core caps, cpu-sata, cpu-pcie, cpu-hdmi
cpu
ref. for DDR memories, gen. with volt. divider
B
B
CONTROLED BY
NAME
LEVEL
USED BY
0
POK_3V3
+1V2_ETH
1V2
ethernet phy
POK_2V5
+3V3
3V3
cpu, pull up
POK_1V5
+2V5
2V5
cpu, ethernet phy
1
2
3
4
5
POWER UP SEQUENCE
C
C
POK_1V375
EN_1V375
+VIN
+1V5_DDR
+1V375
+3V0_ALWAYS
+VIN
1V5
cpu, memory
1V375
cpu, cpu core voltages
3V0
cpu, supervisor, pull up
4.75V-25V
switching power supplies
TIME
D
Variant:
Title:
iMX6 Rex Module
Page Contents:
[18] - POWER SEQUENCING.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
7
Size:
DWG NO
Date:
27. 9. 2013
V1I1
Sheet
8
18
of
20
D
1
2
3
4
5
6
7
8
DOC: REVISION HISTORY
A
01-AUG-2013
Some HDMI and Ethernet signals swapped on J1
19-AUG-2013
Signals for SPI FLASH has been moved to CSPI3
A
Added additional capacitors to +2V5 and +1V1_VDDSOC_CAP
21-AUG-2013
Added resistor from CPU_XTALO to GND
I2C3_SDA and I2C3_SCL has been moved to another CPU pins
22-AUG-2013
Always powered voltage change level to 3V0 - supply voltage +3V0_ALWAYS
Added bead to connect together +1V2_ETH and +1V375 (Only for testing purpose).
B
23-AUG-2013
Added resistor to connect SLEEP pin of TPS62175DQCT to +3V0_ALWAYS.
27-AUG-2013
On connector J1 added BOOT_MODE signal to select boot source.
B
C
C
D
Variant:
CLOCKS (CPU & PCIE)
Title:
iMX6 Rex Module
Page Contents:
[19] - DOC REVISION HISTORY.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
Size:
DWG NO
Date:
27. 9. 2013
7
V1I1
Sheet
of
19
8
20
D
1
2
3
4
5
6
7
8
A
A
TEMPLATE NOTES
Set Project Parameters
1) Go to Project -> Project Options -> Parameters
2) Set Company, Project and VersionRevision
B
B
[15] - PWR 3V3, 1V375.SchDoc
[15] - PWR 3V3, 1V375.SchDoc
[17] - MECH.SchDoc
[17] - MECH.SchDoc
Mark Not Fitted Components as
NF
Net Class Example
i Net Class
ClassName: PCIE
Differential signal example
C
C
TITLE Examples (You can change the color to reflect your company color)
PAGE TITLE
Peripheral / Group of component title
Smaller Ttitle
Schematic Status Explanation
DRAFT - Very early stage of schematic, ignore details.
PRELIMINARY - Close to final schematic.
D
Variant:
CHECKED - There should not be any mistakes. Tell the engineer if you find one.
RELEASED - A board with this schematic has been sent to production.
Title:
iMX6 Rex Module
Page Contents:
iMX6 Rex_V1I1 Project.SchDoc
Prototype
Checked by
Revision:
1
2
3
4
5
6
Size:
DWG NO
Date:
27. 9. 2013
7
V1I1
Sheet
of
20
8
20
D
COMH4 COC210
COMH1
COFID3
COR82
COR81
COR28
COR94
COR39
COC16COC228
COC8COR8COC38
COC36
COC37
COC34
COC35
COR29
COR100
COR102
COC239COC15
PAFID301
PAC22802
COU4
PAC1601 PAC1602
COC2 PAC1502 PAC1501
COR144
COC240
COR26
COR24
COR25
COR40
COC242
COQ4 PAC21001
COQ6
PAC22801
COR51
COC241
COR143
COR137
PAC201
PAC202
COR22
COR45
COR162
COR111
COR38
COR84
COR49
COFB7
COR21
COR44
P
A
C
2
4
1
0
1
P
A
C
2
4
1
0
2
COR65
COC17
COR85
COL2
COR89
COR99
COR75
COL4
COU8
PAMH401 PAU8049
PAC21002
PAQ401
PAQ408
PAQ402
PAQ407
PAQ403
PAQ406
PAQ404
PAQ405
PAU8024 PAU8023 PAU802 PAU8021 PAU802 PAU8019 PAU8018 PAU8017 PAU8016PAU8015 PAU8014 PAU8013
PAR9402 PAR9401 PAR8201 PAR8202
PAU8025
PAU8012
PAU8026
PAU8011
PAU8027
PAU8010
PAU8028
PAU809
PAU8029
PAU808
PAU8030
PAU807
PAU8031
PAU806
PAU8032
PAU805
PAU8033
PAU804
PAU8034
PAU803
PAU8035
PAU802
PAU8036
PAU801
PAU8037 PAU8038 PAU8039 PAU8040 PAU8041 PAU8042 PAU8043 PAU804 PAU8045PAU8046 PAU8047 PAU8048
PAL201
PAR8501
PAR8901
PAR9901
PAR8701
PAR8602
PAR3601
PAR9802 PAR9801
PAC3602 PAC3601 PAC3702 PAC3701 PAC3402 PAC3401
PAC23901
PAR2602
PAR14301 PAR14302
PAR8401 PAR8402 PAFB702 PAFB701 PAR11102 PAR11101
PAR2401 PAR14402 PAR2501
PAR4002
PAR4001
PAC24201
PAC24002
PAC24202
PAC24001
PAR13701 PAR13702 PAR4502 PAR4501
PAR2201 PAR2202
PAR5101 PAR5102
PAR2101 PAR2102
PAR3801 PAR3802
PAR4902 PAR4901
PAR4402 PAR4401
PAC8601 PAC8501
PAU10A24 PAU10B24 PAU10C24
PAU10D24
PAU10E24 PAU10F24 PAU10G24 PAU10H24
PAU10J24
PAU10K24 PAU10L24 PAU10M24
PAU10N24
PAU10P24 PAU10R24 PAU10T24
PAU10U24
PAU10V24 PAU10W24 PAU10Y24 PAU10AA24
PAU10AB24
PAU10AC24 PAU10AD24 PAU10AE24
PAU10D23
PAU10J23
PAU10N23
PAU10U23
PAU10AB23
PAU10D22
PAU10J22
PAU10N22
PAU10U22
PAU10AB22
PAU10D19
PAU10J19
PAU10N19
PAU10U19
PAU10AB19
PAU10D18
PAU10J18
PAU10N18
PAU10U18
PAU10AB18
PAU10D15
PAU10J15
PAU10N15
PAU10U15
PAU10AB15
PAU10D14
PAU10J14
PAU10N14
PAU10U14
PAU10AB14
PAU10A13 PAU10B13 PAU10C13 PAU10D13 PAU10E13 PAU10F13 PAU10G13 PAU10H13 PAU10J13 PAU10K13 PAU10L13 PAU10M13 PAU10N13 PAU10P13 PAU10R13 PAU10T13 PAU10U13 PAU10V13 PAU10W13 PAU10Y13 PAU10A 13 PAU10AB13 PAU10AC13 PAU10AD13 PAU10AE13
COC213
COC83
COR37
PAC21402 COR53
COC215
PAU10D11
PAU10J11
PAU10N11
PAU10U11
PAU10AB11
PAU10D10
PAU10J10
PAU10N10
PAU10U10
PAU10AB10
PAR5402 PAR5401
PAU10D9
PAU10J9
PAU10N9
PAU10U9
PAU10AB9
PAC8302 PAR3702
2
PAL102 PALCOC220
101 PAC21301 PAC2130COC84
COC63
COC65
PAC8301 PAR3701
PAR5301
PAC8401 PAR5302
PAC8402
PAU40MECH08
PAR802 PAR801
PAMH101
PAC3801 PAC3802 PAC3501 PAC3502
PAU40MECH05
PAU40A9 PAU40B9
PAU40C9
PAU40D9
PAU40E9 PAU40F9
PAU40G9
PAU40H9
PAU40J9 PAU40K9 PAU40L9
PAU40M9
PAU40N9
PAU40MECH10
PAU40MECH16
PAU40MECH15
PAU40A8 PAU40B8 PAU40C8 PAU40D8 PAU40E8 PAU40F8 PAU40G8 PAU40H8 PAU40J8 PAU40K8 PAU40L8 PAU40M8 PAU40N8 PAU40P8 PAU40R8 PAU40T8
PAR101
PAU40MECH06
PAU40MECH04
PAR102
PAC802 PAC801
PAC23902
PAR9702 PAR9701
COC216
COC232
COC86
COC85
PAL202
PATP701
COR50
COC217
PAR9102 PAR9101 COR91
PAC21701 PAC21601 COTP6
PAC23201 PAR5002COY2
PAC8602 PAC8502
COL1PAC21702 PAC21602 PATP601 COC214
PAY202COR54
PAY201
PAC23202
PAC21401
PAR10 01 PAR10002
PAR2402 PAR14401 PAR2502
PAC1702
PAC1701
PAR16202 PAR8801
PAR5001
PAR3901 PAR3902
PAR10201 PAR10202 PAR2902 PAR2901
PAR2601
PAR8502 COR86
PAR8902 COR36
PAR9902
COR87
PAR7502 PAR7501
PAR9502
PAR9501COR98
COR96
COR97
COR88
PAR8702 PAR8601 PAR3602
COR95
PAR16201 PAR8802
PAR9602 PAR9601
COR1
COTP7
PAR6502 PAR6501
PAR8102 PAR8101 PAR2802 PAR2801
PAU40MECH03
PAU40A7 PAU40B7
PAU40C7
PAU40D7
PAU40E7 PAU40F7
PAU40G7
PAU40H7
PAU40M7
PAU40N7
PAU40A3 PAU40B3
PAU40C3
PAU40D3
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20751CAP 10951CAP
1015CAP 2015CAP 1006CAP 2006CAP
20171CAP 10171CAP
7031UAP
6031UAP
105PTAP
1021 RAP 2021 RAP 20531CAP
1047RAP
20951RAP 10951RAP
50HCEM05UAP
8031UAP
42031UAP
20641RAP
7P05UAP 7N05UAP
8R05UAP
9T05UAP
20422CAP
10741RAP 20741RAP
71031UAP
10522CAP
7R05UAP
8T05UAP
20 51RAP 10 51RAP
61031UAP51031UAP 41031UAP 31031UAP 21031UAP 1 031UAP 01031UAP 9031UAP
81031UAP
91031UAP
7T05UAP
51HCEM05UAP
20871CAP
205BFAP
20091CAP 20202CAP 20291CAP
10 91CAP 10202CAP 10291CAP
2021RAP 1002CAP
41HCEM05UAP
105BFAP 20381CAP 10381CAP
10002CAP 20002CAP
30HCEM05UAP
1011RAP 2081CAP
1021RAP 2002CAP
10681CAP 20681CAP
601ROC

iMX6 Rex Module - Schematic

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