TMS470M - Texas Instruments Wiki

•TMS470M
Cost Effective Safety MCUs for Transportation
Cortex™ M3 – 32bit ARM™
Presenters:
•Justin Hua, TI China Field Applications Engineering
•Haixiao Weng, TI Auto MCU Applications Engineering
•Chuck Davenport, TI Auto MCU Applications Engineering
•Brian Fortman, TI Auto MCU Marketing
TMS470M Workshop Day-1 Agenda
• Introduction and Roadmap
• Development Tools: Hardware kits, Software tools
• Safety Overview and Modules
– Lab 1:TMS470M Safety MCU Demos
• TMS470M Architecture: Memory Map, Clocking, Exceptions
• Embedded Flash Memory tools: nowECC, nowFlash, Application Programmer
Interface (API)
• Real Time Interrupt (RTI)
• Vectored Interrupt Manager (M3VIM)
• General-purpose I/O (GIO)
• Programmable Timer Unit (HET)
– Lab 2: Using HET as GIO
• Multi-Buffered Serial Peripheral Interface (MibSPI)
• Controller Area Network (DCAN)
• Local Interconnect Network (LIN) / Serial Communication Interface (SCI)
– Lab 3: PC to SCI Communication
• Multi-buffered Analog-to-Digital Converter (MibADC)
• Support Structure: Web, Forum, WIKI
2
ARM Cortex Advanced Processors
Architectural innovation, compatibility
across diverse application spectrum
•ARM Cortex-A family:
– Applications processors for featurerich OS and 3rd party applications
x1-4
Cortex-A9
...2GHz
Cortex-A8
x1-4
•ARM Cortex-R family:
– Embedded processors for real-time
signal processing, control applications
Cortex-A5
Cortex-R4(F)
Cortex-M4
SC300™
•ARM Cortex-M family:
– Microcontroller-oriented processors
for MCU, ASSP, and SoC applications
Cortex™-M3
Cortex-M1
Cortex-M0
12k gates...
•ARM® Cortex™
•Embedded Processing Cores at Texas Instruments
•ARM Cortex-A family:
• High-performance, low power core
• Multimedia, DSP acceleration
• Mobile computing capabilities
••AMxx
• Internet-enabled
AMxx
• Interactive media and graphics
experience
• Neon optimization
• Full-featured OS support (Linux,
WinCE, etc…)
•Sitara
•Sitara
•ARM Cortex-R family
•ARM
•ARM
Processor
•PRocessor
Family
• Real-time control
• High-reliability
• Built
in redundancies
••TMS570
TMS570
• Safety-focused
••RM5xx
RM5xx
• Commitment
to enhancing performance
and increasing memory footprint
• System coherency
•Hercules
•Hercules
•
•ARM Cortex-M family
•Stellaris®
•Stellaris®
• Active/sleep power efficiency
• Efficient gate counts for better price/performance
• Optimized price/performance
••LMxx
LMxx
••TMS470M
TMS470M for
for
Transportation
Transportation
Proven processors cores with ongoing architectural innovation that simplifies the ease of use
What is TMS470M?
Cost Effective ARM 32 – bit MCUs for Transportation
•Ideal for applications requiring
•What’s new
• High performance real time control
using model based development flows
• Performance in harsh environments
• Safety sensitive and high reliability
• And…
• Scalability
• System cost constraints
• Software re-use and portability
• Cost-Effective 32-bit ARM® Cortex™
- M3 –- TMS570 compatible
• Developed specifically for safety
critical systems
• Extends TMSx70 configurations
down to 320 KB flash.
• Support for fast engineering ramp
and time to market.
•TMS470 – also good fit for Transportation & Safety
Hybrid &
Electric
Vehicles
Automotive Safety Systems
Railway
Offroad Vehicles
Avionics
•5
Cortex-M3 – The New MCU Standard
• An ARM7TDMI-S for the 21st century
–
–
–
–
For extreme cost and power-sensitive complex applications
Comparable or better FMAX and gate count with r2p0 min config
30% more DMIPS, 28% more geomean EEMBC
85% more DMIPS per mW
• State-of-the-art functionality
– Code everything in C
– Thumb-2 ISA → 6X code density, 10X perf. v 8051
– Integrated Nested Vectored Interrupt Controller
(NVIC) with lowest interrupt latency of any ARM
– Configurable/optional memory protection, debug, trace
– uA device stand-by enabled with integrated sleep modes,
ULL libraries, state retention
• Broad adoption within microcontroller and embedded SoC
markets
High Performance ARM Cortex-M3 CPU
•ARM v7M Cortex® ISA
•Upward compatible to
Cortex-R4F/TMS570
•Up to 80 MHz with
roadmap to 200+
ARM®
Cortex™- M3
•Superior performance /
code density
•Thumb-2 instructions
•80MHz
•
3 stage pipeline delivers
1.25 DMIPS/MHz
•8 region memory
protection
• •>>96
96DMIPS
DMIPSand
androadmap
roadmapto
to>>330
330
• •Superior
Code
Density
Superior Code Density
• •ARM-based:
ARM-based:broad
broadindustry
industryadoption
adoption
TMS470M Safety Features
• •Developed
Developedfor
forsafety
safetyapplications
applications
• •Reduces
code
size
and
Reduces code size andcomplexity
complexity
•ECC for flash / RAM
•(SECDED)
•TMS470M
•CPU Self Test
Controller requires
little S/W overhead
•Memory
•Up to 640KB
• Flash
•w/ ECC
•ARM®
Cortex™M3
•80MHz
•Up to 64 KB
•RAM w/ ECC
•CPU Self Test
•Error Signaling
Module w/ External
Error Pin
•VREG
•MBIST
•CRC
•LBIST
•RTI
•Memory Protection
•JTAG Debug
•Embedded Trace
•Enhanced System Bus
•Serial I/F
•MibSPI2
•64 Buffers; 4 CS
•Network I/F
•ADC
•Timers / IO
•On-Chip Clock
Monitoring
•CAN1 (16mb)
•CAN2 (32mb)
•MibADC
•64 Buffers
•10-bit, 16ch
•High End Timer
•(HET)
•64 words, 26 ch
•UART1 (LIN1)
•SPI3 (4 CS)
•Memory BIST on all
RAMS allows fast
memory test at startup
•Debug / Trace
•Vectored Interrupt Management
•MibSPI1
•64 Buffers; 8 CS
•Parity on all Peripheral
SRAMS
•Power, Clock, & Safety
•OSC PLL
•UART2 (LIN2)
•GIOA/INTA (8)
•CRC, Calibration, ADC
Self Test, …
•Performance / Memory / Features
Hercules TMSx70 Family Roadmap
Broad and Scalable for Transportation Applications
•Sampling
•Development
•MC4x Series
•MC4x Series
•EMAC option
•Concept
•
•Lockstep or Multicore Dual R4F
•over 225MHz on R4
•up to 4MB Flash; 512kB RAM
•TMS 3Q13
•LS3x Series
•LS3x Series
•EMAC option
•LS2x Series
•LS2x Series
•
option
•Lockstep dual R4F
•up to 180MHz/ •Lockstep dual R4F
•up to 3MB Flash; 256kB RAM
•up to 160MHz/250 DMIPS •up to 2MB Flash; 160kB RAM •TMS 3Q12
•TMS 4Q10
•LS1x Series
•
option
option
•LS1x Series
•
option
•TMS470M
•TMS470M
• Lower Cost Roadmap
•up to 80MHz/96 DMIPS •up to 640 kB Flash; up to 128KB E2emu
•up to 64kB RAM
•80QFP (100 coming) •TMS 4Q10
•Samples available NOW
2011
2012
•Performance / Memory / Features
TMS470M ARM® Cortex™‐M3 Family Lineup
Cost Effective Safety MCU for Transportation Applications
•Sampling
•Development
•Concept
•TMS470MF066
•TMS470MF066
•TMS470MF042
•TMS470MF042
•TMS470MF031
•TMS470MF031
•48 MHz to 80MHz
•320kB Flash or
•256KB+64KB E2emu
•16kB RAM
•80 or 100 QFP •TMS 2Q11
•memory
•320kB
•up to 80MHz/96 DMIPS •428KB Flash or
•384KB+64KB E2emu
•32kB RAM
•100 QFP •TMS 2Q11
•428kB
•up to 80MHz/96 DMIPS •640KB Flash or
•512KB+128KB E2emu
•64kB RAM
•100 or 144 QFP •Features
• Scalable Flash w/ ECC
•TMS 4Q10
• Scalable RAM w/ ECC
• EEPROM emulation capable
• Single 3.3v Supply Voltage
• High End Timer Co-Processor
• 16ch, 10-bit ADC
• Up to 2x Multi-Buffered SPI
• 2x CAN Interfaces + 2x UART/LIN
• -40c to 125c
• AECQ100 Qualified
• Sampling Now
•640kB
TMS470M Family Configurations
EEPROM
MibSPI
UART HET
Or
RAM CAN
SPI
(CS)
(LIN) (ch)
Flash*
MibADC
10-b(ch)
Device
Speed
Flash
TMS470MF03106
48MHz
256kB
64kB
16kB
1
1 (8)
2(2)
11
14
8
3.3V
TMS470MF03107
80MHz
256kB
64kB
16kB
2
2 (12)
2(2)
16
16
4
TMS470MF04207
80MHz
384kB
64kB
24kB
2
2 (12)
2(2)
16
16
TMS470MF06607
80MHz
512KB
128kB
64kB
2
2 (12)
2(2)
16
TMS470MF06608
80MHz
512KB
128kB
64kB
2
2 (12)
2(2)
26
1
GIO Voltage Package
Temp
Q100
80QFP
-40..+125C
Yes
3.3V
100QFP
-40..+125C
Yes
4
3.3V
100QFP
-40..+125C
Yes
16
4
3.3V
100QFP
-40..+125C
Yes
16
8
3.3V
144QFP
-40..+125C
Yes
•* EEPROM Flash bank can also be used as normal Flash program memory
•Please note that the 100pin packages are pin compatible across the family.
TMS470M Block Diagram
TI Automotive Qualified ARM Cortex-M3 MCU
Performance / Memory
• Up to 80 MHz ARM Cortex-M3
• Up to 640KB Flash (128KB can be used as EEPROM)
• Up to 64KB Data SRAM
ROM Emulation Capability
Targeted Automotive Applications
 Airbag
 Braking – ABS / ESP
•Sampling Now
 General Infrastructure Micro (ADAS, Chassis) •Production 4Q10
• Features
• Safety
• CPU Self Test Controller
• Flash & RAM w/ ECC
• Memory Built-in Self Test
• Cyclic redundancy checker module (CRC)
• Reliability
• Low PPM Production Flow Support
• Extended Temp and AEC-Q100 Qualification
• On-chip VREG (only 3.3v required)
• Enhanced I/O Control
• High End Timer Coprocessor (HET)
• Up to 26ch (144QFP); 16ch (100QFP)
• All pins can be used as PWM or Input Capture
• Hardware Encoders & Time Stamping
• 10-bit MibADC (16 channels)
• Continuous Conversion Channels
• Buffered FIFO
• Self Test on ADC
• Strong Communication Networks
• 2 x CAN Interfaces
• 2 Buffered SPI + 1 Standard SPI
• 2 x LIN / UART (SCI)
Packages: LQFP: 80pin, 100 pin, 144pin
-40 to 125 C Temperature Range
•12
HET: High End Timer Co-Processor
Address/Data Bus
•User Programmable
•64/128 word instruction
RAM with Parity
•Up to 26 I/O pins for
complex or typical
timing fns - capture,
compare, PWM, GPIO
• Pulse Width Modulation
Host
interface
Timer
RAM
Global & prescale control register
Shadow registers
Prescaler
Program RAM
Control RAM
Data RAM
Address Register
Register A, B, T
Interrupt Control
25 bit ALU
Operation Control
Input/
Output
Unit
22 High Resolution
Channels
Compare
6 Standard
Resolution Channels
I/O Control
Register
Synchronizers
•Multiple 25-bit virtual
counters for timers,
event counters, and
angle counters
16 I/O Channels
Single, multi channel PWMs
PWM with duty cycle update
PWM with sync/async update
Phase shift PWM's
Symmetrical & asymmetrical
PWM with deadband
• Timer/Counter Functions
Instruction Register
Execution
Unit
•Conditional program
execution based on pin
conditions and
compares
CPU wait control
•
•
•
•
•
• •Frees
FreesCPU
CPUMHz
MHz
• •Supports
typical/complex
Supports typical/complexfunctions
functions
• •Simplified
development
environment
Simplified development environment
•
•
•
•
•
•
Frequency Modulated Output
Pulse width count
Time stamp
Event counter
Pulse accumulator
Multi-resolution scheme
• Freq / Pulse
Measurements
• Pulse and period
measurement (same channel)
• Quadrature Decoding
• Special Functions
• SPI Emulation
• TFT Display Timing
TMS470M Development Tools
14
•Timer Co-Processor Development Tools
•Example code palette
•Clocks
•Edit mode
•Pins
•Instruction
•drag and drop
•Internal Registers & Memory
• Graphical Programming Environment
• Output Simulation Tool
• Generates CCS-ready software modules
• Includes functional examples from TI
•Select pins for waveform
• Graphical Waveform Viewer
• Input Generation Tool
• Seamless interface to coding tool
• Upgradable to Full SynaptiCAD
•15
•05/08/08
•15
Code Composer Studio v4.1
• Based on Eclipse industry standard
for embedded debug tools
– Modern window environment
– Advanced source code editor
– Scalable multi-core/processor
environment
– Program and Debug Application
via JTAG
– Test Automation via Scripting
• Low cost tools enable developers to
easily evaluate and start development
– Develop with CCS for <$100
• TMS470M Debug Features
– 6 Hardware Breakpoints
– Unlimited Software Breakpoints
– Integrated Flash Programming
16
Code Composer Studio Components:
Fully Integrated, Easy to Use Development Tools
Help
Menus or
Icons
Watch
Window
Target Connection
 Source & object
files
 File dependencies
 Compiler,
assembler & linker
build options
Source Code View
Disassembly
Window
CPU
Window
Memory
Window
17
HalCoGen:
Hardware Abstraction Layer Code Generator
Features
• User Input on High Abstraction Level
– Graphical-based code generation
– Easy configuration
– Quick start for new projects
• Generates C Source Code
– ANSI Conforming
– Clear, structured, coding style
– Customizable code for user
maintenance
• Supported Peripherals
– System Module
– RTI
– GIO
– SCI/LIN
– CAN
– SPI
– ADC
– Timer Co-processor (nHET)
• Interactive Help System
– Describes tool features and
functions
– Provides detailed dependency
graphs
– Provides useful example code
– Tool tip help available
• Hierarchical project code viewing
18
TMS470M Tools
External Tools:
• IDE’s
• Lauterbach, iSystems, CCS
• Compiler
• ARM, CCS
• Emulator
• Spectrum Digital, Lauterbach, iSystems, Blackhawk, Signum
Systems, XDS100, XDS560 …
• Operating System
• ETAS
• CAN
• Vector
• Trace / Calibration
• Lauterbach, iSystems
• Production Flash Programming
• BP Microsystems, Data-IO
19
TMS470M Development and Evaluation Kits
•
TMDX470MSF066USB ($79) – Low Cost TMS470M Evaluation Kit
•
•
•
•
•
•
USB Powered
On Board USB XDS100v2 JTAG Debug
On Board SCI to PC Serial Communication
Access to Select Signal Pin Test Points
LEDs, Temp Sensor, Light Sensor and CAN transceiver
QFP Packaged CPU
• Software Included in Each:
•
•
•
•
CCStudio v4.1 IDE
– Includes C/C++ Compiler/Linker/Debugger
Flash programming integrated into CCS
HET GUI/Simulator/Assembler
Demo Project/Code Examples
•20
TMS470M RTM Development Support Collateral
Documentation
•
•
•
•
Data Sheets ‘MF066 Preview
Technical Reference Manual (TMS470M Series)
Errata Sheet
Application Notes (4 Available)
Available
Available
Available
Available
Hardware/Kits
•
•
TMS470M USB Development Stick Kit
TMS470M ABS Reference Design
Production: 30-Sep-2010
4Q10
Virtual Support Network
•
•
TMS470M Safety MCU Forum
TMS470M Safety MCU Wiki
Available
Available
Software/Tools
•
•
•
•
•
•
•
•
•
nowFlash & CCS Config (Add M3 Support – Config file Rev1)
nowECC
HET Assembler
HET IDE
F035 FMzPLL Calculator
Demo Software, source code examples
CCSv4 Device XML Files
(Pre-rls 4.2)
CCSv4 Flash Programming Support (CCS 4.2)
HALCoGen – Driver and Init code generator
•TI Confidential – NDA Restrictions
Available
Available
Available
Available
Available
30-Sep-2010
Available
4Q10
1Q11
•21
TI Suggested ABS System
•Power Management Module
•Battery
•Supervisor
•Supervisor
•ABS IC
•TPIC7218
•Pump Motor Driver
•Charge
•Charge Pump
Pump
•Main Relay Driver
•Wake up
•LS Switch Driver
•Watchdog
•Watchdog
•Monitor
•Monitor
•Chassis
•CAN Bus
•CAN
•CAN
•Transceiver
•Transceiver
•Wheel
•Speed
•Sensor x4
•ABS
•ABS
•MCU
•MCU
•TMS470M/570
•TMS470M/570
•SPI
•SPI
•Wheel
•Wheel Speed
Speed
•Sensor
•Sensor
•Interface
•Interface
•Solenoi
d
•LS Switch Driver
•x4
•LS Switch Driver
•PWM
•Solenoi
d
•LS Switch Driver
•PWM x4
•Lamp Driver
•K-Line
•K-Line
•Diagnostic Systems
•ISO K-Line
M
•Buck/LDO
•Buck/LDO
•Lamp Driver
•x2
•Warning
•Lamp
TMS470M Safety Features
24
CPU Self Test Controller (STC/LBIST)
Clock
controller
ROM
ROM
interface
FSM
CPU_nRESET
CPU1
STC BYPASS/
ATE Interface
Test
controller
DBIST
CNTRL
STC
PCR
Clock cntrl
VBUSP
interface
REG Block
&
Compare
Block
ERR
ESM
•
•
•
•
Provides High Diagnostic Coverage
Significantly Lowers S/W and Runtime Overhead
No SW BIST (Built In Self Test) Code overhead in Flash
Simple to configure and start BIST via register
25
Flash / RAM ECC Protection
Cortex-M3
64b Inst.
Flash
64 Data
3 stage pipeline
ECC Logic
64 Data Bits
8 ECC Bits
RAM
ECC Logic
64 Data Bits
8 ECC Bits
• ECC evaluated in the Memory Wrapper Logic
– Single Bit Error Correction and Double Bit Error Detection
26
Safety Aspects of Network Interfaces
• Networked peripherals (DCAN, and SCI/LIN) are considered grey-channel /
black-channel communications
• In such communications application level protocols (time redundancy, CRC in
data packet, etc.) are necessary
• When such assumption is made, the Dangerous Undetected Failure from the
network is effectively not measurable (<0.001 Failure In Time (FIT))
• Detailed fault data available upon request
27
Error Signaling Module (ESM)
From modules
Errors for
error_group2
INTEN
Low-Level
Interrupt Handling
Low-Level
High-Level
Interrupt Handling
High-Level
Interrupt
INTLVL
Interrupt
To interrupt manager, M3VIM
Errors for
error _group1
28
TMS470M ESM Features
• ESM functions
– Up to 64 error channels, divided into 2 different groups
• 32 channels with configurable output for interrupt and error
behavior
• 32 channels with predefined output for interrupt and error behavior
– Error forcing capability for self test
• ESM hardware
– Hardware assistance for prioritizing error sources
29
Additional Safety Features
• On chip voltage regulator (VReg)
– Regulates core supply voltage (VCC) from digital I/O supply (VCCIOR)
– Required operating range
• 3.0-3.6 V (nom=3.3 V) for VCCIOR
• 1.4-1.7 V (nom=1.55 V) for VCC
• Clock monitoring
– Oscillator monitor
• Detects failure if oscillator frequency exceeds defined min/max
thresholds
• Selectable hardware response on oscillator fail
– PLL slip detector
• Indicates PLL slip if phase lock is lost
• Selectable hardware response on PLL slip
• Internal backup ‘low power oscillator’ (LPO) clock source
– External clock prescaler
• Allows external monitoring of CPU clock frequency
• CPU with dedicated Memory Protection Unit (MPU)
30
Programmable Memory BIST (MBIST)
• All on-chip RAMS
can be tested
Functional
Read/Write
Datapath
VBUS I/f
Tester I/f
ROM I/f
• Run at startup
Cfg
block
Ext
block
PBIST
Controller
ROM
block
RAM
Data
path/
Collars
• Multiple Memory Test
Algorithms
To / From
Memories
(RAM
groups)
• Detects multiple failure
modes
Data
Logger
31
LAB1: TMS470M Safety Features Demo
32
Lab1: TMS470M Safety MCU Demos
33