Analog Synthesis/Optimization Revisited…

Transcription

Analog Synthesis/Optimization
Revisited…
Rob A. Rutenbar
Bliss Professor and Head
Analog: Six Facts / Problems / Opportunities
1.
Optimization works for analog 2.
Circuit designers are not optimization experts
3.
Layout optimization != circuit optimization
4.
Mixed‐sig systems = hierarchical, heterogeneous
5.
It’s all about the constraints, stupid…
6.
Usage models matter (Powerpoint=NO, Photoshop=YES)
© Rob A. Rutenbar 2010
PUNCH
LINE
Slide 2
1. Optimization Works for Analog

Yes, can formulate many design problems as optimizer tasks

Many examples of real tools in this space, doing real circuits
Help size, optimize for perform/yield, layout, migrate …

180nm
0.12 mm
120nm
Auto Sizing
Auto Sizing
STMicroelectronics result [Shah, Dugalleix, Lemery DATE02]
Auto Layout
Auto Layout
Both sizing and layout
Area: ~9000 μm2
Power: 9.15mW Area: ~4000 μm2
Power: 1.1mW [Source: Cadence]
Slide 3
Example: Commercial Analog IP Library

A library of topologies, constraints, and validation (sim) steps
Slide 4
Lots of Commercial Examples

Industrial cell migration
Proprietary 0.6um Æ 0.35um
Industrial systems design
Renasas, ~1K devices, 2.5GHz © Rob A. Rutenbar 2010
BiCMOS, 1st silicon success
Slide 5
Lots of Commercial Examples
Courtesy: Neolinear, Cadence

So, why are these not in universal, widespread use…?
Slide 6
Broadly Speaking, Landscape Is Like This
Simulation‐based tools (“SPICE‐in‐the‐loop”)
PRO: same setup as validation
PRO: quicker to set up
CON: slowest to run; scaleup?

Analytical modeler tools
(“convex”, “smooth” etc)
PRO: run really, really fast
PRO: scale up to big things
CON: long setup; accuracy?
year
How long
to run?
month
week
day
Ex: Cadence
Virtuoso ADE GXL
hour
r
u
ho
y ek th ear
a
d we on y
m
Ex: Magma
Titan AVP
How long to setup?
Slide 7
2. Analog Experts != Optimization Experts

CAD view: “Hey, its just a big cost landscape, find the bottom”
Analog view: “Huh…?”

Not everything that matters in analog is robustly – or even
explicitly, and correctly – represented in the design process. Consequence: Often use aesthetics as a surrogate for correctness
Hey, why is that
W/L in that
device, right there?
…and I really
don’t like the
look of that via!
Slide 8
‘Sociology’ of Aesthetic Engineering Is Daunting

This does not happen with you design out 50M digital gates…
Gosh, does NOR #1,034,237 look odd to you…?
Oh Brad – I was just thinking
the same thing!
Copyright © 1993, The National Gallery, London
Slide 9
3. Layout Optimization != Circuit Optimization

Both optimization processes – but very, very different
Specs
Topology
Schematic
Size
Center
Floorplan
Devices
Place/Route
Slide 10
…But, Now Tightly Coupled
Image provided by ©2010 Cadence Design Systems, Inc. All rights reserved worldwide

Bad news:
Can’t even pretend these are
separate problems
Heterogeneous landscape of objects (devices, shapes, routes, wells) and goals (specs, yield, reliability) makes for tough optimizer tasks
ID vs VGS vs proximity to well edge
Source: Cao and McAndrew, ICCAD 2007 tutorial, and
P. G. Drennan, M. L. Kniffin, and D. R. Locascio, CICC 2006
Slide 11
Mixed‐Signal Sys: Hierarchical, Heterogeneous

To first order: all digital (ASIC) designs look alike
Source: Juergen Koehl, IBM

Source: Zhong Xiu, CMU
Source: Zhong Xiu, CMU
Not remotely true for analog and mixed‐signal designs
0.37mm
0.37mm
Pipeline Stages
2.8mm
Source: B. Tsang, Y. Chiu, B. Nikolić UCB
Source: P. Gray, UCB
Test
Comparator
Source: H.‐S. Lee, C. Sodini, MIT
Slide 12
Hierarchy Æ Heterogeneous Design Representations

Life would be great if we could design, simulate, optimize these flat at tx level. (We can’t; it isn’t)
Simplifications
Analytical Eqns
M
nq + ∑ ni,input <
i =1
(2N −1 Δ)2 / 2
10
SNRmax
10
Vout (t = T1) − Vslew_ ideal ≤ Vtol
[Ch
ien,
M
Circuit Simulations
Layout Details
ukh
erje
e et
a
l, A
SSC
C’0
5]
Slide 13
So: 5. It’s All About The Constraints…

Constraint extraction and tradeoff management
Critical stuff in real designs
often never written down
Exists implicitly in design group’s legacy portfolio and human resources

..then optimizing all the right stuff, simultaneously
Analog steps less independent,
More
comments
in your
code!
less sequential than digital
Hierarchical, heterogeneous, statistical, simultaneous…
vs
Slide 14
Robust Constraint Acquisition: Opportunity

High‐performing design teams often evolve highly individualized
‘channels’ for communicating critical design constraints.
Sadly, it’s not universal across teams, technologies, companies
Opportunity: Stop thinking of this as just a “users don’t get it”problem.
Maybe its a data mining / machine learning / HCI problem…
So: 6. Usage Models Matter (A Lot)
Current perceptions of
most of these tools
Is this really what we
should be aiming for?
Usage Model: Completing vs Improving Designs

Doesn’t respect dominant usage culture/sociology of design groups
I now like very fast “what if…” for all electrical/geometric steps

What if every improve op was fast+deterministic+incremental?
Gain

I used to want “push the button, get the final design”
??
Bandwidth
Gain

!!
Bandwidth
Improvement
[Source:
Cadence]
Note – in modern nm processes, small changes
can have big impacts on ckt
Slide 17
Opportunity: Incremental Tools + New Use Models

Adobe Photoshop offers an interesting vision of this
This is “Image variations”
A palette of incremental changes
to base image

Can I do this for analog …?
For critical analog metrics?
Shorter wires? Straighter signal path? More like schematic? Different point on pareto frontier? More resistance to +nσ on <ParamX>? Etc etc?
Slide 18
Summary

My opinions, after pounding on this stuff for 25 years
Optimization = good
Optimize all the concerns the

best designers are handling
Constraint extraction is key
Usage models matter
Aesthetic engineering is a crutch – we can do better
Slide 19