SuperI/O PC87351EB Reference Manual

Transcription

420521694-001
®
SuperI/O
PC87351EB
Reference Manual
SuperI/O
PC87351EB
Reference Manual
Part Number: 420521694-001
May 1998
PRELIMINARY
REVISION RECORD
REVISION
RELEASE DATE
SUMMARY OF CHANGES
1.0
March 1998
First release.
1.1
May 1998
Minor Changes.
iv
PREFACE
Thank you for your interest in National Semiconductor’s PC87351 SuperI/O device.
The PC87351 Evaluation Board (PC87351EB) is designed to demonstrate the basic I/O functions of
the PC87351. It also demonstrates an implementation of the PC87351 on a low chip-count, low-cost
PCB.
This Reference Manual provides the information you need to get acquainted with the PC87351, and
to develop your own applications.
We at National Semiconductor want you to make the fullest use of your PC87351EB. If you have
any questions, please contact your nearest Regional Marketing Office, as listed on the back cover.
PC, PS/2 are registered trademarks of International Business Machines Corporation.
v
CONTENTS
Chapter 1
OVERVIEW
1.1
INTRODUCTION ....................................................................................................... 1-1
1.2
MANUAL ORGANIZATION ....................................................................................... 1-2
1.3
BOARD FEATURES.................................................................................................. 1-2
1.4
PHYSICAL DESCRIPTION OF BASE BOARD ......................................................... 1-4
1.5
PHYSICAL DESCRIPTION OF EXTENSION BOARD.............................................. 1-7
Chapter 2
INSTALLATION AND CONFIGURATION
2.1
INTRODUCTION ....................................................................................................... 2-1
2.2
UNPACKING ............................................................................................................. 2-2
2.3
SYSTEM REQUIREMENTS ...................................................................................... 2-2
2.4
SYSTEM INSTALLATION ......................................................................................... 2-4
2.5
HARDWARE CONFIGURATION............................................................................... 2-5
2.5.1
DIP Switch Setup ........................................................................................... 2-6
2.5.2
Base Board Jumper Setup ............................................................................ 2-6
JP2 ................................................................................................................ 2-6
JP4 ................................................................................................................ 2-6
2.5.3
Extension Board Jumper Setup ..................................................................... 2-7
JP1-4, JP6-7, JP9 ......................................................................................... 2-7
JP4 ................................................................................................................ 2-9
JP5 ................................................................................................................ 2-9
JP7 ................................................................................................................ 2-9
JP8 ................................................................................................................ 2-9
JP10 ............................................................................................................ 2-10
JP11 ............................................................................................................ 2-10
JP12 ............................................................................................................ 2-10
VDD ............................................................................................................. 2-10
JP14 ............................................................................................................ 2-10
VBAT ........................................................................................................... 2-11
VSB ............................................................................................................. 2-11
JP17 ............................................................................................................ 2-11
JP18-23, 25 ................................................................................................. 2-11
JP24 ............................................................................................................ 2-11
2.6
2.5.4
KBC Connection to the Motherboard ........................................................... 2-11
2.5.5
KBC Automatic Hardware Configuration ..................................................... 2-12
SOFTWARE CONFIGURATION ............................................................................. 2-12
2.6.1
Configuring the PC87351 to Work in Parallel IRQ Mode ............................. 2-12
Without the KBC .......................................................................................... 2-12
PC87351EB Reference Manual
CONTENTS-vii
With the KBC............................................................................................... 2-13
Chapter 3
2.6.2
Easyreg Software Utility .............................................................................. 2-14
2.6.3
PC87351 Reset ........................................................................................... 2-14
2.6.4
Configuration Register Access .................................................................... 2-14
THEORY OF OPERATION
3.1
INTRODUCTION ....................................................................................................... 3-1
3.2
STANDARD ISA BUS ADD-ON CONNECTOR ........................................................ 3-1
3.3
GLUE LOGIC............................................................................................................. 3-1
3.4
DEBUG RESET CIRCUIT ......................................................................................... 3-3
3.5
PC87351 CHIP .......................................................................................................... 3-3
3.6
BATTERY CIRCUIT .................................................................................................. 3-3
3.7
FDC ........................................................................................................................... 3-3
3.8
UART1 AND UART2 ................................................................................................. 3-4
3.9
INFRARED ................................................................................................................ 3-4
3.10 PARALLEL PORT ..................................................................................................... 3-5
3.11 FAN CONTROL CIRCUIT ......................................................................................... 3-5
3.12 ISP............................................................................................................................. 3-6
3.13 GPIO PORTS AND PME ........................................................................................... 3-7
3.13.1 GPIO1 ........................................................................................................... 3-7
3.13.2 GPIO2 ........................................................................................................... 3-8
3.13.3 PME Connector ............................................................................................. 3-8
3.14 PS/2 KEYBOARD AND MOUSE CONNECTORS .................................................... 3-9
3.15 KBC CONNECTOR ................................................................................................... 3-9
3.16 TEST CONNECTORS ............................................................................................. 3-10
Chapter 4
SPECIFICATIONS
4.1
INTRODUCTION ....................................................................................................... 4-1
4.2
PHYSICAL SPECIFICATIONS .................................................................................. 4-1
4.3
CONTENTS-viii
BASE BOARD CONNECTORS................................................................................ 4-1
4.3.1
SERIAL1 Connector, J1 ................................................................................ 4-2
4.3.2
SERIAL2 Connector, J2 ................................................................................ 4-2
4.3.3
KBC Connector, J4 ....................................................................................... 4-2
4.3.4
Mouse Connector, J6 ................................................................................... 4-3
4.3.5
KBD Connector, J7 ........................................................................................ 4-4
4.3.6
Standby Power Connector, J8 ....................................................................... 4-4
4.3.7
FDC Connector, J10 ...................................................................................... 4-4
4.3.8
IRFE Connector, J12 ..................................................................................... 4-5
4.3.9
Parallel Port Connector, J13 .......................................................................... 4-6
4.3.10 ISA XT and AT Connectors, P1 and P2 ........................................................ 4-6
4.4
4.5
EXTENSION BOARD CONNECTORS...................................................................... 4-6
4.4.1
PME Connector, J1 ....................................................................................... 4-6
4.4.2
Fan Connector, J2 ......................................................................................... 4-7
4.4.3
GPIO2 Connector, J3 .................................................................................... 4-7
4.4.4
GPIO1 Connector, J4 .................................................................................... 4-7
4.4.5
ISP Connector, J10 ....................................................................................... 4-8
CURRENT REQUIREMENTS ................................................................................... 4-8
Appendix A BASE BOARD SCHEMATIC DIAGRAMS
Appendix B EXTENSION BOARD SCHEMATIC DIAGRAMS
Appendix C BILL OF MATERIALS
Appendix D PAL EQUATIONS
INDEX
CONTENTS-ix
FIGURES
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 2-1.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
FIGURES-x
PC87351EB Features ............................................................................................ 1-4
PC87351EB Base Board Component-Side Layout ............................................... 1-5
PC87351EB Base Board Print-Side Layout .......................................................... 1-6
PC87351EB Extension Board Component-Side Layout ........................................ 1-7
PC87351EB Extension Board Print-Side Layout ................................................... 1-8
PC87351 Chip Evaluation System ........................................................................ 2-1
ISA Bus and X-Bus Data Architecture ................................................................... 3-2
Fan Control Circuit ................................................................................................. 3-6
ISP Block ............................................................................................................... 3-7
GPIO1 Circuit ........................................................................................................ 3-8
TABLES
Table 2-1.
Table 2-2.
Table 2-3.
Table 3-1.
Table 3-2.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
Table 4-9.
Table 4-10.
Table 4-11.
Table 4-12.
Table 4-13.
Table 4-14.
Table 4-15.
Table 4-16.
Jumper Default Settings on Base Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Jumper Default Settings on Extension Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Base Address Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
PME1/RING Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
PME2/SUSP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
PC87351EB Connector List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
SERIAL1 Connector, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
SERIAL2 Connector, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
KBC Connector, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Mouse Connector, J6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
KBD Connector, J7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Standby Power Connector, J8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
FDC Connector, J10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
IRFE Connector, J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Parallel Port Connector, J13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
PME Connector, J1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Fan Connector, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
GPIO2 Connector, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
GPIO1 Connector, J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
ISP Connector, J10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Max Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
TABLES-xi
Chapter 1
OVERVIEW
1.1
INTRODUCTION
The PC87351EB is an evaluation board for the PC87351 SuperI/O chip. This
chip integrates the traditional I/O devices of a PC motherboard with additional
Plug and Play functionality, Infrared, Serial IRQ and Fan support.
The PC87351EB comprises a base board, and an extension board on which
the PC87351 SuperI/O chip is mounted.
The PC87351EB enables you to evaluate the following functions, or modules,
of the PC87351 in their natural environment:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ISA interface
PC87351 external connections
PC87351 hardware configuration
Floppy Disk Controller (FDC), up to 1 MB/sec
16550 serial port 1
Enhanced serial port 2, software compatible with 16550
Infrared (IR) port (supporting IrDA, Sharp, TV Remote)
Parallel Port, IEEE 1284 compatible (including ECP/EPP)
Keyboard Controller (KBC) compatible with 8042
PS/2 mouse and PS/2 keyboard support
Two General Purpose I/O (GPIO) ports. GPIO1 with 8 bits, and GPIO2 with
3 bits
System wake-up events detection for energy-saving system
Two fan speed controls
Motherboard Plug and Play interface
VSB standby power pin to minimize battery drainage
Certain features of the PC87351 chip are not supported directly on-board.
Figure 2-1 shows the working environment.
Advanced Chip Features
The PC87351 chip supports some of the newest emerging standards in the PC
world:
• The Plug and Play standard, driven by Microsoft and Intel, allows a Plug and
Play BIOS, or an operating system, to automatically configure and resolve
conflicts of I/O addresses, IRQs and DMA channels between ISA boards.
• The TV Remote standard enables you to support applications that either
send signals to external devices, or receive signals from remote controls.
OVERVIEW 1-1
1.2
MANUAL ORGANIZATION
This manual provides information for configuring the PC87351EB. It is organized as follows:
Chapter 1
OVERVIEW - Describes the PC87351EB operating environment and features.
Chapter 2
INSTALLATION AND CONFIGURATION - Describes the system installation and
configuration procedures.
Chapter 3
THEORY OF OPERATION - Provides a detailed description of the PC87351EB
modules, and describes operating principles, based on the schematics in Appendix A.
Chapter 4
SPECIFICATIONS - Provides PC87351EB specifications and physical dimensions.
Appendix A
BASE BOARD SCHEMATICS.
Appendix B
EXTENSION BOARD SCHEMATICS.
Appendix C
BILL OF MATERIALS.
Appendix D
PAL EQUATIONS.
1.3
BOARD FEATURES
The PC87351EB includes the following features (see Figure 1-1):
• 128-pin PC87351 SuperI/O Chip
This device is assembled in a socket for easier upgrade and/or replacement.
• Clock Source
48 MHz external clock oscillator.
• Two Data Switches
74LVX3L384 data switches control the data flow from the PC87351 data
bus to the X-Bus, or the ISA bus.
• Serial Ports 1 and 2
Each serial port has a 10-pin dual-row header and a low-cost RS-232 chip
(three drivers and five receivers), DS14185.
• Infrared Support
A 9-pin D-type connector connects the infrared module of the PC87351 to
an Infrared Front End Device (IRFE, National Semiconductor discrete module).
• Parallel Port
A standard D-type male connector with National ECP terminations.
• Floppy Disk Controller (FDC)
A 34-pin dual-row header connects the FDC block on the PC87351 to a
maximum of two external Floppy Disk Drives.
1-2 OVERVIEW
• Keyboard Controller (KBC)
A 40-pin dual-row header connects the KBC module on the PC87351 to
the 8042 40-pin DIP socket on the motherboard. Two MINI-DIN 6-pin connectors connect the mouse and keyboard to the board.
• 3V battery for RAM backup of the PC87351.
• GPIO1
A 10-pin dual-row header connects all GPIO1 signals to any user-defined
external circuitry.
• GPIO2
A 10-pin dual-row header connects all GPIO2 signals to any user-defined
external circuitry.
• PME
A 10-pin dual-row header connects the multiplexed pins PME1/RING and
PME2/SUSP to any user-defined external circuitry.
• FAN
A 2-pin header connects the fan control to an external fan via optional onboard circuitry.
• Standard AT-type ISA add-on edge connector.
• Voltage Supply
The board operates at 5V, supplied by the ISA bus. The two DS14185 components, and the fan circuitry on the extension board, operate on +12V
and -12V from the ISA bus.
OVERVIEW 1-3
MINIDIN
Mouse
GPIO1
2*5
Conn
PME
2*5
Conn
MINIDIN
GPIO2
2*5
Conn
FDC Conn 17*2
Keyboard
FAN
CIRCUIT
SER1
2*5
Conn
FAN
2*1
Conn
Infrared
Port
Connector
BADDR
DS14185
+
PC87351
BT1
DB9
DB25
3V
Osc
SER2
2*5
Conn
48 MHz
DS14185
GPIO16
Parallel
Port
Connector
IRQ1
SIOD[0..7]
Glue Logic
KBC Conn 20*2
P12,17,20,21,22
74LVX
3L384
PAL 22V10
74AC
74AC
TQ32
74F
74F
132
74LVX
3L384
RST
RST
SW
SW
KBC PRES
IRQ
DMA
SD[0..7]
SA[0.15]
Control
RXD[0..7]
FPGA
1032E
Reset
ISA Bus
Figure 1-1. PC87351EB Features
1.4
PHYSICAL DESCRIPTION OF BASE BOARD
The PC87351EB is designed to be mounted in a PC-AT slot. Figure 1-2 shows
the component side of the base board, and Figure 1-3 the print side.
1-4 OVERVIEW
SER2
24
J3
39
J4
40
1
U5
INT
C1
XU6
1
5
20
10
15
12
13
1
U7
35
VDD
1
U10
TP5 TP6
11
10
XF1
JP3
VDD
P1
C12
C13
C14
C15
C16
C17
C10
C11
A1
C18
F2
RST
1
R81
JP4
ISARST
R31
13
J13 PAR
R22
R23
R19
2A
+
5
J12
IR 1
33
34
XBT2
R29
A31
24
40
30
IRQ 1
Y1
32.768 KHz
TP4
C6
VCC
XU9 48MHz C7
C8
C9
R18
C3
C5
U8
1
30
R30
C18
XJ4E
25
C4
TP3
GND
R82
+
19
20
R28
P2
A
20
85
J11
XJ4B
R27
23
1 3 5 7
980521682-002
REV
PC87351EB
PC87317EB
980521694-001
155
XJ4A
15
90
81
J10
R25
20
XJ4D
10
9
1
10
95
RN2
BT1
3V
9
10
R21
R26
19
0 2 4 6
5
XU4
100
XJ4C
1
FDC
R24
2
1
1
1
0
0
1
0
PC87317 48 MHz
1
CLK
32.768 KHz 0
RESET CFG CFG
Y
KBC RTC FDC
N
Y
X-DATA
N
160
150
29
0
105
29
0 2 4 6
2
50
41
J5
1
110
120
APC
30
GPIO2
1 3 5 7
55
TP2
GND
CFG
SW2
2
145
10
19
3
140
9
TP1
VCC
115
C2
0 2 4 6
1 3 5 7
J9 GPIO1
60
2
2
1
135
= 1
= 0
2
0
1
0
1
3
0
0
1
1
PC87307/8 CFG
24 MHz
RES
48 MHz
32.768 KHz
C1
0
X
1
0
1
JP2
STANDBY
1
R17
1
10
9
GPIO3
L1
65
RTC
J2
L3
B. ADD. BADDR 1
PnP ISA
0
002E 1
PnP MBD
015C 1
L4
BADDR
0
L5
SW1
1
J7
L6
121
130
2
L2
RES
1
0
KBD
EXT
70
80
R20
VCC
GND
SER1
JP1
J6
125
1
KBC
1
MOUSE
nONCTL
75
9
U2
1
4
2
GND J8
1
LD1
SW3
U3
3
1
LED SWITCH
nONCTL
VHEXT
EXTV
NLED
nRING
R9
R10
R11
R12
R13
R14
R15
R16
U1
1
NC
1
R1
R2
R3
R4
R5
R6
10
R7
R8
2
EXTV
NC
nSW
9
J1
VHEXT
++
VCC
GND
VCC
GND
1
SW4
45
RN1
Figure 1-2. PC87351EB Base Board Component-Side Layout
OVERVIEW 1-5
1-6 OVERVIEW
J12
13
45
C29
C28
12
10
15
25
20
R83
5
20
15
105
C34
C36
C35
R85
100
XU6
C39
C38
10
110
1
24
JP2
2
1
XJ4A
B31
C41
5
R86
115
6 4 2 0
C37
C40
GPIO1 J9
7 5 3 1
XJ4E
D1
C42
10
9
C46
1
1
STANDBY
2
1
C43
R59
C47
6
KBD
5
6
5
MOUSE
4 2 1 3
J6
SW1
R62
4
2
C44
D18
R74 R70B R69B R71B R72B
R69A R71A R72A
SW2
R66B R65B R64B R63B
3
1
C45
P2
J5
2 1
9
GPIO3
JP1
1
39
29
19
9
1
C62
C61
R75
C57
C59
C58
KBC
J4
40
20
10
2
C60
LED C56
LD1
C55
R68
10
C54
R67
SW3
SWITCH
R66A R65A R64A R63A
R61
C50 C51 C52
R73 R70A
R60
C48 C49
4 2 1 3
J7
1 3 5 7
B1
R56 P1
XJ4B
C26
C27
13
30
C33
C32
95
6 4 2 0
APC
155
PAR
J11
R58
GPIO2
7 5 3 1
XJ4D
C25
C24
35
R84
C30
C31
90
29
30
S/N
TP6 TP5
50
VDD
55
11
10
IRQ
60
150
JP3
VDD
1
65
145
XU9
TP4
VCC
TP3
GND
R57
+
85
XJ4C
1
2
70
140
C23
Y1
BT1
3V
C22
9
75
135
25
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R41
RN2
19
FDC
10
130
C21
F2
R35
R36
C20
R37
R38
R39
R40
J10
20
125
1
5
R34
C19
30
R77
R78
TP2
GND
TP1
VCC
C64
C63
R76
RTC
J3
24
20
10
2
C65
J2
C74
C75
C76
C77
C78
C79
C80
C81
10
J1
2
C66
C67
C68
C69
C70
C71
C72
C73
1
1
9
23
19
9
1
R79
R80
9
SER2
14
9
6
1 IR
R33
ISARST
33
34
J8
JP4
R32
SW4
RST
SER1
RN1
0 2 4 6
J13
Figure 1-3. PC87351EB Base Board Print-Side Layout
VCC
GND
VCC
GND
VCC
GND
PHYSICAL DESCRIPTION OF EXTENSION BOARD
1.5
The PC87351EB is designed to be mounted in a PC-AT slot. Figure 1-4 shows
the component side of the extension board, and Figure 1-5 the print side.
PME
GPIO2
GPIO1
1
2
0
1
0
1
3
4
2
2
3 1 U3
5
6
4
5
7
8
6
7
9
10
12
JP2 J3
JP3 J4 JP6
JP1 J1
1
2 1
2 1
2 1
2
3
4 3
4 3
4 3
4
5
6 5
6 5
6 5
6
7
8 7
8 7
8 7
8
1
2
3
GND
13
115
24
105
15
100
U1
20
R2 J8
R1
95
25
90
REV
85
JP12
GPIO20
P21
P20*
30
JP14
SIRQ*
PIRQ
35
37
75
12
1 40
JP12 JP14
1
1
2
2
3
3
5
36
38
65
66
67
002
EXT 980521694-001
110
101
102
100
3
2
1
JP11
1
10
JUMPER
UP
DOWN
VDD
1
1
GND
1
7
LD1
1
VSB PWUREQ VDD
LD3
DOWN
LOW
26
50
14
8
51
25
8
VSB
1
2
3
4
5
6
7
8
J10
2
1
ISPEN
1
2
3
ISPDIS
2E 1
1 2
JP18
1 2
JP19
1 2
JP20
1 2
JP21
1 2
JP22
1
TP3
TP4
JP17 IRSL2
UP U1/115 BADDR SPARE
3
OUT HIGH* 15C 4
LD2
U8
VDD
RP1
1
75
VSB
VBAT
76
100
U6 24
13
1
PC87351EB
J7
1
12
5
JP11-PNF
IN FDC
OUT PP*
JP25
SW1
JP23
24
1
13
XU7
TP2
J9
TP1
JP9
2
4
6
8
1
12
62
64
63
41
40
13
1
3
5
7
2 J5
1
9
JP4
JP7 JP10-GPIO1 FROM
UART2* IRQ* U1 PINS 112-119
GPIO GPIO U1 PINS 37-43*
1
2
3
JP5
JP8
FAN0* CONNECT*
FAN1
BYPASS
104
105
128
126
125
130
103
135
140
127
145
J6
JP2
JP3
JP6
JP9
JUMPER
JP1
1-2
PNF
IRQ11 GPIO14* GPIO22* GPIO21*
3-4
GPIO17
P12
P17
FANOUT1 FANOUT0
P20
5-6
P17
IRRX2
P12
IRQ9
P21*
P17
7-8
P12 GPIO15* IRRX2
PNF
J2
1
1
1
1
GND
2
2
2
2
FANOUT
FAN
JUMPER
IN
OUT
1 U2 8
4
JP10
65 JP13 70
39
60
55
50
JP24
1998
C
NSC
C1
JP7
OVERVIEW 1-7
JP8
150
U4
JP4
5
JUMPER
UP
DOWN
U5
JP5
Figure 1-4. PC87351EB Extension Board Component-Side Layout
1-8 OVERVIEW
2 1
R5
SW1
JP23
JP25
XU7
40
55
50
35
30
41
40
1
3
5
25
C9
20
J8
U1
15
C11
10
1
JP11
1
3
2
C10
100
102
101
110
126
2
JP12
1
2
3
36
38
37
67
66
65
105
115
127
C12
1
J7
J6
9
2
4
6
8
J5
1
2
JP9
1
3
5
7
R10
J9
1
2
1
2
JP6
R11
2
4
6
8
1
2
3
TP1 C13
GND
JP10
RP1
39
60
C7
70 JP13 65
145
0
2
4
6
1
2
1
2
3
J4 JP3
2
4
6
8
GPIO1
1
3
5
7
1
3
5
7
JP7
1
VDD
JP14
62
64
63
140
C5
C6
90
95 C8
104
105
C4
7
85
135
JP5
8
1
8
1
1
1
TP2
R9
103
JP18
ISPEN
1
2 1
2
JP19
3
ISPDIS R6 2 1
1 C2
JP20
2
3
1
4 2
JP21
5
6
2 1
7
JP22
8
J10
1
14
R8
GND
130
1
1
C3
VDD
75
2
R3
4
LD3
R7
JP17
LD2
R4
TP3
VDD PWUREQ VSB
LD1
3
TP4
VSB
125
1
3
5
7
1
C16
0
2
R15
R14
R13
R12
J2
GND 1
2
FANOUT
C15
FAN
PME
1
2
3
4
5
6
7
8
9
10
J3 JP2
J1 JP1
2
1 2
1
4
3 4
3
6
5 6
5
8
7 8
7
GPIO2
C14
JP4
JP8
150
128
JP24
Figure 1-5. PC87351EB Extension Board Print-Side Layout
Chapter 2
INSTALLATION AND CONFIGURATION
2.1
INTRODUCTION
The PC87351EB is an ISA add-in board for a desktop personal computer (PC).
The board consists of two parts, a base board and an extension board containing the PC87351 socket. The board can be connected to various external components, including: serial or PS/2 mouse, modem, keyboard, fan, Floppy Disk
Drive (FDD), National Semiconductor’s Infrared Analog Front End (IRFE) module, printer, GPIO lines and wake-up events lines. Figure 2-1 shows the full
PC87351 chip evaluation system.
PS2 Mouse
PS/2 Keyboard
AC
Power
Supply
S SER1
IRFE
Module
Switch LED
Standby FDD
RST
SW
PC
Motherboard
FDC
1
SSER2
Extension
Board
+
5
1
PC87351
13
PC87351EB
IEEE 1284
Peripheral
Device
1
KBC
PC Desktop Motherboard
Figure 2-1. PC87351 Chip Evaluation System
INSTALLATION AND CONFIGURATION 2-1
2.2
UNPACKING
Verify that your PC87351EB package contains the following items1:
1. One PC87351EB (both base board and extension board).
2. One 3.5" floppy disk containing the easyreg configuration program.
3. One 3.5" floppy disk containing the FanDemo program.
4. PC87351 Datasheet.
5. Two Application Notes:
Using the SuperI/O PC87351 for Fan Speed Control
External Circuit Support for Fan Speed Control.
6. This Reference Manual.
7. PC87351EB Release Letter.
8. One IRFE module and documentation.
9. One KBC cable.
10. Two IDC10 to DB9 cable adapters for the serial ports.
If any item is missing or damaged, contact your nearest Regional Marketing
Office, listed on the back cover of this manual.
2.3
SYSTEM REQUIREMENTS
To fully evaluate the PC87351EB, you need the following equipment:
1. Desktop PC
The PC87351 chip is evaluated on the PC87351EB via a PC-based evaluation
system. The PC87351EB is installed in an ISA bus slot on the PC motherboard.
To evaluate the KBC module of the PC87351, the motherboard must have a discrete KBC chip in the DIP socket (DIP40), and you must connect the KBC cable
from the PC87351 Base Board.
2. PS/2 Keyboard and Mouse
Connect the keyboard and mouse to the J7 and J6 connectors, respectively, on
the PC87351EB base board. Do not connect or disconnect PS/2 peripherals
while system power is on.
1. The contents may vary according to the release. See the Release Letter for details.
2-2 INSTALLATION AND CONFIGURATION
Note
Due to keyboard controller ROM code dependency, the PS/2 keyboard connector
and mouse connectors may be swapped. If your keyboard does not respond, try
swapping the keyboard and mouse cables.
3. External RS-232 Compatible Peripheral Device
This device can be a serial mouse, modem, terminal, PC-to-PC serial connection,
etc. The PC87351EB supports up to two RS-232 serial channels via standard
connectors. You can connect the devices to any of the two serial headers on the
PC87351EB base board.
Note
Use only the supplied cables (Type 2), to connect RS-232 compatible peripheral
devices.
There are two industry standards for an IDC10-to-DB9 cable:
–
–
Type 1 - Connections according to pin numbers
Type 2 - Connections according to physical pin locations; used most widely on new motherboards.
Using a Type 1 cable interferes with the functionality of the connection on the
PC87351EB. For more details, see Appendix A, Sheet 8.
4. IrDA Compatible IRFE Module
The PC87351EB supports infrared channel communication via the J12 connector on the PC87351EB base board, which interfaces with the IRFE. For more details about the IRFE features, see the SuperI/O IRFE Reference Manual.
5. TV IR Remote Control Device (not supplied)
To activate the infrared functions of the PC87351EB, you need an external infrared emitting and/or receiving device. This device can be any IrDA-compliant system: another PC, notebook computer, or printer with IR support, etc. You may
also use a TV IR remote control device from any manufacturer. If the remote
control has a 38 KHz carrier frequency, you may be able to use the internal analog demodulator of the IRFE module to increase operating range.
6. External IEEE 1284 Compliant Peripheral Device
Connect this device (e.g., printer) to the J13 parallel port connector on the
PC87351EB base board, using an IEEE 1284 printer cable. Using other types of
cable may lower performance.
7. External Floppy Disk Drive (FDD)
Connect an FDD to the J10 FDD header on the PC87351EB base board.
8. External Fan
Connect this device to the J1 Fan header on the PC87351EB extension board.
2.4
SYSTEM INSTALLATION
To install your PC87351EB system, follow the step-by-step procedure below.
Note
If you use the KBC, start with the software configuration, Section 2.6.1.
Warning
To prevent damage, turn off the PC power supply before you start.
1. Verify the following PC87351EB settings:
a. Check that all jumpers are in their default positions, (see Tables 2-1 and 2-2).
Table 2-1. Jumper Default Settings on Base Board
Jumper
Default Setting
JP2
1-2 (INT)
JP4
IN
Table 2-2. Jumper Default Settings on Extension Board
Jumper
Default Setting
JP1
5-6 (P20)
JP2
7-8 (GPIO15)
JP3
1-2 (GPIO14)
JP4
IN (UART2)
JP5
UP (FAN0)
JP6
1-2 (GPIO22)
JP7
IN (IRQ)
JP8
UP (CONNECT)
JP9
1-2 (GPIO21)
JP10
OUT (U1 PINS 37-43)
JP11
OUT (P.P.)
JP12
DOWN (P21)
JP13
IN
JP14
DOWN (PIRQ) (Vertical Position)
VBAT
IN
VSB
IN
JP17
OUT (HIGH)
JP18
IN
Table 2-2. Jumper Default Settings on Extension Board (Continued)
Jumper
Default Setting
JP19
IN
JP20
IN
JP21
IN
JP22
IN
JP23
IN
JP24
UP (ISPEN)
JP25
IN
b. Set DIP Switch 1 according to the chip’s base address.
2. Install the PC87351EB in an empty ISA slot on the PC motherboard.
3. Connect all peripherals to the appropriate connectors on the PC87351EB.
Verify the polarity of all connectors, as shown in Figure 2-1.
Caution
Incorrect connections may cause irreversible damage to both the PC87351EB
and motherboard. Pay particular attention to the KBC connections.
4. Turn the PC power supply on.
2.5
HARDWARE CONFIGURATION
This section describes the settings of the DIP switch and jumpers, as well as
the KBC cable connection.
Note
To set up the PC87351EB for a specific application, you must set the DIP
switch for the required base address, and the jumpers for the required configuration (Section 2.5.1), and program the PC87351 configuration registers
(Section 2.6). For further details, see the PC87351 Datasheet.
2.5.1
DIP Switch Setup
A DIP switch on the Extension Board, SW1, enables you to configure the
PC87351 base address. The BADDR (Base Address) pin of the PC87351 is
sensed during power-up reset. An external 10 KΩ resistor is recommended to
pull this pin to VCC.
Table 2-3. Base Address Configuration
BADDR SW1
Position
Index Address
Data Address
UP
0x015C R/W
0x015D R/W
PnP motherboard - wake up in Config state
DOWN
0x002E R/W
0x002F R/W
PnP motherboard - wake up in Config state
2.5.2
Plug and Play Configuration Type
Base Board Jumper Setup
Two base board jumpers (JP2 and JP4) and 25 extension board jumpers (JP1
to JP25) enable you to customize the PC87351EB to your needs.
For details on the base board jumpers, see Appendix A Sheet 4.
JP2
JP2 is located near the STANDBY connector, J8. It selects the source for the
chip standby power pin, VSB.
JP2
Description
1-2 (INT, default) On-board VCC
2-3 (EXT)
JP4
Off-board J8
JP4 is located near the manual reset switch, (SW4). It enables you to use
motherboards that assert the ISA reset signal when you perform a system soft
reset (<Ctrl><Alt><Delete>). In its default state, IN, it enables both ISA and
manual reset.
If you remove this jumper, the chip does not receive the power-on reset signal
from the ISA bus. Before you address any of its registers, press the SW4 reset
switch to reset the chip manually. For further details, see Section 2.6.
JP4
Description
IN (default)
ISA reset is connected
OUT
ISA reset is not connected
2.5.3
Extension Board Jumper Setup
For details on the extension board jumpers, see the schematics in Appendix B.
JP1-4, JP6-7,
JP9
JP1-4, JP6-7 and JP9 route, or control the routing of, some of the multiplexed
pins of the PC87351 chip. The SIOCF2 and SIOCF3 registers, of the PC87351
chip, determine the functions of these pins. For a description of these jumpers
settings, and the configuration of the PC87351 registers, see the table below.
To avoid contention, keep to the following rules:
1. Do not use more than one jumper for a function.
2. To change configuration, perform the following steps:
a. Pull out all the above jumpers.
b. Configure the SIOCF2 and SIOCF3 registers according to the table below.
c. Insert the jumpers according to the table below.
Signals
JP1
JP2
JP3
GPIO10-13
GPIO16
JP4
JP6
JP7
OUT
OUT
SIOCF3,
bit 0=0
SIOCF2,
bit 0=0
JP9
1-2
SIOCF2,
bits 2-1=00
or
bits 2-0=011
GPIO14
7-8
SIOCF2,
bits 4-3=00
or
bits 4-3,0
=011
GPIO15
3-4
GPIO17
SIOCF2,
bits 6-5=00
1-2
GPIO21
SIOCF3,
bits 2-1=00
1-2
GPIO22
SIOCF3,
bits 4-3=00
Signals
JP1
JP2
JP3
JP4
JP6
JP7
JP9
IN
IRQ4-7
IRQ12
SIOCF2,
bit 0=1
5-6
IRQ9
SIOCF2,
bits 2-0=011
1-2
SIOCF2,
bits 4-3,0
=010
IRQ11
"Hot Key"
(P12)
7-8
5-6
KBC Lock
(P17)
KBRST
(P20)
PNF
(in PPM
mode)
3-4
5-6
SIOCF2,
SIOCF2,
bits 6-5=10 bits 4-3=10
SIOCF3,
bits 2-1=10
3-4
7-8
SIOCF2,
SIOCF2,
bits 4-3=11 bits 2-1=11
SIOCF3,
bits 4-3=11
5-6
SIOCF2,
bits 6-5=01
1-2
1-2
SIOCF2,
bits 6-5 =11
SIOCF3,
bits 8-7 =11
IRRX2
IRSL0
7-8
5-6
SIOCF2,
bits 2-1=10
SIOCF3,
bits 4-3=10
3-4
FANOUT0
SIOCF3,
bits 2-1=01
3-4
FANOUT1
SIOCF3,
bits 4-3=01
IN
UART2
SIOCF3,
bit 0=1
JP4
JP4 controls the state of the electronic switch U4. This switch routes pins
112-115 and 117-120 of the PC87351 chip to the PC87351EB. Set up JP4 according to SIOCF3 bit 0, which determines the function of these pins.
JP4
SIOCF3, Bit 0
Function
(PC8735 Pins 112-115 and 117-120)
IN (Default)
1
UART2
OUT
0
GPIO10-16
Note
To avoid contention when JP10 is IN, make sure that GPIO1 connector (J4 on
extension board) is not connected to external signals while JP4 and SIOCF3 bit
0 are configured to UART2 mode, or while configuring JP4 and SIOCF3 bit 0.
JP5
JP5 routes either the FAN0, or FAN1, signal from the PC87351 chip to the
FAN connector (J2).
JP5
JP7
Selected Fan
UP
FAN0
DOWN
FAN1
JP7 controls the state of the electronic switch U6. This switch routes pins 3740 and 43 of the PC87351 chip to the PC87351EB board. JP7 should be setup
according to SIOCF2 bit 0 which determines the above pins function. See table
below.
JP7
SIOCF2, Bit 0
Function
(PC87351 Pins 37-40 and 43)
IN (Default)
1
IRQ4-7,12
OUT
0
GPIO10-13, 16
Note
To avoid contention when JP10 is OUT, make sure that GPIO1 connector (J4
on extension board) is not connected to external signals while JP7 and
SIOCF2 bit 0 are configured to IRQ mode, or while configuring JP7 and
SIOCF2 bit 0.
JP8
To work with DC fans, the PC87351 chip requires an external circuit to interface with the fan. For a fan that does not need an external circuit, you can
connect the fan directly to the PC87351 chip.
JP8
Description
UP
The fan is connected to the Fan Control circuit
DOWN
The fan is connected directly to the PC87351 chip
JP10
JP10 selects one of two groups of pins of the PC87351 chip to connect to the
GPIO1 connector (GPIO10-GPIO16).
JP10
JP11
Selected Pins of the PC87351
IN
112-115, 117-120
OUT
37-43
In PPM mode, JP11 indicates to the PC87351 chip the type of device connected to J13 on the base board. Set this jumper as shown below, otherwise results are undefined.
JP11
JP12
IN
Floppy Disk
OUT
Parallel Device
JP12 routes the multiplexed pin 98, of the PC87351 chip, either to the GPIO2
connector (J3 on the extension board) or to the base board. Set this jumper
according to the function of this pin, which is determined by SIOCF2, bit 7.
JP12
VDD
Type of Device Connected to J13
SIOCF2, bit 7
UP
0
GPIO20
DOWN
1
GA20 (P21)
VDD is used only to measure the chip current, and should always be inserted.
Do not power-up the board unless this jumper, or an amperemeter, is connected.
VDD Jumper
JP14
Function (PC87351 Pin 68)
Description
IN
Normal operating mode
OUT
Illegal, unless replaced by an amperemeter
JP14 routes the multiplexed pins 34, 35 of the PC87351 chip. Set the jumper
according to SIOCF2 register of the PC351, bit 0, as shown below.
JP14
SIOCF2, Bit 0
UP
0
PCICLK
SERIRQ
SIRQ
DOWN
1
IRQ1
IRQ3
Parallel IRQs
PC87351 Pin 34 PC87351 Pin 35 Mode of Operation
VBAT
VBAT is used only to measure battery current to the extension board and
should always be inserted.
VBAT Jumper
VSB
Description
IN
OUT
VSB is used only to measure Stand By voltage current to the extension board,
and should always be inserted.
VSB Jumper
JP17
Description
IN
OUT
JP17 selects the IRSL2 source, or polarity. IRSL2 selects the IRFE mode of operation.
JP17
IRSL2
Mode of Operation
UP
GPIO13 of PC87351 chip
OUT
1
TV Remote
DOWN
0
DATA
For more information about the IRFE modes, see the IRFE documentation.
JP18-23, 25
JP18-23, 25 are spare.
JP24
JP24 enables, or disables, the ISP. It is used only for development purposes.
Always set this jumper in the high position.
JP24
2.5.4
CPLD Outputs
HIGH
ACTIVE (ISP Enabled)
DOWN
FLOAT (ISP Disable)
KBC Connection to the Motherboard
The KBC module is connected directly to the motherboard via a custom-made
flat cable that is supplied with the PC87351EB. See Figure 2-1 and Appendix
A, Sheet 13.
To connect the KBC to the 40-pin DIP socket on the motherboard keyboard
controller chip:
1. Remove the original 8042 chip (or equivalent) and replace it with a 40-pin
DIP socket (not supplied).
2. Connect J4 to the socket using only the 40-pin cable provided.
3. Connect the 40-pin cable:
Pin 1 (brown) on the narrow connector corresponds to pin 1 of J4 on the
base board.
Pin 1 on the other end of the 40-pin cable, is connected to pin 1 of the DIP
socket on the motherboard.
Caution
2.5.5
Incorrect connections may cause irreversible damage to your PC87351EB and
motherboard.
KBC Automatic Hardware Configuration
The PC87351EB has an automatic hardware configuration capability. Assuming that you have connected the KBC cable correctly and securely (see Figure
2-1), it detects the presence of a cable by sensing the VCC pin of the motherboard KBC socket. This is accomplished by means of a PAL input, KBCPRES.
For more details, see Appendix D and to Appendix A, Sheet 4 and Sheet 13.
2.6
2.6.1
SOFTWARE CONFIGURATION
Configuring the PC87351 to Work in Parallel IRQ Mode
The PC87351EB supports Parallel IRQ mode only. The configuration process
for this mode depends on whether the KBC is used, or not.
Without the
KBC
To configure the PC87351 chip for Parallel IRQ mode if you are not using the
KBC:
From your prompt line run:
debug
- o BASE ADDRESS 22
- o BASE ADDRESS+1 a0
Where BASE ADDRESS refers to the base address of the chip (either 2E or15C).
For more details on the base address, see Table 2-3.
With the KBC If you are using the KBC, perform the following steps before the hardware installation (an example follows the explanation):
1. Edit a batch file that includes the following lines:
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
q
BASE ADDRESS 23
BASE ADDRESSS+1 1
BASE ADDRESS 7
BASE ADDRESS+1 7
BASE ADDRESS 60
BASE ADDRESS+1 GPIO1_HIGH_ADDRESS
BASE ADDRESS 61
BASE ADDRESS+1 GPIO1_LOW_ADDRESS
BASE ADDRESS 30
BASE ADDRESS+1 1
BASE ADDRESS f0
BASE ADDRESS+1 16
BASE ADDRESS f1
BASE ADDRESS+1 5
GPIO1_ADDRESS 0
BASE ADDRESS 22
BASE ADDRESS+1 a0
GPIO1_HIGH_ADDRESS
refers to the MSB of the GPIO1 address.
GPIO1_LOW_ADDRESS
refers to the LSB of the GPIO1 address.
GPIO1_ADDRESS
refers to the GPIO1 address which consists of
GPIO1_HIGH_ADDRESS and GPIO1_LOW_ADDRESS.
2. At the beginning of your autoexec.bat file, add the following line:
debug < [path]/file_name
Example
The PC87351 chip base address is 15C, and the GPIO1 address is configured
to 200h. The batch file, 351config.bat, is in the root directory.
The first line of the autoexec.bat file is:
debug < 351config.bat
The 351config.bat file is:
o
o
o
o
o
o
o
o
o
o
o
o
o
15c
15d
15c
15d
15c
15d
15c
15d
15c
15d
15c
15d
15c
23
1
7
7
60
2
61
0
30
1
f0
16
f1
o
o
o
o
q
2.6.2
15d
200
15c
15d
5
0
22
a0
Easyreg Software Utility
The advanced features of the PC87351 chip are enabled by software configuration. To facilitate this task, use the easyreg software utility supplied with
this package.
The easyreg Configuration Program is a DOS utility that enables you to view
and configure the major features of the chip, in particular the Enhanced
UART, and Plug and Play features. Easyreg is a stand-alone, executable DOS
file (easyreg.exe). For a detailed description, see the README file on your floppy disk.
2.6.3
PC87351 Reset
The chip must exit the reset cycle prior to accessing its registers. The reset is
performed automatically during each powerup, if the JP4 jumper on the base
board is inserted (default). If not, you must manually reset the chip by pressing the on-board reset switch, SW4, located near the bracket. After reset, you
can override the hardware configuration by programming the configuration
registers.
2.6.4
Configuration Register Access
In the Configuration state, the PC87351 Index and Data registers are determined by the BADDR strap option (see Table 2-3). The location of the PC87351
register set complies with the Plug and Play ISA Specification, Version 1.0a.
For more details, see the ISA Plug and Play Specifications, Rev. 1.0a. For detailed
information on accessing the registers of the PC87351, see the PC87351
Datasheet.
Chapter 3
THEORY OF OPERATION
3.1
INTRODUCTION
This chapter describes the operation of the main circuit blocks of the
PC87351EB, based on the schematics in Appendix A and Appendix B.
See Appendix A, Sheet 1, and Appendix B, Sheet 1, to verify if the revision
numbers on your base and extension boards match those of the schematics. If
your board is a newer revision, contact your nearest National Semiconductor
representative for updated schematics. See the block diagram in Appendix A
(Sheet 2) for a root-level representation of the base board design. This will help
you locate the various modules described in this chapter.
Note
3.2
Unless specified otherwise, all component references are to the components on
the base board.
STANDARD ISA BUS ADD-ON CONNECTOR
See Appendix A, Sheet 3 for a diagram of this connector.
This connector includes the AT gold-plated finger sub-connectors, P1 and P2.
The connector layout corresponds to an ISA bus edge connector. To help you
locate the signals more easily, the connector is shown in its physical layout
position. The power supply to the board comes from the ISA bus, and includes
+5V and ±12V power supplies. Decoupling capacitors are placed on these
power supplies to minimize the voltage ripple. The TC signal from the ISA bus
is filtered by R58 and C33.
3.3
GLUE LOGIC
See Appendix A, Sheet 4 for a diagram of this circuitry.
With the exception of the seven decoupling capacitors on the VDD net, the
components of this module are not required in the motherboard application.
This circuit creates the correct environment for PC87351 evaluation on the
PC87351EB by providing an interface between the on-chip KBC module and
the X-Bus, which is not available on the ISA bus.
Two data switches connect the PC87351 data bus to the system: U10 connects
to the ISA bus, and U5 to the X-Bus. Only the KBC module of the PC87351
needs to be connected to the X-Bus. The PAL controls the U10 and U5 switches. See Figure 3-1.
THEORY OF OPERATION 3-1
IRQ1
PC87351
P12,17,20,21
JUMPERS
SIOD[0..7]
XENBL
KBC Conn. 20*2
ISAENBL
CSIN
74LVX
3L384
U5
74AC
TQ32
PAL 22V10
U6
U7
74LVX
3L384
U10
Glue Logic
RXD[0..7]
SA[12..15]
SA[0..111]
KBCPRES
SD[0..7]
IORD
IOWR
AEN
SA[0..15]
ISA Bus
Figure 3-1. ISA Bus and X-Bus Data Architecture
Switch enabling is based on the ISA access address. The switches are controlled by two of the PAL U6 outputs, XENBL and ISAENBL.
The ISA switch, U10, is enabled for any read or write access from/to any SuperI/O module located at any address, except the KBC legacy addresses: 60
and 64.
The X-Bus switch, U5, is enabled for any read or write access from/to the
KBC module, only when it is enabled in its legacy addresses, as described
above.
One 22V10 PAL device, U6, and one 74ACTQ32, U7, are used in this block.
The 74ACTQ32 decodes the high ISA address bits A12-A15, and provides the
PAL with the CSIN signal that is active low when all the high address bits are
zero. The PAL controls the data switches:
• The ISAENBL signal is active on all I/O cycles, except when the address is
60, 64h (KBC legacy address spaces).
• The XENBL signal is active only on I/O cycles with address 60, 64h (KBC
legacy address space).
3-2 THEORY OF OPERATION
Jumpers on the extension board route P12,17,20,21 signals to the PC87351
chip.
The PAL facilitates automatic hardware configuration for the KBC cable. For
further details, see Section 2.5.5 and Figure 2-1.
3.4
DEBUG RESET CIRCUIT
See Appendix A, Sheet 4 for a diagram of this circuit.
This circuit allows you to reset the chip, at any time, by pressing the SW4
switch located near the bracket. It also allows you to disconnect the reset signal from the ISA bus by removing the JP4 jumper. For a description of this
jumper, see Section 2.5.2. See also Section 2.6 for software configuration details.
3.5
PC87351 CHIP
See Appendix B, Sheet 2, for a diagram of the PC87351 chip connections.
This block contains the PC87351 chip, U1 on the extension board. U1 interfaces directly with the ISA bus, with the exceptions of the 8-bit data bus that
is connected by the U10 switch (Appendix A, Sheet 4) and IRQ1,3 which are
connected by JP14 jumper on the extension board (Appendix B, Sheets 2, 3).
Other external elements, such as decoupling capacitors, pull-up and pulldown resistors are also required.
3.6
BATTERY CIRCUIT
This circuit includes a 3V lithium battery, CR2335, BT1. It serves to keep the
wakeup events configuration valid when the system is powered off.
You do not need any external components to comply with the UL safety standard; all the necessary protection circuitry is on-chip.
The decoupling capacitors, C31 and C11, on the extension board help prevent
noise on the VBAT line. XBT2 is an optional socket for a smaller, CR2032 type,
battery. The R82 resistor serves only for current measuring.
The VBAT jumper on the extension board enables you to measure the battery
current consumption of the PC87351 chip. This jumper should always be inserted.
3.7
FDC
See Appendix A, Sheet 7 for a diagram of the FDC.
You can connect the FDC of the PC87351 to a maximum of two Floppy Disk
Drives via a 34-pin standard header, J10. Standard 1 KΩ pull-ups (RN2) are
used on all input signals.
3.8
UART1 AND UART2
See Appendix A, Sheet 8 for a diagram of the UARTs.
Each serial port connector, J1 and J2, is a 10-pin dual-row header. The
PC87351 chip interfaces these connectors through two DS14185 devices, U1
and U2, respectively. DS14185 is an RS-232 compliant 3-driver/5-receiver
chip, manufactured by National Semiconductor. This chip uses the +5V and
±12V power supplies, assuring the most cost-effective implementation and
minimum chip count in PC desktop applications. A standard EMI filter circuit
is provided for each port (R1-R8/C66-C73 and R9-R16/C74-C81).
Note
The pinout matches the IDC10-to-DB9 adapter cable supplied with the package. For further details, see Section 2.3.
The PC87351 chip’s wakeup module can sense the state of the RI1 and RI2 serial port inputs. This feature supports applications in which an external modem ring signal wakes up the system. To keep these two inputs alive during
system power-off, the corresponding line receivers are separated from the
DS14185 devices, powered from the standby power supply, and consume very
little power. If your application does not implement the above feature, the U3
line receiver can be omitted.
Note
3.9
The standby voltage VSB on the extension board is referred to as VCCH on the
base board.
INFRARED
See Appendix A, Sheet 9 for a diagram of this module.
A 9-pin D-type female connector, J12, interfaces the PC87351 chip with the
supplied analog IRFE module. J12 is located on the bracket for easy access.
The serial resistor R34 (33 Ω) on the IRTX signal from the PC87351 protects
the signal from transmission effects.
When the IRFE is not connected to the board, pull-up resistors R35, R38,
R39, R37 and R36 (150 KΩ) assure legal logic levels for the IRRX1 input signal. If your application implements the IRFE on the same motherboard so that
it is always present, omit these resistors.
The IRFE supports FIR, MIR, SIR and Sharp-IR protocols, as well as TVremote with demodulation outside the PC87351. See Section 4.3.8 for the
header pinout. See also the IRFE documentation for a full description of its
features.
3.10 PARALLEL PORT
See Appendix A, Sheet 10, for a diagram of the parallel port.
The IEEE 1284 parallel port on the PC87351 is connected to a standard DB25
connector, J13, on the board’s bracket via the ECP terminations.
The PC87351 can route the FDD signals to the parallel port connector. This
means that a FDD device can be connected to this DB25 connector. For the
setting for this option see the PC87351 Datasheet.
3.11 FAN CONTROL CIRCUIT
The PC87351 chip includes a fan control which supports two fans. The
PC87351 generates a PWM (Pulse Width Modulation) signal at the fan output
according to a predefined frequency and width. External circuitry is needed to
convert the 5V PWM output to the 12V logic level used by the fan.
There is one control circuit that can be connected either to Fan0 or to Fan1.
The JP5 jumper on the extension board selects which fan is connected to the
fan circuit.
JP8 on the extension board routes the fan control to the fan connector J2 on
the extension board. It selects either the output from the fan control circuit,
or the direct output from the PC87351 chip. This enables the use of a fan that
can be connected directly to the PWM signal.
Note
When using a fan that connects directly to PWM, it is your responsibility to
comply with the PC87351 electrical specifications (see the PC87351 Datasheet).
Before using the fan, set JP6 or JP9 according the desired configuration. See
Section 2.5.3 for more details. See Figure 3-2 for Fan Control Circuit Layout.
12V
18Ω 18Ω 18Ω
1KΩ
10µF
PC87351
JP8
J2
JP5
FANOUT0
FANOUT1
U2
NDS9942
Figure 3-2. Fan Control Circuit
For more details, see Appendix B, Sheet 4.
3.12 ISP
An ISP, U8 on the extension board, is used to enforce a low logic level on the
IRQ1 signal during booting, thus enabling a proper setup of the keyboard in
SIRQ mode. After booting, you must configure the PC87351 chip to toggle the
GPIO16/IRQ12 pin and to work in a parallel IRQ mode. The ISP detects the
toggle and releases the IRQ1 signal.
For more information about the configuration of the PC87351 chip see Section 2.6.1.
The ISP device, a Lattice 1032E, is programmed by a PC parallel port connected to a single-row 8-bit header, J10. In a regular mode, it is not necessary to
program the ISP since it should be already programmed.
Seven jumpers are reserved for future implementations.
J10
ISPEN
HEADER 8X1
SDI
SCLK MODE
SDO
U8
JP18
JP21
JP20
Spare
Jumpers
JP19
JP23
JP25
JP22
Vcc
10K
IRQ1
IRQ3
Vcc
10K
Vcc
10K
ispLSI 1032E
Vcc
10K
IRQ15
Vcc
10K
Vcc
10K
Vcc
10K
Figure 3-3. ISP Block
3.13 GPIO PORTS AND PME
See Appendix B, Sheet 4, for a diagram of the GPIO ports and the PME.
3.13.1
GPIO1
The GPIO1 port is connected to a dual-row, 10-pin header, J4 on the extension board. GPIO1 has eight signals: GPIO10-GPIO17. Except for GPIO17, all
the signals are duplicated on the PC87351 chip to two sets of pins. To allow
evaluation of each of the two sets, two bus changers U5, U3 on the extension
board, are used as shown in Figure 3-4.
U5 74LVX3L383
J4
A
Set A [10-13]
Set A [10-16]
Set B [10-13]
Set B [10-16]
GPIO1 5*2
GPIO1 [10-16]
C
B
PC87351
Bus Exchange
U3 74LVX3L383
A
Set A [14-16]
10K
C
Set B [14-16]
JP10
B
Bus Exchange
Figure 3-4. GPIO1 Circuit
3.13.2
GPIO2
The GPIO2 port is accessible on a dual-row, 10-pin header, J3 on the extension board. To use the port, set the jumpers JP12, JP6, JP9 on the extension
board according to Section 2.5.3.
3.13.3
PME Connector
A dual-row, 10-pin header, J1 on the extension board connects the multiplexed pins: PME1/RING and PME2/SUSP of the PC87351 chip.
Bits 0,2 of SIOCF4 register of the PC87351 chip, determine the functionality
of the pins as described in the two tables below:
Table 3-1. PME1/RING Pin
SIOCF4, Bit 0 Function of PME1/RING Pin
0
RING
1
PME1
Table 3-2. PME2/SUSP Pin
SIOCF4, Bit 2
Function of PME2/SUSP Pin
0
SUSP
1
PME2
The PME1, PME2 and RING signals are used as wake up events.
For more details see the PC87351 Datasheet.
3.14 PS/2 KEYBOARD AND MOUSE CONNECTORS
See Appendix A, Sheet 12 for a diagram of these connectors.
The PC87351 directly interfaces with a keyboard and a PS/2 type mouse. The
KBCLK and KBDAT, MCLK and MDAT signals are connected to the keyboard
and mouse connectors, J7 and J6 (MINI-DIN 6-pin type). They are located at
the top of the board for easy access. A standard EMI filter circuit is provided
(L1-6, C47-52). In a high-end system, you may also implement a protection
circuit on the power pins of J7 and J6. See Sections 4.3.4 and 4.3.5 for connector pinout.
3.15 KBC CONNECTOR
See Appendix A, Sheet 13, for a diagram of this connector.
Only motherboards with a discrete KBC chip in the DIP socket can be used to
evaluate the KBC module from the PC87351 on the PC87351EB.
You can connect the PC87351 KBC block to the motherboard via a 40-pin
header, J4. (See Section 4.3.3 for J4 pinout). Connect J4, located on the left
side of the board, with the supplied cable to the KBC socket on the motherboard. (See Section 2.5.4 for system installation procedures). Bear in mind
that you may have to replace the 8042 KBC chip, which must be a 40-pin DIP
component, with a 40-pin socket.
The KBC module uses two IRQ signals. IRQ1 is connected by the J4 connector, pin 12. IRQ12, used by the PS/2 mouse, is connected directly to the ISA
connector.
Some of the GPIO lines on the original 8042 device are not available on the
PC87351. Instead, pull-up resistors RN1 (1 KΩ, 9-resistor pack) are connected
to these pins to prevent them from floating. Pins P20 and P21 are pulled-up
by resistors R78 and R77 (10 KΩ). These two signals are open drain, and are
used as the GATEA20 and the RESET signals from the KBC.
3.16 TEST CONNECTORS
See Appendix B, Sheet 2 for a diagram of the test connectors.
Connectors XJ4 (A, B, C and D) are used to mount the extension board. All
the PC87351 pins are accessible for testing on XJ4 connector pins. The XJ4E
connector carries the 12V voltage for the Fan circuit from the base board to
the extension board.
Chapter 4
SPECIFICATIONS
4.1
INTRODUCTION
The PC87351EB is designed to be mounted in a PC-AT slot.
4.2
PHYSICAL SPECIFICATIONS
The four-layer PC87351EB measures 231 mm x 107.8 mm. It is designed to
be used in a laboratory environment within normal commercial temperature
and humidity ranges:
Temperature
Humidity
4.3
: 0 °C to + 50 °C
: 0% to 90%, no condensation
BASE BOARD CONNECTORS
The PC87351 base board has 11 connectors, described in this section.
Table 4-1 shows the function and type of each connector.
Table 4-1. PC87351EB Connector List
Connector
Description
J1
SERIAL1 Connector, double-row 10-pin header
J2
SERIAL2 Connector, double-row 10-pin header
J4
KBC Connector, double-row 40-pin header
J6
PS/2 Mouse, MINI-DIN 6-pin round connector
J7
PS/2 Keyboard, MINI-DIN 6-pin round connector
J8
Standby Power Connector, single-row 3-pin header
J10
FDC Connector, double-row 34-pin header
J12
IR Connector, DB9 female connector
J13
Parallel Port Connector, DB25 female connector
P1
ISA Bus Connector, XT, edge 62-pin
P2
ISA Bus Connector, AT, edge 36-pin
SPECIFICATIONS 4-1
4.3.1
SERIAL1 Connector, J1
A double-row, 10-pin header.
Table 4-2. SERIAL1 Connector, J1
Signal
4.3.2
Pin No.
Pin No.
Signal
DCD1F
1
2
DSR1F
SIN1F
3
4
RTS1F
SOUT1F
5
6
CTS1F
DTR1F
7
8
RI1F
GND
9
10
N.C.
SERIAL2 Connector, J2
A double-row, 10-pin header.
Table 4-3. SERIAL2 Connector, J2
Signal
4.3.3
Pin No.
Pin No.
Signal
DCD2F
1
2
DSR2F
SIN2F
3
4
RTS2F
SOUT2F
5
6
CTS2F
DTR2F
7
8
RI2F
GND
9
10
N.C.
KBC Connector, J4
A double-row, 40-pin header whose pinout is similar to the DIP 40-pin KBC
socket on a PC motherboard. Only some of the signals are supplied by the
PC87351. The rest are not connected, or are connected to 1 KΩ pull-up resistors.
Table 4-4. KBC Connector, J4
Signal
4-2 SPECIFICATIONS
Pin No.
Pin No.
Signal
N.C.
1
2
KBCV
N.C.
3
4
N.C.
N.C.
5
6
P27
Table 4-4. KBC Connector, J4 (Continued)
Signal
Pin No.
Pin No.
7
8
P26
N.C.
9
10
N.C.
N.C.
11
12
IRQ1
N.C.
13
14
P17
N.C.
15
16
P16
N.C.
17
18
P15
N.C.
19
20
P14
N.C.
21
22
P13
RXD0
23
24
P12
RXD2
25
26
P11
RXD3
27
28
P10
RXD4
29
30
N.C.
RXD5
31
32
N.C.
RXD6
33
34
P23
RXD7
35
36
P22
RXD2
37
38
P21
GND
39
40
P20
N.C.
4.3.4
Signal
Mouse Connector, J6
A MINI-DIN 6-pin round connector.
Table 4-5. Mouse Connector, J6
Pin No.
Signal
1
MDATC
2
N.C.
3
GND
4
MOUVCC
5
MCLKC
6
N.C.
SPECIFICATIONS 4-3
4.3.5
KBD Connector, J7
A MINI-DIN 6-pin round connector.
Table 4-6. KBD Connector, J7
Pin No.
4.3.6
Signal
1
KBDATC
2
N.C.
3
GND
4
KBDVCC
5
KBCLKC
6
N.C.
Standby Power Connector, J8
A 3-pin header.
Table 4-7. Standby Power Connector, J8
Pin No.
4.3.7
Signal
1
N.C.
2
VHEXT
3
GND
FDC Connector, J10
A double-row, 34-pin header. J10 can connect up to two Floppy Disk Drives.
Table 4-8. FDC Connector, J10
Signal
4-4 SPECIFICATIONS
Pin No.
Pin No.
Signal
GND
1
2
DENSEL
GND
3
4
N.C.
GND
5
6
DRATE0
GND
7
8
INDEX
N.C.
9
10
MTR0
Table 4-8. FDC Connector, J10 (Continued)
Signal
4.3.8
Pin No.
Pin No.
Signal
GND
11
12
DR1
GND
13
14
DR0
GND
15
16
MTR1
MSEN1
17
18
DIR
GND
19
20
STEP
GND
21
22
WDATA
GND
23
24
WGATE
GND
25
26
TRK0
MSEN0
27
28
WP
N.C.
29
30
RDATA
GND
31
32
HDSEL
N.C.
33
34
DSKCHG
IRFE Connector, J12
A 9-pin D-Type, female, right-angle bracket mounted connector, with two additional pins for shield connection
.
Table 4-9. IRFE Connector, J12
Pin
No.
TX/RX
Signals
1
IRTXC
Control
Signals
PnP
Identification
Signals
2
GND
3
4
ID3 (Not Used)
IRRX2
5
6
IRSL0
ID0 (Not Used)
IRSL1
ID1 (Not Used)
IRRX1
7
IRVCC
8
9
10, 11
Power
IRSL2
ID2 (Not Used)
N.C.
SHIELD
SPECIFICATIONS 4-5
4.3.9
Parallel Port Connector, J13
A DB25 female connector.
Table 4-10. Parallel Port Connector, J13
4.3.10
Pin No.
Signal
1
RSTB
2-9
RPD0-RPD7
10
RACK
11
RBUSY
12
PE
13
SLCT
14
AFD
15
ERR
16
INIT
17
RSLIN
18 - 25
GND
ISA XT and AT Connectors, P1 and P2
The pinout for these connectors meets ISA specifications.
4.4
4.4.1
EXTENSION BOARD CONNECTORS
PME Connector, J1
A 10-pin, dual-row header.
.
Table 4-11. PME Connector, J1
4-6 SPECIFICATIONS
Pin No.
Signal
1
PME1/RING
2
PME2/SUSP
3-8
N.C.
9,10
GND
4.4.2
Fan Connector, J2
Table 4-12. Fan Connector, J2
4.4.3
Pin No.
Signal
1
GND
2
FANOUT
GPIO2 Connector, J3
Table 4-13. GPIO2 Connector, J3
4.4.4
Pin No.
Signal
1
GPIO20
2
GPIO21
3
GPIO22
4-8
N.C.
9,10
GND
GPIO1 Connector, J4
Table 4-14. GPIO1 Connector, J4
Pin No.
Signal
1
GPIO10
2
GPIO11
3
GPIO12
4
GPIO13
5
GPIO14
6
GPIO15
7
GPIO16
8
GPIO17
9,10
GND
SPECIFICATIONS 4-7
4.4.5
ISP Connector, J10
An 8-pin, single-row header.
Table 4-15. ISP Connector, J10
4.5
Pin No.
Signal
1
VDD
2
ISPEN
3
SDI
4
SCLK
5
MODE
6
SDO
7,8
GND
CURRENT REQUIREMENTS
The PC87351EB board requires +5V and
±12V.
Table 4-16 shows the maximum calculated power consumption for each chip.
Table 4-16. Max Power Consumption
Chip
Quantity
+5V
Current [mA]
PC87351
1
32a
DS14185
2
60
DS14C89
1
1
PAL22V10
1
140
74ACTQ32
1
6
74F132
1
18
74LVX3L384
4
80
74LVX3L383
2
40
ispLSI1032E
1
190
Total
567
+12V
Current [mA]
−12V
Current [mA]
44
-56
44
-56
a. Typical value
The maximum calculated power consumption for the board is:
567 mA
44 mA
−56 mA
4-8 SPECIFICATIONS
@ +5V
@ +12V
@ −12V
Appendix A
BASE BOARD SCHEMATIC DIAGRAMS
The following pages contain the schematics diagrams for the PC87351EB base
board.
BASE BOARD SCHEMATIC DIAGRAMS A-1
682-002/A
682-002/A
186
189
682-002/B
682-002/C
682-002/A
682-001/A
686-001/A
2.1
2.0
SCH
1.0
1.1
1.2
1.3
1.4
REVISIONS
DESCRIPTION
INITIAL VERSION
DDR REVIEW
UPDATE FOR PC87309 SUPPORT
RELEASED VER AFTER BACKANOTATION
CONFIGURATION RESISTORS, U2, U1
UPDATE FOR PC87309EB USE ONLY.
ASSEMBLY BASE NUMBER --> 686
NEW PCB LAYOUT INCLUDING:
PULL-DOWN OPTION ON STRAP PINS,
SOCKET OPTION FOR U4.
R41 680R PULL-DOWN
R41 10K PULL-DOWN, U8 CMOS
COVER.SCH
PC87317.SCH
ISA.SCH
LOGIC.SCH
CHIP.SCH
CFG.SCH
FDC.SCH
SER.SCH
IR.SCH
PAR.SCH
GPIO_APC.SCH
PS2.SCH
KBC_RTC.SCH
TST_CON.SCH
317EB.LIB
SCHEMATIC:
LIBRARY:
DATE
JAN
JAN
FEB
FEB
MAR
1997
1997
1997
1997
1997
09 APR 1997
23 MAR 1997
07
20
03
09
04
PCB P/N
980521694-001
ASSEMBLEDASSEMBLED
PCB P/N:
980521682-002
REV:C
Title
COVER PAGE
Size Document Number
REV
B
870521682-200
2.1
Date:
April 10, 1997 Sheet
1 of
14
PC87317 EVALUATION
PC87351 BASEBOARD
BOARD
NATIONAL
SEMICONDUCTOR
NATIONAL
SEMICONDUCTOR
NATIONAL SEMICONDUCTOR LIBRARY
IACOB T.
IACOB T.
APPROVED
IACOB T.
IACOB T.
IACOB T.
IACOB T.
IACOB T.
COVER PAGE
BLOCK DIAGRAM
ISA CONNECTOR
GLUE LOGIC
PC87317 CHIP CONNECTIONS
PC87317 CONFIGURATION & CLOCK SOURCES
FLOPPY DISK DRIVE CONNECTOR
SERIAL PORTS DRIVERS & CONNECTORS
INFRARED PORT CONNECTOR
PARALLEL PORT TERMINATIONS & CONNECTOR
GPIO AND ADVANCED POWER CONTROL
PS/2 KEYBOARD AND PS/2 MOUSE
KBC AND RTC CABLE CONNECTORS
TEST CONNECTORS
COVER.SCH
PG.1
PG.2
PG.3
PG.4
PG.5
PG.6
PG.7
PG.8
PG.9
PG.10
PG.11
PG.12
PG.13
PG.14
DESIGN FILES (ORCAD 386+)
682-001/A
682-001/A
184
ECN# PCB 551521 ASS 980521
ISA.SCH
ISAD[0..7]
ISARST
GND
ISAVCC
-12V
+12V
DRQ[0..3]
nZWS
IOCHRDY
AEN
nIORD
nIOWR
SA[0..15]
PG.3
IRQ[1..15]
TCF
nDACK[0..3]
ISA CONNECTOR
PAEN
nCSIN
CFG0A
VCC
EXTVCC
VCC
VCC
RXD[0..7]
PG.4
TST_CON.SCH
GND
VCC
VDD
PG.14
C[6..7]
S[1..160]
PG.12
TEST CONNECTOR
PAEN
nCSIN
CFG0A
PS[1..4]
PS2.SCH
GND
EXTVCC
PS/2 CONNECTORS
VCC
PG.13
K[1..5]
GND
KBC_RTC.SCH
IRQ[1..15]
VCC
KBC AND RTC CONN.
RTCPRES
RXD[0..7]
KBCPRES
LOGIC.SCH
KBCPRES
RTCPRES
LOGIC AND POWER
ISAD[0..7]
SIOD[0..7]
ISARST
MR
SA[0..15] SA[0..15]
AEN
AEN
VCC
nIORD
nIORD
nIOWR
nIOWR
EXTVCC
ISAVCC
CFG0A
CFG0A
VDD
nCSIN
PAEN
GND
ISAVCC
-12V
+12V
VDD
CFG0A
C[6..7]
S[1..160]
PS[1..4]
K[1..5]
IRQ[1,8]
RXD[0..7]
VDD
EXTVCC
VCC
MR
SIOD[0..7]
IRQ[3,4,5,6,7,9,
11,12,14,15]
TCF
nDACK[0..3]
DRQ[0..3]
nZWS
IOCHRDY
AEN
nIORD
nIOWR
SA[0..15]
VDD
VCC
CHIP.SCH
S[1..160]
PS[1..4]
K[1..5]
GND
VDD
VCC
MR
SIOD[0..7]
IRQ[1..15]
TCF
nDACK[0..3]
DRQ[0..3]
nZWS
IOCHRDY
AEN
nIORD
nIOWR
SA[0..15]
nSTB
nAFD
nERR
nINIT
nSLIN
nACK
BUSY
PE
SLCT
PD[0..7]
IRTX
IRRX1
IRRX2
IRSL1
IRSL2
ID3
nDCD2
nDSR2
SIN2
nRTS2
SOUT2
nCTS2
nDTR2
nRI2
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nCTS1
nDTR1
nRI1
F[1..18]
VCCH
PG.5
X1
X2C
X1C
C[0..5]
nSWITCH
nONCTL
nLED
nRING
GPIO3[0..7]
GPIO2[0..7]
GPIO1[0..7]
PC87317 SUPERIO
VCCH
X1
X2C
X1C
C[0..5]
nSWITCH
nONCTL
nLED
nRING
GPIO3[0..7]
GPIO2[0..7]
GPIO1[0..7]
nSTB
nAFD
nERR
nINIT
nSLIN
nACK
BUSY
PE
SLCT
PD[0..7]
IRTX
IRRX1
IRRX2
IRSL1
IRSL2
ID3
nDCD2
nDSR2
SIN2
nRTS2
SOUT2
nCTS2
nDTR2
nRI2
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nCTS1
nDTR1
nRI1
F[1..18]
CFG.SCH
C[6..7]
CFG0A
X1
X2C
X1C
PC87317 CONFIG
C[0..5]
GPIO_APC.SCH
nSWITCH
nONCTL
nLED
nRING
GPIO3[0..7]
GPIO2[0..7]
GPIO1[0..7]
GPIO & APC
PAR.SCH
PARALLEL PORT
nSTB
nAFD
nERR
nINIT
nSLIN
nACK
BUSY
PE
SLCT
PD[0..7]
IR.SCH
IRTX
IRRX1
IRRX2
IRSL1
IRSL2
ID3
IR PORT
SER.SCH
nDCD2
nDSR2
SIN2
nRTS2
SOUT2
nCTS2
nDTR2
nRI2
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nCTS1
nDTR1
nRI1
SERIAL PORT
FDC.SCH
F[1..18]
FDC
VCC
VCCH
VCC
PC87317 EVALUATION BOARD
PC87351 BASE BOARD
NATIONAL SEMICONDUCTOR
BLOCK DIAGRAM
B
870521682-200
Date:
Title
EXTVCC
VCC
SHIELD
VCC
VCCH
EXTVCC
VCCH
-12V
+12V
VCC
VCC
PC87317.SCH
PG.6
GND
VCC
GND
PG.11
VCCH
VCC
EXTVCC
GND
PG.10
VCC
SHIELD
SHIELD
PG.9
GND
VCC
VCCH
EXTVCC
PG.8
GND
VCCH
-12V
+12V
VCC
GND
PG.7
VCC
2 of
REV
2.1
14
PRINT
SIDE
ISA ADD-IN
CARD
EDGE
CONNECTOR
COMPONENT
SIDE
C45
22U
N/A
2
1
J11
N
P
IRQ11
IRQ10
2 C44
0.1U
1
N
P
1
2
TCF
R58
100R
2 C33
47P
1
2
1
N
C29
22U
22U
C25 P
BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB
3322222222221111111111987654321
1098765432109876543210
SSSSSSSSSSSSSSSSSSSSAISSSSSSSSI
AAAAAAAAAAAAAAAAAAAAEODDDDDDDDO
00000000001111111111NC00000000C
01234567890123456789 H01234567H
C
R
K
D
Y
P1
PCXT62
R
E
S
S
E
D
SS
YR D D
B AIIIIISEDADA
MM + -D I T
GO+A CRRRRRCFRCRCIIEEG1Z1R-R+DG
NS5LTKQQQQQLSQKQKOOMMN2W2Q5Q5RN
DCVEC234567KH1133RWRWDVSV2V9VVD
AAAAAAAAAAAAAAAAAAAAAA
3322222222221111111111AAAAAAAAA
1098765432109876543210987654321
C42 C41
22U 0.1U
TC
DDDDDDDDDDDDDDDDDD
111111111987654321
876543210
P2
PCAT36
M
M
IE
A
D D D DIIIIIOM
S DADADADARRRRRCC
GT+RCRCRCRCQQQQQSS
NE5QKQKQKQK1111111
DRV776655004521066
SSSSSSSSMMLLLLLLLS
DDDDDDDDEEAAAAAAAB
11111100MM1112222H
54321098WR7890123E
CCCCCCCCC
111111111CCCCCCCCC
876543210987654321
N
P
C27
22U
2 C24
0.1U
1
P
N
ISAVCC
ISARST
IRQ1
IRQ2
IRQ8
IRQ13
nIOWR
nIORD
nZWS
-12V
+12V
SA[0..15]
ISAD[0..7]
IOCHRDY
AEN
IRQ[1..15]
TCF
nDACK[0..3]
DRQ[0..3]
nIOWR
nIORD
nZWS
-12V
+12V
ISAVCC
ISARST
GND
ISAD[0..7]
SA[0..15]
IOCHRDY
AEN
ISA.SCH
PG.3,13
PG.5
PG.5
PG.5
PG.4,5
PG.4,5
PG.5
PG.8
PG.8
PG.4
PG.4
PG.4
PG.4,5
PG.5
PG.4,5
PC87351 BASE BOARD
ISA CONNECTOR
B
870521682-200
Date:
Title
3 of
REV
2.1
14
ISAD[0..7]
AEN
CFG0A
PG.3 AEN
PG.6 CFG0A
PG.3 ISARST
ISARST
ISARST
JUMPER
RESET
SWITCH
ISAVCC
nIOWR
PG.3 nIOWR
PG.3 ISAVCC
nIORD
PG.3 nIORD
PG.3 SA[0..15]
PG.3
1
4
5
SA13
SA14
SA15
SA12_13
6 SA14_15
U7B
74ACTQ32
74ACTQ32
3
U7A
SW4
5
4
RST_NC
RST_NO
2
JP4
DEFAULT: IN
1
XJP4
R41 10K
1
2
10K
R32
1
2
VCC
1
2
3
10K
R33
1
2
VCC
RST
8
nCSIN
CFG0A
nISAENBL
nXENBL
PAEN
nCSIN
AEN
nIORD
nIOWR
SA11
N/A
MR
nISARST
6
5
74ACT00
nSW 4 U8B
SW
RTCPRES
KBCPRES
C19
0.1U
1
2
VCC
DEBUG
RESET CIRCUIT
C28
2 0.1U
1
VCC
74ACTQ32
U7C
R40
0R
1
2
3
2
74ACT00
1 U8A
9 U8C
8
10
74ACT00
11
13
74ACT00
12 U8D
9
10
U6
VCC 24
C/I
IO10 23
I2
IO9 22
I3
IO8 21
I4
IO7 20
I5
IO6 19
I6
IO5 18
I7
IO4 17
I8
IO3 16
I9
IO2 15
I10
IO1 14
I11
GND
I12 13
PAL22V10
DIP24 ON SOCKET
THIS CIRCUIT EXIST ONLY FOR AN
ISA ADD-IN BOARD APPLICATION.
FOR A MOTHERBOARD APPLICATION
THIS CIRCUIT IS NOT NEEDED.
2
1
2
3
4
5
6
7
8
9
10
11
12
SA12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
VCC
ISAD[0..7]
MR
PG.5
VCC
ISAVCC
2
DEFAULT: IN
VDD
JUMPER
JP3
1
XJP3
nXENBL
SIOD3
SIOD2
SIOD1
SIOD0
SIOD4
SIOD5
SIOD6
SIOD7
nISAENBL
ISAD7
ISAD6
ISAD5
ISAD4
ISAD0
ISAD1
ISAD2
ISAD3
VCC
24
2
5
6
9
10
15
16
19
20
23
VCC
24
2
5
6
9
10
15
16
19
20
23
N/A
1
TP5
N/A
1
TP6
2
1
PIN #
C35
22U
N
P
BE5-9 GND 12
74LVX3L384A
SMD-TSOP24
BE0-4
SWITCH
U5
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
BE5-9 GND 12
74LVX3L384A
SMD-TSOP24
BE0-4
SWITCH
U10
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
C21
0.1U
13
1
3
4
7
8
11
14
17
18
21
22
13
1
3
4
7
8
11
14
17
18
21
22
2
1
VCC
2
1
1 C43
2 0.1U
VCC
1 C26
2 0.1U
2
1
F2
2
2
1
2
1
Title
PC87351 BASE BOARD
61
100 121 140
24
DECOUPLING FOR PC87317
4 of
REV
2.1
14
PG.5
PG.14
PG.9
PG.11
PG.12
GND
TO PC87317
PIN #
1
24
61
100
121
140
VDD
PG.13
PG.5
PG.14
PG.13
VCC
N/A
GND
VCC
1
1
VCC
EXTVCC
TP3
TP4
LOGIC AND POWER
B
870521682-200
LOGIC.SCH Date:
1
N/A
FUSE-SOCKET
1
2
1.5A/125V
1
GND
VCC
N/A
VCC
1
1
VCC
XF1 SMD 2A
FUSE
TP2
TP1
RXD[0..7]
SIOD[0..7]
nCSIN
PAEN
161
162
TO TEST CON
RTCPRES
KBCPRES
TEST POINTS
nCSIN
PAEN
RTCPRES
KBCPRES
C39 C36 C32 C34 C38 C37
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U
2
1
EXT
FUSE
RXD3
RXD2
RXD1
RXD0
RXD4
RXD5
RXD6
RXD7
SIOD7
SIOD6
SIOD5
SIOD4
SIOD0
SIOD1
SIOD2
SIOD3
GND
VCC
VDD
JP1
8X10R
JUMPER
ON SOCKET
1
2
3
4
5
6
7
8
PG.3
PG.4
PG.11
SA[0..15]
SIOD[0..7]
GPIO2[0..7]
GPIO1[0..7]
GPIO3[0..7]
VDD
CFG0
VDD
C0
(CFG2)
PIN
PIN
PIN
PIN
73
74
75
76
PIN 77
C3 (CFG3)
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
C2
CFG1
BADDR1
C5
C1
BADDR0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
C4
SIOD[0..7]
SA[0..15]
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
PIN
79
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO30
GPIO31
GPIO32
C[0..5]
VCC
REMOVE JUMPER JP1
WHEN TESTING GPIO3.
INSERT IT WHEN
TESTING SERIAL2 OR IR.
FROM IR
INTERFACE
nCTS2
nDCD2
nDSR2
nDTR2
nRI2
nRTS2
SIN2
SOUT2
PG.8
IRRX2
nCTS1
nDCD1
nDSR1
nDTR1
nRI1
nRTS1
SIN1
SOUT1
PD[0..7]
BUSY
nSTB
nACK
SLCT
PE
nERR
nINIT
nSLIN
nAFD
VDD
16
15
14
13
12
11
10
9
PD[0..7]
BUSY
nSTB
nACK
SLCT
PE
nERR
nINIT
nSLIN
nAFD
K[1..5]
PS[1..4]
PG.6 C[0..5]
PG.10
PG.13
PG.12
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
IRSL2/ID2
S121
S122
S123
S124
S125
S126
S127
S128
S129
S130
S131
S132
S133
S134
S135
S136
S137
S138
S139
S140
S141
S142
S143
S144
S145
S146
S147
S148
S149
S150
S151
S152
S153
S154
S155
S156
S157
S158
S159
S160
VDD
VDD
VDD
1111111111222222222233333333334
1234567890123456789012345678901234567890
I
O
C
H
IIII
VV
V
AAVVAAAAAZR
RRRRV
DSDDDDDDDDSAAAAAAAAAA11DS1111EWDRWTQQQQS
DS01234567S012345678901DS2345NSYDRC1345S
VASIEPSASBPPPPPMMKKVVDWITRDWHSDWDDMMDMMI
SFLNRELCTU22111DCBBSDSPNRDEGDTIDRRTTRSSR
SDIIR CKBS10762ALDCSDK DKANASERA10RRAEET
/NT
T /Y
C E0TSTEP T
10TNNX
//TKAL
E10
D/
W/
H X AEEL
A
TK
GC
0
SA
RW
G
L
PS
TS
IA
I0
RT
TI
O
BR
ET
2
GPIO24/IRRX1
VDD
B
5
GPIO37/IRRX2/IRSL0/ID0
PD0
IRSL1/ID1/XD7
PD1
IRSL2/SELCS/GPIO21/XD6
PD2
GPIO27/XD5
PD3
PD4
GPIO26/XD4
PD5
GPIO25/XD3
PD6
GPIO24/XD2
PD7
CS2/XD1
VSS
CS1/XD0/CSOUT-NSC
CTS1
XDRD/ID3
DCD1
RING/XDCS
DSR1
LED/CS0
DTR1/BADDR0
ONCTL
RI1
SWITCH
VCCH
RTS1/BADDR1
VBAT
SIN1
U4
X2C
SOUT1/BOUT1/CFG0
X1C
VSS
PC87317-XXX/VUL
VDD
VDD
GPIO30/CTS2
VSS
ON SOCKET
GPIO31/DCD2
DACK3
GPIO32/DSR2
DACK2
NOT MOUNTED
DTR2/CFG1
DACK1
GPIO33/RI2
DACK0
DRQ3
GPIO34/RTS2
DRQ2
GPIO35/SIN2
DRQ1
GPIO36/SOUT2
DRQ0
GPIO10
MR
GPIO11
X1
GPIO12
IRQ15
GPIO13
IRQ14
GPIO14
IRQ12
GPIO15/PME2
IRQ11
GPIO16/PME1
GPIO17/WDO
IRQ10
IRQ9
GPIO20/IRSL1/ID1
GPIO21/IRSL0/IRSL2/ID2
IRQ8
GPIO22/POR
IRQ7
GPIO23/RING
IRQ6
111111111111111111111
2111111111100000000009999999999888888888
0987654321098765432109876543210987654321
nERR
nINIT
nSLIN
nAFD
K4
K5
P20
P21
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Title
nDACK3
nDACK2
nDACK1
nDACK0
DRQ3
DRQ2
DRQ1
DRQ0
MR
X1
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
IRQ9
IRQ8
IRQ7
IRQ6
IRQ2
IRQ13
VCCH
VBAT
VDD
P
X2C
X1C
PC87351EVALUATION
BASE BOARD BOARD
PC87317
5 of
AEN
nZWS
IOCHRDY
nIORD
nIOWR
TCF
IRQ[1..15]
X1
MR
REV
2.1
14
PG.3
PG.6
PG.4
PG.3
PG.6
3.0V
N
XBT2
N
BT1
CR2032
OPTION
SOCKET
N/A
PP
12
PG.11
PG.14
PG.9
PG.7
RTC
BACKUP
DRQ[0..3]
nDACK[0..3]
NEAR
PIN 64
1C31
0.1U
2
R82
1
2
SPARE
1 C30
0.1U
2 NEAR
PIN 65
nRING
nLED
nONCTL
nSWITCH
VCCH
NATIONAL
SEMICONDUCTOR
X2C
X1C
nRING
nLED
nONCTL
nSWITCH
GPIO21
GPIO27
GPIO26
GPIO25
GPIO24
GPIO37
IRTX
IRRX1
IRRX2
IRSL1
IRSL2
ID3
S[1..160]
TO TEST
CONNECTOR
PC87317 CHIP
B
870521682-200
CHIP.SCH Date:
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S[1..160]
TO PC87317
PIN 158
JP1/8
F[1..18]
2
1
3
2
1
4
R71A R71B
10K SMD-1206
SW2B
2
1
5
*3)
R69A
10K
N/A
SW2C
R72A/B AND R71A/B ARE
PROVIDED FOR PC87308/307
SUPPORT ONLY; SEE TABLE 4.
*2)
1
R72B
SMD-1206
2
1
2
2
1
NOTE 2:
R72A
10K
SW2A
1
2
1
4
1
6
1
3
VCC
SW1D
7
1
0
VCC
SW2D
7
1
0
U7D
13
NOTE 3:
0=OFF 1=ON
DEFAULT: 1100
2
1
R74
10K
11
CFG0B
CFG0A
1
R70B
SMD-1206
2
8
9
002E
015C
1
CFG0
1
0
X
X
1
0
0
SW2
ENABLED
CFG1
X
Y
X
N
Y
1
N
0 *3
48MHz ON X1
32.768KHz
0
CFG2
0
1
0
1
1
SW2
CFG3
0
0
1
1
1
1
BADDR0
X
1
0
0
SW1
BADDR1
0
CHIP\SIGNAL
PC87307
PC87308
PC87317
PC87309
BADDR
1
0
CFG0A
CFG
2
1
C[6..7]
C[0..5]
3
PG.14
PG.5
PG.4
PG.14
0
POWER-ON CONFIGURATION SIGNALS
TABLE 4.
X-DATA BUFFER
PC87317 ONLY
CLOCK SOURCE
DEFAULT :
KBC RTC FDC
RESET CONFIG
TABLE 3.
24MHz ON X1
RESERVED
48MHz ON X1
32.768KHz
DEFAULT :
CLOCK CONFIG
PC87308/307 *1)
TABLE 2.
DEFAULT :
PnP MBD
FULL PnP ISA
BASE ADDRESS
TABLE 1.
R69A IS NOT ASSEMBLED SINCE THE
X-BUS DATA BUFFER IS NOT
IMPLEMENTED IN THIS EVALUATION BOARD.
74ACTQ32
R73
2 1K
1
12
1
1
R69B
SMD-1206
2
R70A 2
100R
6
1
1
CFG3
VCC
0=OFF 1=ON
DEFAULT: 1110
1
R66B
SMD-1206
2
8
9
BADDR0
1
1
R65B
SMD-1206
2
R66A 2
10K
6
1
1
CFG2
VCC
1
5
5
VCC
CFG0
SW1C
1
2
VCC
BADDR1
1
1
R64B
SMD-1206
2
R65A 2
10K
4
1
3
CFG1
1
1
R63B
SMD-1206
2
R64A 2
10K
1
3
2
SW1B
1
R63A 2
10K
SW1A
1
4
1
6
1
5
VCC
VCC
RES2
U7D, SW1 AND SW2 ARE NEEDED ONLY FOR THE
EVALUATION BOARD.
THE REAL APPLICATION
NEEDS ONLY SOME PULL-UP RESISTORS.
RES1
NOTE 1:
2
R17
20M
120K
GND SHIELD NET
X1C
1
R18
1
2
XR
2
C4
10P
1
1
2
C3
33P
1 2
Y1
X1
X1
SOCKET
DIP14
CFG.SCH
XU9
8
11
14
VCC
7
1
U9
8
CRYSTAL-OSC
DIP14
DEFAULT: 48MHz
C23
2 0.1U
1
Title
PC87317 CONFIGURATION & CLOCK SOURCE
REV
B
870521682-200
2.1
Date:
6 of
14
PC87351 BASE BOARD
GND
VCC
VCC
THE EXTERNAL OSCILLATOR IS
NEEDED ONLY IF NOT USING
THE ON-CHIP CLOCK MULTIPLIER.
EXTERNAL CLOCK OSCILLATOR
7
4
1
14
32.768KHz
4
3
RTC OSCILLATOR & CLOCK MULTIPLIER SOURCE
X1C
X2C
NOTE 5:
PG.5
PG.5
PG.5 X2C
PG.5
F[1..18]
GND
VCC
nWDATA
nSTEP
nDIR
nMTR1
nDR0
nDR1
nMTR0
F10
F9
F8
F7
F6
F5
F4
DRATE0
DENSEL
F2
F1
F3
nWGATE
F11
nINDEX
MSEN1
nWP
MSEN0
nTRK0
F12
nRDATA
nDSKCHG
F15
F14
F13
nHDSEL
F16
F17
F18
C22
2 0.1U
1
SIP6
5X1K
123456
RN2
J10
HD17X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FLOPPY
DISK
DRIVE
CONNECTOR
FDC.SCH
PC87351 BASE BOARD
FLOPPY DISK DRIVE CONNECTOR
B
870521682-200
Date:
7 of
Title
REV
2.1
14
HD5X2
U3B
DS14C89A
7
6
U3C
DS14C89A
10
7
1
4
1
4
4
VCCH
8
HD5X2
VCCH
SPARE
SERIAL
PORT #2
CONNECTOR
J2
USE ONLY THE CABLES
WITH STRIGHT CONNECTIONS
IMPORTANT NOTE :
SERIAL
PORT #1
CONNECTOR
J1
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
2
2
2
2
2
2
2
2
DCD1F
DSR1F
nSIN1F
RTS1F
nSOUT1F
CTS1F
DTR1F
RI1F
C66
C67
C68
C69
C70
C71
C72
C73
R1
R2
R3
R4
R5
R6
R7
R8
200P
200P
200P
200P
200P
200P
200P
200P
33R
33R
33R
33R
33R
33R
33R
33R
EMI FILTER
NOTE:
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
DCD2F
DSR2F
nSIN2F
RTS2F
nSOUT2F
CTS2F
DTR2F
RI2F
DCD2F
DSR2F
nSIN2F
RTS2F
nSOUT2F
CTS2F
DTR2F
RI2F
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
C74
C75
C76
C77
C78
C79
C80
C81
R9
R10
R11
R12
R13
R14
R15
R16
200P
200P
200P
200P
200P
200P
200P
200P
33R
33R
33R
33R
33R
33R
33R
33R
3.
ON THIS BOARD,
DUE TO LAYOUT
LIMITATIONS,
THE CAPACITORS
ARE CONNECTED
TO GND.
2.
CONNECT THE
CAPACITORS
TO SHIELD.
1.
PLACE CLOSE TO
CONNECTORS.
1
1
1
1
1
1
1
1
DCD1F
DSR1F
nSIN1F
RTS1F
nSOUT1F
CTS1F
DTR1F
RI1F
DCD2
DSR2
nSIN2
RTS2
nSOUT2
CTS2
DTR2
RI2
DCD1
DSR1
nSIN1
RTS1
nSOUT1
CTS1
DTR1
RI1
C62
0.1U
20
19
18
17
16
15
14
13
12
11
2
1
C56
2 0.1U
13
20
19
18
17
16
15
14
13
12
11
1
7
1
4
VCCH
3
DS14185M
SMD-SO20W
U3A
DS14C89A
2
1
C60
2 0.1U
1
2
3
4
5
6
7
8
9
10
1
VCC
2
U2
11
C55
2 0.1U
1
VCCH
1
+12V
7
1
4
VCCH
DS14185M
SMD-SO20W
1
2
3
4
5
6
7
8
9
10
1
U1
2
VCC
1
U3D
DS14C89A
-12V
C61
0.1U
C59
0.1U
-12V
C57
0.1U
+12V
VCC
nDCD2
nDSR2
SIN2
nRTS2
SOUT2
nCTS2
nDTR2
nRI2
GND
VCC
VCCH
+12V
-12V
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nCTS1
nDTR1
nRI1
PC87351 BASE BOARD
SERIAL
PORT #2
SERIAL
PORT #1
PG.5
PG.11
PG.3
PG.3
PG.5
Title
SERIAL PORTS DRIVERS AND CONNECTORS
B
870521682-200
Date:
8 of
VCCH
+12V
-12V
SER.SCH
nDCD2
nDSR2
SIN2
nRTS2
SOUT2
nCTS2
nDTR2
nRI2
C58
N 22U
P
VCC
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nCTS1
nDTR1
nRI1
REV
2.1
14
EXTVCC
PG.5
IRSL1
IRRX2
IRSL2
ID3
IRRX1
IRTX
GND
VCC
PG.11 VCCH
PG.4
VCC
VCCH
IRRX2
IRTXC
IRRX1
IRTX
IRRX1
IRRX2 IRSL0 ID0
IRSL1 ID1
IRSL2 ID2
ID3
IR MULTIPLEXED
SIGNALS
33R
R34
1
2
EXTVCC
IRSL1
IRSL2
IRSL0
C5
N 100U
P
ID1
ID3
ID2
ID0
1
C20
2 0.1U
1
R38
150K
2
ID0
IRRX1
VCCH
1
R35
150K
2
VCCH
1
R37
150K
2
ID2
ID1
VCC
1
R39
150K
2
VCC
ID3
1
R36
150K
2
VCC
THE PULL-UPS ON IRRX1
AND IRRX2 ARE CONNECTED
TO VCCH SINCE THEY
CAN BE INPUTS TO APC.
PULL-UPS TO ASSURE
THE LOGIC LEVEL WHEN
THE IR FRONT END (IRFE)
IS NOT CONNECTED.
1
0
IR.SCH
PC87351 BASE BOARD
INFRARED PORT CONNECTOR
B
870521682-200
Date:
9 of
Title
PG.10
SHIELD
INFRARED
PORT
CONNECTOR
DB9
SHIELD
J12
CON DB9 FEMALE
1
6
2
7
3
8
4
9
5
1
1
REV
2.1
14
PG.5
SLCT
PE
BUSY
nACK
nSLIN
nINIT
nERR
nAFD
nSTB
PD[0..7]
SLCT
PE
BUSY
nACK
nSLIN
nINIT
nERR
nAFD
nSTB
PD[0..7]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
R51
1
2
4.7K
R52
1
2
4.7K
R53
1
2
4.7K
R54
1
2
4.7K
VCC
VCC
VCC
VCC
VCC
R56
1
2
4.7K
R55
1
2
4.7K
R50
1
2
4.7K
VCC
VCC
R49
1
2
4.7K
R48
1
2
4.7K
VCC
VCC
R47
1
2
4.7K
R46
1
2
4.7K
VCC
VCC
R45
1
2
4.7K
R44
1
2
4.7K
R43
1
2
4.7K
R42
1
2
4.7K
VCC
VCC
VCC
VCC
680P
C18
1 2
680P
C17
1 2
330P
C16
1 2
330P
C15
1 2
330P
C14
1 2
330P
C13
1 2
330P
C12
1 2
330P
C11
1 2
330P
C10
1 2
330P
C9
1 2
330P
C8
1 2
330P
C7
1 2
330P
C6
1 2
1
1
1
1
1
1
1
1
1
1
1
1
1
2 R31
2 R30
2 R29
2 R28
2 R27
2 R26
2 R25
2 R24
2 R23
2 R22
2 R21
2 R20
2 R19
100R
100R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
SLCT
PE
RBUSY
nRACK
RPD7
RPD6
RPD5
RPD4
RPD3
nRSLIN
RPD2
nINIT
RPD1
nERR
RPD0
nRAFD
nRSTB
RPD7
RPD6
RPD5
RPD4
RPD3
RPD2
RPD1
RPD0
nERR
2
2
6
2
7
PC87351 BASE BOARD
Title
PARALLEL PORT TERMINATIONS AND CONNECTOR
REV
B
870521682-200
2.1
Date:
10 of
14
GND
VCC
SHIELD
PG.6
VCC
SHIELD
PARALLEL
PORT
R81
PCB SHORT
N/A
1
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
J13
CON DB25 FEMALE
PE
RBUSY
SLCT
nINIT
nRACK
PAR.SCH
nRSLIN
nRSTB
nRAFD
GPIO1
APC
GPIO1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3
2
1
1
2
3
4
5
6
7
8
9
10
HD5X2
J5
CONNECTOR
GPIO3
STANDBY
POWER
CONNECTOR
J8
HD15X2
0.1"
J9
VHEXT
nONCTL
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
VHEXT
nONCTL
EXTVCC
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
nRING
nSW
nLED
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
ADVANCED
POWER
CONTROL
CONNECTOR
AND
GENERAL
PURPOSE I/O 1,2
P C40
N 22U
1 C2
2 0.1U
ACPI
LED
SWITCH
2
JP2
1
2
3
XJP2
VCCH
EXTVCC
VCC
P C46
N 22U
1 C1
2 0.1U
1 C54
2 0.1U
INTERNAL
2-3
DEFAULT
VCCH
SOURCE
nRING
VCCH
nONCTL
nLED
nSWITCH
R68
100K
2 N/A
(ON CHIP 1M PULL-UP)
1
R57
100K
LED WITH RES
R67
10K
1
EXTERNAL
1-2
VCCH
2
4
VHEXT
CA
LD1
1
3
SW3
VCCH
2
1
VCCH
PG.5
PG.5
GPIO_APC.SCH
GPIO3[0..7]
GPIO2[0..7]
GPIO1[0..7]
EXTVCC
VCC
VCCH
GND
nONCTL
nLED
nSWITCH
nRING
PC87351 BASE BOARD
GENERAL PURPOSE I/O AND APC
B
870521682-200
Date:
11 of
Title
REV
2.1
14
GND
VCC
VCC
PS[1..4]
PG.2 EXTVCC
PG.5
MCLK
MDAT
PS4
KBDAT
PS2
PS3
KBCLK
PS1
R62
10K
2
1
1
2
VCC
VCC
2
1
R60
10K
1
2
VCC
VCC
R61
10K
R59
10K
L4
2
KBCLKC
L1
2
MCLKC
L3
BLM31A02PT
L2
BLM31A02PT
1
2
MOUVCC
BLM31A02PT
1
2
MDATC
1
1
C49
2330P
1
C48
2330P
1
C52
2330P
1
C51
2330P
EMI FILTERS
L6
BLM31A02PT
L5
BLM31A02PT
1
2
KBDVCC
BLM31A02PT
1
2
KBDATC
1
1
C50
20.1U
1
C47
20.1U
2
6
4
3
5
1
2
6
4
3
5
1
12 of
PC87351 BASE BOARD
PS/2
MOUSE
CONNECTOR
PS/2
KEYBOARD
CONNECTOR
PS/2 CONNECTORS
B
870521682-200
Date:
Title
J6
CON-MDIN-6P
MINI-DIN
J7
CON-MDIN-6P
MINI-DIN
PS2.SCH
98
7
98
7
REV
2.1
14
3. PIN 1 (BROWN COLOR) OF THE
CABLE MUST BE CONNECTED TO PIN 1
OF J4 AND PIN 1 OF THE SOCKET.
2. CONNECT J4 TO THE ABOVE
SOCKET USING THE SUPPLIED CABLE.
CS
AS
R/W
NC
DS
RST
IRQ
NC
NC
NC
SQW
DS1287
DIP24
GND
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NC
VCC
13
14
15
16
17
18
VSS
D7
D6
D5
D4
D3
D2
D1
D0
SYNC
WR
A0
RD
EA
CS
SS
T1
VCC
P20
P21
P22
P23
PROG
VDD
P10
P11
P12
P13
P14
P15
P16
P17
P24/OB
P25/BF
P26/DRQ
P27/DAK
8042
DIP40
RESET
X2
X1
T0
PS/2 SYSTEM
FUNCTIONALITY
28
10
11
12
13
31
30
29
28
16
17
MCLK-OUT
MDAT-OUT
GATE-A20
SYS-RST
25
24
23
22
21
20
19
18
15
26
14
29
9
32
KBDAT-IN
30
8
33
27
31
7
21
22
23
24
25
26
27
32
33
34
6
35
36
37
38
39
40
34
5
4
3
2
1
13
14
15
16
17
35
MDAT-IN
IRQ1
IRQ12
36
KBCLK-OUT
37
KBDAT-OUT
MCLK-IN
38
39
40
12
11
10
9
8
18
20
19
5
20
21
7
4
21
22
23
24
6
3
19
2
22
1
23
8042 MICROCONTROLLER
PINOUT
20
19
18
17
16
15
14
13
12
11
10
9
7
6
5
4
3
2
1
PROCEED AS FOLLOWS :
1. REMOVE THE ORIGINAL 8042
CHIP (OR EQUIVALENT) AND REPLACE
IT WITH A 40-PIN DIP SOCKET.
MOT
NC
KBC IC PINOUT
8
SA2
KBCLK-IN
PS/2 SYSTEM
FUNCTIONALITY
12
11
10
9
8
7
6
5
4
3
2
24
DS1287 / MC146818
RTC PINOUT
CONNECT IT TO THE 40-PIN DIP
SOCKET ON THE MOTHERBOARD’S
KEYBOARD CONTROLLER CHIP.
THIS CONNECTOR IS NEEDED
FOR EVALUATION PURPOSES ONLY.
KBD
CONNECTOR
3. PIN 1 (BROWN COLOR) OF THE
CABLE MUST BE CONNECTED TO PIN 1
OF J3 AND PIN 1 OF THE SOCKET.
2. CONNECT J3 TO THE ABOVE
SOCKET USING THE SUPPLIED CABLE.
1. REMOVE THE ORIGINAL DS1287
CHIP (OR EQUIVALENT) AND REPLACE
IT WITH A 24-PIN DIP SOCKET.
PROCEED AS FOLLOWS :
CONNECT IT TO THE 24-PIN DIP
SOCKET ON THE MOTHERBOARD’S
REAL-TIME CLOCK CHIP.
THIS CONNECTOR IS NEEDED
FOR EVALUATION PURPOSES ONLY.
RTC
CONNECTOR
1
RTC IC PINOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
RXD7
RXD6
RXD5
RXD4
RXD2
IRQ8
RXD3
RXD1
RXD0
RTCV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HD20X2
J4
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
KBCV
ALL UNAVAILABLE
SIGNALS ARE
PULLED UP.
HD12X2
J3
1
P20
P21
P22
P23
P10
P11
P12
P13
P14
P15
P16
P17
IRQ1
P26
P27
2
1
2
1
SIP10
9X1K
C63
2 0.1U
1
C65
2 0.1U
1
K4
K5
K1
K2
K3
PG.5
PG.4
PAL
PG.4
VCC
PC87351 BASE BOARD
GND
VCC
K[1..5]
REV
2.1
14
PG.5
10K PULL-UPS
ON P20, P21
SINCE THEY ARE
OPEN-DRAIN.
P20
P21
P12
P16
P17
P20
1
R78
10K
2
VCC
IRQ[1..15]
KBCPRES
RTCPRES
P21
1
R77
10K
2
VCC
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ1
IRQ8
KBCPRES
RTCPRES
RXD[0..7]
KBC AND RTC CONNECTORS
B
870521682-200
Date:
13 of
Title
1234567891
0
RN1
R76
1K
2
R79
1K
2
KBC_RTC.SCH
C64
0.1U
2
1
VCC
R75
100R
1
R80
100R
RXD[0..7]
PG.4
PG.6
PG.4
PG.4
PG.5
VCC
C[6..7]
CFG0A
PAEN
nCSIN
S[1..160]
GND
VDD
VDD
C6
C7
CFG0A
PAEN
nCSIN
S[1..160]
S161
S162
S163
S164
S165
S166
S167
S168
S169
S170
R86
1
2
SPARE
SPARE
R83
1
2
SPARE
R85
1
2
VDD
VDD
R84
1
2
SPARE
VDD
SPARE
CONNECTIONS
TO EXTENSION
BOARD
S[161..170]
12V
1
1 2 3 4 5 6 7 8 9 0 XJ4E
HD5X2
0.05" FEM
N/A
1111111111222222222233333333334
1234567890123456789012345678901234567890
VDD
VDD
VDD
XJ4A
HD40X1
0.05" FEM
N/A
XJ4D
HD40X1
0.05" FEM
N/A
1
S121
2
S122
3
S123
4
S124
5
S125
6
S126
7
S127
8
S128
9
S129
10
S130
11
S131
12
S132
13
S133
14
S134
15
S135
16
S136
17
S137
18
S138
19
S139
20
S140
21
S141
22
S142
23
S143
24
S144
25
S145
26
S146
27
S147
28
S148
29
S149
30
S150
31
S151
32
S152
33
S153
34
S154
35
S155
36
S156
37
S157
38
S158
39
S159
40
S160
4333333333322222222221111111111
0987654321098765432109876543210987654321
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
XJ4B
HD40X1
0.05" FEM
N/A
XJ4C
HD40X1
0.05" FEM
N/A
GND
VCC
GND
VCC
GND
VCC
TST_CON.SCH
PC87351 BASE BOARD
14 of
REV
2.1
14
BRACKET DB25/9
M2
TYRAP-99MM
(X-TAL OSC.)
PCB
PC87317EB
PRINTED
CIRCUIT
BOARD
M1
LABEL REV A
M3
LB2
LABEL S/N
SOCKET-24
DIP24 TH
FOR PAL
XU6
LB1
SOCKET-16
DIP16 TH
FOR JP1
XJP1
SOCKET-160
PQFP160-SMD-SMD
XU4
TEST CONNECTORS
B
870521682-200
Date:
Title
WIRE WRAP AREA
W11 W12 W13 W14 W15 W16
W21 W22 W23 W24 W25 W26
VCC VCC VCC VCC VCC VCC
W31 W32 W33 W34 W35 W36
W41 W42 W43 W44 W45 W46
W51 W52 W53 W54 W55 W56
W61 W62 W63 W64 W65 W66
Appendix B
EXTENSION BOARD SCHEMATIC DIAGRAMS
The following pages contain the schematics diagrams for the PC87351EB extension board.
EXTENSION BOARD SCHEMATIC DIAGRAMS B-1
NSC IS EXPRESSLY FORBIDDEN.
COPYRIGHT 1998
DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF
TO NATIONAL SEMICONDUCTOR CORP. (NSC). USE OR
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
EXTENSION BOARD
PC87351
LIBRARY:
NSC1.LIB
SCH
1.0
1.1
REVISIONS
DESCRIPTION
INITIAL VERSION
RELEASED VERSION AFTER
BACK ANOTATION
DATE
25 FEB 1998
4 MAR 1998
Date:
Size
B
Title
1
2
3
4
Sheet
1
of
NATIONAL SEMICONDUCTOR LIBRARY
4
Rev
1.1
APPROVED
Y. MARGALIT
Y. MARGALIT
COVER PAGE
PC87351 CHIP CONNECTIONS AND GLUE LOGIC
SERIAL IRQ CIRCUIT
FAN CIRCUIT AND PARTS
Thursday, March 19, 1998
Document Number
8 7 0 5 2 1 6 9 4-100
COVER PAGE
PG.
PG.
PG.
PG.
DESIGN FILES (ORCAD)
694-001/A
ASS 980521
SCHEMATIC: COVER
PC87351 CONNECTIONS
SIRQ
FAN_PARTS
694-001/A
ECN# PCB 551521
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
15C
12V
PAGE 4
HD40X1
J6
2E
VDD
R2
10K
VDD
1
1 R3
10K
1 R5
10K
VDD
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VSS
nCTS1
nDCD1
nDSR1
nDTR1/BADDR
nRI1
nRTS1
SIN1
SOUT1
VSS
VDD
nCTS2
nDCD2
nDSR2
nDTR2
nRI2_S
nRTS2
SIN2
SOUT2/BOUT2
SW1
PNF
GPIO17
GPIO20
J5
2
13
1
3
4
7
8
11
14
17
18
21
22
3
1
PAGE 4
JP4
VDD
2
2 SPARE
GPIO20
GND
VCC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
12
24
JP1
R8
10K
IRSL2
1
3
5
7
1
2
GPIO10/nDCD2
GPIO11/nDSR2
GPIO12/SIN2
GPIO13/nRTS2
GPIO14/SOUT2
GPIO15/nCTS2
GPIO16/nDTR2
VDD
P21_M
1
VBAT
1
3
5
7
1
3
5
7
GPIO14/SOUT2
GPIO15/nCTS2
GPIO16/nDTR2
nRI2
MDAT
nDCD1
nDSR1
SIN1
nRTS1
SOUT1
nCTS1
nDTR1/BADDR
nRI1
GPIO10/nDCD2
GPIO11/nDSR2
GPIO12/SIN2
GPIO13/nRTS2
VSB
nPWUREQ
JP17
3
VDD
2
4
6
8
GPIO15/nCTS2
GPIO10/nDCD2
GPIO11/nDSR2
GPIO16/nDTR2
nRI2
GPIO13/nRTS2
GPIO12/SIN2
GPIO14/SOUT2
IRSL2
2
5
6
9
10
15
16
19
20
23
IRRX2
P17
P12
PNF
FANOUT1
FANOUT0
GPIO22
GPIO21
PME1/nRING
PME2/nSUSP
GPIO10_A
GPIO11_A
GPIO12_A
GPIO13_A
GPIO14_A
GPIO15_A
GPIO16_A
7 4 L V X 3 L 3 8 4A
BE5-9
BE0-4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
U4
P20
2 P20_M
JP12
PNF
GPIO17
P21
P12
JP9
JP6
J8
MDAT
DCD1
DSR1
SIN1
RTS1
SOUT1
CTS1
BADDR/DTR1/BOUT1
RI1
GPIO10/DCD2
GPIO11/DSR2
GPIO12/SIN2
GPIO13/RTS2
VSS3
GPIO14/SOUT2
GPIO15/CTS2
GPIO16/DTR2/BOUT2
RI2
NC11
VBAT
VSB
PWUREQ
PME1/RING
PME2/SUSP
GPIO21/FANOUT0/PNF/P12
GPIO22/FANOUT1/IRRX2/P17
HD40X1
2
4
6
8
2
4
6
8
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
U1
p c 8 7 351
HD40X1
J7
nAFD
SLIN
nINIT
nERR
PE
SLCT
nACK
nSTB
BUSY
P21
P20
P17
MCLK
KBDAT
KBCLK
P20_M
P21_M
VDD
4
3
ON
1
2
1
2
VDDC
P12
MDAT
MCLK
KBDAT
KBCLK
nSTB
nAFD
PD0
nERR
PD1
nINIT
PD2
SLIN
PD3
PAGE 4
VDD
VDDC
1
2
1
2
3
4
5
6
7
8
9
10
PD4
PD5
PD6
PD7
nACK
BUSY
PE
SLCT
VDD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
TC
SERIRQ/IRQ3
PCICLK/IRQ1
IRQ1
IRQ3
WGATE
TRK0
WP
RDATA
HDSEL
DSKCHG
NC6
IRRX1
IRTX
NC5
TC
DACK3
DACK2
VSS1
DACK1
DRQ3
DRQ2
DRQ1
MR
CLKIN
NC4
GPIO16/IRQ12
GPIO15/IRQ11/P12/P17
GPIO14/IRQ9/IRRX2/P17
GPIO13/IRQ7
GPIO12/IRQ6
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
VDD
VSS
A12
A13
A14
A15
AEN
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VDD
nDSKCHG
nWP
nINDEX
nTRK0
nRDATA
DENSEL
nWGATE
nHDSEL
nSTEP
nDIR
nWDATA
nDR1
nDR0
n M T R1
nMTR0
DRATE0
DENSEL
DRATE0
nINDEX
nMTR0
nDR1
nDR0
n M T R1
nDIR
nSTEP
nWDATA
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
MCLK
K B D AT
KBCLK
KBRST/GPIO20
G A 2 0 / G P IO17/PNF/P12
NC10
NC9
STB/WRTIE
AFD/DSTRB/DENSEL
PD0/INDEX
ERR/HDSEL
PD1/TRK0
INIT/DIR
PD2/WP
S L IN/ASTRB/STEP
PD3/RDATA
VDD2
V S S2
PD4/DSKCHG
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
ACK/DR1
BUSY/WAIT/MTR1
P E / W DATA
SLCT/WGATE
NC8
NC7
DENSEL
DRATE0
INDEX
M T R0
DR1
DR0
M T R1
DIR
STEP
WDATA
NC
NC1
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
VDD
VSS
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
AEN
IOCHRDY
IORD
IOWR
NC2
PCICLK/IRQ1
SERIRQ/IRQ3
NC3
GPIO10/IRQ4
GPIO11/IRQ5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
IOCHRDY
RD
WR
TC
IRQ1
IRQ3
IRQ4
IRQ5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
VDD
TC
R11
10K
JP7
2
PAGE 3
nWGATE
nTRK0
nWP
nRDATA
nHDSEL
nDSKCHG
1
2
Date:
Size
B
Title
13
1
3
4
7
8
11
14
17
18
21
22
1
3
5
7
1
3
5
7
GND
VCC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
12
24
2
5
6
9
10
15
16
19
20
23
VDD
T h u r s d a y , M arch 19, 1998
Document Number
8 7 0 5 2 1 6 9 4 - 1 00
PC87351 CONNECTIONS
7 4 L V X 3 L 3 8 4A
BE5-9
BE0-4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
U6
GPIO16_B
GPIO15_B
GPIO14_B
GPIO13_B
GPIO12_B
PAGE
GPIO11_B
4
GPIO10_B
X1
Sheet
IRRX1
IRRX2
2
of
HD40X1
J9
4
Rev
1.1
PAGE 3
IRQ12
IRQ7
IRQ6
IRQ5
IRQ4
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
40
39
38
37
IRSL2
36
IRSL2
35
34
33
32
VSB
31
30
JP16
VBAT
1
2
29
28
1
2
27
26
JP15
25
24
23
VDD
22
21
20
19
nDACK3
18
nDACK2
17
nDACK1
PAGE 3
16
MR
15
DRQ3
14
JP2
DRQ2
2
13
DRQ1
4
12
6
11
MR
X1
8
10
X1
IRQ15 9
IRQ14 8
IRQ12 7
JP3
IRQ11 6
2
IRQ10 5
P12
4
4
IRQ9
P17
6
IRQ8 3
8
2
IRQ7
IRRX2
1
IRQ6
IRRX2
PAGE
2
SERIRQ/IRQ3
PCICLK/IRQ1
1
2
XU7
1
3
IRQ3 5
7
4
SERIRQ
C6
0.1u
1
J P 14
2
4
6 IRQ1
8
11
14
PCICLK
VDD
RP1
7*10K
8
7
6
5
4
3
2
1
VDD
PAGE 2
J P 21
2
J P 20
2
J P 19
2
J P 18
2
J P 23
2
J P 25
2
1
1
1
1
1
J P 22
2
1
1
sl_length0
sl_length1
irq_en
serirq_mode
quiet_start_a
sr_length1
id_length1
MR
OPTIONAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
U8
U8
NC
NC
I/O38
I/O37
I/O36
I/O35
I/O34
I/O33
I/O32
GOE0/IN4
Y1
VCC
GND
Y2
Y3
SCLK*/IN3
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NC
NC
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
IN7
Y0
VCC
GND
ispEN**/NC
RESET
S D I*/IN0
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
NC
NC
ispLSI1032-100LT100
NC
NC
I/O56
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
IN6
GND
G O E1/IN5
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I/O39
NC
NC
NC
NC
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
M O DE*/IN1
GND
S D O * /IN2
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
I/O24
NC
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PAGE 2
Date:
Size
B
Title
SDI
SCLK
MODE
SDO
nISPEN
2
1
JP24
3
VDD
Thursday, April 09, 1998
Document Number
870521694-100
SIRQ
VDD
1
2
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
R6
1K
Sheet
C2
10n
VDD
1
2
3
of
1
2
3
4
5
6
7
8
4
Rev
1.1
HD8X1
J10
2
1
1
2
3
4
5
6
7
8
9
10
PME
PME1/nRING
PME2/nSUSP
R4
510R
2
1
PWUREQ LED
nPWUREQ
PAGE 2
J1
1
VSB
R7
510R
VSB LED
R9
510R
2
1
PAGE
2
LD3
LD2
LD1
J3
1
2
3
4
5
6
7
8
9
10
GPIO2
FANOUT1
FANOUT0
PAGE
2
FAN CONNECTOR
GPIO20
GPIO21
GPIO22
JP11
2
J2
J4
2
1
JP8
1
2
3
4
5
6
7
8
9
10
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
1
3
GPIO17
PAGE 2
PNF PAGE 2
2 FANOUT_SEL
JP5
GPIO1
2
3
1
FAN CIRCUIT
1
1
2
R1
10K
1
2
3
4
U2
S1
G1
S2
G2
1
2
6
10
16
20
5
9
15
19
23
12
1
2
6
10
16
20
5
9
15
19
23
12
8
7
6
5
12V
R12
1K
24
3
7
11
17
21
4
8
14
18
22
13
74LVX3L383
nBE V C C
C0
A0
C1
A1
C2
A2
C3
A3
C4
A4
D0
B0
D1
B1
D2
B2
D3
B3
D4
B4
GND B X
24
3
7
11
17
21
4
8
14
18
22
13
74LVX3L383
U3
PCB
12V
PCB2
nBE V C C
C0
A0
C1
A1
C2
A2
C3
A3
C4
A4
D0
B0
D1
B1
D2
B2
D3
B3
D4
B4
GND B X
U5
NDS9942
D1-1
D1-2
D2-1
D2-2
PAGE 2
33M
GND OUT
1
2
P
C15
10U
VDD
N
R13
20R
1
2
VDD
R14
20R
GPIO14_B
GPIO15_B
GPIO16_B
G P IO14_A
GPIO15_A
GPIO16_A
GPIO10_B
GPIO11_B
GPIO12_B
GPIO13_B
G P IO10_A
GPIO11_A
GPIO12_A
GPIO13_A
PAGE 2
1
2
VDD
JP13
2
PAGE 2
1
JP10
R10
10K
VDDC
VDD TO THE SIO
R15
20R
1
2
1
2
M1
VDD
C8
0.1u
Date:
Size
B
Title
C9
0.1u
VDDC
C7
0.1u
1
2
VCC
JUMPERS
C1
0.1u
VSB
C4
0.1u
C12
0.1U
C11
0.1u
VBAT
TP4
TP3
Sheet
1
4
TP1
TP2
C3
10u
1
TEST POINTS
C13
0.1U
T h u r s d a y , M arch 19, 1998
Document Number
8 7 0 5 2 1 6 9 4 - 1 00
1
1
C10
0.1u
FAN_PARTS
VSB
VDD
C5
0.1u
C14
10u
DECOUPLING CAPS
XJP14
of
C16
10u
12V
XJP18XJP19XJP20XJP21XJP22XJP23XJP24 XJP25
XJP9 XJP10 XJP11XJP12XJP13XJP15XJP16XJP17
XJP1 XJP2 XJP3 XJP4 XJP5 XJP6 XJP7 XJP8
1
2
U7
1
2
NC
1
2
VDD
1
2
PNF
1
2
2
1
2
1
2
1
2
POWER ONV D DLED
1
2
1
2
1
2
1
2
1
2
1
2
1
2
4
Rev
1.1
Appendix C
BILL OF MATERIALS
Description
Location
Qty
Base Board
74LVX3L384A SMD-TSOP24 BUS SWITCH 3 OR 5V
U10, U5
2
PAL22V10 DIP24 7.5NS, 0.3"
U6
1
74ACTQ32 SMD-SO14S QUAD OR GATES
U7
1
74ACT00 SMD-SO14S QUAD NAND GATES
U8
1
DS14185M SMD-SO20W +/-12, +5V UART DRV/RCV
U1, U2
2
DS14C89A SMD-SO14S +5V UART RECEIVER
U3
1
33R SMD-1206 1/4W 5%
R1, R2, R3, R4, R5, R6, R7, R8,
R9, R10, R11, R12, R13, R14,
R15, R16, R19, R20, R21, R22,
R23, R24, R25, R26, R27, R28,
R29, R34
28
100R SMD-1206 1/4W 5%
R30, R31, R58, R75
4
1K SMD-1206 1/4W 5%
R76
1
4.7K SMD-1206 1/4W 5%
R42, R43, R44, R45, R46, R47,
R48, R49, R50, R51, R52, R53,
R54, R55, R56
15
10K SMD-1206 1/4W 5%
R32, R33, R59, R60, R61, R62,
R77, R78
8
10K DIP 1/4W 5%
R41
1
150K SMD-1206 1/4W 5%
R35, R36, R37, R38, R39
5
SPARE SMD-1206 1/4W SPARE FOOTPRINT
R82, R83, R84, R85, R86
5
RES-NET-COM-9 SIP10 9X1K SIP10, 2%, 1/8W
RN1
1
RN2
1
RES-NET-ISOL-8 DIP16 8X10R DIP16, 0.3”, 1%, 1/8W
JP1
1
47P SMD-0805 50V C-NP, CER NPO, 10%,
C33
1
200P SMD-0805 50V C-NP, CER NPO, 10%
C66, C67, C68, C69, C70, C71,
C72, C73, C74, C75, C76, C77,
C78, C79, C80, C81
16
330P SMD-0805 50V C-NP, CER NPO, 10%
C6, C7, C8, C9, C10, C11, C12,
C13, C14, C15, C16, C48, C49,
C51, C52
15
680P SMD-0805 50V C-NP, CER NPO, 10%
C17, C18
2
BILL OF MATERIALS C-1
Description
Location
Qty
0.1U SMD-1206 50V C-NP, CER X7R, 10%
C1, C2, C19, C21, C22, C23, C24,
C26, C28, C30, C31, C32, C34,
C36, C37, C38, C39, C41, C43,
C44, C47, C50, C55, C56, C57,
C59, C60, C61, C62, C63, C64
31
22U SMD-6032 16V C-POL, TANT, 10%
C25, C27, C29, C35, C40, C42,
C45, C46, C58
9
BLM31A02PT SMD-1206 200mA INDUCTOR, EMI
BEAD
L1, L2, L3, L4, L5, L6
6
CRYSTAL-OSC DIP14 48MHz 100PPM, CMOS, 5V
U9
1
CON-MDIN-6P MINI-DIN 6 PINS + 3 SHIELD PINS
J7, J6
2
CON DB9 FEMALE TH-RA PCB
J12
1
CON DB25 FEMALE TH-RA PCB
J13
1
CON 3 PIN POL 2.5MM HD LOCK POLARIZED
J8
1
HD1X1 0.1” HEADER, 1 PIN
TP2, TP3
2
HD2X1 0.1” HEADER, 2 PINS
JP4
1
JUMPER-COVER-2PIN, BLACK
XJP2, XJP4
2
JP2
1
HD40X1 0.05” FEM HEADER, 40 PINS
XJ4D, XJ4C, XJ4B, XJ4A
4
HD5X2 0.1” SHROUDED HEADER, 10 PINS
J1, J2
2
J10
1
J4
1
HD5X2 FEM HD 0.05”X0.1”
XJ4E
1
SOCKET-24 DIP24, O.3”
XU6
1
SW-SPDT-MOM 0.1” 5P 2 SHIELD PINS
SW4
1
FUSE-SOCKET SMD 2A SOCKET + FUSE SLOW
BLOW
XF1
1
BATT-3PIN COIN 3.0V LITHIUM CELL 380mAH
BT1
1
PCB PC87317EB PRINTED CIRCUIT BOARD
M1
1
BRACKET DB25/9 IBM PC-AT
M2
1
LABEL REV A REV LET ‘A’
LB2
1
LABEL S/N
LB1
1
Extension Board
PC87351-XXX/ SMD-PQFP128 SUPERI/O
U1
1
SI9942 DUAL MOSFET
U2
1
CRYSTAL-OSC DIP14 33MHz 50PPM, TTL, 5V
U7
1
74LVX3L383 SMD-TSOP24 BUS CHANGER 3 OR 5V
U3, U5
2
C-2 BILL OF MATERIALS
Description
Location
Qty
74LVX3L384A SMD-TSOP24 BUS SWITCH 3 OR 5V
U4, U6
2
ispLSI1032E-100LT CPLD
U8
1
SW-DP-NO-NC-X2 DIP4 DIPSWITCHX2
SW1
1
SOCKET-OSC 14/6 DIP14 6PINS ROUND
XU7
1
JP5, JP8, JP12, JP17, JP24
5
J10
1
J2, JP4, JP7, JP10, JP11, JP13,
JP15, JP16, JP18, JP19, JP20,
JP21, GP22, JP23, JP25
15
J1, J2, J3
3
JP14
1
JP1, JP2, JP3, JP6, JP9
5
HD5X2 FEM HD 0.05”X0.1”
J5
1
HD40X1 0.05” MALE
J7, J8, J9
3
HD30X1 0.05” MALE
J6
1
HD1X1 0.1” HEADER, 1 PIN
TP1, TP2, TP3, TP4
4
JUMPER-COVER-2PIN, BLACK
XJP1, XJP2, XJP3, XJP4, XJP5,
XJP6, XJP7, XJP8, XJP9, XJP10,
XJP11, XJP12, XJP13, XJP15,
XJP24, XJP25
24
JUMPER-COVER-2PIN-X2, BLACK
XJP14
1
SOCKET-128 PQFP128-SMD-SMD
XU1
1
10K SMD-1206 1/4W 5%
R1, R2, R3, R5, R8, R10, R11
7
510R SMD-1206 1/4W 5%
R4, R7, R9
3
20R SMD-1206 1/4W 5%
R13, R14, R15
3
1K SMD-1206 1/4W 5%
R6, R12
2
RP1
1
0.1U SMD-0805 50V C-NP, CER X7R, 10%
C1, C4, C5, C6, C7, C8, C9, C10,
C11, C12, C13
11
10n SMD-0805 50V C-NP, CER X7R, 10%
C2
1
10U SMD-6032 20V C-NP, 10%
C3, C14, C15, C16
LABEL REV A REV LET ‘A’
LB1
1
RED LED SQUARE
LD1, LD2, LD3
3
BILL OF MATERIALS C-3
Appendix D
PAL EQUATIONS
The PAL equations of the PC87351EB PLD - XU6:
”************************************************************************
“*
NATIONAL
SEMICONDUCTOR
CORPORATION
*
“*
*
“*
*
“*
Revision
Date
Description
*
“*
--------------------------------------------------*
“*
0.1
Feb 21, 1997
PC87351EB EVALUATION BOARD
*
“*
Author: Theodor Iacob
*
“*************************************************************************
module M351EB
title ‘351EB XBUS/ISA buffer control logic ‘
M351EBdevice‘P22V10’;
declarations
“INPUTS
“======
SA0,SA1,SA2,SA3,SA4,SA5 pin 1,2,3,4,5,6;
SA6,SA7,SA8,SA9,SA10,SA11 pin 7,8,9,10,11,13;
NCSIN
pin 17;“ NCSIN = SA15 # SA14 # SA13 # SA12
“ delivered by external logic
AEN
pin 16;
NIORD
pin 15;
NIOWR
pin 14;
CFG0A
pin 21;
KBCPRES
pin 22;
RTCPRES
pin 23;
“OUTPUTS
“=======
NISAENBL
NXENBL
PAEN
ADDR12
ADDR11
pin 20;
pin 19;
pin 18;
= [SA11,SA10,SA9,SA8,SA7,SA6,SA5,SA4,SA3,SA2,SA1,SA0];
=
[SA10,SA9,SA8,SA7,SA6,SA5,SA4,SA3,SA2,SA1,SA0];
KBC_ACCESS= !NCSIN & (( ADDR12 == ^h060 ) # ( ADDR12 == ^h064 ));
RTC_ACCESS= !NCSIN & (( ADDR12 == ^h070 ) # ( ADDR12 == ^h071 ));
H,L,X,C
= 1, 0 , .X. , .C.;
PAL EQUATIONS D-1
equations
!NXENBL
= (( KBCPRES & KBC_ACCESS ) #“KBC cable connected AND
“KBC address match OR
( RTCPRES & RTC_ACCESS ) “RTC cable connected AND
) &
“RTC address match OR
!AEN &
“AEN must be low AND
(!NIORD # !NIOWR ); “read OR write cycle
!NISAENBL= (!NIORD # !NIOWR ) &
“read or write cycle AND
(AEN #
“ for DMA cycles: AEN is High
“
AND any addr. OR
“ for IO
cycles:
(!AEN &
“AEN is LOW AND
(!KBC_ACCESS &
“there is not a KBC access AND
!RTC_ACCESS“there is not a RTC access.
)
)
);
D-2 PAL EQUATIONS
INDEX
A
FDC connector 4-4
Floppy Disk Controller 1-2
Advanced Power Controller 1-3
and 4-6
AT connector 3-1
G
GATEA20 3-9
B
base board layout 1-5
I
IRTX signal 3-4
C
configuration program 2-14
connector (on base)
AT 4-6
FDC 4-4
ISA XT 4-6
J2 4-4
KBC 4-2
KBD 4-3, 4-4
mouse 4-3
Parallel Port 4-6
SERIAL1 4-2
SERIAL2 4-2
connector (on extension)
fan 4-7
GPIO1 4-7
GPIO2 4-7
ISP 4-8
PME 4-6
D
data buffers 1-2
DS14185 3-4
J
J3 3-4
J4 3-4
J5 3-9
J8 3-4
J9 3-5
jumper (on base)
J1 4-2
J10 4-4
J12 4-5
J13 4-6
J2 4-2
J4 4-2
J6 4-3
J7 4-4
J8 4-4
jumper (on extension)
J1 4-6
J10 4-8
J2 4-7
J3 4-7
J4 4-7
K
E
EasyReg 2-14
ECP terminations 3-5
EMI filter 3-4, 3-9
extension board layout 1-6
KBC connector 4-2
KBC IRQ12 3-9
KBD connector 4-4
KBDAT 3-9
KBDCLK 3-9
Keyboard Controller 1-3
F
FanController 3-5
INDEX-1
M
MCLK signal 3-9
MDAT signal 3-9
mouse connector 4-3
P
P2 4-6
parallel port 1-2
parallel port block 3-5
Parallel Port connector 4-6
power consumption 4-8
R
reset cycle 2-14
RI1 3-4
RI2 3-4
S
Standby 4-4
SW1 2-6
T
TC signal 3-1
U
UART1 block 3-4
INDEX-2
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SuperI/O PC87351EB Reference Manual

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