Bitvis Company Presentation - February 2015

Bitvis Company Presentation - February 2015

Exhibitor
presentation
February 2015
Independent
Design Center
FPGA & ESW
(ASIC)
FPGA-forum, Trondheim - Britannia Hotel
William Braathen
Core
Vision: Be the leading independent design center in Scandinavia for
FPGA
ESW
Field Programable
Gatearrays
Embedded
Software
HARDWARE: Parallel execution
SOFTWARE: Serial execution
Mission: Deliver quality in every design based on a structured approach and proven methodology
People
Developer (2)
FPGA
Senior (3)
Principal (3)
ESW
Senior (3)
Principal (3)
Espen T.
Dag Sverre
Sverre
Steffen
Jonathan
Daniel
Jørgen
Michal
Espen S.
Tord
Herman
Fredrik
Trond
William
Resources: 9 people in FPGA design, 5 people in Embedded Software Development
History
Methodology
HDD (2013)
Halfwave (2013)
Schlumberger (2013)
Kongsberg Defence &
Aerospace (2013)
(5+1)
14 employees
12 employees
Barco (2009)
Cisco (2011)
Aker Solutions (2011)
July 2007
January 2012
January 2010
2.5 years
16
14
12
10
8
6
4
2
0
2 years
January 2015
3 years
Experience
Average: 10 year of working experience
Master (11)
10
Years
Distribution
International
Semi / ASIC
Arrow Norway
VingCard Elsafe
Acte
Tandberg Storage
Lyng Electronics
Nera Satcom
Data Respons
Ericsson AB
ARROW OCS
ABB
Cadence Design
Western Geco
Inphi Corporation
4tech AS
Cold Spring
Telenor R&D
Digitas
Kongsberg Ericsson
Micron Imaging
Kongsberg Defence
NXP Semiconductor
Maritime Com. Partner
Nordic VLSI
Kongsberg Def. &
Chipcon
Norwegian Navy
Nordic Semiconductor
Ship & Modelling
28 companies: from Norwegian startups to world wide players
Industrial
Military
Services
•
Cover all itterations of the entire development chain
Architecture
Specification
•
Implementation
Test
Verification
Knowledge based services
Methodology
as a service
Sparring
partner
Review as a service
Best practice couse
Competence
Operating
Systems
Bootloader
C
RTOS
Ubuntu
GNU
Toolchain
Git
C++
BSP
Fedora
Programming
Language
CVS
SVN ClearCase
Windows
Version
Handling
Pyton
Bash
VxWorks
5.4 6.6
8051
Domain
M16C
CPU
RTL
Simulation
x86
Actel
GUI
Drivers
Sensor SPI Protocols
Interface
I2C RS485 BRI
Design
VHDL
ISE
Xilinx
Xilinx
Xilinx
SDK
PlanAhead
Mentor
Drivers
RS232
ARM
Blackfin
Xilinx
Libero/Designer
TCP/IP
Timing
Analysis
SystemVerilog
Assertions Clock
Script
Apps
FPGA
SVA
AVR
Tcl
Xilinx
FPGA
MSP430
Perl
SW
Matlab
Atlera
FPGA
Actel
FPGA
(Ver. hand)
Linux
uCLinux
General Tools Labview
HW
(Ver. hand)
(Ver. hand)
Java
Real time Make
Modelsim
Xilinx
Xilinx
ISIM
Chipscope
Test
XPS/EDK
FPGA Tools
Altera
Quartus II
Debug
System
Verilog
Verification
Location
Bankveien 7
1383 Asker
140m 2
15. February 2015
Strøket 3
1383 Asker
300m 2
Numbers
Focus and structured approach -> Happy Customers
30
22,5
15
7,5
0
8.4 (6)
2012
16.1
(9)
2013
18
(14)
20
2014
2015
Continuous Growth: From 1 and 6 to 7, 9, 10, 12, 13 ,14 people, becomming 15 in April
Products
Bitvis Utility Library: More than 500 downloads World wide
FREE!
Register Wizard
Bitvis Utility Library
Universial
VHDL
Verification
Methodology
Register Wizard and UVVM: Being presented in more detail during FPGA-forum
2012
2013
2014
2015