ERL-0631-GD PR

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ERL-0631-GD PR
UNCLASSIFIED
ELECTRONICS RESEARCH LABORATORY
Information Technology
Division
GENERAL DOCUMENT
ERL- 0631-GD
SHIVA MARK I1 HARDWARE ARCHITECTURE,
VERSION 1
by
D.A. Krnak, A.J.S. Yakovleff, J.D. Yesberg, M.S. Anderson and P.C. Drewer
SUMMARY
This document describes the hardware aspects of the Shiva multiprocessor, which has a
dynamically reconfigurable architecture and supports heterogeneity. The system is
meant to be used as an accelerator for computationally intensive tasks, and is used in
conjunction with a workstation.
O COMMONWEALTH OF AUSTRALIA 1992
AUG 92
APPROVED FOR PUBLIC RELEASE
POSTAL ADDRESS: Director, Electronics Research Laboratory, PO Box 1500, Salisbury, South Australia, 5108
UNCLASSIFIED

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