IPT-Shark537 Development Kit Manual

Transcription

IPT-Shark537
Development
Kit Manual
Revision 1.0.1a, August 2008
Hardware Revision
IP Thinking AS
Karl Bjarnhofs Vej 13
DK-7120 Vejle
Denmark
1.0.A
Copyright Information
All rights to this hardware and software product (the product) is the property of IP
Thinking A/S and a written approval for any copying of this product for commercial use
must be obtained from IP Thinking A/S prior to such act.
All software supplied with this product, with the exception of the BF537-NECLN6448BC20-18D driver, is supplied under the GNU licence. In case of any
modifications of the software, a copy of this modified software together with source
codes for the complete software must be send to IP Thinking A/S via e-mail
([email protected]) for publishing on the IP Thinking A/S website.
The supplied BF537-NEC-LN6448BC20-18D driver is the property of IP Thinking A/S
and is only licensed for use by the customers of IP Thinking A/S in connection with the
relevant hardware platform. Should anyone whish use the driver in its present or a
modified state for commercial purposes, a licence to do so can be obtained from IP
Thinking A/S.
Limited Warranty
All products from IP Thinking A/S are guaranteed to be free from defects in material
and workmanship under normal and intended, use for a period of 180 days from the
date of your purchase.
IP Thinking A/S offers no other warranty in cases of damage in transit, inadequate care
or neglect, abnormal- or misuse, accidents, damage due to environmental or natural
elements, failure to follow product instructions, immersion in water, battery leakage,
improper installation, storage or maintenance or service of the products or causes not
arising out of defects in materials and workmanship and the limited warranty including
aggregate liability is limited to the monies paid to IP Thinking A/S for the specific
product by the customer of IP Thinking A/S.
Technical or customer Support
IP Thinking A/S offers a free limited support on the product as supplied, consisting of
either 30 minutes telephone support – calculated per started 15 minutes – or two emails of maximum one A4 page (with answers).
For further support, please see either www.ipthinking.dk/support or purchase support
from IP Thinking A/S. For further information here of, please feel free to contact
[email protected].
2
Regulatory Compliance
The IPT-Shark537 development kit is pending certification to comply with the
essential requirements of the European EMC directive 89/336/EEC (inclusive
93/68/EEC) and therefore, get not CE marked.
Warning
The IPT-Shark537 development kit contains
ESD (electrostatic discharge) sensitive devices.
Electrostatic charges readily accumulate on the
human body and equipment and can discharge
without detection. Permanent damage may
occur on devices subjected to high-energy
discharges.
Proper
recommended
to
ESD
precautions
avoid
are
performance
degradation or loss of functionality. Store
unused IPT-Shark537 development boards in
the protective shipping package.
3
Contents
COPYRIGHT INFORMATION ................................................................................................................... 2
LIMITED WARRANTY.............................................................................................................................. 2
TECHNICAL OR CUSTOMER SUPPORT .................................................................................................... 2
REGULATORY COMPLIANCE................................................................................................................... 3
WARNING.............................................................................................................................................. 3
CONTENTS ............................................................................................................................................. 4
CHAPTER 1: GENERAL INFORMATION.......................................................................... 6
1.1. PREFACE...............................................................................................................................................6
1.2. ABOUT THE PROCESSOR BEHIND THIS DEVELOPMENT BOARD: ..........................................................................7
1.3. PACKAGE CONTENTS ...............................................................................................................................9
1.4 PRODUCT REGISTRATION ........................................................................................................................10
1.5. SYSTEM OVERVIEW...............................................................................................................................11
CHAPTER 2: HARDWARE CONFIGURATION .............................................................. 20
2.1. INTRODUCTION ....................................................................................................................................20
2.2. ADSP-BF537.....................................................................................................................................21
2.3. MEMORY MAP ....................................................................................................................................21
2.3. EXTERNAL BUS INTERFACE UNIT ..............................................................................................................22
2.4. SDRAM INTERFACE .............................................................................................................................22
2.4.1. SDRAM configuration ..............................................................................................................22
2.4.2. SDRAM Memory Global Control Register (EBIU_SDGCTL).......................................................23
2.4.3. SDRAM Memory Bank Control Register (EBIU_SDBCTL) .........................................................25
2.4.4. SDRAM Refresh Rate Control Register (EBIU_SDRRC) .............................................................25
2.5. NAND-FLASH MEMORY .......................................................................................................................26
2.6. USB INTERFACE ...................................................................................................................................26
2.7. ETHERNET INTERFACE ............................................................................................................................29
2.8. AUDIO INTERFACE ................................................................................................................................30
2.9. PARALLEL PERIPHERAL INTERFACE (TFT-DISPLAY INTERFACE) .......................................................................32
2.10. SPI INTERFACE...................................................................................................................................34
2.10.1. Serial Boot Flash ....................................................................................................................34
2.10.2. Touch Screen Controller ........................................................................................................35
2.10.3. MMC/SD reader ....................................................................................................................36
2.10.4. WLAN Interface .....................................................................................................................37
2
2.11. I C INTERFACE (16-BIT I/O EXPANDER) ..................................................................................................38
2.12. UART PORT .....................................................................................................................................39
2.13. JTAG EMULATION PORT .....................................................................................................................39
2.14. EXPANSION INTERFACE ........................................................................................................................40
2.15. CONNECTORS ....................................................................................................................................41
CONNECTOR OVERVIEW ...............................................................................................................................41
4
CHAPTER 3: SOFTWARE QUICK REFERENCE GUIDE .................................................44
3.1. INTRODUCTION: .................................................................................................................................. 44
3.1.1. System overview ..................................................................................................................... 45
3.2 READING GUIDE.................................................................................................................................... 45
3.3. SETTING UP THE HOST SYSTEM ................................................................................................................ 47
3.3.1. Terminal program ................................................................................................................... 47
3.3.2. Toolchain ................................................................................................................................ 48
3.4. COMPILING YOUR FIRST KERNEL/SYSTEM IMAGE......................................................................................... 49
3.4.1. Getting a kernel ...................................................................................................................... 49
3.4.2. Patching the kernel ................................................................................................................. 49
3.4.3. Kernel setup ............................................................................................................................ 49
3.4.3.1. Compiling/Customizing the kernel/user settings.............................................................................50
3.4.4. Loading the new kernel on the board ..................................................................................... 51
3.4.4.1. TFTP Server ......................................................................................................................................51
3.4.4.2. Loading a “image” in u-boot ............................................................................................................51
3.4.4.3. Flashing the board with the new kernel/system image ...................................................................52
3.5. COMPLING “DAS U-BOOT”..................................................................................................................... 54
3.5.1. Getting u-boot ........................................................................................................................ 54
3.5.2. Patching u-boot ...................................................................................................................... 54
3.5.3. U-boot setup ........................................................................................................................... 55
3.5.3.1 Compiling ..........................................................................................................................................55
3.6 LOADING AND FLASHING U-BOOT ............................................................................................................. 56
3.7 MAKING YOUR OWN APPLICATIONS .......................................................................................................... 58
3.6.1 The “hello world” example....................................................................................................... 58
3.6.1.1 Compiling ..........................................................................................................................................58
3.7.1.2 Downloading and testing on the board ............................................................................................59
3.7.2 Adding an application to the uClinux configuration ................................................................ 61
3.7.3 QT ............................................................................................................................................ 63
3.7.3.1 Getting QT.........................................................................................................................................63
3.7.3.2 Patching QT.......................................................................................................................................63
3.7.3.3 Compiling ..........................................................................................................................................63
3.7.3.4“Hello world” example.......................................................................................................................65
3.8 GETTING SUPPORT ................................................................................................................................ 66
3.9 TROUBLESHOOTING............................................................................................................................... 68
3.10 ABBREVIATIONS.................................................................................................................................. 69
CHAPTER 4: MECHANICAL LAYOUT .............................................................................71
MECHANICAL DRAWING ............................................................................................................................... 71
SILKSCREEN DRAWING ................................................................................................................................. 72
CHAPTER 5: BILL OF MATERIALS ..................................................................................74
CHAPTER 6: SCHEMATIC DIAGRAMS...........................................................................82
5
Chapter1: General information
Chapter 1
General information
1.1. Preface
Thank you for purchasing the IPT-Shark537 development kit, it is based on an Analog
Devices, Blackfin® 537 DSP running up to 600MHz, configured with 128 Mbyte
SDRAM and 128 Mbyte NAND-Flash. The IPT-Shark development kit is delivered with
a 6.5” VGA industry TFT-Display, includes 4-wire Resistive Touch Panel and a
backlight inverter. The system is default running uClinux version 2.6.22.18 loaded from
the onboard NAND-flash booted by U-boot ADI-2008R1 version 1.1.6. That’s stored in
the serial-flash.
The IPT-Shark537 development board has default support for USB low-speed devices
in host mode designed for keyboard. Audio option for connections a mono microphone,
Line-In, Line-Out, headphone and a external 8 ohm speaker. Ethernet for updating
software and communication via the internet, and an RS232 port for debugging the
system via a terminal program connected to a personal computer.
The Software package for the IPT-Shark development kit includes a demo QT
application, that show the main features of the board, including a Linphone user
interface ready for use, after network and SIP account settings are configured.
The IPT-Shark537 development board is designed to running uClinux and will be
supported from www.ipthinking.dk/support. The development board can also be
accessed via VisualDSP++, but this feature is not supported by IP-Thinking.
6
1.2. About the processor behind this development board:1
The Analog Devices, Blackfin® processors support a media instruction set computing
(MISC) architecture. This architecture is the natural merging of RISC, media functions,
and digital signal processing (DSP) characteristics. Blackfin® processors deliver signalprocessing performance in a microprocessor-like environment.
Based on the Micro Signal Architecture (MSA), Blackfin processors combine a 32-bit
RISC instruction set, dual 16-bit multiply accumulate (MAC) DSP functionality, and 8-bit
video processing performance that had previously been the exclusive domain of verylong instruction word (VLIW) media processors.
The IPT-Shark537 development board is designed as it is able to be used with the
VisualDSP++® development environment to test the capabilities of the ADSP-BF537
Blackfin processors.
The VisualDSP++ development environment gives you the ability to perform advanced
application code development and debug, such as:
•
Create, compile, assemble, and link application programs written in C++, C and
ADSP-BF537 assembly.
•
Load, run, step, halt, and set breakpoints in application program.
•
Read and write data and program memory.
•
Read and write core and peripheral registers.
•
Plot memory.
Access to the ADSP-BF537 processor from a personal computer (PC) is achieved
through an optional JTAG emulator. The JTAG emulator gives unrestricted access to
the ADSP-BF537 processor and the development board peripherals. Analog Devices
JTAG emulators offer faster communication between the host PC and target hardware.
Analog Devices carries a wide range of in-circuit emulation products. To learn more
about Analog Devices emulators and processor development tools, go to
http://www.analog.com/dsp/tools/.
1
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
7
Note: The VisualDSP++ software and JTAG emulator is not included and supported
with the IPT-Shark537 development board, but can be purchased via Analog Devices,
Blackfin®.
8
1.3. Package Contents
Your IPT-Shark537 development kit package contains the following items:
•
IPT-Shark537 board
•
6.5” VGA TFT-display (NEC NL6448BC20-18D)
•
DC/AC Inverter (NEC 65PW061)
•
6.5” Touch screen (FUJITSU N010-0554-T043)
•
25 mm inverter cable (Molex 532610871 connectors)
•
Small back with fixings
o 4. Pc. 3 mm x 10 mm metal bolts
o 2. Pc. 25 mm mountings fittings
o 2. Pc. 12 mm mountings fittings
o 2. Pc. 12 mm mountings fittings with bolt
•
Universal 9V DC/15W power supply
•
2m Ethernet patch cable
•
1.8m Serial cable DB9-DB9 male/femal
•
2W Loudspeaker with approximate 15 cm cable
•
DVD containing
o Manual in PDF-format
o U-boot (version 1.1.6 – ADI 2008R1)
Precompiled images (multiple formats)
Source code
Patch
9
o uClinux (version 2.6.22)
Precompiled image
Source code
Patch
o Demo software application QT source code
•
Quick start guide (hardcopy in A5 size)
If any items are missing, contact the vendor where you purchased your IPT–
Shark537 development kit or contact IP Thinking A/S via www.ipthinking.dk/support
1.4 Product Registration
At http://www.ipthinking.dk you are encouraged to register your product. This gives
access to our support forum, file downloads and more.
10
1.5. System Overview
Interface
2MB -SERIAL
BOOT FLASH
SPI (4)
64MB – SDRAM
(8-bit)
DATA(0:7)
64MB – SDRAM
(8-bit)
DATA(8:15)
Parallel Peripheral Interface (0:15)
SPI (8)
128Mbyte
NAND Flash
(8-bit)
ADDRESS,
DATA &
CONTROL
DATA(0:7)
TOUCH
SCREEN
CONTROLLER
TFT-Display
(18-bit*)
CONTROL (2)
DC TO AC
INVERTER
X+,X-,Y+,Y- (4)
TOUCH
(4-wire)
GPIO4 (1)
CRADLE
SWITCH
Interface
SLAVE
S
W
I
T
C
H
HOST
ETHERNET
IEEE 802.3
AUDIO OUT (4)
SDATA (4)
USB 1.1
(8-bit)
DATA(0:7)
AUDIO IN (3)
Blackfin
ADSP-BF537
LINE-IN
LINE-OUT
MICROPHONE
HEADPHONES
1.5W Audio
Power Amplifier
MONO (1)
SPEAKER
(MONO)
I2C (2)
REMOTE
16-BIT I/O
EXPANDER
GPIO(0:15)
GPIO(0:15)
UART1 (2)
RS-232
DRIVER/
RECEIVER
RS-232 (2)
RS-232 (2)
Diff. RX
PHY
AUDIO CODEC
MII (20)
Diff. TX
MMC/SD
Reader
SPI (4)
WLAN
ConnectBlue
(OWLAN211g)
CONNECTOR
SPI (6)
EXPANSION
CONNECTOR
DATA(0:15), ADDRESS(1:19), CONTROL(6), I2C(2),
SPI(3), UART0(2), CAN(2) & CLK(25MHz)
JTAG (6)
JTAG
Figure 1.1: Block Diagram
The board features:
•
Processor
o ADSP-BF537 Blackfin processor from Analog Devices
o Core performance up to 600 MHz (Running uClinux at 525 MHz)
o External bus performance up to 133 MHz (Running uClinux at 131 MHz)
o 182-pin mini-BGA package
o 25 MHz oscillator
•
Synchronous dynamic random access memory (SDRAM)
11
o MT48LC64M8A2P-75 (16 Mega x 8 x 4 banks), 2 x 64 MByte chips
(totalling 128MByte)
12
•
Serial Flash memory
o M25P16 is a 16 Mbit or 2 Mbyte (Used for u-boot and MAC address)
•
NAND Flash memory
o NAND01G is a 1 Gbit or 128 Mbyte NAND Flash memory
(Used for uClinux and software applications)
•
Analog audio interface
o AD1981BL AC ’97 SoundMAX codec
o Stereo full-duplex codec 20-bit PCM DAC, supporting 7040 Hz to 48 KHz
sample rates with 1 Hz resolution.
o Integrated stereo headphone amplifier
o Standard 3.5 mm stereo Jack connectors, for headphones, Microphone ,
line-in & line-out (SHALLIN K36406)
o Jack modular 4/4, for headset connection in mono left channel (MOLEX
855025005)
o SSM2211SZ 1.5 Watt Audio Power Amplifier for mono loudspeaker
o Loudspeaker connector (MOLEX 533980271)
•
Ethernet interface (LAN)
o LAN8700 Single-Chip Ethernet Physical Layer Transceiver (PHY)
o Compliant with IEEE 802.3-2005
o 10-BaseT (10 Mbits/sec) and 100-BaseT (100 Mbits/sec)
o Media Independent Interface (MII)
13
o Ethernet Media Access Controller (MAC)
o 2 LEDs that indicate 10/100 Mbs and full/half duplex
o RJ45 Ethernet connector with 2 LEDs that indicate LINK and ACTIVITY
•
Universal asynchronous receiver/transmitter (UART)
o ADM3101EACPZ
o RS232 Serial interface via UART1
o DSUB connector
14
•
Universal Serial Bus interface NOT VERIFTIED IN SLAVE MODE
o SL811HS is a Cypress USB 1.1 Host/Slave Controller, with option for
Host or Slave mode
o Limited to Low-Speed when using TFT-Display in VGA mode
o Jumper selection for Host/Slave mode setup
o USB connector type A for Host mode
o USB connector type B for Slave mode
•
TFT-Display (16-bit Parallel Peripheral Interface)
o Designed for NEC NL6448BC20-18D
o 18bit* TFT Panel (6-bit digital RGB signals)
o Resolution 640 x 480 pixels (VGA)
o LCD Interface connector (Hirose DF9-31S-1V W(31))
•
DC to AC Inverter interface
o Designed for 65PW061, 4 W Dual output Backlight converter with
dimming function
o Inverter connector (MOLEX 532610871)
•
Touch screen controller interface
o AD7877 Touch Screen Controller
o Standard 4-wire Resistive Touch Panel
o Touch screen connector (TYCO ELECTRONICS 84953-4)
o GPIO1 to Display On/Off
15
o GPIO2 from Interrupt WLAN
o GPIO3 from Interrupt I/O expander
o GPIO4 from cradle switch connector (MOLEX 533980271)
•
I/O - Expander
o PCF8575 Remote 16-bit I/O expander for I2C-bus
o Port 00-07 is populate with 10ohm series resistor for 4x4 keypad
Port 10-17 is populate with 10Kohm pull-up resistor for LCD Display
Interface
o Connector type (Samtec TSM-110-01-L-DV)
16
•
MMC/SD-Card reader via SPI NOT VERIFTIED (Driver not available from IP Thinking)
o reader (YAMAICHI ELECTRONICS FPS009-2405-0)
•
Expansion connector (Optional)
o 16-bit Data bus (D0-D15)
o 20-bit Address bus (A1-A19)
o Control signal (Reset, AMS2 to AMS3, AWE, ARE)
o CLK BUF (25 MHz)
o CAN Bus
o I2C Bus
o Interrupt for I2C
o SPI Bus
o UART0
o Connector type (Samtec SFC-130-T2-F-D-A)
•
WiFi Add-on-module (Optional) – NOT VERIFTIED (Driver not available from IP Thinking)
o OWLAN211g from connectBlue
o Connector type (Samtec TLE-110-01-G-DV-A)
•
Debugging
o JTAG ICE 14-pin header
o Connector type (Samtec TSM-107-01-L-DV)
o Compatible with Analog Devices ADZS-HPUSB-ICE
17
•
Power consumption (without USB devices, WLAN module or Expansion-board
connected)
o Booting: 2.5 W
o Idle: 2 W
o Max. brightness at TFT-display (under load): 8,2 W
o Min. brightness at TFT-display (under load): 4 W
o Peak power for the standard board: 9 W
18
19
Chapter2: Hardware Configuration
Chapter 2
Hardware Configuration
2.1. Introduction
This chapter describes the IPT-Shark537 development board’s hardware configuration
and features in detail. The board is build up with two Switch-Mode Power Supplies
(SMPS) step down converters which convert the voltage input from 9 VDC to 3.3 VDC
and 5 VDC. The board’s main processor is the Analog Devices, Blackfin® ADSPBF537, which can be seen in figure 1.1 on page 9, with its connections to the board’s
peripherals.
The system includes:
•
128 Mbyte SDRAM, 128 Mbyte NAND-Flash and USB 1.1 device that
communicate via the External Bus Interface Unit.
•
The Physical Layer Transceiver (PHY) for Ethernet that communicates in MMI
mode.
•
Audio Codec for Audio input and output, communicate via SPORT0.
•
TFT-Display interface via a Parallel Peripheral Interface (PPI).
•
Serial Boot Flash, Touch Screen Controller, MMC/SD Reader and WLAN
module, communicates via SPI bus.
•
16-Bit I/O Expander, communicates via I2C bus.
•
RS232, communicate via UART1.
•
JTAG interface
•
The expansion port provides data/address and control signals from the External
Bus Interface Unit, UART1, and CAN, I2C & SPI busses.
20
2.2. ADSP-BF537
The processor has an I/O voltage of 3.3 V supplied from a local 3.3 V SMPS. The core
processor voltage is supplied by the voltage regulator. The core voltage and the core
clock rate can be set on-the-fly by the processor. Switch down from 3.3 V to between
0.8 and 1.2 V with on-chip voltage regulation controlled by the external MOSFET at
position Q1 in a buck circuit setting. The input clock is supplied by a 25 MHz oscillator.
A 32.768 kHz crystal supplies the Real Time Clock (RTC) inputs of the processor.
The default boot mode on the development board is boot mode 3 (boot from SPI
memory). To change the boot mode on this board, it is necessary to change the
resistor value at the resistor network R5-R7(10K ohm pull-up resistors) & R10-R12(0
ohm pull-down resistors).
Table 2.1: Boot mode settings
Mode
0
1
2
3
4
5
6
7
R5
DNP
10K
DNP
10K
DNP
10K
DNP
10K
R6
DNP
DNP
10K
10K
DNP
DNP
10K
10K
R7
DNP
DNP
DNP
DNP
10K
10K
10K
10K
R10
R11
R12
0R
0R
0R
DNP
0R
0R
0R
DNP
0R
DNP
DNP
0R
0R
0R
DNP
DNP
0R
DNP
0R
DNP
DNP
DNP
DNP
DNP
DNP: Do Not Place
Description
Execute from 16-bit external memory
Boot from 16-bit flash memory
Reserved
Boot from SPI memory (default)
Boot from SPI host
Boot from Serial TWI Memory
Boot from TWI host
Boot from UART host
2.3. Memory Map
The ADSP-BF537 processor has internal SRAM that can be used for instruction or data
storage. On the IPT-Shark537 development board there are included two types of
external memory, SDRAM and NAND-flash both at 128 Mbyte.
Table 2.2: External Memory Map
Start Address
End Address
0x0000 0000
0x03FF FFFF
0x2000 0000
0x200F FFFF
0x2010 0000
0x201F FFFF
0x2020 0000
0x202F FFFF
0x2030 0000
0x203F FFFF
0x203F 0000
Content
SDRAM bank 0 (SDRAM)
ASYNC memory bank 0 (NAND-Flash)
ASYNC memory bank 1 (USB device)
ASYNC memory bank 2 (AMS2)
ASYNC memory bank 3 (AMS3)
MAC address
21
2.3. External Bus Interface Unit
The External Bus Interface Unit (EBIU) connects external memory to the ADSP-BF537
processor. The unit includes a 16-bit wide data bus, an address bus, and a control bus
on the IPT-Shark537 development board, the EBIU connects to the (onboard) 128
Mbyte SDRAM, 128Mbyte NAND-flash, USB 1.1 device and an expansion connector.
2.4. SDRAM Interface
The SDRAM is connected to the synchronous memory select 0 pin (~SMS0). The
SDRAM is clocked from the processor’s serial Clock Out (CLKOUT); the system clock
frequency must run between 54 MHz and 133 MHz. The IPT-Shark537 development
board is running with a default clock at 131.25 MHz. The three SDRAM control
registers must be initialled in order to use the onboard SDRAM.
2.4.1. SDRAM configuration
The three SDRAM registers that must be configured, in the order as listed, are
EBIU_SDGCTL, EBIU_SDBCTL and EBIU_SDRRC. The EBIU_SDGCTL uses the
access timing parameters defined in the SDRAM memory global control register
EBIU_SDGCTL. The EBIU_SDBCTL configures the memory size and bank column
address width. The EBIU_SDRRC provides a flexible mechanism for specifying the
auto-refresh timing. Since the clock supplied to the SDRAM can vary, the SDRAM
Controller (SDC) provides a programmable refresh counter, which has a period based
on the value programmed into the RDIV field of this register. The EBIU_SDBCTL
register should be programmed before powerup and should be changed only when the
SDC is idle.
These registers are configured from the SDRAM’s parameters, found in the
manufactures datasheet.
22
2.4.2. SDRAM Memory Global Control Register (EBIU_SDGCTL)
The configuration of the EBIU_SDGCTL register is from the ADSP-BF537 Blackfin®
Processor hardware reference guide and the SDRAM Micron MT48LC64M8A2P-75
Datasheet. The necessary values from the SDRAM datasheet is shown under this text.
SDRAM Datasheet information:
• Time pr. cycles = 1/131.25MHz = 7.62ms = 7.62 ⋅ 10−3
•
t
RAS
= 44ns = 44 ⋅ 10 -9/7.62 ⋅ 10 -9 = 5.775 = 6 cycles
•
t
RP
•
t
RCD
= 20ns = 20 ⋅ 10 -9/7.62 ⋅ 10 -9 = 2.625 = 3 cycles
•
t
WR
= 1CLK + 7.5ns = 2 cycles
= 20ns = 20 ⋅ 10 -9/7.62 ⋅ 10 -9 = 2.625 = 3 cycles
Table 2.3: SDRAM Memory Global Control Register (EBIU_SDGCTL)
Bit no.
0
1
3:2
Label
SCTLE
CL
Value
1
0
11
5:4
9:6
PASR
TRAS
00
0110
10
13:11
TRP
0
011
14
17:15
TRCD
0
011
18
20:19
TWR
0
10
21
PUPSD
0
22
PSM
0
23
PSSE
1
24
25
SRFS
EBUFE
0
0
26
27
28
29
FBBRW
EMREN
TCSR
0
0
0
0
30
CDDBG
0
31
1
Content
Enable CLKOUT
Fixed
3 cycles (Datasheet information “Speed Grade =
57 with 133MHz and an access time at 5.4ns”)
All 4 banks refreshed
SDRAM tRAS in SCLK cycles (6 cycles) Look up
under highlighted datasheet information
Fixed
SDRAM tRP in SCLK cycles (3 cycles) Look up
Fixed
SDRAM tRCD in SCLK cycles (3 cycles) Look up
Fixed
SDRAM tWR in SCLK cycles (2 cycles) Look up
Powerup start delay (No extra delay added before
first Precharge command)
SDRAM powerup sequence (Precharge, 8 CBR
refresh cycles, mode register set)
Enables SDRAM powerup sequence on next
SDRAM access
SDRAM self-refres disable
SDRAM timing for external buffering of address
and control (External buffering timing disabled)
Fast back-to-back read to write is disabled
Fixed
Extended mode register disabled
Temperature compensated self-refresh value in
extended mode register (0 - 45 degrees C)
Control disable during bus grant 0 - Continue
driving SDRAM controls during bus grant
Fixed
23
This configration gives the binary value of “1000 0000 1001 0001 1001 1001 1000
1101” or Hex 8091998D.
24
2.4.3. SDRAM Memory Bank Control Register (EBIU_SDBCTL)
Table 2.4: SDRAM Memory Bank Control Register (EBIU_SDBCTL)
Bit no.
0
3:1
5:4
Label
EBE
EBSZ
EBCAW
Value
1
011
11
Content
Enable External SDRAM bank
Totally memory size set to 128Mbyte
SDRAM external bank column address width set
to 11bits
This setting gives a binary value of “00110111” or Hex 37.
2.4.4. SDRAM Refresh Rate Control Register (EBIU_SDRRC)
To calculate the value that should be written to the EBIU_SDRRC register, use the
following equation:
= ((fSCLK ⋅ tREF) / NRA) – (tRAS + tRP)
RDIV
where:
•
f
SCLK
•
t
REF
= SDRAM row refresh period
•
t
REFI
= SDRAM row refresh interval
•
NRA
= SDRAM clock frequency (system clock frequency)
= Number of row addresses in SDRAM (refresh cycles to refresh whole
SDRAM)
•
t
RAS
= Active to precharge time (TRAS in the SDRAM memory global control
register) in number of clock cycles
•
t
RP
= RAS to precharge time (TRP in the SDRAM memory global control
register) in number of clock cycles
Calculation:
((fSCLK ⋅ tREF) / NRA) – (tRAS + tRP)
((131.25 ⋅ 10−6 ⋅ 64 ⋅ 10−3) / 8192) – (6 + 3) = 1016 clock = 0x3F8
Table 2.5: IPT-Shark537 SDRAM default settings
Register
EBIU_SDGCTL
Value
0x8091998D
Function
Calculated with SCLK = 131.25 MHz
16-bit data path
External buffering timing disabled
tWR = 2 SCLK cycles
tRCD = 3 SCLK cycles
tRP = 3 SCLK cycles
tRAS = 6 SCLK cycles
pre-fetch disabled
CAS latency = 3 SCLK cycles
25
EBIU_SDBCTL
0x00000037
EBIU_SDRRC
0x000003F8
SCLK1 disabled
Bank 0 enabled
Bank 0 size = 128 MB
Bank 0 column address width = 11 bits
Calculated with SCLK = 131.25 MHz
RDIV = 1016 clock cycles
2.5. NAND-Flash Memory
The NAND-Flash on the IPT-Shark537 development board, is a 1 Gbit memory chip
(128 Mbyte) from ST Micro NAND01GW3B2BN6 with a 8 bit bus width interface,
multiplexed Address/Data with a page size of (2048 + 64 spare) Bytes and a Block size
of (128 K + 4 K spare) Bytes. Controlled by Address Latch Enable (AL), Command
Latch Enable (CL), read and write. The chip is selected by AMS0, memory address
area is from 0x2000 0000 to 0x200F FFFF.
Table 2.6: Circuit interface between processor and NAND-Flash
Processor Pin
D[0:7]
Flash Pin
I/O[0:7]
A1
A2
nAOE
nAWE
nRESET
nAMS0
PF6
CL
AL
nR
nW
nWP
nE
R/nB
IPT-Shark537 Function
Data Input/Outputs, Address Inputs, or
Command Inputs for x8 devices
Command Latch Enable
Address Latch Enable
Read Enable
Write Enable
Write Protect
Chip Enable
Ready/Busy (open-drain output)
2.6. USB interface
The Universal Serial Bus interface contains a Cypress SL811HST-AXC embedded
USB Host/Slave Controller. The USB Controllers capable of communicating in either
full speed or low speed mode, the SL811HS USB Host Controller conforms to USB
Specification 1.1.
The USB controller supports and operates in both USB full speed mode at 12 Mbps, or
in low speed mode at 1.5 Mbps. When in host mode, the USB is the master and
controls the USB bus and the devices that are connected to it. In peripheral mode,
otherwise known as slave mode, the SL811HS operates as of full or low speed device.
The SL811HS has 256-bytes of internal RAM which is used for control registers and
data buffer.
The USB controller interface uses an 8 bit data bus and is chip selected by AMS1 at
memory address 0x2010 0000 to 0x201F FFFF. The USB controller supports DMA in
slave mode; in this case it’s important to make sure the R156 (R0603) and R157
(R0603), are mounted with a 0 ohm resistor; (default settings on the IPT-Shark537
26
development board). Note: The DMA connection option can also be used as UART0,
via the expansion port J1.
27
Attention: The IPT-Shark537 development board should be limited to Low-Speed mode
devices, when using TFT-display in VGA mode.
The IPT-Shark537 development board can run in slave or host mode. This is controlled
by the jumper J28. The Jumper has to be set in SLAVE mode.
Table 2.7: Jumper option
USB Mode
J28
HOST
OFF
SLAVE
ON
Table 2.8: Circuit interface between processor and USB controller
Processor Pin
D[0:7]
A2
USB Pin
D[0:7]
A0
nARE
nRD
nAWE
nWR
nASM1
nCS
PF1
nDRQ
PF0
nDACK
PF5
INT
Data/Address Bus interface.
A0 = ’0’. Selects address pointer. Register
A0 = ’1’. Selects data buffer or register.
Read Strobe Input. An active LOW input
used with nCS to read registers/data
memory.
Write Strobe Input. An active LOW input
used with nCS to write to registers/data
memory.
Active LOW 48-Pin TQFP Chip select.
Used with nRD and nWr when accessing
the 48-Pin TQFP.
DMA Request. An active LOW output
used with an external DMA controller.
nDRQ and nDACK form the handshake
for DMA data transfers. In host mode,
leave the pin unconnected.
DMA Acknowledge. An active LOW
input used to interface to an external
DMA controller. DMA is enabled only in
slave mode. In host mode, the pin should
be tied HIGH (logic ’1’).
Active HIGH Interrupt Request output to
external controller. (IRQ55)
28
2.7. Ethernet interface
The ADSP-BF537 processor is able to connect to a network directly, with the help of an
embedded Fast Ethernet Media Access Controller (MAC). The Ethernet MAC provides
a 10/100 Mbit/s Ethernet interface, compliant to IEEE Std. 802.3-2002, between an MII
(Media Independent Interface) and the Blackfin peripheral subsystem.
The Ethernet interface contains a SMSC LAN8700 single-chip Ethernet Physical Layer
Transceiver (PHY). The LAN8700 is a low-power and highly-integrated analog interface
IC for high-performance embedded Ethernet applications. The Ethernet connector, (J2)
is a RJ45 type connector with built-in magnetics and LEDs that shows Link and Data
activity. It is a J3011G21DNL from PULSJACK.
Table 2.9: Ethernet LEDs overview
Pos.
J4
J4
D11
D12
LED colour
Green
Yellow
Red
red
LED status
Data
Link
Full Speed (100Mbit/s)
Full Duplex
The LAN8700 is designed for MII operation and is supplied with a 25 MHz clock from
the ADSP-BF537 processors clock buffer.
Table 2.10: Circuit interface between processor and PHY
Processor Pin
PH0
PH1
PH2
PH3
PH4
PH5
PH6
LAN Pin
TXD0
TXD1
TXD2
TXD3
TX_EN
TX_CLK
nINT/TX_ER
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH7
PH15
PJ1
PJ0
CLKBUF
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_CLK
RX_ER
COL
CRS
MDIO
MDC
CLK
Transmit data bit 0 (MII-mode)
Transmit strobe (MII-mode)
Transmit clock (MII-mode)
Interrupt (IRQ88) & Transmit error
(MII-mode)
Receive data bit 0 (MII-mode)
Receive strobe (MII-mode)
Receive clock (MII-mode)
Receive error (MII-mode)
Collision indication (MII-mode)
Carrier sense (MII-mode)
Serial Management Data Input/Output
Serial Management Clock
Clock input (25MHz in MII-mode)
29
2.8. Audio interface
The audio circuit on the IPT-Shark537 development board consists of an AD1981BL
AC ’97 SoundMAX codec and a SSM2211 1.5 W Audio Power Amplifier from Analog
Devices. The codec support full-duplex stereo with 20-bit PCM DAC, Full-duplex
variable sample rates from 7040 Hz to 48 kHz with a 1 Hz resolution. Built-in digital
equalizer function for optimized speaker sound and Software-programmed VREFOUT
output for biasing mono microphone.
The audio codec is interface via the ADSP-BF537s synchronous Serial Peripheral Port
(SPORT0); the SPORT0 module support a variety of serial data communication
protocols to the audio codecs.
The SPORT, transfers serial data words from 3 to 32-bits in length, either MSB first or
LSB first. It has FIFO plus double buffered data (both receive and transmit functions
have a data buffer register and a shift register), providing additional time to
service the SPORT0. Furthermore it provides direct memory access transfer to
and from memory under DMA master control.
Table 2.11: Circuit interface between processor and Audio Codec
Processor Pin
DT0PRI
Audio Pin
SDATA_OUT
DR0RPI
SDATA_IN
RSCLK0 &
TSCLK0
BIT_CLK
RFS0
SYNC
AC-Link Serial Data Output,
AD1981BL Data Input Stream
AC-Link Serial Data Input, AD1981BL
Data Output Stream
AC-Link Bit Clock Output (12.288
MHz) or Bit Clock Input, if Secondary
Mode Selected.
AC-Link Frame Sync
The IPT-Shark537 development board provides two audio inputs and three audio
outputs. The input is a mono microphone with bias option and a line-in for external
audio input. The output is a line-out for connecting a audio recorder or audio power
amplifier. The stereo headphone amplifier can drive a headphone down to 32 ohm. The
1.5 W Audio Power Amplifier can source an 8 ohm loudspeaker via LS1 a Molex
connector type 533980271.
The board have option for connect a telephone handset via a Jack modular 4/4
connector, designed to KIRK DELTA headset specifications. The headset connection is
show in figure 2.1 on page 22. Attention: the headset is connected in parallel with the
microphone and the headphone left channel.
Note: Don’t connect the telephone headset while the microphone and headphone
connectors are in use.
30
Table 2.12: 3.5mm Jack connectors
Name
Mono microphone
Connector
J18
Line-In
Line -Out
Headphone
J13
J12
J17
Signal
0.0707Vrms or 0.2Vpp with 20dB Gain
0.707Vrms or 2Vppwith 0dB Gain
0.707Vrms or 2Vpp
0.707Vrms or 2Vpp
1Vrms or 2.83Vpp
Impedance
20K ohm
20K ohm
800 ohm
32 ohm
Table 2.13: Loudspeaker connector (LS1)
Name
Mono-Out
Connector
LS1
Signal
1.5W
Impedance
8 ohm
Table 2.14: Headset connections for Modular 4/4 (J11)
Pin no.
1
2
3
4
Wire colour
Yellow
Green
Red
Black
Description of Headset connections
Electret Microphone (Plus) Impedance approximate 2K ohm
Speaker (Ground)
Speaker (Plus) Impedance approximate 130 Ohm
Electret Microphone (Ground)
Figure 2.1: Modular Plug 4/4
31
2.9. Parallel Peripheral Interface (TFT-Display Interface)
The IPT-Shark537 development board is designed for a 6.5” colour LCD module form
NEC type NL6448BC20-18D, a TFT-Display with VGA resolution (640 (H) x 480 (V)
pixels). The TFT-Display is composed of the amorphous silicon thin film transistor liquid
crystal display (a-Si TFT LCD) active matrix panel structure with driver LSIs for driving
the TFT (Thin Film Transistor) array and a backlight. The display supports 6 bit data for
Red, Green, Blue totalling 18 bit or 262,144 colours.
The TFT-Display is interfaced via an Hirose DF9-31S-1V_W31 board-to-board
connector, that provides the RGB signal for the display via the ADSP-BF537s 16bit
Parallel Peripheral Interface PPI[0:15]. Because of too few GPIOs it was necessary to
add LSB Red bit 0 & 1 and LSB Blue bit 0 & 1 together to save two GPIO pins. This
change has reduced the display performance to 65,536 colours.
The clock is provided directly by the ADSP-BF537s source oscillator (Y2) at 25 MHz
(40 ns). This signal is used for the ADSP-BF537s PPI input clock at pin PF15 and to
the displays source clock pin. The ADSP-BF537 receives the reference clock via the
PPICLK every 40 ns; the clock is used to drive the TMR0 timer for horizontal sync and
TMR1 timer for vertical sync. The TMR0 is calculated from the display datasheet
information (800 pixels x 40 ns = 32 µs or 31.25 kHz) for horizontal sync output via pin
PF9. TMR1 is also calculated from the datasheet information ((480+45 lines) x 32 µs =
16.8 ms or 59.52 Hz). Every 16.8 ms the vertical sync is set active low via PF8 for one
clock cycle.
The PPI module synchronizes and updates the internal frame syncs via the Direct
Memory Access (DMA) channel. This is configured by the PPI Control Register
(PPI_CONTROL) set to HEX F81E, and the Transfer Count Register (PPI_COUNT) set
to HEX 27F. The DMA configuration register (DMA_CONFIG_REG) is set to HEX
10B4. The tables below show the configuration for the PPI Control Register and the
DMA Configuration registers. The DMA register is enable (DMAEN), when the frame
buffer is activated.
Table 2.15: DMA Configuration Register (DMA_CONFIG_REG)
Bit no.
0
1
3:2
4
5
6
7
8:11
12:14
Label
DMAEN
WNR
WDSIZE
DMA2D
SYNC
DI_SEL
DI_EN
NDSIZE
FLOW
Value
0
0
01
1
1
0
1
0000
0001
Content
Disabled
Direction
Transfer word size
DMA mode
Retain FIFO
Data interrupt timing select
Data interrupt enabled
Flex descriptor size
Flow
32
Table 2.16: PPI Control Register (PPI_CONTROL)
Bit no.
0
1
Label
PORT_EN
PORT_DIR
Value
0
1
3:2
XFR_TYPE
11
5:4
6
7
8
9
10
13:11
14
PORT_CFG
FLD_SEL
PACK_EN
SKIP_EN
SKIP_EO
DLEN
POLC
01
0
0
0
0
0
111
1
15
POLS
1
Content
PPI disabled
Direction PPI in Transmit mode
(output)
Transfer Type Output mode with 1, 2,
or 3 frame syncs
Port Configuration 2 or 3 frame syncs
Active Field Select External trigger
Packing Mode Disabled
Fixed
Skipping disabled
Skip odd-numbered elements
Data Length 16 bits
PPI samples data on falling edge and
drives data on rising edge of PPI_CLK
PPI_FS1 and PPI_FS2 are treated as
falling edge asserted
Table 2.17: Circuit interface between processor and TFT-Display (J4)
Processor
Pin
PF15
PF9
PF8
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
Label
Pin no.
CK
HS
VS
R0 & R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0 & B1
B2
B3
B4
B5
2
3
4
6&7
8
9
10
11
13
14
15
16
17
18
20 & 21
22
23
24
25
Clock input from oscillator (PPICLK)
Horizontal sync form timer (TMR0)
Vertical sync from timer (TMR1)
Red data (LSB)
Red data
Red data
Red data
Red data (MSB)
Green data (LSB)
Green data
Green data
Green data
Green data
Green data (MSB)
Blue data (LSB)
Blue data
Blue data
Blue data
Blue data (MSB)
In case of another TFT-Display configuration, it is possible to mount an external
oscillator with another output frequency at position Y8, in this case move resistor R63
to position R127. Note: the footprint is in size R0402.
Selection of scan direction is controlled by the DPS pin at the display, as default the
display will run in normal scan direction. But it is also possible to run in reverse scan
direction by removing resistor R68 and mounting a 10 kΩ pull-up resistor in position
R66 size R0603.
33
2.10. SPI Interface
The Serial Peripheral Interface (SPI) on the IPT-Shark537 development board is setup
in master mode and support full-duplex synchronous serial communication. The Master
Out Slave In (MOSI) pin at the ADSP-BF537 (PF11) becomes a bidirectional data
transmit output pin and Master In Slave Out (MISO) pin (PF12) becomes a data receive
input pin, both in master mode. The SCK signal is the serial clock signal and sourced
by the ADSP-BF537 (PF13). This clock signal is driven by the master and controls the
rate at which data is transferred. The SCK signal cycles once for each bit transmitted.
The board support four SPI selects, the SPISSEL1 and SPISSEL6 are by default used
for the Serial Boot Flash and the Touch Screen Controller. The SPISSEL3 and
SPISSEL7 are free, but can be used by the WLAN interface and the MMC/SD reader;
This SPI selection is also available on the expansion connector (J1) for other interface
options.
Table 2.18: Circuit interface between processor and SPI devices
Label
SPICLK
MOSI
MISO
Processor pin
PF13
PF11
PF12
Device
SPI Clock
Master Out Slave in
Master In Slave Out
Table 2.19: SPI Select option
SPI Select
SPISSEL1
SPISSEL6
SPISSEL7
Processor pin
PF10
PF4
PJ5
SPISSEL3
PJ10
Device
Serial Boot Flash (U6)
Touch screen controller (U9)
MMC/SD reader (J26) or Onboard
Flash on the WLAN module (J23)
WLAN interface (J23)
2.10.1. Serial Boot Flash
The serial flash memory from STMicroelectronics type M25P16 is a 16 Mbit (2 Mbyte),
with high speed SPI compatible bus running up to 75 MHz clock rate. More than
100000 erase and program cycles per sector and more than 20 years of data retention.
The serial flash’s primary function is to load the initial boot loader (U-boot). Default
settings make it possible to re-program the serial flash with another boot loader, but the
board has an option for write protecting the serial flash: Remove the R39 resistor and
add a 10 kΩ pull-down resistor at position R41 (R0603).
34
2.10.2. Touch Screen Controller
The 4-wire touch screen controller from Analog Devices type AD7877 is a high speed,
low power, 12-bit analog-to-digital converter (ADC) with input multiplexer, on-chip
track-and-hold, and on-chip clock. It can monitor two battery voltages, ambient
temperature and control four general-purpose logic I/O pins. The touch screen
controller is connected to the 4-wire touch panel from Fujitsu LCD type N010-0554T043 (support all 4-wire resistive touch panels) via J8; a TYCO ELECTRONICS FPC
connector family 84953-4.
Table 2.20: Touch Screen Connector (J8)
Pin no.
1
2
3
4
Label
XYX+
Y+
Fujitsu touch panel
Top
Right
Bottom
Left
The IPT-Shark537 development board uses the four GPIOs at the touch screen
controller for the following functions. GPIO1 is configured as an output, to switch the
Backlight inverter for the TFT-Display on or off. The last three GPIO’s (GPIO2, GPIO3
& GPIO4) are configured as inputs with the possibility to detect an interrupt and send a
ALERT signal to the ADSP-BF537s (FP14 pin) that is configured as an INTERRUPT
handler dispatcher. The GPIO2 and GPIO3 handle the interrupts from optional WLAN
module and I2C 16-bit I/O expander.
Table 2.21: GPIO status for touch screen controller
Pin no.
GPIO1
GPIO2
Label
Output
Input
GPIO3
Input
GPIO4
Input
Display Backlight on/off
Interrupt from optional
WLAN module (active high)
Interrupt from I2C 16-bit I/O
Expander (active low)
Interrupt or poll signal from
cradle switch (SW2)
35
GPIO4 is connected to a mechanical slide switch (SW2) on the IPT-Shark537
development board, which simulate a telephone cradle switch (hook switch). When the
switch is in the ON position, the logic signal level will be high on the GPIO4 pin, by a 10
kΩ resistor pulled-up to 3.3 V.
If the slide switch is kept in the ON position, it is possible to use another external switch
in parallel via connector J22 and use this switch instead of the onboard slide switch
(SW2).
Table 2.22: Switch 2 function
Position
ON
Signal
HIGH
OFF
LOW
Pull up by a 10K ohm
Resistor (Position for use an
external Switch via J22)
Connected direct to ground
2.10.3. MMC/SD reader
The IPT-Shark537 development board is mounted with a MMC/SD card reader that
gives the possibility to extend the local data storage on the board. The SD-card is
accessed via the SPI bus, which runs with a maximum speed rate of 20 MHz. The
ADSP-BF537 does not support the SD-Interface. The card detect is not active by
default, but in case the WLAN module isn’t used it is possible to add a 0 ohm resistor at
position R137 (R0603) and the WLAN interrupt will be used as card detect.
Figure 2.1: MMC/SD connections
36
2.10.4. WLAN Interface
The IPT-Shark537 development board comes ready to connect the Wireless LAN
(IEEE 802.11b/g) module from connectBlue type OMLAN211g. The module can be
connected to the IPT-Shark537’s WLAN connector (J23), type Samtec TLE-110-01-GDV-A.
The OWLAN211g is a small size WLAN module (23 x 36mm) based on the Phillips
BGW211 system in package (SiP) chipset. The OWLAN211gi-02 has a internal
antenna and pin header ready for be used together with IPT-Shark537.
Table 2.23: Interface connection for WLAN (J23)
Pin no.
Label
Description
1, 2
VSS
Power Ground (0V)
3, 4
VDD
Supply voltage 3.3Volt
Reserved
5 – 9, 12
10
nRESET
Active low, Must be driven by open drain.
Internal pull-up 56k ohm.
11
nCS1
13
MOSI
SPI Secondary Chip Select. (Flash memory). Internal pull-up 56K
ohm. If not used this signal should be decoupled with 10 nF to VSS
SPI Slave Input
14
nCS0
15
VDD
SPI Primary Chip Select. (BGW211)
Internal pull-up 56K ohm.
Supply voltage 3.3Volt
16, 17
VSS
Ground (0V)
18
CLK
SPI Clock input, Max clock frequency 48 MHz
19
INT
SPI Interrupt signal (BGW211)
20
MISO
SPI Slave Output, 3-state output buffer active when: SPI-CS0-n =
low OR SPI-CS1-n = low Internal pull-up 56K ohm.
Datasheet information for WLAN (OMLAN211g) module from connectBlue.
Note: The WLAN hardware is not yet verified to work and the driver is not available
from IP Thinking. Please contact connectBlue to purchase hardware module and
driver.
37
2.11. I2C interface (16-bit I/O expander)
The IPT-Shark537 development board is designed with a NXP PCF8575C 16-bit I/O
expander, using the I2C-Bus it provides 16 GPIO’s extra for the system to use. A
keypad (4x4) input and LED status output or an LCD Character Display could be
connected to this port (J27). The 16 extra GPIOs are split into two ports: P0 and P1.
The port P0 is configured with a 10 Ω series resistors (R148-R155) and P1 is
configured with 10 kΩ pull-up resistors (RN2 & RN3) by default. The I/O expander is
hooked up via the I2C-Bus, using synchronous serial clock and data lines. The device
will interrupt the ADSP-BF537s PF14 via the touch screen controller if the I/O expander
port is configured to detect an interrupt, and the touch screen controller is configured to
allow the IRQ (default).
Table 2.24: Circuit interface between processor and I/O Expander
Processor Pin
PJ2
PJ3
PF14
(EXT. INT.)
I/O Pin
SCL
SDA
nINT
Clock
Data
Interrupt
NOTE: The Interrupt is switched
through the touch screen controller (U9)
via GPIO3 to PF14 on the processor.
Table 2.25: Pin out configuration at 16-bit I/O Expander (J27)
Label
P[10:17]
GND
P[00:07]
3V3
5V
Pin no.
1 to 8
2
11 to 18
19
20
Description of Header
8 bit I/O port with Pull-up resistor at 10K ohm
Ground
8 bit I/O port with series resistor 10 ohm
3.3 V
5V
38
2.12. UART Port
The universal asynchronous receiver/transceiver (UART1) port on the processor
connects to the Analog Devices ADM3101EACPZ RS-232 single line driver; This RS232 line driver is connected to the DB9 female connector, provides an interface to a
personal computer and other serial devices. The UART on the IPT-Shark537
development board only supports communication via Data transmit and Data receive
lines.
Table 2.26: RS-232 Interface (J19)
Processor Pin
UART1TX/PF2
UART1RX/PF3
DB9 Pin
2
3
Data Transmit
Data Receive
2.13. JTAG Emulation Port
The JTAG emulation port allows an emulator to access the processor’s internal and
external memory through a 6-pin interface. JTAG emulators offer faster communication
between the host PC and target hardware (IPT-Shark537). Analog Devices carry a
wide range of in-circuit emulation products. The board connector is from Samtec (type
TSM-107-01-L-DV), and is compatible with Analog Devices ADZS-HPUSB-ICE JTAG
emulator.
Table 2.27: JTAG Emulation Interface (J20)
Processor Pin
nEMU
TMS
TCK
nTRST
TDI
TDO
Pin
2
6
8
10
12
14
Emulators
Test Mode Select
Test Clock
Test Reset
Test Data In
Test Data Out
39
2.14. Expansion Interface
The expansion interface consists of a 60-pin Samtec connector type SFC-130-T2-F-DA. It supports data/address bus and control signals, Pins as GPIOs and/or the following
bus types (depending on configuration): CAN, I2C, SPI and UART0.
Table 2.28: Pin out configuration at expansion interface (J1)
Processor
Pin
D[0:15]
Pin
External data bus interface
nRESET
nARE
nAWE
nAMS2
nAMS3
CAN Tx/PJ5
CAN Rx/PJ4
2, 4, 6, 8, 10,
12, 14, 16, 18,
20, 22, 24, 26,
28, 30, 32
1, 3, 5, 7, 9, 11,
13, 15, 17, 19,
21, 23, 25, 27,
29, 31, 33, 35,
37
39
41
43
38
40
45
47
SPIMOSI
SPIMISO
49
51
SPICLK
SCL
SDA
PF14
(EXT. INT.)
53
42
44
46
PJ10
CLK BUF
PF0/UART_
Tx/DMAR0
48
50
52
PF1/UART0
_Rx/DMAR1
54
A[1:19]
External address bus interface
Hardware Reset
Asynchronous memory read enable
Asynchronous memory write enable
Asynchronous memory selects
Asynchronous memory selects
Controller Area Network interface (CAN Tx)
Controller Area Network interface (CAN Rx) or SPI select 7
NOTE: This pin is share with SPI select for MMC/SD card reader.
Master Out Slave In (MOSI), SPI Serial Data IN (SDI) to device
Master In Slave Out (MISO), SPI Serial Data Out (SDO) from
device
SPI CLK
I2C CLK
I2C DATA
Common Interrupt pin for I2C devices, share with local NXP
PCF8575C (U18)
NOTE: The Interrupt is switched through the touch screen
controller (U9) via GPIO3 to PF14 as the processor.
SPI select 3. NOTE: This pin is shared with SPI select for WLAN
25 MHz from ADSP-BF537s Clock buffer
Can be used as PF0-GPIO or UART Tx or DMAR0. NOTE: This
pin can be share with USB controllers DMA interface in SLAVE
mode
Can be used as PF1-GPIO or UART Rx or DMAR1. NOTE: This
pin can be share with USB controllers DMA interface in SLAVE
mode
Table 2.29: Power limit via expansion connector (J1)
Voltage
5V
3V3
GND
Pin
34,36
55, 57, 59
56, 58, 60
IPT-Shark537 Configuration
5 Volt DC with maximum current at 1000mA (5W)
3.3 Volt DC with maximum current at 500mA (1.65W)
Ground
Attention: The data/address bus impedance is designed to be 60 ohm +/-10%, on the
IPT-Shark537 development board. For a potential layout design for an add-on-board to
40
the IPT-Shark537, it is important the impedance matches through the expansion
connector (J1) to the device.
2.15. Connectors
This section describes the connector functionality and provides information about
mating connectors. The connector locations are shown the figure 2.2.
Backlight-PCB
Connector Overview
Figure 2.2: Connector Locations
Handset connector (J11)
Part Description
Modular 4/4 jack socket
Modular 4/4 jack plug (RJ10)
Manufacturer
MOLEX
Mating connector
LUMBERG
Part Number
855025005
P126RJ104P/4C
Audio connectors (J12 – J13 & J27- J28)
Part Description
3.5 mm stereo jack socket
Manufacturer
SHALLIN
Mating connector
SHALLIN
3.5 mm stereo jack plug
Part Number
K36406
K302D
Loudspeaker connector (LS1)
Part Description
PicoBlade™ Wire-to-Board Header
Wire-to-Board Receptacle
Manufacturer
MOLEX
Mating connector
MOLEX
Part Number
533980271
510210200
41
Ethernet connector (J2)
Part Description
Ethernet jack
Manufacturer
Part Number
PULSE JACE
J3011G21DNL
Mating Cable (shipped with IPT-Shark537)
2M Cat 5E patch cable (RJ45)
BELKIN
A3L791b02M-GRY
RS-232 connector (J19)
Part Description
DB9, female
Manufacturer
Part Number
Shallin Electronics
YFR09S
Mating Cable (shipped with IPT-Shark537)
1.8 m RS232 Cable DB9 M-F
ROLINE
11.01.6218-50
USB-B connector (J14)
Part Description
USB Slave (Type-B)
1.8 m USB Cable, Type A-B
Manufacturer
TAITEX
Mating Cable
ROLINE
Part Number
USB RSI-04SW12R
Manufacturer
FCI
Mating Device
HP
Part Number
87583-2010BLF
11.02.8818-100
USB-A connector (J15)
Part Description
USB Host (Type-A)
Tested with HP keyboard
KU-0316
Expansion connector (J1)
Part Description
60 pins SFC series board connector
2m female-to-male cable
Manufacturer
SAMTEC
Mating connector
SAMTEC
Part Number
SFC-130-T2-F-D-A
TFC-130-32-F-D-A
DC connector (J16)
Part Description
2.5 mm power jack
9 V power supply
Manufacturer
Part Number
SWITCHCRAFT
RASM722X
Mating Power Supply (shipped with IPT-Shark537)
CRAFTEC
PSA15R-090-P-R
Inverter connector (J5)
Part Description
Manufacturer
MOLEX
Mating connector
MOLEX
Part Number
532610871
Manufacturer
MOLEX
Mating connector
MOLEX
Part Number
533980271
510210800
External switch connector (J22)
Part Description
510210200
JTAG connector (J20)
Part Description
14 pins, TSM series, 2.54 mm spacing
Emulator
Manufacturer
SAMTEC
Mating Device
ANALOG DEVICES
Part Number
TSM-107-01-L-DV
ADZS-HPUSB-ICE
42
43
Chapter3: Quick reference guide
Chapter 3
Software Quick reference guide
3.1. Introduction:
This guide will help you set up your system to develop applications for the IPTshark537 development board.
The board uses uClinux2 as its operating system and “das u-boot” as it's bootloader.
Both of these are open source projects, that can be customised for individual use.
This guide assumes you have at least some basic knowledge about the unix/linux
operating system; even so we've tried to be very explicit in our examples.
You'll be shown how to compile, customise and load the kernel and system image
(then together make up the operating system), also it will show how to compile,
customise and load a new bootloader.
A small sample program is also included, and it is shown how to compile and run it.
A section for using Trolltech’s graphical framework “QT” is also included.
The board comes pre-flashed with a fully working kernel, that demonstrates some of
the features of the board. The source code for all of which is available on the support
disc, or on our website.
Please keep in mind that this is just a quick reference, for more in-depth information
and guides visit: http://docs.blackfin.uclinux.org
2 http://www.uclinux.org
44
3.1.1. System overview
The linux kernel provides a unified way to access hardware. Applications don't need to
care about any hardware specific details, only how to communicate with the platform
independent kernel interface.
Writings program for uClinux is like writing for any other linux dritribution. There are a
few pitfalls to be aware of, but most applications should be easily portable. The uClinux
distribution also supports graphical frameworks
like Trolltech's QT,
nano-X
(microwindows), DirectFB and SDL that you can build upon to make impressive
programs quickly.
Ha rdwa re US B
Ne twork
Audio
Dis pla y
...
RAM
Ha rdwa re
s pe cific
drive rs
P la tform
s pe cific
ke rne l
Linux ke rne l
P la tform
toolcha in
(compile r)
Gra phica l
fra me work
QT
Fra me work
compile r
Applica tions
Applica tion
Applica tion
Figure 3.1: System software overview
3.2 Reading guide
Filenames, programs or directories are all styled with a fixed monospace font, like this:
uClinux Each time something that is encapsulated in less-than and bigger-than
braces like this: <ip_address>, you must replace this with something that matches the
configuration of your system. In the example above you should replace it with an ip
45
address.
46
3.3. Setting up the host system
The host system is the machine that you will be using to develop your applications and
working with the board to test and demonstrate new kernels and bootloaders (if
needed). Your host system should ideally be using Linux as its operating system. It is
however possible to use coLinux under Microsoft Windows.
Installing any of these are not included in this guide as there are many good guides
around to support the distribution you've chosen to use. Once you have your host
installed and running you should make sure that the following packages are installed
(and their development versions): binutils, gcc, glibc, ncurses, zlib, texinfo and “host
side kernel source”. This is typically done with a “package manager” like yast (for
openSuSE), apt-get/aptitude (for ubuntu/debian), emerge (for gentoo), just to name a
few.
3.3.1. Terminal program
For linux: minicom, telnet or similar
Note: If you use minicom make sure you disable init/reset strings, dialing prefix's and
the connect string in the options menu.
For Windows: HyperTerminal, telnet or similar
Serial console settings (default – these can be changed by the bootloader):
Table 3.1: Serial console settings
Option:
Speed
Parity
Data bits
Stop bits
Hardware flow control
Software flow control
Setting:
57600
No
8
1
No
No
After setting up the terminal program and connecting the console cable you are ready
to plug in the power plug. If you see the u-boot boot loader starting in the terminal
window your settings are correct.
If garbage characters are printed in the terminal, your terminal settings are incorrect.
If your see no output at all, check that the serial cable is correctly connected at both
ends and you've selected the correct serial (COM) port. If you are sure your settings
are correct you may have flashed an invalid u-boot image and “bricked” your board
(see the troubleshooting section for more help).
47
3.3.2. Toolchain
To compile applications for the board, you will need a set of processor-specific
compilers (toolchain). These files are located on the support disc, and match the kernel
version that also resides on the disc.
Note: If you update to a newer kernel, it might be necessary to update the toolchain as
well.
The newest toolchain is always available at: http://blackfin.uclinux.org. On most linux
distributions the toolchain can be installed by using the rpm utility.
In the openSuSE distribution, the command is:
rpm -Uvh <filename>
(e.g. rpm -Uvh blackfin-toolchain-08r1-8.i386.rpm)
Note: You need to install both blackfin-toolchain-uclibc-full-<version>.rpm
and blackfin-toolchain-<version>.rpm.
After the installation you need to include the toolchain files to your path:
export PATH=$PATH:/opt/uClinux/bfin-uclinux/bin:/opt/uClinux/bfinlinux-uclibc/bin
It's a good idea to add this to your boot script, so it gets loaded every time you log-in.
In openSuSE you can add it to /etc/profile.local, other distributions may require a
different setup.
If you use Windows, the toolchain comes as a single executable installer.
48
3.4. Compiling your first kernel/system image
The kernel is the core of the linux operating system (OS), it handles drivers, devices,
multitasking (concurrency), scheduling and much more. The kernel simplifies access to
your hardware, ensuring a standardized interface for applications that want to use it,
and it even does this across platforms.
The kernel is not the complete OS however. It comes with a lot of small applications
that make the OS more usable. On this board many of these utilities are replaced by a
single multifunction application called “busybox”3. The kernel image, these utilities and
the programs you choose to embed in your uClinux distribution will be in the system
image. One file, that’s ready to load your entire system.
Note: Make sure you've set up your toolchain before compiling your kernel.
3.4.1. Getting a kernel
On the support disc you'll find both a precompiled kernel (this is also flashed into the
board when shipped), and also the kernel source. Another option is to download the
kernel source files from our website. As updates are released regularly, this is the
recommended method. It's also possible to download the latest version from
http://blackfin.uclinux.org, though this may require some patching to work properly.
Once you've chosen a kernel source, unpack it:
tar -xf <filename>
(e.g. tar -xf dist_2007r1.tar.bz2)
3.4.2. Patching the kernel
If you've used the kernel sources from the support disc, or downloaded it from our
website, all necessary patches have already been applied.
If you've chosen to download the official blackfin uClinux distribution you may need to
apply some additional patches. Check our website to see if any patches are available
for the kernel you're using.
3.4.3. Kernel setup
To setup and compile the kernel, navigate to the kernel source directory and execute:
make menuconfig
This will bring up the uClinux configuration utility. From here you can setup both the
kernel itself and also the applications that will be compiled into the final system image.
3 http://busybox.net/
49
It is important to select the correct vendor and board type. in the uClinux configuration
utility go to:
Vendor/Product Selection -->
From the Vendors list you want to select IpThinking and IPT-Shark537 under the
IpThinking Products list.
This will load the default setup for the selected board (overriding the current setup).
3.4.3.1. Compiling/Customizing the kernel/user settings
If you wish to add or remove functionality, navigate to the kernel source directory and
execute:
make menuconfig
If you wish to add/remove something from the kernel, select:
Kernel/Library/Defaults Selection
--->
and select:
[ ] Customize Kernel Settings
now exit and save, this will bring up the normal kernel configuration utility.
On the other hand if you wish to add/remove something from the filesystem, select:
Kernel/Library/Defaults Selection
--->
and select:
[ ] Customize Vendor/User Settings
now exit and save, this will bring up the uClinux embedded configuration utility.
It is also possible to select both options (this will show both utilities, one after the
other).
Once you've customized the settings to your likings, compile the new kernel by
executing:
make
This will generate a kernel and system image, in different formats. These are located
the images directory under the kernel source directory (uClinux-dist).
The system image is called uImage
50
3.4.4. Loading the new kernel on the board
The system image you want to load is called uImage.initramfs (or just uImage – that
are the same).
Before you can load the image you need to set up a TFTP server so the board can find
and load the new image.
3.4.4.1. TFTP Server
Install your favorite TFTP server daemon (or service if you wish to load the image from
a windows machine).
Place the system image in the TFTP server root directory.
3.4.4.2. Loading a “image” in u-boot
These steps/commands are execute at the u-boot prompt. Executing help or help
<command> gives a short help message.
There are several options that need to be set in order to load the new image, these are:
Table 3.2: Important u-boot parameters
Option:
kernelfile
ipaddr
serverip
gatewayip
netmask
Description:
The filename to look for on the server, when booting a system/kernel
image via The image name to transfer and load, when booting from a
TFTP server.
The IP address of the board.
The TFTP server address.
If the server and board aren't on the same subnet, use this gateway to
make contact.
The subnet mask of the board.
You can set each option with:
set <option> <value>
(e.g. set kernelfile uImage)
If you wish to save the new settings, execute:
save
It's possible to see all the options by executing:
printenv
Note: the EEPROM has a limited number of write cycles (~100000).
Once these parameters are set, you can boot the image by executing:
run imageboot
51
3.4.4.3. Flashing the board with the new kernel/system image
Programming the nand flash involves the following steps:
1. Getting the image file (using either TFTP or serial).
2. Calculating the correct size of the image for flashing.
3. Programming the flash chip.
Step 1: Getting the image file (using either TFTP or serial)
Using TFTP:
tftp <offset> <filename>
(e.g. TFTP 0x1000000 $(kernelfile)
This will copy the file named in the kernelfile variable into the boards memory at
location 0x1000000.
Using serial transfer:
There are too modes (kermit or ymodem). The one you should use depends to what
your terminal program supports.
For kermit mode:
loadb [offset] [baud rate]
and for ymodem mode:
loady [offset] [baud rate]
(e.g. loady 0x1000000)
Once you've hit enter after the command, you need to send the file using your terminal
program, and using the selected transfer protocol. Check your terminal program to see
which protocols are supported.
Note: Serial transfers are only recommended for small files because the bandwidth is
low.
52
Step 2: Calculating the correct size of the image for flashing
The filesize of the transferred image is shown after the transfer has completed no
matter if TFTP or serial transfer was used. This size needs to be padded to match the
page size of the nand chip (512).
If the filesize is 3488137 (353989 hex) or ~3,3 Mb, the programming size should be:
3488137/512 = 6812.767 => 6813*512 = 3488256 (353A00 hex)
Another option, to avoid the calculation, is simply to type in a much bigger filesize (still
padded to 512). If other data (like filesystems) are stored in the NAND chip be careful
not to overwrite these.
Note: The NAND chip has a limited number of write cycles per. sector (~100000).
Step 3: Programming the flash chip
Programming is done via the built-in nand command in u-boot:
nand write.jffs2 <address-start> <size>
(e.g. nand write 0x0
353A00)
If you want to execute the image stored in the nand chip as the default, set the variable
bootcmd to run flashboot, by executing:
set bootcmd 'run flashboot'
Make sure the variable autostart is set to “yes”, by executing:
set autostart yes
And remember to save (otherwise all changes will be lost when the board is reset):
save
If you at a later time want to load a image from TFTP, you can just interrupt u-boot in its
boot process and execute:
run imageboot
Or set the imageboot option as the default with (and again remember to save):
set bootcmd 'run imageboot'
53
3.5. Compling “das u-boot”
Das U-boot4 (from here-on just called “u-boot”) is the bootloader used on the board. Its
function is simply to prepare the board for the OS and afterwards handle control over to
the OS. The board comes with a fully functional u-boot already programmed into the
EEPROM, and there should be no need to reload/edit it if you only want to develop
applications for uClinux.
3.5.1. Getting u-boot
There are three options for getting the u-boot source code:
1. The support disc contains both a binary image and the source code, so you can
compile it for yourself.
2. Download the image/source code from our website.
3. Download and patch a version downloaded from another location.
Once you have u-boot, unpack it:
tar -xf <filename>
(e.g. tar -xf u-boot-1.1.6-2008R1-iptshark537.tar.gz)
3.5.2. Patching u-boot
If you've used the u-boot sources from the support disc, or downloaded the it from our
website, all necessary patches have already been applied.
If you've chosen to download u-boot from another location you may need to apply
some additional patches. Check our website to see if any patches are available for the
u-boot version you're using.
4 http://sourceforge.net/projects/u-boot/
54
3.5.3. U-boot setup
All u-boot configuration options are saved in a header file located in
<u-boot_source>include/configs/bf537-iptshark537.h.
Note: There should be no need to edit this file, unless hardware modifications are
made, or you require different cpu/bus speeds.
3.5.3.1 Compiling
To compile u-boot, execute the commands:
make bf537-iptshark537_config
make
The first command will configure u-boot for the board. The second command will then
begin to compile u-boot and make a image ready for loading onto the board.
Note: Because the configuration is saved in a header file, it's necessary to execute
“make clean/make mrproper”, before compiling again (updates to header files does
not automatically trigger a recompile).
Once compiling is complete you've have the following files available in the u-boot
source root directory:
Table 3.3: u-boot files and function
Filename:
u-boot
u-boot.ldr
u-boot.bin
u-boot.hex
u-boot.ldr.hex
u-boot.ldr.srec
Description:
Used to load a u-boot image via the JTAG connector (for loading the file
via Visual DSP, add the .dxe extension)
Loader file - Used for flashing the eeprom with a new u-boot image
Binary file - Used for testing u-boot (loading via TFTP)
Not used
Not used
Motorola loader fileformat (not used)
55
3.6 Loading and flashing u-boot
U-boot can load its file via TFTP or via serial transfer.
Note: If you program the EEPROM chip with an invalid file, or a broken u-boot image
you board will be “bricked”. If this happens, see the troubleshooting section of this
document for details.
Loading using TFTP:
Copy u-boot.bin and u-boot.ldr to your TFTP server root directory.
It's a good idea to test your new u-boot image before programming it into the eeprom.
This is done by executing:
tftp 0x1000000 u-boot.bin
go 0x1000000
The commands first transfers the binary u-boot image to the board (in RAM at location
0x1000000), after which you tell it to start loading from address 0x1000000 in memory
(where the image is).
Note: Not all changes can be tested this way. Memory size and processor/bus speeds
are not updated this way (the registers are set once, and cannot be changed without a
cold reset); other settings may also require a cold reset.
Once you're sure the image you've created works, you can write it to the EEPROM by
executing:
run update
This will write u-boot.ldr to the EEPROM (if the u-boot variable ubootfile hasn't been
changed – otherwise that filename will be loaded).
56
Loading using serial transfer:
U-boot supports two serial transfer protocols: ymodem and kermit. Which one you
should use depends on what your terminal program supports.
The ymodem command is loady, while the kermit command is loadb.
It's a good idea to test your new u-boot image before programming it into the
EEPROM. This is done by executing:
loadX 0x1000000
go 0x1000000
Replace loadX with the proper command.
After the first command is entered, use your terminal program to send u-boot.bin using
the selected protocol. The second command starts loading from memory at location
0x1000000 where the file was transferred to. This will bring up the new u-boot.
Note: Not all changes can be tested this way. Memory size and processor/bus speeds
are not updated this way (the registers are set once, and cannot be changed without a
cold reset); other settings may also require a cold reset.
Flashing u-boot
Once you're sure the image you've created works, you can write it to the eeprom by
executing:
loadX 0x1000000
eeprom write 0x1000000 0x0 $(filesize)
Again, replace loadX with the proper command.
Next, you write the image at location 0x1000000 in memory to the eeprom, beginning
at offset 0x0.
Note: Remember to send the correct file (u-boot.ldr), as programming the wrong file
will “brick” your board.
Once you've reset the board with the new u-boot, you need to re-enter the ethernet
MAC address.
This is because the MAC address is stored in the flash chip.
To set the MAC address type:
set etheraddr <MAC-address>
save
The boards MAC address is located on a sticker on the main PCB.
57
3.7 Making your own applications
When making your own c/c++ programs there are a few things you need to keep in
mind:
−
uClinux uses uClibc and not glibc.
−
The microprocessor does not support MMU, so memory management is more
confined.
For more in-depth information we encourage you to read:
http://docs.blackfin.uclinux.org/doku.php?id=uclinux_on_blackfin
3.6.1 The “hello world” example
This is as simple as it gets, but it will determine if you build setup is correct.
The hello.c file:
#include <stdio.h>
int main() {
printf("Hello, World\n");
return 0;
}
3.7.1.1 Compiling
bfin-uclinux-gcc is used to build FLAT format application and the Linux kernel (in
ELF format), while bfin-linux-uclibc-gcc is used to build FDPIC format binary.
The bfin-elf-gcc compiler is used to compile the Linux kernel and standalone
programs (non-Linux programs in other words, for example u-boot) as it uses a
different set of libraries.
For the example you'll use the bfin-linux-uclibc-gcc compiler (since you're compiling a
program to run under uClinux). Execute the command:
bfin-linux-uclibc-gcc hello.c -o hello
You should now have a binary file called hello thats ready to run to the board. If you
wish to test the application on your host system, you'll need to use a different compiler
(the plain gcc compiler):
gcc hello.c -o hello
58
3.7.1.2 Downloading and testing on the board
Two methods exist to do this:
1. Integrate the application into the system image, or
2. Run/copy the application over a network/serial connection.
1. Integrating the application into the system image
cp hello <uClinux-dist>/romfs/bin/hello
and then in the kernel source (uClinux-dist) directory do:
make image
This will re-build the files <uClinux-dist>/images/linux and <uClinuxdist>/images/uImage
Once you've booted the new image, run the application on the board like any other
program:
/bin/hello
This should print on the console:
Hello, World
2. Run/copy the application over a network connection
Make sure the network interface is up on the board and its got a valid IP and subnet
address.
You can use either:
dhcpcd &
or
ifconfig eth0 <ip_address> up
to set or get an IP address.
Now you can either get the file via TFTP, HTTP, samba or serial transfer.
For TFTP (make sure you've copied the hello application to the TFTP server root
directory on your host machine):
tftp -g -r hello <your_tftp_host>
For HTTP (make sure you've copied the hello application to the web server):
wget http://<your_http_host>/hello
chmod 777 hello
The first command downloads the file from the web server, and the second sets the
permissions.
59
For Samba (make sure you've copied the hello application to an accessible share):
smbmount //<your_samba_host>/<share_name> /mnt
For serial transfer (make sure lrz is compiled into the system image – this uses zmodem protocol):
On the development board execute:
lrz
and using your terminal program, send the application to the board. Afterwards, set the
permissions, and you're ready to run the application:
chmod 777 hello
Running the application is simple, either run (for serial, HTTP and TFTP transfers):
./hello
or run (if connected to a network share via samba):
/mnt/hello
This should print on the console:
Hello, World
60
3.7.2 Adding an application to the uClinux configuration
For in-depth information see:
http://docs.blackfin.uclinux.org/doku.php?id=adding_user_applications
The following procedure describes how to add a user written application to the uClinux
system image:
First create a new directory in <uClinux-dist>/user/ folder to store the source files
for the new application.
Next you need to edit <uClinux-dist>/user/Makefile, you'll need to add your new
directory (in this example myprog) to the file:
dir_$(CONFIG_USER_MYPROG_MYPROG) += myprog
If the directory contains two executables, for example myprog1 and myprog2, this is
changed to:
dir_$(CONFIG_USER_MYPROG_MYPROG1)
dir_$(CONFIG_USER_MYPROG_MYPROG2)
+= myprog
+= myprog
Next, edit <uClinux-dist>/config/Configure.help. Add an help-text that describes
your application:
CONFIG_USER_MYPROG_MYPROG
This is my program
For two executables in the same directory add something like:
CONFIG_USER_MYPROG_MYPROG1
This is my program
This is my program too
Note: Each line of the help text must be indented two spaces. Furthermore, each line
must be shorter than 70 characters. Blank lines within the help text are not allowed.
Next you'll want to edit <uClinux-dist>/config/config.in. This file determines
which section(s) your program(s) appear under in the application configuration window.
Under a appropriate section add an entry similar to the following:
bool 'myprog'
CONFIG_USER_MYPROG_MYPROG
61
For two executables in the same directory add entries similar to the following:
bool 'myprog1'
bool 'myprog2'
Next step is to ensure that there is a Makefile in your application directory.
This Makefile should have a form similar to the following:
EXEC = myprog
OBJS = myprog.o
all: $(EXEC)
$(EXEC): $(OBJS)
$(CC) $(LDFLAGS) -o $@ $(OBJS) $(LDLIBS)
romfs:
$(ROMFSINST)
/bin/$(EXEC)
clean:
rm -f $(EXEC) *.elf *.gdb *.o
The Makefile for two executables in the same directory would look like this:
EXEC = myprog1 myprog2
OBJS = myprog1.o myprog2.o
all: $(EXEC)
$(EXEC): $(OBJS)
$(CC) $(LDFLAGS) -o $@ [email protected] $(LDLIBS)
romfs:
$(ROMFSINST) -e CONFIG_USER_MYPROG_MYPROG1
$(ROMFSINST) -e CONFIG_USER_MYPROG_MYPROG2
/bin/myprog1
/bin/myprog2
clean:
-rm -f $(EXEC) *.elf *.gdb *.o
The application should appear in the application configuration window under the
section you've chosen. Make sure your application is selected and recompile the
kernel/system image. Once compilation has completed, load the system image on the
board. Your application should appear in the /bin directory.
62
3.7.3 QT
QT is a graphical framework developed by Trolltech5. It's free of charge for developing
open source applications under the GPL license. Another option is to buy a commercial
license and you'll have full control over your software and license, QT offers both.
3.7.3.1 Getting QT
The easiest way to get started with QT is to use the version supplied on the support
disc. These source files have already been patched to support the development board.
If you download QT yourself, you can do so at Trolltech's website:
http://trolltech.com/downloads
Once gotten you'll need to extract the source:
tar -xf <filename>
(e.g. tar -xf qtopia-core-opensource-src-4.2.2-src-bfin.tar.gz)
3.7.3.2 Patching QT
If you've gotten the source file from the support disc, this step is not needed.
You need to look for at patch for the QT version you've downloaded in:
<uClinux-dist>/bfin_patch/
If a patch exist apply it, and you should be ready to go; if not, you need to find version
of QT that is supported or create a patch yourself.
3.7.3.3 Compiling
Before you begin writing applications in QT, you need to configure it to compile
programs for the embedded development platform.
The configure command for QT is:
./configure -embedded bfin -depths 16 -static -prefix <output_dir> qt-kbd-usb -no-separate-debug-info -no-cups -no-nis -DQT_NO_SOUND DQT_NO_QWS_MULTIPROCESS -xplatform qws/linux-bfin-g++
(e.g. ./configure -embedded bfin -depths 16 -static -prefix
/lib/qt4bfin/ -qt-kbd-usb -no-separate-debug-info -no-cups -no-nis DQT_NO_SOUND -DQT_NO_QWS_MULTIPROCESS -xplatform qws/linux-bfin-g++)
Once configured you can build QT by executing:
make
5 http://www.trolltech.com
63
3.7.3.3.1 Touchscreen support
To have touchscreen support on the board, you'll need to add the following options to
the build command:
-qt-mouse-tslib
and include the tslib libraries, by adding:
-I <uClinux-dist>/lib/tslib-1.0/src/
-L <uClinux-dist>/lib/tslib-1.0/build/src/.libs
The complete configure command (with touchscreen support) will be:
./configure -embedded bfin -depths 16 -static -prefix <output_dir> qt-kbd-usb -qt-mouse-tslib -no-separate-debug-info -no-cups -no-nis DQT_NO_SOUND -DQT_NO_QWS_MULTIPROCESS -I <uClinux-dist>/lib/tslib1.0/src/ -L <uClinux-dist>/lib/tslib-1.0/build/src/.libs -xplatform
qws/linux-bfin-g++
(e.g. ./configure -embedded bfin -depths 16 -static -prefix
/lib/qt4bfin/ -qt-kbd-usb -qt-mouse-tslib -no-separate-debug-info -nocups -no-nis -DQT_NO_SOUND -DQT_NO_QWS_MULTIPROCESS -I
/home/urup/dist_2007r1/lib/tslib-1.0/src/ -L
/home/urup/dist_2007r1/lib/tslib-1.0/build/src/.libs -xplatform
qws/linux-bfin-g++)
Once configured you can build QT by executing:
make
Note: Make sure tslib is selected for compilation in the system image (by default it is
selected), and that the system image has been compiled with this option set, at least
once. Otherwise it will not work.
You'll need to declare some basic options on the board before tslib will work:
export
export
export
export
export
export
TSLIB_CALIBFILE=/etc/pointercal
TSLIB_CONFFILE=/etc/ts.conf
TSLIB_PLUGINDIR=/lib
TSLIB_TSDEVICE=/dev/input/event0
TSLIB_CONSOLEDEVICE=none
TSLIB_FBDEVICE=/dev/fb0
export QWS_MOUSE_PROTO="tslib:$TSLIB_TSDEVICE"
Before firing up any application, it's a good idea first to calibrate the touchscreen, this
can be done by executing:
/bin/ts_calibrate
Note: The pointer calibration file can be embedded in the image, so you don't need to
calibrate it after every reboot, so too can the declared variables.
64
3.7.3.4“Hello world” example
This is as simple as it gets. The program will show a single dialog box with one button
labeled “Hello world!” (Clicking the button has no effect).
#include <QApplication>
#include <QPushButton>
int main(int argc, char *argv[]) {
QApplication app(argc, argv);
QPushButton hello("Hello world!");
hello.resize(100, 30);
hello.show();
return app.exec();
}
3.7.3.4.1 Compiling
QT is also cross-platform, so its possible to test out your application on your
development host, before you try it out on the board.
The procedure is the same, whether compiling for the board, or your development host.
In your application directory do:
qmake -project
qmake
make
The first command builds the project file (.pro), the second will create the Makefile
thats used by make. The last commands build all other files (ui files and objects), then it
links them together and create an executable.
If you use the qmake program compiled for the development board, your executable will
be able to run there.
If you on the other hand use a qmake that is compiled for your development host, then
the program will be able to run there, and not on the development board.
Compiling QT for your development host is not covered in this document, but make
sure that you use the same compile options, to get similar results, when running on the
host system and on the development board.
Basically you only need to strip the embedded, qt-mouse-tslib flags, and change (or
omit) the prefix flag on compile for your host system.
65
3.7.3.4.2 Testing
To run a QT application you'll need to run:
/<program> -qws
If you're running the application on the development board you'll also need to copy the
font-files for QT onto the board (not all fonts are needed). These can be found in the
<qt_configure_prefix>/lib/fonts/ directory. As a minimum you need fontdir
and a font file. The file location on the development board should be the same as on
the host system.
The “qws” option, makes the program act as a server (meaning there's no other QT
applications currently running that it can attach itself to).
3.8 Getting support
You can get support at http://www.ipthinking.dk or more generic uClinux support at
http://blackfin.uclinux.org and http://uclinux.org.
Updated software is regularly released. This will be released on our website.
The blackfin uClinux project contains a lot of good guides and a great support forum. If
you get stuck it's a very good idea to check out: http://docs.blackfin.uclinux.org.
66
67
3.9 Troubleshooting
This section contains a brief list of potential problems, and their possible solutions. The
FAQ on our website contains a more exhaustive list and is updated regularly when new
questions arise.
Table 3.4: Troubleshooting table
Problem
Possible solutions
Nothing is displayed
in the terminal when
power is applied.
When power is applied to the board, the D1 diode (Power led) should
light up.
If D1 does not light up, check the power connection.
If D1 does light up, check your cable connection and terminal settings
(see relevant section in this document), and check the status leds on
the network interface. If the bootloader is running, without printing
anything, your should see some activity on these (if ethernet is enabled
in the bootloader - default is enabled).
If the board seems dead (bricked), it might still be possible to resurrect
it by changing the boot mode to UART.
Note: This requires a minor hardware modification. (Chapter 2, Figure
2.2 on page 32.)
“Garbage” characters
are displayed in the
terminal when power
is applied.
Wrong terminal settings. Check your settings (see relevant section in
this document at chapter 2, Table 3.1 on page 36).
When testing my
The application is compiled for a different architecture. Recompile the
uClinux application on program using the correct compiler (see relevant section in this
my host machine, I get document at chapter 3.7.1.1 on page 47).
the error:
cannot execute binary
file
When running my
The application is compiled for a different architecture. Recompile the
uClinux application on program using the correct compiler (typically bfin-linux-uclibc-gcc)
the development
(see relevant section in this document at chapter 3.7.1.1 on page 47).
board, I get the error:
DEL
ELF♦♦♦: not found
The terminal output
stops after “Starting
Kernel at =
XXXXXX”.
Make sure the kernel is correctly configured.
If only the console out is missing, but the kernel is running, make sure
you've selected UART1 in the kernel configuration.
68
3.10 Abbreviations
Blackfin
The microprocessor name. Visit http://www.analogdevices.com/en/embeddedprocessing-dsp/blackfin/processors/index.html for more details.
Brick(ing)
The term “brick” is commonly used when a device ceases to function, and
afterwards is as useful as a brick.
coLinux
Cooperative Linux. A linux distribution that runs under Microsoft Windows.
See http://www.colinux.org for more details.
das u-boot
A universal bootloader, used to boot the linux kernel.
See http://sourceforge.net/projects/u-boot/ for details.
DirectFB
Graphical framework. See http://www.directfb.org for details.
eeprom
Electrically Erasable Programmable Read-Only Memory.
Non-volatile storage media for small amounts of data.
FAQ
Frequently asked questions (list). The typical and most common problem are
explained and answered here.
gLibc
The gnu C library implementation.
GUI
Graphical User Interface.
JTAG
Joint Test Action Group. A standardized connector for debugging and testing.
kermit
A computer file transfer/management protocol for serial transfers.
mmu
memory mapping unit. On system that does not have this, the memory management
capabilities are limited. See uClinux kernel documentation (nommu-mmap.txt).
nand
A type of flash memory. A non-volatile storage medium for data.
nano-X
(microwindows)
The Nano-X Window System, that attempts on bring some of the features of X11 to
the embedded world. See http://www.microwindows.org for details.
Samba (smb)
File and print services access to Microsoft Windows networks from unix/linux.
See http://www.samba.org for details.
SDL
Simple DirectMedia Layer. Graphical framework.
See http://www.libsdl.org for details.
TFTP
Trivial File Transfer Protocol. Similar to FTP, but only implements the basic
functionality.
UART
Universal asynchronous receiver/transmitter. Also known as a serial port.
uClibc
The uClinux C library implementation.
uClinux
The linux distribution used on the development board.
Visual DSP
Analog Devices development suite.
See http://www.analog.com/en/embedded-processing-dsp/blackfin/VDSP-BF-SHTS/products/product.html for more details.
ymodem
A protocol for file transfer used between modems (serial transfer)
QT
A cross-platform GUI application framework for desktop and embedded
development.
69
70
Chapter 4: Mechanical Layout
Chapter 4
Mechanical Layout
40.6 mm
17 mm
46 mm
97 mm
118 mm
23.85mm
Mechanical drawing
3.65 mm
5,32 mm
45.98 mm
78.6 mm
19.36 mm
153 mm
Figure 4.1: Mechanical Layout Top side
71
Silkscreen drawings
Figure 4.2:Silkscreen Top Layer
Figure 4.3:Silkscreen Bottom Layer
72
73
Chapter 5: Bill of Materials
Chapter 5
Bill of Materials
Ref. Qty. Description
Reference
Manufacturer
Part Number
C1,C2,C111
PHYCOMP
C0603JRNP09BN180
CAP,CER,100NF,16V,
C3-30,C32-46,
YAGEO
C0402KRX7R7BB104
+-10%,X7R,CC0402
C60,C61,C65,
C20
AVX
PKTA 06036
CAP,TAN,10UF,6V3,
C31,C59,C62-64,
KEMET
T491A106K006AT
+-10%,85,CT3216-18
C75,C76,C83,C85,
C47
TDK
C1005X7R1E223KT-S
CAP,CER,10NF,16V,
C48-51,C53-C55,
AVX
0402YC103KAT2A
+-10%,X7R,CC0402
C77-80,C86,C132,
C67,C68,C69,C70
EPCOS
B37931-K5821-K 60
C84
SAMSUNG
CL10B224K08NNNC
C88,C89,C92,C93
SAMSUNG
CL10B271JB8NNNC
CAP,CER,470PF,50V,
C90,C96,C97,C138-
KEMET
PC0603C471J5GAC7867
+-5%,NP0,CC0603
140,C143
CAP,CER,220NF,16V,
C91
SAMSUNG
CL10B224K08NNNC
CAP,TAN,10UF,6V3,
C98,C103,C136,
KEMET
T491A106K006AT
+-10%,85,CT3216-18
C137, C144,C148,
Designator
1
3
CAP,CER,18PF,50V,
+-5%,NP0,CC0603
2
70
C66,C71-74,C81,
C82,C87,C99-102,
C108,C115,C122125,C145,C146,
C152,C155,C156,
C158,C159
3
1
CAP,TAN,68UF,16.V,
+-10%,X7R,CT6032-28
4
14
C94,C95,C130,
C133, C135
5
1
CAP,CER,22NF,25V,
+-10%,X7R,CC0402
6
14
C134
7
4
CAP,CER,820PF,50V,
+-10%,X7R,CC0603
8
1
CAP,CER,220NF,16V,
+-10,X7R,CC0603
9
4
CAP,CER,270PF,50V,
+-5%,X7R,CC0603
10
11
7
1
+-10,X7R,CC0603
12
7
C149
74
13
4
Reference
Designator
C104-107
Manufacturer
Part Number
SAMSUNG
CL10C470JB8NNNC
C110
PHYCOMP
C0603JRNP09BN561
C112,C116
PHYCOMP
C0603KRX7R9BB102
C113,C114,C120
EPCOS
PB45196H5106M309
CAP,TAN,100UF,10V,
C117,C121,C141,
VISHAY
293D107X9010D2TE3
+-10%,MAX85,CT7343-31
C142,C147
CAP,CER,680PF,50V,
C118
PHYCOMP
C0603KRX7R9BB681
C119,C126-129
PHYCOMP
C0603JRNP09BN220
CAP,CER,47PF,50V,
+-5%,COG,CC0603
14
1
CAP,CER,560PF,50V,
+-5%,NP0,CC0603
15
2
CAP,CER,1NF,50V,
+-10,X7R,CC0603
16
3
CAP,TAN,10UF,16V,
+-20%,NP0,CT6032-28
17
18
5
1
10%,X7R,CC0603
19
5
CAP,CER,22PF,50V,
+-5%,NP0,CC0603
20
3
LED, RED
D1,D11,D12
VISHAY
TLMS1000-GS08
21
1
DIO,SCH,VR=40V,
D2
ZETEX
ZHCS1000
D4,D5,D6,D7
LITTELFUSE
PGB0010603MR
D8,D9,D10
ON
MBRS540T3G
IF=1A,VF=0.425V,
PTOT=0,5W,TSTG=-55
TO + 150,SOT-23
22
4
DIO,ESD,TV=1000V,
CV=150V,RV=24VDC
CAP=0.0055PF,
RT=<1NS,LC=1NA,
D0603
23
3
DIO,SCH,VR=40V,
IF=5A,VF=0.5V,
SEMICONDUCTOR
TSTG=-55 TO + 150,
SMC
24
1
FUSE,POLYSWITCH,
F1
TYCO
VO=15V,CH=2.5A,
ELECTRONICS
CT=5V,-40°CTO85°C
RAYCHEM
SMD250F-2
25
1
CON,30PIN,FEMALE
J1
SAMTEC
SFC-130-T2-F-D-A
26
1
CON,RJ45,ETHERNET
J2
PULSEJACK
J3011G21DNL
J4
HIROSE
DF9-31S-1V_W(31)
CONNECTOR WITH
TRAFO AND LED'S G/Y
27
1
CON,HEADER31,
BOARD TO BOARD
CONECTOR
75
28
1
CON,HEADER,
Reference
Designator
J5
Manufacturer
Part Number
MOLEX
532610871
J8
TYCO
84953-4
SMTR/A, 8WAY,
BOARD TO CABEL
29
1
CON,FPC SMT,
1.0MM,4WAY
30
1
ELECTRONICS
CON,JACK,
J11
MOLEX
855025005
J12,J13,J17,J18
SHALLIN
K36406
J14
TAITEX
USB RSI-04SW12R
J15
FCI
87583-2010BLF
SMT,R/A,4/4
31
4
CON,3.5MM,
AUDIO_JACK_ST.
32
1
CON,USB,SLAVE,
TYPE_B
33
1
CON,USB,HOST,
TYPE_A
34
1
CON,2.5MM
J16
SWITCHCRAFT
RASM722X
35
1
CON,DSUB,
J19
SHALLIN
YFR09S
DB9 FEMALE
ELECTRONICS
RIGHT ANGLE
36
1
CON,2X7 PINS
J20
SAMTEC
TSM-107-01-L-DV
J22
MOLEX
533980271
J23
SAMTEC
TLE-110-01-G-DV-A
J26
YAMAICHI
ELECTRONICS
FPS009-2405-0
J27
SAMTEC
TSM-110-01-L-DV
J28
MOLEX
901200762
LS1
MOLEX
533980271
L1
EPCOS
B82472G4103M
HEADER,SMT
37
1
CON,HEADER,
SMT VERT,2WAY,
BOARD_TO_WIRE
38
1
SOCKET STRIP
CENTERLINE 2MM
(.0787") ROW 2 X PIN 10
39
1
CON,9 SKT,MMC-SD,
READER
40
1
CON,2X10PINS
HEADER,SMT
41
1
CON,2 PINS,
THROUGH-HOLD,
JUMPER OPTION
42
1
CON,HEADER,
SMT VERT,2WAY,
BOARD_TO_WIRE
43
1
IND,POW,10UH,
FL=100KHZ,
TOL.=20%,
IR=1,34,
RMAX=0,08
76
44
15
EMI,FILTER,
Reference
Designator
L2-5,L7-10,
Z=600OHM,
L13-19
Manufacturer
Part Number
MURATA
BLM18AG601SN1D
RC=200MA,
RDC_MAX.=0.5OHM
45
1
IND,4U7H,DO1813H
L11
COILCRAFT
DO1813H-472MLD
46
1
IND,3U8H,MSS1038
L12
COILCRAFT
MSS1038-382NLC
47
1
P-CHANNEL 2.5V
Q1
FAIRCHILD
FDS9431A
SEMICONDUCTOR
Q4,Q5
VISHAY
SI5435BDC-T1-E3
RN1,RN2,RN3
PHYCOMP
TC164-JR-0710K
RES,MF,4K7,0.10W,
R1,R4,R37,R40,
VISHAY
CRCW06031004K71%
1%,R0603
R100,R110,R120-
R2
YAGEO
RC0603JR-0710M
RES,MF,10K,0.10W,
R3,R5,R6,R13,R15
VISHAY
CRCW060310010K1%
1%,R0603
-17,R34,R36,R38,
VISHAY
CRCW060310010K1%
ASJ
CCR16-330-JL
YAGEO
RC0603JR-070R
VISHAY
CRCW040210022R1%
SPECIFIED MOSFET
48
2
P-CHANNEL 30-V
(D-S) MOSFET
49
3
RNET,10K,1/16W,
±5%,4X0603
50
13
122,R138,R139,
R206,R207
51
1
RES,MF,10M,1/10W,
5%,R0603
52
25
R39,R47,R76,R77,
R91,R96,R125,R128,
R145-147,R158,
R159, R160,R161
52
25
RES,MF,10K,0.10W,
1%,R0603
53
6
RES,MF,33R,1/10W,
R3,R5,R6,R13,
R15-17,R34,R36,
R38,R39,R47,
R76,R77,R91,
R96, R125,R128,
R145-147,R158,
R159, R160,R161
R8,R59,R82,R83,
5%,R0603
R84,R86
RES,MF,0R,I=1A,
R9,R12,R14,R68,
5%,RC0603
R80,R109,R111,
54
16
R112,R132,R140144,R156,R157
55
56
21
1
RES,TF,22R,0.063W,
R18-33,R63-65,
1%,R0402
R92,R93
RES,MF,2K2,1/10W,
R35
YAGEO
RC0603FR-072K2
R42,R57
YAGEO
RC0603FR-07330R
1%,R0603
57
2
RES,MF,330R,1/10W,
1%,R0603
77
58
59
4
1
RES,TF,49R9,0.063W,
Reference
Designator
R43,R44,R105,
Manufacturer
Part Number
YAGEO
RC0402FR-0749R9
1%,R0402
R118
RES,TF,10R,0.063W,
R45
YAGEO
RC0402-JR-0710RL
R49,R60
YAGEO
RC0402FR-0712K4L
R53-56,R58
YAGEO
RC0603FR-07100K
RES,MF,10R,1/10W,
R71-75,R148-155,
YAGEO
RC0603JR-0710R
5%,R0603
R200-205
RES,TF,2K21,0.10W,
R85
VISHAY
CRCW06031002K211
RES,MF,1K,1/10W,
R87,R88,R123,
YAGEO
RC0603JR-071K
5%,R0603
R124
RES,MF,47K,1/10W,
R89,R90
YAGEO
RC0603JR-0747K
R97,R98
YAGEO
RC0603FR-0715K
R99,R126
VISHAY
CRCW060345K3FKEA
R101,R106
YAGEO
RL1206FR-07R022
R102,R107
YAGEO
RC0603FR-0780K6
R103
YAGEO
RC0603FR-07422K
R104
YAGEO
RC0603FR-0735K7L
R108
YAGEO
RC0603FR-07255K
R114,R117
YAGEO
RC0603JR-071M
R115,R116
YAGEO
RC0805FR-07100R
RES,TF,100R,0.063W,
R129-131,
BOURNS
CR0402-FX-1000GLF
1%,R0402
R133-136
SMD,MICRO SWITCH,
SW1
DIPTRONICS
DTSM-62R
SW2
C&K
OS102011MS2QN1
1%,R0402
60
2
RES,TF,12K4,0.063W,
1%,R0402
61
5
RES,MF,100K,1/10W,
1%,R0603
62
63
19
1
1%,R0603
64
65
4
2
5%,R0603
66
2
RES,MF,15K,1/10W,
1%,R0603
67
2
RES,TF,45K3,0.10W,
1%,R0603
68
2
RES,TF,R022,1/4W,
1%,R1206
69
2
RES,MF,80K6,1/10W,
1%,R0603
70
1
RES,MF,422K,1/10W,
1%,R0603
71
1
RES,MF,35K7,1/10W,
1%,R0603
72
1
RES,MF,255K,1/10W,
1%,R0603
73
2
RES,MF,1M,1/10W,
5%,R0603
74
2
RES,MF,100R,1/8W,
1%,R0805
75
76
7
1
TACT RED 6X6X5
77
1
SLIDE SWITCH,SLIDE
SPDT, DC_MAX=0.2A
78
78
2
SMD,EMC,CM_IMP
AT 100MHZ = 90OHM
ｱ25%,RC=370MA,
Reference
Designator
TR1,TR2
Manufacturer
Part Number
MURATA
DLW31SN900SQ2L
TR3
MURATA
DLW5BSN191SQ2L
U1
ANALOG
ADSPBF537KBCZ6AVX
RV=50VDC,1206
79
1
SMD,EMC,CM_IMP
AT 100MHZ = 190OHM
(TYP.),RC=5000MA,
RV=50VDC,2020
80
81
82
1
1
2
IC, ADSP-BF537 BBC7-5A
V1.0.3
DEVICES
IC, VOLTAGE MONITORING U2
MICROPROCESSOR
SUPERVISORY CIRCUIT
ANALOG
DEVICES
IC,SDRAM,512MBIT,133MHZ U3,U4
ST
ADM708SARZ
MT48LC64M8A2P-75:C
MICRO
ELECTRONICS
83
1
IC,NAND FLASH MEMORY
2.7-3.6V 1G (128MX8)
U5
ST
NAND01GW3B2BN6
MICRO
ELECTRONICS
84
1
85
1
86
1
87
1
88
1
89
2
90
1
91
1
92
1
93
1
94
1
95
1
IC,16-MBIT,LOW VOLTAGE,
SERIAL FLASH MEMORY
WITH 40 MHZ OR 50 MHZ
SPI BUS INTERFACE
IC, AD7877 TOUCH SCREEN
CONTROLLER
IC,AD1981BL LOW
VOLTAGE AC'97
SOUNDMAX CODEC
IC,SL811HS,EMBEDDED
USB HOST/SLAVE
CONTROLLER
IC,ADG787 2.5 Ω CMOS
LOW POWER DUAL 2:1
MUX/DEMUX USB 1.1
SWITCH
IC,ADP1864 CONSTANT
FREQUENCY CURRENTMODE STEP-DOWN DC-TODC CONTROLLER IN TSOT
3.3V, RS232 DRIVER, 1
RECIEVER
IC,ETHERNET PHY
NETWORKING
LOW DISTORTION, 1.5 W
AUDIO POWER AMPLIFIER
REMOTE 16-BIT I/O
EXPANDER FOR I2C-BUS
CRYSTAL 32.7680KHZ,
85SMX 20/-/-/12.5 FUND TR /
A103F
SG8002CA - 25.000MHZ
U6
ST
M25P16-VMN6 P
U9A
ANALOG
DEVICES
ANALOG
DEVICES
AD7877ACPZ-REEL7
U11
CYPRESS
SL811HST-AXC
U12
ANALOG
DEVICES
ADG787BRMZ
U13,U14
ANALOG
DEVICES
ADP1864AUJZ-R7
U15
ANALOG
DEVICES
SMSC
ANAADM3101EACPZ250R7
LAN8700-AEZG
SSM2211SZ
U18
ANALOG
DEVICES
NXP
Y1
EPSON
MC-156-32.7680KA-A0
Y2
EPSON
SG-8002CA-PCCND(25.00M)
U10
U16
U17
AD1981BLJSTZ
PCF8575TS
79
96
1
12.000MHZ - ACT531SMX-4
Reference
Designator
Y6
Manufacturer
Part Number
ADVANCED
QA1200EFGROFL-PF
CRYSTAL
TECHNOLOGY
97
1
24.576MHZ - ACT531SMX-4
Y7
ADVANCED
CRYSTAL
TECHNOLOGY
80
QA2457IFGROFL-PF
81
82
Chapter 6
IPT-Shark537
Development Board
Schematic Diagrams
Schematic Diagrams
Chapter 6: Schematic Diagrams
83
84
85
86
87
88
89
90
91

IPT-Shark537 Development Kit Manual

Transcription

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