ECM-5710 1st manual.DOC

Transcription

User's Manual
EBC5710/5710V
All-in-One FC- 478 Pentium IV/Celeron Single
Board with LCD, LVDS (EBC5710V), AC97
Audio, 1394, Dual 10/100Base-Tx Ethernet
Interfaces, & 4COMs
1st Ed – 23 May 2003
Part No.
User's Manual
FCC STATEMENT
THIS DEVICE COMPLIES WITH PART 15 FCC RULES. OPERATION IS SUBJECT TO
THE FOLLOWING TWO CONDITIONS:
(1) THIS DEVICE MAY NOT CAUSE HARMFUL INTERFERENCE.
(2) THIS DEVICE MUST ACCEPT ANY INTERFERENCE
RECEIVED INCLUDING
OPERATION.
INTERFERENCE
THAT
MAY
CAUSE
UNDESIRED
THIS EQUIPMENT HAS BEEN TESTED AND FOUND TO COMPLY WITH THE LIMITS
FOR A CLASS "A" DIGITAL DEVICE, PURSUANT TO PART 15 OF THE FCC RULES.
THESE LIMITS ARE DESIGNED TO PROVIDE REASONABLE PROTECTION AGAINTST
HARMFUL INTERFERENCE WHEN THE EQUIPMENT IS OPERATED IN A
COMMERCIAL ENVIRONMENT. THIS EQUIPMENT GENERATES, USES, AND CAN
RADIATE RADIO FREQUENCY ENERGY AND, IF NOT INSTATLLED AND USED IN
ACCORDANCE WITH THE INSTRUCTION MANUAL, MAY CAUSE HARMFUL
INTERFERENCE TO RADIO COMMUNICATIONS.
OPERATION OF THIS EQUIPMENT IN A RESIDENTIAL AREA IS LIKELY TO CAUSE
HARMFUL INTERFERENCE IN WHICH CASE THE USER WILL BE REQUIRED TO
CORRECT THE INTERFERENCE AT HIS OWN EXPENSE.
2 BCM Advanced Research.
User's Manual
Notice:
This guide is designed for experienced users to setup the system within the shortest time.
For detailed information, please always refer to the electronic user's manual.
Copyright Notice
Copyright  2003, BCM Advanced Research, ALL RIGHTS RESERVED.
No part of this document may be reproduced, copied, translated, or transmitted in any form
or by any means, electronic or mechanical, for any purpose, without the prior written
permission of the original manufacturer.
Trademark Acknowledgement
Brand and product names are trademarks or registered trademarks of their respective
owners.
Disclaimer
BCM Advanced Research reserves the right to make changes, without notice, to any
product, including circuits and/or software described or contained in this manual in order to
improve design and/or performance. BCM assumes no responsibility or liability for the use
of the described product(s), conveys no license or title under any patent, copyright, or mask
work rights to these products, and makes no representations or warranties that these
products are free from patent, copyright, or mask work right infringement, unless otherwise
specified. Applications that are described in this manual are for illustration purposes only.
BCM Advanced Research makes no representation or warranty that such application will
be suitable for the specified use without further testing or modification.
BCM Advanced Research 3
User's Manual
Life Support Policy
BCM’s PRODUCTS ARE NOT FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE PRIOR WRITTEN APPROVAL OF
BCM Advanced Research
As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for
surgical implant into body, or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to
perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
A Message to the Customer
BCM Customer Services
Each and every BCM ’s product is built to the most exacting specifications to ensure
reliable performance in the harsh and demanding conditions typical of industrial
environments. Whether your new BCM device is destined for the laboratory or the factory
floor, you can be assured that your product will provide the reliability and ease of operation
for which the name BCM has come to be known.
Your satisfaction is our primary concern. Here is a guide to BCM ’s customer services. To
ensure you get the full benefit of our services, please follow the instructions below carefully.
4 BCM Advanced Research
User's Manual
Technical Support
We want you to get the maximum performance from your products. So if you run into
technical difficulties, we are here to help. For the most frequently asked questions, you can
easily find answers in your product documentation. These answers are normally a lot more
detailed than the ones we can give over the phone. So please consult the user’s manual
first.
To receive the latest version of the user’s manual, please visit our Web site at:
http://www.bcmcom.com/
If you still cannot find the answer, gather all the information or questions that apply to your
problem, and with the product close at hand, call your dealer. Our dealers are well trained
and ready to give you the support you need to get the most from your BCM ’s products. In
fact, most problems reported are minor and are able to be easily solved over the phone.
In addition, free technical support is available from BCM ’s engineers every business day.
We are always ready to give advice on application requirements or specific information on
the installation and operation of any of our products. Please do not hesitate to call or e-mail
us.
BCM Advanced Research
1Hughes,
Irvine, CA, 92618
U.S.A
Tel : 949-470-1888
Fax : 949-470-0971
http://www.bcmcom.com
E-mail: [email protected]
BCM Advanced Research. 5
User's Manual
Product Warranty
BCM warrants to you, the original purchaser, that each of its products will be free from
defects in materials and workmanship for one year from the date of purchase.
This warranty does not apply to any products which have been repaired or altered by
persons other than repair personnel authorized by BCM, or which have been subject to
misuse, abuse, accident or improper installation. BCM assumes no liability under the terms
of this warranty as a consequence of such events. Because of BCM ’s high quality-control
standards and rigorous testing, most of our customers never need to use our repair service.
If any of BCM ’s products is defective, it will be repaired or replaced at no charge during the
warranty period. For out-of-warranty repairs, you will be billed according to the cost of
replacement materials, service time, and freight. Please consult your dealer for more
details. If you think you have a defective product, follow these steps:
1. Collect all the information about the problem encountered. (For example, CPU type and
speed, BCM ’s products model name, hardware & BIOS revision number, other
hardware and software used, etc.) Note anything abnormal and list any on-screen
messages you get when the problem occurs.
2. Call your dealer and describe the problem. Please have your manual, product, and any
helpful information available.
3. If your product is diagnosed as defective, obtain an RMA (return material authorization)
number from your dealer. This allows us to process your good return more quickly.
4. Carefully pack the defective product, a complete Repair and Replacement Order Card
and a photocopy proof of purchase date (such as your sales receipt) in a shippable
container. A product returned without proof of the purchase date is not eligible for
warranty service.
5. Write the RMA number visibly on the outside of the package and ship it prepaid to your
dealer.
6 BCM Advanced Research.
User's Manual
Packing List
Before you begin installing your single board, please make sure that the following materials
have been shipped:
• 1 EBC5710/5710V All-in-One FC-478 Pentium IV/Celeron Computing Module
• 1 Quick Installation Guide
• 1 CD-ROM contains the followings:
— User’s Manual (this manual in PDF file)
— Ethernet driver and utilities
— VGA drivers and utilities
— Audio drivers and utilities
— Latest BIOS (as of the CD-ROM was made)
If any of these items are missing or damaged, please contact your distributor or sales
representative immediately.
1.
1.1
Safety Precautions
Warning!
Always completely disconnect the power cord from your chassis whenever
you work with the hardware. Do not make connections while the power is on.
Sensitive electronic components can be damaged by sudden power surges.
Only experienced electronics personnel should open the PC chassis.
1.2
Caution!
Always ground yourself to remove any static charge before touching the CPU
card. Modern electronic devices are very sensitive to static electric charges.
As a safety precaution, use a grounding wrist strap at all times. Place all
electronic components in a static-dissipative surface or static-shielded bag
when they are not in the chassis.
BCM Advanced Research. 7
User’s Manual
Packing List
Before you begin installing your single board, please make sure that the following materials
have been shipped:
n
1 EBC-5710/5710V All-in-One FC- 478 Pentium IV/Celeron Computing Module
n
1 Quick Installation Guide
n
1 ATX-AT Power connector converter cable
n
1 CD-ROM contains the followings:
—
User’s Manual (this manual in PDF file)
—
VGA drivers and utilities
—
Audio drivers and utilities
—
LAN drivers and utilities
—
Latest BIOS (as of the CD-ROM was made)
If any of these items are missing or damaged, please contact your distributor or sales
representative immediately.
BCM Advanced Research.
EBM-5710/5710V
1.
MANUAL OBJECTIVES......................................................................................12
1.
INTRODUCTION................................................................................................13
1.1
System Overview ...........................................................................................13
1.2
System Specifications....................................................................................14
1.3
Architecture Overview....................................................................................17
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.3.9
1.3.10
1.3.11
1.3.12
1.3.13
2.
SiS651 IGUI Host Memory Controller ............................................................................. 18
SiS962 MuTIOL Media I/O.............................................................................................. 19
PCI Bus........................................................................................................................... 20
DDR SDRAM Interface ................................................................................................... 20
TFT Panel Interface........................................................................................................ 21
Audio............................................................................................................................... 21
IDE Interface ................................................................................................................... 21
USB 2.0 .......................................................................................................................... 21
IEEE1394A Host Controller ............................................................................................ 21
Realtek RTL8139C Ethernet Controller.......................................................................... 22
Intel 82559ER Ethernet Controller (Optional) ................................................................. 22
Winbond W83697UF ...................................................................................................... 23
Compact Flash Interface................................................................................................. 23
HARDWARE CONFIGURATION..........................................................................24
2.1
ATX Power Connection ..................................................................................24
2.2
Installation Procedure ....................................................................................25
2.3
Safety Precautions.........................................................................................25
2.3.1
2.3.2
2.4
Warning! ......................................................................................................................... 25
Caution! .......................................................................................................................... 25
Intel FC-478 Pentium 4 Processor ..................................................................26
2.4.1
2.4.2
Installing Intel Pentium 4 CPU ........................................................................................ 26
Removing CPU ............................................................................................................... 26
2.5
Main Memory .................................................................................................26
2.6
Jumper & Connector......................................................................................27
2.6.1
2.6.2
2.7
Jumper & Connector Layout ........................................................................................... 27
Jumper & Connector List ................................................................................................ 28
Setting Jumpers.............................................................................................30
2.7.1
2.7.2
2.7.3
2.7.4
COM2 RS-232/422/485 Select (J2, J3) .......................................................................... 31
COM3 / 4 Pin 9 Signal Select (J4, J5) ............................................................................ 31
Clear CMOS (J6) ............................................................................................................ 32
LVDS Power Signal Select (J7) ...................................................................................... 32
BCM Advanced Reseaarch.
User’s Manual
2.8
Connector Definitions ....................................................................................33
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
2.8.10
2.8.11
2.8.12
2.8.13
2.8.14
2.8.15
2.8.16
2.8.17
2.8.18
2.8.19
2.8.20
2.8.21
2.8.22
2.8.23
2.8.24
2.8.25
2.8.26
2.8.27
2.8.28
2.8.29
2.8.30
2.8.31
2.8.32
2.8.33
2.8.34
2.8.35
2.8.36
2.8.37
2.8.38
2.8.39
2.8.40
2.8.41
2.8.42
3.
TFT Panel Connector (CN2) .......................................................................................... 33
Signal Description – TFT Panel Connector (CN2) ......................................................... 33
Signal Configuration –TFT Panel Connector (CN2)....................................................... 34
CPU Fan Connector (CN3)............................................................................................. 34
Signal Description – CPU Fan Connector (CN3)............................................................ 34
ATX PSON Connector (CN4) ......................................................................................... 35
Audio / TV Output Connector (CN5) ............................................................................... 35
Signal Description – Audio / TV Output Connector (CN5) .............................................. 35
Floppy Disk Connector (FLP1) ....................................................................................... 36
Signal Description – Floppy Disk Connector (FLP1) ...................................................... 36
Pin Header Serial Port 1 / 2 / 3 / 4 Connector in RS-232 Mode (CN7)........................... 37
Serial Port 1 / 2 / 3 / 4 with External DB9 Connector (CN7) ........................................... 37
Signal Description – Serial Port 1 / 2 / 3 / 4 Connector in RS-232 Mode (CN7)............. 38
Pin Header Serial Port 2 Connector in RS-422 Mode (CN7 / Pin 11~20) ...................... 38
Signal Description – Serial Port 2 in RS-422 Mode (CN7 / Pin 11~20).......................... 38
Pin Header Serial Port 2 Connector in RS-485 Mode (CN7 / Pin 11~20) ...................... 39
Signal Description – Serial Port 2 in RS-485 Mode (CN7 / Pin 11~20).......................... 39
CD-ROM Audio Input Connector (CN8).......................................................................... 40
Signal Description – CD-ROM Input Connector (CN8)................................................... 40
Keyboard and PS/2 Mouse Connector (CN9) ................................................................ 40
Signal Description – Keyboard / Mouse Connector (CN9) ............................................. 40
Front Panel Connector (CN10)....................................................................................... 41
Signal Description – Front Panel Connector (CN10)...................................................... 41
Primary IDE Device Connector (CN11) .......................................................................... 41
Secondary IDE Connector (CN12) ................................................................................. 42
Signal Description - Primary & Secondary IDE Device Connector (CN11 & CN12) ....... 43
IEEE1394 Connector (I1, I2) ........................................................................................... 46
Signal Description – IEEE1394 Connector (I1, I2).......................................................... 46
IrDA Connector (IR1) ...................................................................................................... 47
Signal Description – IR Connector (IR1)......................................................................... 47
LCD Inverter Connector (J1)........................................................................................... 47
Signal Description – LCD Inverter Connector (J1).......................................................... 47
Ethernet LED Connector (LNLED1) ............................................................................... 48
Signal Description – Ethernet LED Connector (LNLED1) .............................................. 48
LVDS Connector (LVDS1, EBC-5710V only) ................................................................. 48
Signal Description – LVDS Connector (LVDS1, EBC-5710V only) ................................ 48
USB Connector (USB1).................................................................................................. 49
Signal Description – USB Connector (USB1)................................................................. 49
CRT Connector (VGA1).................................................................................................. 49
Signal Description – CRT Connector (VGA1)................................................................. 49
STN LCD Contrast Adjustment Connector (VR1) ........................................................... 50
LCD Backlight Brightness Adjustment Connector (VR2) ................................................ 50
AWARD BIOS SETUP ........................................................................................51
3.1
Starting Setup................................................................................................51
3.2
Using Setup ...................................................................................................52
3.3
Getting Help...................................................................................................52
EBC-5710/5710V
3.4
In Case of Problems .......................................................................................52
3.5
Main Menu .....................................................................................................53
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.5.13
4.
DRIVER INSTALLATION ....................................................................................77
4.1
Driver Installation for Display Adapter............................................................77
4.1.1
4.1.2
4.2
4.3
Windows 9x .................................................................................................................... 93
Windows 2000 Audio Installation .................................................................................... 99
Driver Installation for Ethernet Adapter........................................................107
4.3.1
4.3.2
4.4
Windows 9x .................................................................................................................... 77
Windows 2000 Display Installation ................................................................................. 85
Driver Installation for Audio Adapter ..............................................................93
4.2.1
4.2.2
5.
Setup Items..................................................................................................................... 53
Standard CMOS Setup................................................................................................... 55
Advanced BIOS Features ............................................................................................... 58
Advanced Chipset Features ........................................................................................... 61
Integrated Peripherals .................................................................................................... 63
Power Management Setup ............................................................................................. 67
PnP/PCI Configuration Setup ......................................................................................... 70
PC Health Status ............................................................................................................ 71
Frequency / Voltage Control ........................................................................................... 72
Load Fail-Safe Defaults .................................................................................................. 73
Load Optimized Defaults................................................................................................. 73
Set Password ................................................................................................................. 74
Exit Selecting .................................................................................................................. 75
Windows 9x .................................................................................................................. 107
Windows 2000 Ethernet Installation ............................................................................. 114
Driver Installation for SiS USB 2.0................................................................120
MEASUREMENT DRAWING .............................................................................121
User’s Manual
APPENDIX A: BIOS REVISIONS ...............................................................................122
APPENDIX B: SYSTEM RESOURCES.......................................................................123
Memory Map .............................................................................................................................. 123
I/O – Map ................................................................................................................................... 124
Interrupt Usage .......................................................................................................................... 126
DMA-channel Usage .................................................................................................................. 127
APPENDIX C: AWARD BIOS ERROR MESSAGE.......................................................128
Beep 128
BIOS ROM Checksum Error – System Halted ........................................................................... 128
CMOS Battery Failed ................................................................................................................. 128
CMOS Checksum Error – Defaults Loaded ............................................................................... 128
CPU at nnnn .............................................................................................................................. 128
Display Switch Is Set Incorrectly. ............................................................................................... 128
Press ESC to Skip Memory Test ............................................................................................... 128
Floppy Disk(s) Fail ..................................................................................................................... 129
Hard Disk(s) Initializing; Please Wait a Moment......................................................................... 129
Hard Disk(s) Install Failure......................................................................................................... 129
Hard Disk(s) Diagnosis Fail ....................................................................................................... 129
Keyboard Error or No Keyboard Present ................................................................................... 129
Keyboard Is Locked Out – Unlock The Key ............................................................................... 129
Memory Test .............................................................................................................................. 129
Memory Test Fail ....................................................................................................................... 129
Override Enabled – Defaults Loaded......................................................................................... 129
Press TAB to Show POST Screen ............................................................................................ 130
Primary Master Hard Disk Fail ................................................................................................... 130
Primary Slave Hard Disk Fail ..................................................................................................... 130
Resuming from Disk, Press TAB to Show POST Screen .......................................................... 130
Secondary Master Hard Disk Fail .............................................................................................. 130
Secondary Slave Hard Disk Fail ................................................................................................ 130
Proprietary Notice and Disclaimer.............................................................................................. 130
APPENDIX D: AWARD BIOS POST CODES..............................................................131
EBC-5710/5710V
Document Amendment History
Revision
Date
1st
May. 2003.
By
Stephen Tsao Initial Release
Comment
User’s Manual
1. Manual Objectives
This manual describes in detail of the BCM EBC-5710/5710V series Single Board.
We have tried to include as much information as possible but we have not duplicated
information that is provided in the standard IBM Technical References, unless it proved to
be necessary to aid in the understanding of this board.
We strongly recommend that you study this manual carefully before attempting to interface
with EBC -5710/5710V or change the standard configurations. Whilst all the necessary
information is available in this manual we would recommend that unless you are confident,
you contact your supplier for guidance.
Please be aware that it is possible to create configurations within the CMOS RAM that
make booting impossible. If this should happen, clear the CMOS settings, (see the
description of the Jumper Settings for details).
If you have any suggestions or find any errors concerning this manual and want to inform us
of these, please contact our Customer Service department with the relevant details.
EBC-5710/5710V
1.
1.1
Introduction
System Overview
The EBC-5710/5710V series is a compact 5.25” CD-ROM size Single Board Computer that
equips with SiS651 IGUI HMAC 3D Graphic DDR/SDR Chipset, LCD & TMDS Interfaces,
AGP 4X 3D Graphics, NTSC/PAL TV output, AC97 Audio, Dual 10/100Base-Tx Ethernet,
IEEE1394 interfaces, and USB2.0 interfaces.
The EBC-5710/5710V series is equipped with an Intel FC-478 Socket supports Intel P4
series processors with data transfer rate of 533MHz, powerful in performance. Its display
is bolstered up with the chipset SiS651 Integrated AGP4X graphics which supports 24-bit
flat panel and one channel LVDS with a programmable frame buffer size from 8MB to 64MB.
This makes this PC engine a perfect solution for Retail / Financial Transaction Terminals,
and high-end multimedia POS / KIOSK Terminals.
Furthermore, the EBC-5710/5710V series is outstanding in a 5.25" form factors designed
with dual PCI-bus Realtek 8139C 10/100Base-Tx Ethernet controllers. Making it the ideal
solution for popular networking devices like Gateway, Router, Thin Server, Firewall and EBox.
In addition, the on board IEEE1394, dual USB 2.0, and NTSC/PAL TV output interface
make the EBC-5710/5710V series also ideal for demanding high-end Entertainment
Devices that require high integration multimedia Single Board Computer.
Other impressive features include a built-in 40-pin TFT LCD interface, the AC97 Audio, a
Compact Flash socket for type I/ II Compact Flash storage card, four serial ports, one
parallel port, and one 184-pin DDR DIMM socket allowing for up to 512MB of DDR
333/266/200 SDRAM to be installed, and a PCI slot for future expansion.
EBC-5710/5710V User’s Manual 13
User’s Manual
1.2
System Specifications
General Functions
•
CPU: Supports Intel P4 series processors with data transfer rate of 533MHz
•
CPU socket: Intel FC-478
•
BIOS: Award 256KB Flash BIOS
•
Chipset: SiS651
•
I/O Chipset: SiS962 & Winbond W83697UF
•
Memory: Onboard one DDR SDRAM socket supports up to 512 Mbytes DDR
333/266/200 SDRAM.
•
Enhanced IDE: Supports up to four IDE devices. Supports Ultra DMA/133 mode
with data transfer rate up to 133MB/sec. (20 x 2 header x 2 onboard)
•
FDD Interface: Supports one floppy disk drive, 5.25" (360KB and 1.2MB) or 3.5"
(720KB, 1.44MB, and 2.88MB)
•
Parallel Port: Supports SPP, ECP, and EPP modes
•
Serial Port: Three RS-232 and one RS-232/422/485 serial port. Ports can be
configured as COM1, COM2, COM3, COM4, or disabled individually. (16C550
equivalent)
•
IR Interface: Supports IrDA
•
KB/Mouse Connector: 8-pin (4 x 2) connector supports PC/AT keyboard and PS/2
mouse
•
USB Connectors: Dual USB 2.0 ports onboard
•
Watchdog Timer: Can generate a system reset, IRQ15 or NMI. Software
selectable time-out interval (32 sec. ~ 254min., 1 min./step)
•
Hardware status monitoring: Monitoring system temperature, voltage, and cooling
fan status. Auto throttling control when CPU overheats
•
Power management: Supports ATX power supply. Supports PC97, LAN wake up
and modem ring-in functions. I/O peripheral devices support power saving and
doze/standby/suspend modes. APM 1.2 compliant
EBC-5710/5710V
IEEE1394 Interface
•
Chipset: SiS962 integrated PCI 1394A Host Controller + Realtek RTL8801
IEEE1394A PHY
•
IEEE1394 interface: Supports 2 x 400 Mbit IEEE1394A Ports
Flat Panel/CRT Interface
•
Chipset: SiS651 integrated AGP high performance 256-bit GUI, 3D engine
•
Display Memory: Programmable frame buffer size from 8Mbytes to 64MBytes
•
Display Type: Simultaneously supports CRT and TFT displays
•
Interface: Accelerator Graphics Ports 2.0 compliant
•
Display mode:
u
LCD panel supports up to 1280 x 1024 @ 32 bpp
u
CRT displays support up to 2048 x 1536 @ 32 bpp
TV Output Interface (EBC-5710V only)
•
•
Chipset: SiS301LV Video Bridge
TV output interface: Supports both NTSC and PAL systems
LVDS Interface
•
Chipset: SiS301LV Video Bridge
•
LVDS interface: Maximum pixel 110M pixels/sec with 110MHz pixel clock, 24–bit
one pixel per clock.
Audio Interface
•
Chipset: SiS962 integrated Audio controller with AC97 interface
•
AC97 Codec: AD1881
•
AC97 Interface: AC97 ver. 2.2 compliant interface. Supports Microphone in, Line in,
CD audio in, line out
Ethernet Interface
•
Chipset: Dual Realtek 8139C or Intel 82550/82559/82559ER PCI-bus Ethernet
controllers onboard
•
Ethernet Interface: PCI 100/10 Mbps, IEEE 802.3U compatible
•
Remote Boot-ROM: For diskless system
User’s Manual
SSD Interface
•
Compact Flash: One CF socket supports Type I / II Compact Flash Card
Expansion Interface
•
PCI Interface: One 32-bit PCI slot onboard
Mechanical and Environmental
•
Power Supply Voltage: ATX type, +5V and +12V
•
Operating Temperature: 32 to 140 °F (0 to 60 °C)
•
Board Size: 8”(L) x 5.75”(W) (203mm x 146mm)
•
Weight: 0.3 Kg
EBC-5710/5710V
1.3
Architecture Overview
The following block diagram shows the architecture and main components of EBC-5710/
5710V.
The two key components on board are the SiS651 IGUI HMAC and the SiS962 MuTIOL
media I/O chips. These two devices provide the PCI bus to which all the major components
are attached.
The following sections provide detail information about the functions provided onboard.
User’s Manual
1.3.1 SiS651 IGUI Host Memory Controller
SiS651 IGUI Host Memory Controller integrates a high performance host interface for Intel
Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance
memory controller, an AGP 4X interface, and SiS MuTIOL® Technology connecting w/
SiS962 MuTIOL® Media IO.
SiS651 Host Interface features the AGTL & AGTL+ compliant bus driver technology with
integrated on-die termination to support Intel Pentium 4 series processors with FSB
533/400MHz. SiS651 provides a 12-level In-Order-Queue to support maximum outstanding
transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video
Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the
Intel Pentium 4 series based PC systems. It also integrates a high performance 2.7GB/s
DDR333 Memory controller to sustain the bandwidth demand from the integrated GUI or
external AGP master, host processor, as well as the multi I/O masters.
In addition to integrated GUI, SiS651 also can support external AGP slot with AGP
1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature SiS
MuTIOL® technology is incorporated to connect SiS651 and SiS962 MuTIOL® Media I/O
together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Link
Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external
PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link
Encoder/Decoder in SiS962 to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded
I/O Link layer to/from SiS651, and the Multi-threaded I/O Link Encoder/Decoder in SiS651
to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
The memory controller can support both DDR and SDR. It can offer bandwidth up to
2.7GB/s under DDR333, 2GB/s under DDR266 and 1GB/s under PC 133 in order to sustain
the bandwidth demand from host processor, as well as the multi I/O masters and AGP
masters. Delivering a high performance data transfer to/from memory subsystem from/to
the Host processor, the integrated graphic engine or external AGP master, or the I/O bus
masters. The memory controller also supports the Suspend to RAM function by retaining
the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The
SiS651 adopts the Shared Memory Architecture, eliminating the need and thus the cost of
the frame buffer memory by organizing the frame buffer in the system memory. The frame
buffer size can be allocated from 8MB to 64MB.
The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture,
and a 128 bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video
Accelerator and advanced hardware acceleration logic to deliver high quality DVD playback.
A Dual 12 bit DDR digital video link interfaced to SiS301B Video Bridge packaged in 100pin PQFP is incorporated to expand the SiS651 functionality to support the secondary
display, in addition to the default primary CRT display. The SiS 301B Video Bridge
integrates an NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display,
a TMDS transmitter with Bi-linear scaling capability for TFT LCD panel support, and an
analog RGB port to support a secondary CRT. The primary CRT display and the extended
secondary display (TV, TFT LCD Panel, 2'nd CRT) features the Dual View
Capability in the sense that both can generate the display in independent resolutions, color
depths, and frame rates.
EBC-5710/5710V
Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the
width of 128 bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC
streaming. In PC133, DDR266 or DDR333 memory subsystem, the 128 bit GUI-t-MC bus
will attain the AGP4X, AGP 8X equivalent or higher texture transfer rate, respectively. The
Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues,
and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access
requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a
default optimized priority list with the capability of dynamically prioritizing the I/O bus master
requests in a bid to offering privileged service to 1) the isochronous downstream transfer to
guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb
the latency within the maximum tolerant period of 10us. Prior to the memory access
requests pushed into the M-data queue, any command compliant to the paging mechanism
is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further
orders and forwards these queuing requests to the Memory Interface in an effort to utilizing
the memory bandwidth to its utmost by scheduling the command requests in the
background when the data requests streamlines in the foreground.
1.3.2 SiS962 MuTIOL Media I/O
The SiS962 MuTIOL Media I/O integrates one Universal Serial Bus 2.0 Host Controllers,
the 1394a Controller, the Audio Controller with AC 97 Interface, the Ethernet MAC
Controller w/ standard MII interface, three Universal Serial Bus 1.1 Host Controllers, the
IDE Master/Slave controllers, and SiS MuTIOL technology. The PCI to LPC bridge, I/O
Advanced Programmable Interrupt Controller, legacy system I/O and legacy power
management functionalities are integrated as well.
The USB2.0 Host Controller includes one high-speed mode host controller and three
USB1.1 host controllers. The high-speed host controller implements an EHCI interface that
provides 480Mb/s bandwidth for six USB 2.0 ports. The three USB1.1 host controllers
implement an OHCI interface and each USB1.1 host controller provides 12Mb/s bandwidth
for two USB 1.1 ports. Each of six USB ports can be automatically routed to support a
High-speed USB 2.0 device or Full- or Low-speed USB 1.1 device. Besides, each port can
be optionally configured as the wake-up source. Legacy USB devices as well as over
current detection are also implemented.
The integrated 1394a function complies with 1394 Open Host Controller Interface
Specification 1.1, IEEE 1394- 1995 and IEEE 1394a-2000. The bus transfer rate of 100,
200, 400 Mbits/s is supported, and both Asynchronous and Isochronous data transfers are
supported as well. With external 1394 physical layer chip, it can support up to three 1394
ports to connect with 1394 devices.
The Integrated AC97 v2.2 compliance Audio Controller that features a 6-channels of audio
speaker out and HSP v.90 modem support. Additionally, the AC97 interface supports 4
separate SDATAIN pins that is capable of supporting multiple audio codecs with one
separate modem codec.
The integrated Fast Ethernet MAC Controller features an IEEE 802.3 and IEEE 802.3x
compliant MAC with external LAN physical layer chip supporting full duplex 10 Base-T, 100
Base-T Ethernet, or with external Home networking physical layer chip supporting 1Mb/s &
User’s Manual
10Mb/s Home networking. Additionally, 5 wake-up Frames, Magic Packet and link status
changed wake-up function in G1/G2 states are supported. For storing Mac address, two
schemes are provided: 1. Store in internal APC register or 2. Store in external EEPROM.
The integrated IDE Master/Slave controllers features Dual Independent IDE channels
supporting PIO mode 0,1,2,3,4, and Ultra DMA 33/66/100/133. It provides two separate
data paths for the dual IDE channels that sustain the high data transfer rate in the
multitasking environment.
SiS962 supports 6 PCI masters and complies with PCI 2.2 specification. It also
incorporates the legacy system I/O like: two 8237A compatible DMA controllers, three
8254 compatible programmable 16-bit counters, hardwired keyboard controller and PS2
mouse interface, Real Time clock with 512B CMOS SRAM and two 8259A compatible
Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial
and FSB interrupt delivery modes is supported.
The integrated power management module incorporates the ACPI 1.0b compliance
functions, the APM 1.2 compliance functions, and the PCI bus power management interface
spec. v1.1. Numerous power-up events and power down events are also supported. 21
general purposed I/O pins are provided to give an easy to use logic for specific application.
In addition, the SiS962 supports Deeper Sleep power state for Intel Mobile processor. For
AMD processor, the SiS962 use the CPUSTP# signal to reduce processor voltage during
C3 and S1 state.
A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS645DX
and SiS962 MuTIOL Media I/O together. SiS MuTIOL technology is developed into three
layers, the Multi-threaded I/O Channels Layer delivering 1.2GB bandwidth to connect
embedded DMA Master devices and external PCI masters to interface to
Multi-threaded I/O Channels layer, the Multi-threaded I/O Packet Layer in SiS962 to
transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Channels layer to/from
SiS645DX, and the Multi-threaded I/O Packet Layer in SiS645DX to transfer data w/ 533
MB/s from/to memory sub-system to/from the Multi-threaded I/O Packet Layer in SiS962.
1.3.3
PCI Bus
The PCI-bus on the board is provided by the SiS962 MuTIOL Media I/O chip and will
always run at 33MHz.
The SiS962 MuTIOL Media I/O chip provides support for up to six bus masters. These bus
master signals are used by the SiS962 MuTIOL Media I/O and other PCI-bus peripherals
on the board.
1.3.4
DDR SDRAM Interface
This module uses one DDR SDRAM socket onboard supports up to 512 Mbytes DDR
333/266/200 SDRAM.
EBC-5710/5710V
1.3.5
TFT Panel Interface
An alternative display to the standard CRT monitor is a digital flat panel interface in which
the color of each pixel is digitally encoded. The panel data may be transferred in parallel
where the color of each pixel is transferred over a number of signal lines at rates up to
65MHz.
The parallel interface is only suitable for short distance (less than 50 cm) and is typically
implemented by using of ribbon cables. One should be careful in the EMC design of the box
and cabling when this interface is used.
It should also be noted that the signal level of this interface is 3.3V, but does comply with
the TTL signal levels. Some - most older displays require 5V signal level.
1.3.6
Audio
The SiS962 MuTIOL Media I/O chip provides audio support through an AC97 codec
interface. The audio codec provides mixing of the analog signals as well as Digital/Analog
conversion.
1.3.7 IDE Interface
A primary as well as a secondary IDE controller is provided by the SiS962 MuTIOL Media
I/O chip which supports Ultra DMA 33/66/100/133 and PCI bus mastering for the data
transfer.
1.3.8 USB 2.0
the SiS962 MuTIOL Media I/O chip supports three Independent OHCI USB 1.1 Host
Controllers and One EHCI USB 2.0 Host Controller, can support up to six ports.
1.3.9
IEEE1394A Host Controller
The SiS962 MuTIOL Media I/O chip provides high performance serial connectivity. It
implements the Link and Phy layers for IEEE 1394-1995 High Performance Serial Bus and
1394a Draft 4.0. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support
for high performance data transfer via a 32-bit bus master PCI host bus interface.
The SiS962 supports 100, 200 and 400 Mbit/sec transmission via an integrated 3-port PHY.
The SiS962 services two types of data packets: asynchronous and isochronous (real time).
The 1394 link core performs arbitration requesting, packet generation and checking, and
bus cycle master operations. It also has root node capability and performs retry operations.
The SiS962 is ready to provide industry-standard IEEE 1394 peripheral connections for
desktop and mobile PC platforms. Support for the SiS962 is built into Microsoft Windows
98, Windows ME, and Windows 2000.
User’s Manual
1.3.10
Realtek RTL8139C Ethernet Controller
The Ethernet interfaces are based on two Realtek RTL8139C Ethernet controllers which
support both 100Mbit as well as 10Mbit Base-T interface.
The Ethernet controllers are attached to the PCI bus and use PCI bus mastering for data
transfer. The CPU is thereby not loaded during the actual data transfer.
The Realtek RTL8139C is a highly integrated and cost-effective single-chip Fast Ethernet
controller that provides 32-bit performance, PCI bus master capability, and full compliance
with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It
also supports Advanced Configuration Power management Interface (ACPI), PCI power
management for modern operating systems that is capable of Operating System Directed
Power Management (OSPM) to achieve the most efficient power management.
1.3.11
Intel 82559ER Ethernet Controller (Optional)
The 82559ER is part of Intel's second generation family of fully integrated 10BASET/100BASE-TX LAN solutions. The 82559ER consists of both the Media Access Controller
(MAC) and the physical layer (PHY) combined into a single component solution. 82559
family members build on the basic functionality of the 82558 and contain power
management enhancements.
The 82559ER is a 32-bit PCI controller that features enhanced scatter-gather bus
mastering capabilities which enables the 82559ER to perform high-speed data transfers
over the PCI bus. The 82559ER bus master capabilities enable the component to process
high-level commands and perform multiple operations, thereby off-loading communication
tasks from the system CPU. Two large transmit and receive FIFOs of 3 Kbytes each help
prevent data underruns and overruns, allowing the 82559ER to transmit data with minimum
interframe spacing (IFS).
The 82559ER can operate in either full duplex or half duplex mode. In full duplex mode the
82559ER adheres to the IEEE 802.3x Flow Control specification. Half duplex performance
is enhanced by a proprietary collision reduction mechanism.
The 82559ER includes a simple PHY interface to the wire transformer at rates of 10BASET and 100BASE-TX, and Auto-Negotiation capability for speed, duplex, and flow control.
These features and others reduce cost, real estate, and design complexity.
The 82559ER also includes an interface to a serial (4-pin) EEPROM and a parallel interface
to a 128 Kbyte Flash memory. The EEPROM provides power-on initialization for hardware
and software configuration parameters
EBC-5710/5710V
1.3.12
Winbond W83697UF
The Winbond W83697UF Super I/O chip provides most input / output interfaces of the
system as the following:
n
COM 1
n
COM 2
n
FDD or LPT. Support for SPP, EPP and ECP modes
n
Keyboard interface
n
PS/2 Mouse interface
n
IrDA interface for infrared communication. This interface shares the controller of COM2
n
Provision of buffered ISA data bus for BIOS (denoted XDBus)
n
NVRAM with battery backup for BIOS configuration and real time clock
n
Watchdog timer
1.3.13
Compact Flash Interface
A Compact Flash type II connector is connected to the secondary IDE controller. The
Compact Flash storage card is IDE compatible. It is an ideal replacement for standard IDE
hard drives. The solid-state design offers no seek errors even under extreme shock and
vibration conditions. The Compact Flash storage card is extremely small and highly suitable
for rugged environments, thus providing an excellent solution for mobile applications with
space limitations. It is fully compatible with all consumer applications designed for data
storage PC card, PDA, and Smart Cellular Phones, allowing simple use for the end user.
The Compact Flash storage card is O/S independent, thus offering an optimal solution for
embedded systems operating in non-standard computing environments. The Compact Flash
storage card is IDE compatible and offers various capacities.
User’s Manual
2.
Hardware Configuration
2.1
ATX Power Connection
1. Make sure your ATX power supply can meet EBC -5710/5710V spec requirement and
workable.
2. Check the ATX-AT power connector cable, P/N 1702204500 in the EBC-5710/5710V
product package as the following figure.
3. Make the cable connectors AT1 & AT2 be properly connected to connector PWR2 on
EBC-5710/5710V. For the connector location information, please refer to the chapter
3.6 Jumper and Connector in this manual.
4. Link the cable connector ATX2 to EBC-5710/5710V CN4 connector.
5. Make the cable connector ATX1 connected to the ATX connector from your ATX power
supply.
6. Connect the 12V ATX power connector of your ATX power supply to the connector
PWR1 on EBC -5710/5710V.
7. Now you can turn on the system power to check if the power supply work properly on
EBC-5710/5710V or not.
Note:
Although the connector PWR2 on EBC -5710/5710V is a standard AT power
connector, EBC -5710/5710V only can work by ATX power supply. BCM don’t
guarantee all the board functions can work normally by using an AT power supply.
EBC-5710/5710V
2.2
Installation Procedure
1. Turn off the power supply.
2. Insert the DIMM module (be careful with the orientation).
3. Insert all external cables for hard disk, floppy, keyboard, mouse, USB etc. except for
flat panel. A CRT monitor must be connected in order to change CMOS settings to
support flat panel.
4. Connect power supply to the board via the PWR2.
5. Turn on the power.
6. Enter the BIOS setup by pressing the delete key during boot up. Use the “L OAD BIOS
DEFAULTS” feature. The Integrated Peripheral Setup and the Standard CMOS
Setup Window must be entered and configured correctly to match the particular system
configuration.
7. If TFT panel display is to be utilised, make sure the panel voltage is correctly set before
connecting the display cable and turning on the power.
2.3
2.3.1
Safety Precautions
Warning!
Always completely disconnect the power cord from your chassis or power
cable from your board whenever you work with the hardware. Do not make
connections while the power is on. Sensitive electronic components can be
damaged by sudden power surges. Only experienced electronics personnel
should open the PC chassis.
2.3.2
Caution!
Always ground yourself to remove any static charge before touching the
board. Modern electronic devices are very sensitive to static electric
charges. As a safety precaution, use a grounding wrist strap at all times.
Place all electronic components in a static-dissipative surface or staticshielded bag when they are not in the chassis.
User’s Manual
2.4
Intel FC-478 Pentium 4 Processor
2.4.1
Installing Intel Pentium 4 CPU
n
Lift the handling lever of CPU socket outwards and upwards to the other end.
n
Align the processor pins with pin-holes on the socket. Make sure that the notched
corner or dot mark (pin 1) of the CPU corresponds to the socket’s bevel end. Then
press the CPU gently until it fits into place. If this operation is not easy or smooth,
don’t do it forcibly. You need to check and rebuild the CPU pin uniformly.
n
Push down the lever to lock processor chip into the socket.
n
Follow the installation guide of cooling fan or heat sink to mount it on CPU surface
and lock it on the socket FC-478.
n
Make sure to follow particular CPU speed and voltage type to adjust the jumper
settings properly.
2.4.2
Removing CPU
n
Unlock the cooling fan first.
n
Lift the lever of CPU socket outwards and upwards to the other end.
n
Carefully lift up the existing CPU to remove it from the socket.
n
Follow the steps of installing a CPU to change to another one or place handling
bar back to close the opened socket.
2.5 Main Memory
EBC-5710/5710V provides a DDR DIMM socket (184-pin Dual In-line Memory Module) to
support DDR SDRAM of un-buffer DIMM DDR333 and un-buffered Double-sided DIMM
DDR266/200.
The maximum memory size is 512MB. For system compatibility and stability, please do not
use memory module without brand.
Watch out the contact and lock integrity of memory module with socket, it will influence the
system’s reliability. Follow the normal procedure to install your DDR SDRAM module into
the DDR DIMM socket. Before locking the DDR DIMM module, make sure that the memory
module has been completely inserted into the DDR DIMM socket.
Note:
Please do not change any DDR SDRAM parameter in BIOS setup to increase your
system’s performance without acquiring technical information in advance.
EBC-5710/5710V
2.6
2.6.1
Jumper & Connector
Jumper & Connector Layout
User’s Manual
2.6.2
Jumper & Connector List
Connectors on the board are linked to external devices such as hard disk drives, keyboard,
mouse, or floppy drives. In addition, the board has a number of jumpers that allow you to
configure your system to suit your application.
The following tables list the function of each of the board's jumpers and connectors.
Jumpers
Label
Function
Note
J2
COM2 RS-232/422/485 select
4 x 3 header, pitch 2.0mm
J3
COM2 RS-232/422/485 select
J4
COM3 pin 9 signal select
J5
COM4 pin 9 signal select
J6
Clear CMOS
J7
LVDS power signal select
(EBC -5710V only)
EBC-5710/5710V
Connectors
Label
Function
CN2
TFT panel connector
HIROSE DF13-40DP-1.25V
CN3
CPU fan connector
3 x 1 wafer, pitch 2.54mm
CN4
CN5
ATX PSON connector
Audio / TV output connector
CN6
Floppy connector
CN7
Serial port 1 / 2 / 3 / 4 connector
CN8
CD-ROM audio input connector
CN9
Keyboard and PS/2 mouse connector 4 x 2 header, pitch 2.54mm
CN10
Front panel connector
CN11
Primary IDE device connector
CN12
Secondary IDE device connector
DIMM1
168-pin DIMM socket
I1, I2
IEEE-1394 connector
IR1
IrDA connector
J1
LCD inverter connector
LN1
10/100Base-Tx Ethernet 1 connector RJ-45
LN2
10/100Base-Tx Ethernet 1 connector RJ-45
LNLED1
Ethernet LED connector
LVDS1
LVDS connector
(EBC -5710V only)
PCI1
PCI connector
PNT1
Printer port connector
PWR1
ATX 12V Power connector
PWR2
AT power connector
SN1
Compact Flash connector
USB1
USB connector
VGA1
CRT connector
VR1
STN LCD contrast adjustment
connector
LCD Backlight brightness adjustment
connector
VR2
Note
User’s Manual
2.7
Setting Jumpers
You can configure your board to match the needs of your application by setting jumpers. A
jumper is the simplest kind of electric switch.
It consists of two metal pins and a small metal clip (often protected by a plastic cover) that
slides over the pins to connect them. To “close” a jumper you connect the pins with the clip.
To “open” a jumper you remove the clip. Sometimes a jumper will have three pins, labeled 1,
2, and 3. In this case, you would connect either two pins.
The jumper settings are schematically depicted in this manual as follows:
A pair of needle-nose pliers may be helpful when working with jumpers.
If you have any doubts about the best hardware configuration for your application, contact
your local distributor or sales representative before you make any changes.
EBC-5710/5710V
2.7.1 COM2 RS-232/422/485 Select (J2, J3)
The EBC-5710/5710V COM2 serial port can be selected as RS-232, RS-422, or RS-485
by setting J2 & J3.
COM2 RS-232/422/485 Select (J2, J3)
RS-232*
J2
3
6
9
12
1
4
7
10
RS-422
3
6
9
12
RS-485
1
4
7
10
3
6
9
12
1
4
7
10
5 3 1
5 3 1
5 3 1
6 4 2
6 4 2
6 4 2
J3
* default
2.7.2 COM3 / 4 Pin 9 Signal Select (J4, J5)
The EBC-5710/5710V series COM3 / 4 pin 9 signal can be selected as +12V, +5V, or Ring
by setting J4 / J5.
COM3 Select (J4)
Ring*
+5V
+12V
5 3 1
5 3 1
5 3 1
6 4 2
6 4 2
6 4 2
Ring*
+5V
+12V
J4
* default
COM4 Select (J5)
5 3 1
5 3 1
5 3 1
6 4 2
6 4 2
6 4 2
J5
* default
User’s Manual
2.7.3 Clear CMOS (J6)
You can use J6 to clear the CMOS data if necessary. To reset the CMOS data, set J6 to
1-2 closed for just a few seconds, and then move the jumper back to 2-3 closed.
Clear CMOS (J6)
Protect*
J6
Clear CMOS
1
2
3
1
2
3
* default
2.7.4
LVDS Power Signal Select (J7)
The EBC-5710/5710V series LVDS power signal can be selected as +5V, or +3.3V
by setting J7.
LVDS Power Signal Select (J7)
+5V
J7
1
2
3
+3.3V*
1
2
3
* default
EBC-5710/5710V
2.8
Connector Definitions
2.8.1
TFT Panel Connector (CN2)
Signal
2.8.2
PIN
Signal
VDDSAFE5
2
1
VDDSAFE5
GND
4
3
GND
VDDSAFE3
6
5
VDDSAFE3
GND
8
7
Vcon
P1
10
9
P0
P3
12
11
P2
P5
14
13
P4
P7
16
15
P6
P9
18
17
P8
P11
20
19
P10
P13
22
21
P12
P15
24
23
P14
P17
26
25
P16
P19
28
27
P18
P21
30
29
P20
P23
32
31
P22
GND
34
33
GND
FLM
36
35
SHFCLK
LP
38
37
M
ENVEE
40
39
ENBKL
Signal Description – TFT Panel Connector (CN2)
P [23:0]
Flat Panel Data Bit 23 to Bit 0 for panel implementation.
SHFCLK
Shift Clock. Pixel clock for flat panel data
LP
Latch Pulse. Flat panel equivalent of HSYNC (horizontal synchronization)
FLM
First Line Marker. Flat panel equivalent of VSYNC (vertical synchronization)
M
Multipurpose signal, function depends on panel type. May be used as AC drive control
signal or as BLANK# or Display Enable signal
ENBKL
Enable backlight signal. This signal is controlled as a part of the panel power sequencing
ENVEE
Enable VEE. Signal to control the panel power-on/off sequencing. A high level may turn on
the VEE (LCD bias voltage) supply to the panel
VDDSAFE5
LCD Backlight Voltage +5V
VDDSAFE3
LCD Driving Voltage +3.3V
User’s Manual
2.8.3
Signal Configuration –TFT Panel Connector (CN2)
Pin name
TFT 9-Bit
TFT 18-Bit
TFT 24-Bit
P23
R2
R5
R7
P22
R1
R4
R6
P21
R0
R3
R5
P20
R2
R4
P19
R1
R3
P18
R0
R2
R1
P17
R0
P16
P15
G2
G5
G7
P14
G1
G4
G6
P13
G0
G3
G5
P12
G2
G4
P11
G1
G3
P10
G0
G2
P9
G1
P8
G0
P7
B2
B5
B7
P6
B1
B4
B6
P5
B0
B3
B5
P4
B2
B4
P3
B1
B3
P2
B0
B2
P1
B1
P0
B0
Note:
The principle of attachment of TFT panels is that the bits for red, green, and blue
use the most significant bits and skip the least significant bits if the display interface
width of the TFT panel is insufficient.
2.8.4
2.8.5
TAC
CPU Fan Connector (CN3)
Signal
PIN
TAC
3
+12V
2
GND
1
Signal Description – CPU Fan Connector (CN3)
Fan speed monitor
EBC-5710/5710V
2.8.6
2.8.7
ATX PSON Connector (CN4)
Signal
PIN
PSON#
1
VCC
2
VCCSB
3
Audio / TV Output Connector (CN5)
Signal
2.8.8
PIN
Signal
COMP
16
15
GND
Cout
14
13
GND
Yout
12
11
AGND
Line-In R
10
9
Line-In L
SPK R
8
7
SPK L
Line-Out R
6
5
Line-Out L
AGND
4
3
AGND
Mic Bias
2
1
Mic
Signal Description – Audio / TV Output Connector (CN5)
SPK L/R
Left and right speaker output. These are the speaker outputs directly from the speaker
amplifier. Coupling capacitors must be used in order to avoid DC-currents in the speakers. If
the Audio Bracket is used these signals are supplied on the PCB. GND should be used as
return for each speaker. Maximum power: 0.5W@4 Ω load for each channel.
Mic / Mic Bias The MIC signal is used for microphone input. This input is fed to the left microphone channel.
Mic Bias provides 3.3V supplied through 3.2K Ω with capacitive decoupling to GND. This
signal may be used for bias of some microphone types.
Line-In L/R
Left and right line in signals.
Line-Out L/R
Left and right line out signals. Both signals are capacitor coupled and should have GND as
return.
Yout
Luminance output
Cout
Chrominance output
COMP
Composit video output
User’s Manual
2.8.9
Floppy Disk Connector (FLP1)
Signal
2.8.10
PIN
Signal
DSKCHG#
34
33
GND
SIDE1#
32
31
GND
RDATA#
30
29
GND
WPT#
28
27
GND
TRAK0#
26
25
GND
WE#
24
23
GND
WD#
22
21
GND
STEP#
20
19
GND
DIR#
18
17
GND
MOB#
16
15
GND
DSA#
14
13
GND
DSB#
12
11
GND
MOA#
10
9
GND
INDEX#
8
7
GND
DRVDEN1#
6
5
GND
NC
4
3
GND
DRVDEN0#
2
1
GND
Signal Description – Floppy Disk Connector (FLP1)
RDATA#
The read data input signal from the FDD.
WD#
Write data. This logic low open drain writes pre-compensation serial data to the selected FDD.
An open drain output.
WE#
Write enable. An open drain output.
MOA#
Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output.
MOB#
Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output.
DSA#
Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output.
DSB#
Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output.
SIDE1#
This output signal selects side of the disk in the selected drive.
DIR#
Direction of the head step motor. An open drain output
Logic 1 = outward motion
Logic 0 = inward motion
STEP#
Step output pulses. This active low open drain output produces a pulse to move the head to
another track.
DRVDEN0/1#
This output indicates whether a low drive density (250/300kbps at low level) or a high drive
density (500/1000kbps at high level) has been selected.
TRAK0#
Track 0. This Schmitt-triggered input from the disk drive is active low when the head is
positioned over the outermost track.
INDEX#
This Schmitt-triggered input from the disk drive is active low when the head is positioned over
the beginning of a track marked by an index hole.
WP#
Write protected. This active low Schmitt input from the disk drive indicates that the diskette is
write-protected.
DSKCHG#
Diskette change. This signal is active low at power on and whenever the diskette is removed.
EBC-5710/5710V
2.8.11
Pin Header Serial Port 1 / 2 / 3 / 4 Connector in RS-232 Mode (CN7)
Signal
2.8.12
PIN
Signal
NC
40
39
GND
RI4/5V/12V
38
37
DTR4
CTS4
36
35
TxD4
RTS4
34
33
RxD4
DSR4
32
31
DCD4
NC
30
29
GND
RI3/5V/12V
28
27
DTR3
CTS3
26
25
TxD3
RTS3
24
23
RxD3
DSR3
22
21
DCD3
NC
20
19
GND
RI2
18
17
DTR2
CTS2
16
15
TxD2
RTS2
14
13
RxD2
DSR2
12
11
DCD2
NC
10
9
GND
RI1
8
7
DTR1
CTS1
6
5
TxD1
RTS1
4
3
RxD1
DSR1
2
1
DCD1
Serial Port 1 / 2 / 3 / 4 with External DB9 Connector (CN7)
Signal
GND
DTR
TxD
RxD
DCD
PIN
Signal
5
9
RI
8
CTS
7
RTS
6
DSR
4
3
2
1
User’s Manual
2.8.13
Signal Description – Serial Port 1 / 2 / 3 / 4 Connector in RS-232 Mode (CN7)
TxD
Serial output. This signal sends serial data to the communication link. The signal is set to a
marking state on hardware reset when the transmitter is empty or when loop mode operation is
initiated.
RxD
Serial input. This signal receives serial data from the communication link.
DTR
Data Terminal Ready. This signal indicates to the modem or data set that the on-board UART is
ready to establish a communication link.
DSR
Data Set Ready. This signal indicates that the modem or data set is ready to establish a
communication link.
RTS
Request To Send. This signal indicates to the modem or data set that the on-board UART is
ready to exchange data.
CTS
Clear To Send. This signal indicates that the modem or data set is ready to exchange data.
DCD
Data Carrier Detect. This signal indicates that the modem or data set has detected the data
carrier.
RI
Ring Indicator. This signal indicates that the modem has received a telephone ringing signal.
2.8.14
Pin Header Serial Port 2 Connector in RS-422 Mode (CN7 / Pin 11~20)
Signal
2.8.15
PIN
Signal
NC
20
19
GND
NC
18
17
Rx-
NC
16
15
Tx+
NC
14
13
Rx+
NC
12
11
Tx-
Signal Description – Serial Port 2 in RS-422 Mode (CN7 / Pin 11~20)
Tx +/-
Serial output. This differential signal pair sends serial data to the communication link. Data is
transferred from Serial Port 2 Transmit Buffer Register to the communication link, if the RTS
register of the Serial Port 2 is set to LOW.
Rx +/-
Serial input. This differential signal pair receives serial data from the communication link.
Received data is available in Serial Port 2 Receiver Buffer Register.
EBC-5710/5710V
2.8.16
Pin Header Serial Port 2 Connector in RS-485 Mode (CN7 / Pin 11~20)
Signal
2.8.17
DATA +/-
PIN
Signal
NC
20
19
GND
NC
18
17
NC
NC
16
15
DATA+
NC
14
13
NC
NC
12
11
DATA-
Signal Description – Serial Port 2 in RS-485 Mode (CN7 / Pin 11~20)
This differential signal pair sends and receives serial data to the communication link. The
mode of this differential signal pair is controlled through the RTS register of Serial Port 2. Set
the RTS register of the Serial Port 2 to LOW for transmitting, HIGH for receiving.
Warning: Do not select a mode different from the one used by the connected peripheral,
as this may damage CPU board and/or peripheral.
The transmitter drivers in the port are short circuit protected by a thermal
protection circuit. The circuit disables the drivers when the die temperature
reach 150 °C.
RS-422 mode is typically used in point to point communication. Data and control
signal pairs should be terminated in the receiver end with a resistor matching the
cable impedance (typ. 100-120 Ω). The resistors could be placed in the
connector housing.
RS-485 mode is typically used in multi drop applications, where more than 2
units are communicating. The data and control signal pairs should be terminated
in each end of the communication line with a resistor matching the cable
impedance (typical 100-120 Ω). Stubs to substations should be avoided.
User’s Manual
2.8.18
2.8.19
CD-ROM Audio Input Connector (CN8)
Signal
PIN
CD_R
4
CD_GND
3
CD_L
2
CD_GND
1
Signal Description – CD-ROM Input Connector (CN8)
CD L/R
Left and right CD audio input lines.
CD_GND
GND for left and right CD. This GND level is not connected to the board GND.
2.8.20
Keyboard and PS/2 Mouse Connector (CN9)
Signal
2.8.21
PIN
Signal
4
NC
MCLK
7
3
MDAT
VCC
6
2
GND
KCLK
5
1
KDAT
Signal Description – Keyboard / Mouse Connector (CN9)
KCLK
Bi-directional clock signal used to strobe data/commands from/to the PC-AT keyboard.
KDAT
Bi-directional serial data line used to transfer data from or commands to the PC-AT keyboard.
MCLK
Bi-directional clock signal used to strobe data/commands from/to the PS/2 mouse.
MDAT
Bi-directional serial data line used to transfer data from or commands to the PS/2 mouse.
EBC-5710/5710V
2.8.22
Front Panel Connector (CN10)
Signal
2.8.23
Signal
GND
8
7
RSTIN
GND
6
5
PWBTI
SPK
4
3
VCC
VCC
2
1
HD_LED
Signal Description – Front Panel Connector (CN10)
HD_LED
IDE device activity signal
PWBTI
Power Button
RSTIN
System Reset
SPK
External Speaker
2.8.24
PIN
Primary IDE Device Connector (CN11)
Signal
PIN
Signal
GND
40
39
PDDACT#
PDCS3#
38
37
PDCS1#
PDA2
36
35
PDA0
PD_80P
34
33
PDA1
NC
32
31
IRQ14
GND
30
29
PDDACK#
GND
28
27
PDRDY
GND
26
25
PDIOR#
GND
24
23
PDIOW#
GND
22
21
PDDRQ
NC
20
19
GND
PDD15
18
17
PDD0
PDD14
16
15
PDD1
PDD13
14
13
PDD2
PDD12
12
11
PDD3
PDD11
10
9
PDD4
PDD10
8
7
PDD5
PDD9
6
5
PDD6
PDD8
4
3
PDD7
GND
2
1
RESET#
User’s Manual
2.8.25
Secondary IDE Connector (CN12)
Signal
PIN
Signal
RESET#
1
2
GND
SDD7
3
4
SDD8
SDD6
5
6
SDD9
SDD5
7
8
SDD10
SDD4
9
10
SDD11
SDD3
11
12
SDD12
SDD2
13
14
SDD13
SDD1
15
16
SDD14
SDD0
17
18
SDD15
GND
19
20
NC
SDDREQ
21
22
GND
SDIOW#
23
24
GND
SDIOR#
25
26
GND
SDIORDY
27
28
GND
SDDACK#
29
30
GND
IRQ15
31
32
NC
SDA1
33
34
NC
SDA0
35
36
SDA2
SDCS1#
37
38
SDCS3#
SDDACT#
39
40
GND
EBC-5710/5710V
2.8.26
CN12)
Signal Description - Primary & Secondary IDE Device Connector (CN11 &
PDA [2:0]
Primary Disk Address [2:0]. These signals indicate which byte in either the ATA command
block or control block is being addressed. If the IDE signals are configured for Primary and
Secondary, these signals are connected to the corresponding signals on the Primary IDE
connector. If the IDE signals are configured for Primary 0 and Primary 1, these signals are
used for the Primary 0 connector.
SDA [2:0]
Secondary Disk Address [2:0]. These signals indicate which byte in either the ATA command
block or control block is being addressed. If the IDE signals are configured for Primary and
Secondary, these signals are connected to the corresponding signals on the Secondary IDE
connector. If the IDE signals are configured for Primary Master and Primary Slave, these
signals are used for the Primary Slave connector.
PDCS1#
Primary Disk Chip Select for 1F0H~1F7H Range. For ATA command register block. If the
IDE signals are configured for Primary and Secondary, this output signal is connected to the
corresponding signal on the Primary IDE connector. If the IDE signals are configured for
Primary Master and Primary Slave, this signal is used for the Primary Master connector.
PDCS3#
Primary Disk Chip Select for 3F0H~3F7H Range. For ATA control register block. If the IDE
signals are configured for Primary and Secondary, this output signal is connected to the
SDCS1#
Secondary Chip Select for 170H~177H Range. For ATA command register block. If the IDE
corresponding signal on the Secondary IDE connector. If the IDE signals are configured for
Primary Master and Primary Slave, these signals are used for the Primary Slave connector.
SDCS3#
Secondary Chip Select for 370H~377H Range. For ATA control register block. If the IDE
PDD [15:0]
Primary Disk Data [15:0]. These signals are used to transfer data to or from the IDE device. If
the IDE signals are configured for Primary and Secondary, these signals are connected to the
corresponding signals on the Primary IDE connector. If the IDE signals are configured for
SDD [15:0]
Secondary Disk Data [15:0]. These signals are used to transfer data to or from the IDE
device. If the IDE signals are configured for Primary and Secondary, these signals are
connected to the corresponding signals on the Secondary IDE connector. If the IDE signals
are configured for Primary Master and Primary Slave, these signals are used for the Primary
Slave connector.
User’s Manual
PDIOR#
Primary Disk IO Read. In normal IDE this is the command to the IDE device that it may drive
data onto the PDD [15:0] lines. Data is latched by PIIX4 on the negation edge of PDIOR#. The
IDE device is selected either by the ATA register file chip selects (PDCS1#, PDCS3#) and the
PDA [2:0] lines, or the IDE DMA slave arbitration signals (PDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4
to pause Ultra DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the
STROBE signal, with the drive latching data on rising and falling edges of STROBE.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the
SDIOR#
Secondary Disk IO Read. In normal IDE mode, this is the command to the IDE device that it
may drive data onto the SDD [15:0] lines. Data is latched by the PIIX4 on the negation edge of
SDIOR#. The IDE device is selected either by the ATA register file chip selects (SDCS1#,
SDCS3#) and the SDA [2:0] lines, or the IDE DMA slave arbitration signals (SDDACK#).
In an Ultra DMA/33 read cycle, this signal is used as DMARDY# which is negated by the PIIX4
to pause Ultra DMA/33 transfers. In an Ultra DMA/33 write cycle, this signal is used as the
STROBE signal, with the drive latching data on rising and falling edges of STROBE.
PDIOW#
Primary Disk IO Write. In normal IDE mode, this is the command to the IDE device that it may
latch data from the PDD [15:0] lines. Data is latched by the IDE device on the negation edge of
PDIOW#. The IDE device is selected either by the ATA register file chip selects (PDCS1#,
PDCS3#) and the PDA [2:0] lines, or the IDE DMA slave arbitration signals (PDDACK#).
For Ultra DMA/33 mode, this signal is used as the STOP signal, which is used to terminate an
Ultra DMA/33 transaction. If the IDE signals are configured for Primary and Secondary, this
signal is connected to the corresponding signal on the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for
the Primary Master connector.
SDIOW#
Secondary Disk IO Write. In normal IDE mode, this is the command to the IDE device that it
may latch data from the SDD [15:0] lines. Data is latched by the IDE device on the negation
edge of SDIOW#. The IDE device is selected either by the ATA register file chip selects
(SDCS1#, SDCS3#) and the SDA [2:0] lines, or the IDE DMA slave arbitration signals
(SDDACK#).
In read and write cycles this signal is used as the STOP signal, which is used to terminate an
Ultra DMA/33 transaction.
corresponding signal on the Secondary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, these signals are used
for the Primary Slave connector.
EBC-5710/5710V
PDIORDY
Primary IO Channel Ready. In normal IDE mode, this input signal is directly driven by the
corresponding IDE device IORDY signal. In an Ultra DMA/33 read cycle, this signal is used as
STROBE, with the PIIX4 latching
data on rising and falling edges of STROBE. In an Ultra DMA/33 write cycle, this signal is used
as the DMARDY# signal which is negated by the drive to pause Ultra DMA/33 transfers.
corresponding signal on the Primary IDE connector.
This is a Schmitt triggered input.
SDIORDY
Secondary IO Channel Ready. In normal IDE mode, this input signal is directly driven by the
corresponding IDE device IORDY signal. In an Ultra DMA/33 read cycle, this signal is used as
STROBE, with the PIIX4 latching
data on rising and falling edges of STROBE. In an Ultra DMA write cycle, this signal is used as
the DMARDY# signal which is negated by the drive to pause Ultra DMA/33 transfers.
This is a Schmitt triggered input.
PDDREQ
Primary Disk DMA Request. This input signal is directly driven from the IDE device DMARQ
signal. It is asserted by the IDE device to request a data transfer, and used in conjunction with
the PCI bus master IDE function. It is not associated with any AT compatible DMA channel.
corresponding signal on the Primary IDE connector.
SDDREQ
Secondary Disk DMA Request. This input signal is directly driven from the IDE device
DMARQ signal. It is asserted by the IDE device to request a data transfer, and used in
conjunction with the PCI bus master IDE function. It is not associated with any AT compatible
DMA channel.
PDDACK#
Primary DMA Acknowledge. This signal directly drives the IDE device DMACK# signal. It is
asserted by PIIX4 to indicate to IDE DMA slave devices that a given data transfer cycle
(assertion of PDIOR# or PDIOW#) is a DMA data transfer cycle. This signal is used in
DMA channel. If the IDE signals are configured for Primary and Secondary, this signal is
connected to the corresponding signal on the Primary IDE connector. If the IDE signals are
configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
User’s Manual
SDDACK#
Secondary DMA Acknowledge. This signal directly drives the IDE device DMACK# signal. It is
asserted by PIIX4 to indicate to IDE DMA slave devices that a given data transfer cycle
(assertion of SDIOR# or SDIOW#) is a DMA data transfer cycle. This signal is used in
DMA channel.
PDDACT#
Primary Disk Act. Signal from Primary IDE device indicating Primary IDE device activity. The
signal level depends on the hard disk type, normally active low. The signal is routed directly to
the CN10 HD_LED.
SDDACT#
Secondary Disk Act. Signal from Secondary IDE device indicating Secondary IDE device
activity. The signal level depends on the hard disk type, normally active low. The signal is routed
directly to the CN10 HD_LED.
RESET#
IDE Reset. This signal resets all the devices that are attached to the IDE interface.
IRQ14/15
Interrupt line from hard disk. Connected directly to PC-AT bus.
2.8.27
IEEE1394 Connector (I1, I2)
Signal
2.8.28
Signal
XTPA0P
6
5
XTPA0M
XTPB0P
4
3
XTPB0M
GND
2
1
+12V
Signal Description – IEEE1394 Connector (I1, I2)
XTPA0P
Twisted Pair A Positive.
XTPA0M
Twisted Pair A Negative.
XTPB0P
Twisted Pair B Positive.
Twisted Pair B Negative.
XTPB0M
PIN
EBC-5710/5710V
2.8.29
IrDA Connector (IR1)
Signal
2.8.30
Signal
NC
6
5
ITX
GND
4
3
IRX
NC
2
1
VCC
Signal Description – IR Connector (IR1)
IRRX
Infrared Receiver input
IRTX
Infrared Transmitter output
2.8.31
PIN
LCD Inverter Connector (J1)
Signal
PIN
VCC
5
VR
4
ENBKL
3
GND
2
+12V
1
Note: For inverters with adjustable Backlight function, it is possible to control the
LCD brightness through the VR signal (pin 4) controlled by VR2 Please see
the VR2 section for detailed circuitry information.
2.8.32
Signal Description – LCD Inverter Connector (J1)
VR
Vadj = 5V ~ 0V.
ENBKL
LCD backlight ON/OFF control signal.
User’s Manual
2.8.33
Ethernet LED Connector (LNLED1)
Signal
2.8.34
PIN
Signal
NC
10
9
NC
SPDLED2#
8
7
VCC3SB
LINKLED2#
6
5
ACTLED2#
SPDLED1#
4
3
VCC3SB
LINKLED#1
2
1
ACTLED1#
Signal Description – Ethernet LED Connector (LNLED1)
ACTLED1# / 2# Activity LED. The Activity LED pin indicates either transmit or receive activity. When activity
is present, the activity LED is on; when no activity is present, the activity LED is off. Work
with VCC3SB.
LILED1# / 2#
Link Integrity LED. The Link Integrity LED pin indicates link integrity. If the link is valid in
either 10 or 100 Mbps, the LED is on; if link is invalid, the LED is off. Work with VCC3SB.
SPDLED1# / 2# Speed LED. The Speed LED pin indicates the speed. The speed LED will be on at 100
Mbps and off at 10 Mbps. Work with VCC3SB.
2.8.35
LVDS Connector (LVDS1, EBC-5710V only)
Signal
2.8.36
PIN
Signal
GND
19
20
LVDSPWR
TX3-
17
18
TX3+
TXCLK+
15
16
GND
GND
TX2-
13
14
TXCLK-
11
12
TX2+
TX1+
9
10
GND
GND
7
8
TX1-
TX0-
5
6
TX0+
GND
3
4
GND
LVDS PWR
1
2
LVDSPWR
Signal Description – LVDS Connector (LVDS1, EBC-5710V only)
TX0+, TX1+,
TX2+, TX3+
Positive LVDS differentiaI data output
TX0-, TX1-, TX2- Negative LVDS differential data output
, TX3TXCLK+
Positive LVDS differential clock output
TXCLK-
Negative LVDS differential clock output
ENBKL
Enable backlight signal. This signal is controlled as a part of the panel power sequencing
LVDSPWR
+5V or +3.3V. Selectable by J7
EBC-5710/5710V
2.8.37
USB Connector (USB1)
Signal
2.8.38
PIN
CH2 CH1
Signal
VCC2
10
9
GND
D2-
8
7
GND
D2+
6
5
D1+
GND
4
3
D1-
GND
2
1
VCC1
Signal Description – USB Connector (USB1)
D1+ / D1-
Differential bi-directional data signal for USB channel 0. Clock is transmitted along with the
data using NRZI encoding. The signalling bit rate is up to 12 Mbs.
D2+ / D2-
Differential bi-directional data signal for USB channel 1. Clock is transmitted along with the
data using NRZI encoding. The signalling bit rate is up to 12 Mbs.
VCC
5 V DC supply for external devices. Maximum load according to USB standard.
2.8.39
CRT Connector (VGA1)
Signal
2.8.40
PIN
Signal
NC
16
8
GND
DDCCLK
15
7
GND
VSYNC
14
6
GND
NSYNC
13
5
GND
DDCDAT
12
4
NC
NC
11
3
BLUE
GND
10
2
GREEN
VCC
9
1
RED
Signal Description – CRT Connector (VGA1)
HSYNC
CRT horizontal synchronisation output.
VSYNC
CRT vertical synchronisation output.
DDCCLK
Display Data Channel Clock. Used as clock signal to/from monitors with DDC interface.
DDCDAT
RED
Display Data Channel Data. Used as data signal to/from monitors with DDC interface.
Analog output carrying the red colour signal to the CRT. For 75 O cable impedance.
GREEN
Analog output carrying the green colour signal to the CRT. For 75 O cable impedance.
BLUE
Analog output carrying the blue colour signal to the CRT. For 75 O cable impedance.
User’s Manual
2.8.41
2.8.42
STN LCD Contrast Adjustment Connector (VR1)
Signal
PIN
VCC3
3
Vcon
2
GND
1
LCD Backlight Brightness Adjustment Connector (VR2)
Signal
PIN
GND
VBR
VCC
1
2
3
VCC
VR2
1
J1 pin 4
2
3
Variation Resistor (Recommended: 4.7KΩ, >1/16W)
EBC-5710/5710V
3.
3.1
AWARD BIOS Setup
Starting Setup
The AwardBIOS™ is immediately activated when you first power on the computer. The
BIOS reads the system information contained in the CMOS and begins the process of
checking out the system and configuring it. When it finishes, the BIOS will seek an operating
system on one of the disks and then launch and turn control over to the operating system.
While the BIOS is in control, the Setup program can be activated in one of two ways:
By pressing <Del> immediately after switching the system on, or
By pressing the <Del> key when the following message appears briefly at the bottom of the
screen during the POST (Power On Self Test).
Press DEL to enter SETUP
If the message disappears before you respond and you still wish to enter Setup, restart the
system to try again by turning it OFF then ON or pressing the "RESET" button on the
system case. You may also restart by simultaneously pressing <Ctrl>, <Alt>, and <Delete>
keys. If you do not press the keys at the correct time and the system does not boot, an
error message will be displayed and you will again be asked to.
Press F1 To Continue, DEL to enter SETUP
User’s Manual
3.2
Using Setup
In general, you use the arrow keys to highlight items, press <Enter> to select, use the
PageUp and PageDown keys to change entries, press <F1> for help and press <Esc> to
quit. The following table provides more detail about how to navigate in the Setup program
using the keyboard.
Up arrow
Move to previous item
Down arrow
Move to next item
Left arrow
Move to the item in the left hand
Right arrow
Move to the item in the right hand
Esc key
Main Menu -- Quit and not save changes into CMOS
Status Page Setup Menu and Option Page Setup Menu -- Exit
current page and return to Main Menu
PgUp key
Increase the numeric value or make changes
PgDn key
Decrease the numeric value or make changes
+ key
Increase the numeric value or make changes
- key
Decrease the numeric value or make changes
F1 key
General help, only for Status Page Setup Menu and Option Page
Setup Menu
(Shift) F2 key
Change color from total 16 colors. F2 to select color forward,
(Shift) F2 to select color backward
F3 key
Calendar, only for Status Page Setup Menu
F4 key
Reserved
F5 key
Restore the previous CMOS value from CMOS, only for Option
Page Setup Menu
F6 key
Load the default CMOS value from BIOS default table, only for
Option Page Setup Menu
F7 key
Load the default
F8 key
Reserved
F9 key
Reserved
F10 key
Save all the CMOS changes, only for Main Menu
Table 1 : Legend Keys
3.3
Getting Help
Press F1 to pop up a small help window that describes the appropriate keys to use and the
possible selections for the highlighted item. To exit the Help Window press <Esc> or the F1
key again.
3.4
In Case of Problems
If, after making and saving system changes with Setup, you discover that your computer no
longer is able to boot, the Award BIOS supports an override to the CMOS settings which
resets your system to its defaults.
EBC-5710/5710V
3.5
Main Menu
Once you enter the AwardBIOS™ CMOS Setup Utility, the Main Menu will appear on the
screen. The Main Menu allows you to select from several setup functions and two exit
choices. Use the arrow keys to select among the items and press <Enter> to accept and
enter the sub-menu.
3.5.1
Setup Items
The main menu includes the following main setup categories. Recall that some systems
may not include all entries.
Standard CMOS Features
Use this menu for basic system configuration.
Advanced BIOS Features
Use this menu to set the Advanced Features available on your system.
Advanced Chipset Features
Use this menu to change the values in the chipset registers and optimize your system's
performance.
Integrated Peripherals
Use this menu to specify your settings for integrated peripherals.
User’s Manual
Power Management Setup
Use this menu to specify your settings for power management.
PNP / PCI Configuration
This entry appears if your system supports PnP / PCI.
PC Health Status
This entry appears your system Hardware Monitor Status
Frequency / Voltage Control
Use this menu to specify your settings for frequency/voltage control.
Load Fail-Safe Defaults
Use this menu to load the BIOS default values for the minimal/stable performance for your
system to operate.
Load Optimized Defaults
Use this menu to load the BIOS default values that are factory settings for optimal
performance system operations. While Award has designed the custom BIOS to maximize
performance, the factory has the right to change these defaults to meet their needs.
Set Password
Use this menu to set Passwords.
Save & Exit Setup
Save CMOS value changes to CMOS and exit setup.
Exit Without Save
Abandon all CMOS value changes and exit setup.
EBC-5710/5710V
3.5.2
Standard CMOS Setup
The items in Standard CMOS Setup Menu are divided into 10 categories. Each category
includes no, one or more than one setup items. Use the arrow keys to highlight the item and
then use the <PgUp> or <PgDn> keys to select the value you want in each item.
Main Manu Selection
This table shows the selections that you can make on the Main Menu.
Item
Date
Time
Options
Month
DD
Description
YYYY
HH : MM : SS
Set the system date. Note that the ‘Day’
automatically changes when you set the date
Set the system time
IDE Primary Master
Options are in its sub menu Press <Enter> to enter the sub menu of
(described in Table 3)
detailed options
IDE Primary Slave
detailed options
IDE Secondary Master
detailed options
IDE Secondary Slave
detailed options
Drive A
Drive B
None
360K, 5.25 in
1.2M, 5.25 in
720K, 3.5 in
1.44M, 3.5 in
2.88M, 3.5 in
Select the type of floppy disk drive installed in
your system
User’s Manual
Item
Options
Description
Video
EGA/VGA
CGA 40
CGA 80
MONO
Halt On
All Errors
No Errors
All, but Keyboard
All, but Diskette
All, but Disk/Key
LCD Panel ID Sel
SPWG ID
800 X 600
1024 X 768
1280 X 1024
1400 X 1050
1600 X 1200
SiS301 Display Type
CRT / LCD /TV
Select the display device for LCD or
CRT or TV
LCD & TV Select
LCD / TV
Select the display device for LCD or
TV
Base Memory
N/A
Displays the amount of conventional memory
detected during boot up
Extended Memory
N/A
Displays the amount of extended memory
detected during boot up
Total Memory
N/A
Displays the total memory available in the
system
Select the default video device
Select the situation in which you want the
BIOS to stop the POST process and notify
you
Select the resolution of LCD
Table 2 : Main Menu Selections
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IDE Adapters
The IDE adapters control the hard disk drive. Use a separate sub menu to configure each
hard disk drive.
Use the legend keys to navigate through this menu and exit to the main menu. Use Table 3
to configure the hard disk.
Item
IDE HDD Auto-detection
IDE Primary Master
Capacity
Access Mode
Options
Description
Press Enter
Press Enter to auto-detect the HDD on this
channel. If detection is successful, it fills the
remaining fields on this menu.
None
Auto
Manual
Selecting ‘manual’ lets you set the remaining
fields on this screen. Selects the type of
fixed disk. "User Type" will let you select the
number of cylinders, heads, etc. Note:
PRECOMP=65535 means NONE !
Disk drive capacity (Approximated). Note
Auto Display your disk drive that this size is usually slightly greater than
size
the size of a formatted disk given by a disk
checking program.
Normal
LBA
Large
Auto
Choose the access mode for this hard disk
The following options are selectable only if the ‘IDE Primary Master’item is set to ‘Manual’
Cylinder
Min = 0
Max = 65535
Set the number of cylinders for this hard
disk.
Head
Min = 0
Max = 255
Precomp
Min = 0
Max = 65535
**** Warning: Setting a value of 65535
means no hard disk
Landing zone
Min = 0
Max = 65535
****
Sector
Min = 0
Max = 255
Set the number of read/write heads
Number of sectors per track
Table 3: Hard disk selections
User’s Manual
3.5.3
Advanced BIOS Features
This section allows you to configure your system for basic operation. You have the
opportunity to select the system’s default speed, boot-up sequence, keyboard operation,
shadowing and security.
Virus Warning
Allows you to choose the VIRUS Warning feature for IDE Hard Disk boot sector protection.
If this function is enabled and someone attempt to write data into this area, BIOS will show
a warning message on screen and alarm beep.
Enabled
Activates automatically when the system boots up causing a warning
message to appear when anything attempts to access the boot sector
or hard disk partition table.
Disabled
No warning message will appear when anything attempts to access the
boot sector or hard disk partition table.
CPU L1 & L2 Cache
This item allows you to speed up memory access. However, it depends on CPU design.
Enabled
Enable cache
Disabled
Disable cache
Hyper-Threading Technology
This item allows you to enable/disable CPU Hyper-Threading
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CPU L2 Cache ECC Checking
This item allows you to enable/disable CPU L2 Cache ECC checking.
Enabled
Enable L2 Cache ECC Checking
Disabled
Disable L2 Cache ECC Checking
Quick Power On Self Test
This category speeds up Power On Self Test (POST) after you power up the computer. If it
is set to Enable, BIOS will shorten or skip some check items during POST.
Enabled
Enable quick POST
Disabled
Normal POST
First/Second/Third/Other Boot Device
The BIOS attempts to load the operating system from the devices in the sequence selected
in these items.
Floppy
Floppy Device
LS120
LS120 Device
HDD-0
First Hard Disk Device
SCSI
SCSI Device
CDROM
CDROM Device
HDD-1
Secondary Hard Disk Device
HDD-2
Third Hard Disk Device
HDD-3
Fourth Hard Disk Device
ZIP100
ZIP-100 Device
USB-FDD
USB Floppy Device
USB-ZIP
USB ZIP Device
USB-CDROM
USB CDROM Device
USB-HDD
USB Hard Disk Device
LAN
Network Device
Disabled
Disabled any boot device
Boot Up Floppy Seek
Seeks disk drives during boot up. Disabling speeds boot up.
Enabled
Enable Floppy Seek
Disabled
Disable Floppy Seek
Boot Up NumLock Status
Select power on state for NumLock.
Enabled
Enable NumLock
Disabled
Disable NumLock
User’s Manual
Typematic Rate Setting
Key strokes repeat at a rate determined by the keyboard controller. When enabled, the
typematic rate and typematic delay can be selected.
The choice: Enabled/Disabled.
Typematic Rate (Chars/Sec)
Sets the number of times a second to repeat a key stroke when you hold the key down.
The choice: 6, 8, 10, 12, 15, 20, 24, or 30.
Typematic Delay (Msec)
Sets the delay time after the key is held down before it begins to repeat the keystroke.
The choice: 250, 500, 750, or 1000.
Security Option
Select whether the password is required every time the system boots or only when you
enter setup.
System
The system will not boot and access to Setup will be denied if the
correct password is not entered at the prompt.
Setup
The system will boot, but access to Setup will be denied if the correct
password is not entered at the prompt.
Note: To disable security, select PASSWORD SETTING at Main Menu and then you will be
asked to enter password. Do not type anything and just press <Enter>, it will disable
security. Once the security is disabled, the system will boot and you can enter Setup
freely.
OS Select for DRAM > 64MB
Select the operating system that is running with greater than 64MB of RAM on the system.
The choice: Non-OS2, OS2.
Video BIOS Shadow
This item allows you to speed up Video BIOS access.
Enabled
Enable Video BIOS Shadow
Disabled
Disable Video BIOS Shadow
Small Logo (EPA) Show
This item allows you enabled/disabled the small EPA logo show on screen at the POST
step,
Enabled
EPA Logo show is enabled
Disabled
EPA Logo show is disabled
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3.5.4
Advanced Chipset Features
4Advanced DRAM Control 1
User’s Manual
This section allows you to configure the system based on the specific features of the
installed chipset. This chipset manages bus speeds and access to system memory
resources, such as DRAM and the external cache. It also coordinates communications
between the conventional ISA bus and the PCI bus. It must be stated that these items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might consider
making any changes would be if you discovered that data was being lost while using your
system.
The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered if data
is being lost. Such a scenario might well occur if your system had mixed speed DRAM chips
installed so that greater delays may be required to preserve the integrity of the data held in
the slower memory chips.
Advanced DRAM Control 1
This feature allows you to setup the timing & driving about DRAM.
Prefetch Caching
This Item allows you to setup the Prefetch Caching function.
Memory Hole at 15M-16M
This option sets the Memory Hole location.
The Choice: Disabled, Enabled.
System BIOS Cacheable
This feature is only valid when the system BIOS is shadowed. It enables or disables the
caching of the system BIOS ROM at F0000h-FFFFFh via the L2 cache. This greatly speeds
up accesses to the system BIOS. However, this does not translate into better system
performance because the OS does not need to access the system BIOS much.
The Choice: Disabled, Enabled.
Video RAM Cacheable
This Item allows you to speed up Video RAM access.
The Choice: Enabled, Disabled.
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3.5.5
Integrated Peripherals
4SiS OnChip IDE Device
User’s Manual
4SiS OnChip PCI Device
Internal PCI/IDE
The chipset contains a PCI IDE interface with support for two IDE channels. Select which
channel Enabled to activate the primary or secondary IDE interface .
The choice: Disabled.Primary,Secondary,Both.
Primary/Secondary Master/Slave PIO
The four IDE PIO (Programmed Input/Output) fields let you set a PIO mode (0-4) for each
of the four IDE devices that the onboard IDE interface supports. Modes 0 through 4 provide
successively increased performance. In Auto mode, the system automatically determines
the best mode for each device.
The choice: Auto, Mode 0, Mode 1, Mode 2, Mode 3, or Mode 4.
Primary/Secondary Master/Slave UDMA
Ultra DMA/33 implementation is possible only if your IDE hard drive supports it and the
operating environment includes a DMA driver (Windows 95 OSR2 or a third-party IDE bus
master driver). If your hard drive and your system software both support Ultra DMA/33,
select Auto to enable BIOS support.
The Choice: Auto, Disabled.
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SiS USB Controller/USB 2.0/USB KB/1394/AC97 Audio
These items allow you to decide to enable/disable the SIS chipset family to support or not.
The choice: Enabled, Disabled.
Onboard FDC Controller
Select Enabled if your system has a floppy disk controller (FDC) installed on the system
board and you wish to use it. If you install and-in FDC or the system has no floppy drive,
select Disabled in this field.
The Choice: Enabled, Disabled.
Onboard Serial Port 1/Port2
Select an address and corresponding interrupt for the first and second serial ports.
The choice: 3F8/IRQ4, 2F8/IRQ3, 3E8/IRQ4, 2E8/IRQ3, Disabled.
UART Mode
Select UART 2 mode as standard serial port or IR port.
The choice: Normal, IrDA, ASKIR.
UR2 Duplex Mode
Select the value required by the IR device connected to the IR port. Full-duplex mode
permits simultaneous two-direction transmission. Half-duplex mode permits transmission in
one direction only at a time.
The Choice: Half, Full.
Onboard Serial Port 3/Port4
Select an address and corresponding interrupt for the first and second serial ports.
The choice :I/O Address--- 3F8, 2F8, 3E8, 2E8, Disabled.
IRQ Select------IRQ5, IRQ10.
Onboard Parallel Port
Select a logical LPT port name and matching address for the physical parallel (printer) port.
The choice : 378H/IRQ7, 278H/IRQ5, 3BCH/IRQ7, Disabled.
Onboard Parallel Mode
Select an operating mode for the onboard parallel port. Select Compatible or Extended
unless you are certain both your hardware and software support EPP or ECP mode.
The choice: SPP, EPP, ECP, ECP+EPP,Normal
User’s Manual
ECP Mode Use DMA
Select a DMA channel for the port.
The choice: 3, 1.
Init Display First
This item allows you to decide to active whether PCI Slot or AGP first.
The choice: PCI Slot, AGP.
Watch Dog Timer Select
This option will determine watch dog timer.
The choice: Disabled,10/20/30/40 Sec,1/2/3/4 Min.
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3.5.6
Power Management Setup
The Power Management Setup allows you to configure you system to most effectively save
energy while operating in a manner consistent with your own style of computer use.
ACPI Function
This item allows you to enable/disable the ACPI function.
The choice: Enable, Disable.
Suspend Mode
This item will set what time suspend mode will be used.
User’s Manual
Power Management
This category allows you to select the type (or degree) of power saving and is directly
related to the following modes:
1. Suspend Mode
There are three selections for Power Management, both of them have fixed mode settings.
Min. Power Saving
Minimum power management,
Suspend Mode = 1 Hour,
Max. Power Saving
Maximum power management,
Suspend Mode =1 Min,
User Defined
Allows you to set each mode individually. When not
disabled, each of the ranges are from 1 min. to 1 hr.
except for HDD Power Down which ranges from 1 min. to
15 min. and disable.
Video Off Method
This determines the manner in which the monitor is blanked.
V/H SYNC+Blank
This selection will cause the system to turn off the vertical
and horizontal synchronization ports and write blanks to
the video buffer.
Blank Screen
This option only writes blanks to the video buffer.
DPMS
Initial display power management signaling.
MODEM Use IRQ
This determines the IRQ in which the MODEM can use.
The choice: Auto, 3, 4, 5, 7, 9, 10, and 11.
HDD Off After
When enabled and after the set time of system inactivity,the hard disk drive will be powered
down while all other devices remain active.
The choice: 1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 Min, Disabled.
Power Button Override
Pressing the power button for more than 4 seconds forces the system to enter the Soft-Off
state when the system has “hung”.(Only could working on ATX Power supply)
The choice: Delay 4 Sec, Instant-Off.
POWER State Resume Control
This option will determine how the system will power on after a power failure.
The choice: Off, On. Former-Sts
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PCIPME Power Up Control
This item allows you to determine that does any activity from one of the list system
peripheral devices wakes up the system.
The Choice. Enable, Disabled.
Ring Resume
An input signal on the serial Ring Indicator (RI) line (in other words, an incoming call on the
modem) awakens the system from a soft off state
The Choice. Enable, Disabled.
Power by Alarm
This function is for setting date and time for your computer to boot up.
Reload Global Timer Events
Reload Global Timer events are I/O events whose occurrence can prevent the system from
entering a power saving mode or can awake the system from such a mode. In effect, the
system remains alert for anything which occurs to a device which is configured as Enabled,
even when the system is in a power down mode.
User’s Manual
3.5.7
PnP/PCI Configuration Setup
This section describes configuring the PCI bus system. PCI, or Personal Computer
Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed
the CPU itself uses when communicating with its own special components. This section
covers some very technical items and it is strongly recommended that only experienced
users should make any changes to the default settings.
Reset Configuration Data
Normally, you leave this field Disabled. Select Enabled to reset Extended System
Configuration Data (ESCD) when you exit Setup if you have installed a new add-on and the
system reconfiguration has caused such a serious conflict that the operating system cannot
boot.
The choice: Enabled, Disabled.
Resource Controlled by
The Award Plug and Play BIOS has the capacity to automatically configure all of the boot
and Plug and Play compatible devices. However, this capability means absolutely nothing
unless you are using a Plug and Play operating system such as Windows95. If you set
this field to “manual” choose specific resources by going into each of the sub menu that
follows this field (a sub menu is preceded by a “Ø”).
The choice: Auto, Manual.
IRQ Resources
When resources are controlled manually, assign each system interrupt a type, depending
on the type of device using the interrupt.
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IRQ3/4/5/7/9/10/11/12/14/15 Assigned to
This item allows you to determine the IRQ assigned to the ISA bus and is not available to
any PCI slot. Legacy ISA for devices compliant with the original PC AT bus specification,
PCI/ISA PnP for devices compliant with the Plug and Play standard whether designed for
PCI or ISA bus architecture.
The Choice: PCI Device,Reserved.
PCI / VGA Palette Snoop
Leave this field at Disabled.
Choices are Enabled, Disabled.
3.5.8
PC Health Status
This section show the status of your CPU , Fan & System status.
User’s Manual
3.5.9
Frequency / Voltage Control
CPU Clock Ratio
This item allows you to set the CPU Clock Ratio
Auto Detect DIMM/ PCI Clk
This item allows you to enable/disable auto detect DIMM/PCI Clock.
Spread Spectrum
This item allows you to enabled Spread Spectrum Modulated.
CPU Host Clock (CPU / PCI / SDRAM)
This item allows you to select the CPU host clock frequency.
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3.5.10
Load Fail-Safe Defaults
When you press <Enter> on this item you get a confirmation dialog box with a message
similar to:
Pressing ‘Y’ loads the BIOS default values for the most stable, minimal-performance
system operations.
3.5.11
Load Optimized Defaults
When you press <Enter> on this item you get a confirmation dialog box with a message
similar to:
Pressing ‘Y’ loads the default values that are factory settings for optimal performance
system operations.
User’s Manual
3.5.12
Set Password
You can set password by the feature.
ENTER PASSWORD:
Type the password, up to eight characters in length, and press <Enter>. The password
typed now will clear any previously entered password from CMOS memory. You will be
asked to confirm the password. Type the password again and press <Enter>. You may
also press <Esc> to abort the selection and not enter a password. To disable a password,
just press <Enter> when you are prompted to enter the password. A message will confirm
the password will be disabled. Once the password is disabled, the system will boot and you
can enter Setup freely.
PASSWORD DISABLED.
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3.5.13
Exit Selecting
Save & Exit Setup
Pressing <Enter> on this item asks for confirmation:
Pressing “Y” stores the selections made in the menus in CMOS – a special section of
memory that stays on after you turn your system off. The next time you boot your computer,
the BIOS configures your system according to the Setup selections stored in CMOS. After
saving the values the system is restarted again.
User’s Manual
Exit Without Saving
Pressing <Enter> on this item asks for confirmation:
This allows you to exit Setup without storing in CMOS any change. The previous selections
remain in effect. This exits the Setup utility and restarts your computer.
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4.
Driver Installation
4.1
4.1.1
Driver Installation for Display Adapter
Windows 9x
You could install the SiS 650/651 Video driver by Setup program or update the current
driver by Windows Update Device Driver Wizard.
The following steps show how to install the SiS 650/651 video driver by Setup program.
1. Click the ‘Start’button on the task bar, select ‘Run’and specify the location of SiS
650/651 Video driver setup program. This should start the SiS 650/651 Video driver
setup program as shown below:
2. Click the ‘Next’as shown below.
User’s Manual
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6. Click the ‘Finish’button to complete the driver setup.
User’s Manual
The following steps will install the display driver for the SiS 650/651 display controller.
1.
Click the ‘Start’ button on the task bar, select ‘Settings’ and ‘Control Panel’ from the
sub-menu. This should start the Control Panel as shown below:
2.
Double click the ‘Display’icon and select the ‘Settings’tab as shown below.
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3.
4.
Click the ‘Advanced… ’ button. This will show the following window. Click the
‘Change… ’ button in the Adapter Type frame to select another driver. Your display will
probably have another driver then the ‘Standard PCI Graphics Adapter (VGA)’ installed
at this moment.
Click the ‘Next’to update the display driver.
User’s Manual
5.
Click the ‘Next’to continue the display driver installation.
6.
Locate the path of Graphics adapter driver and click the ‘Next’button.
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7.
8.
The driver files will now be read and the display adapter is shown as the following.
Click the ‘Next’button to install the display driver.
Click the ‘Finish’button.
User’s Manual
9.
To complete the display driver installation, reboot the computer by clicking the ‘Yes’
button in the window shown below.
10. Further configuration of the display adapter may be made from the ‘Display Properties’
window (follow step 1 above). The ‘Settings’tab allows you to change resolution, number
of colours etc.
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4.1.2
Windows 2000 Display Installation
A display driver for Windows 2000 is supplied with the system on the Supporting CD-ROM.
You could install the SiS 650/651 Video driver by Setup program or update the current
driver by Windows Update Device Driver Wizard.
The following steps show how to install the SiS 650/651 video driver by Setup program.
1. Click the ‘Start’ button on the task bar, select ‘Run’ and specify the location of SiS
650/651 Video driver setup program. This should start the SiS 650/651 Video driver
setup program as shown below:
User’s Manual
EBC-5710/5710V
User’s Manual
The SiS 650/651 Video driver installation may be performed by following steps shown
below:
1.
Start the control panel by clicking the ‘Start’ button, click ‘Settings’ and ‘Control Panel’
from the sub-menu. Double click the ‘System’icon in the control panel as shown below.
2.
On the System properties window, click the ‘Hardware’tab as shown below.
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3.
Click the ‘Device Manager… ’button to show the Device Manager.
4.
Double click ‘Video Controller (VGA Compatible)’. This will show the following window.
Click the ‘Reinstall Driver’button.
User’s Manual
5.
Click the ‘Next’button to run upgrade device driver wizard.
6.
Click the ‘Next’button to continue the video driver installation.
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7.
Select the ‘Specify a location’check item, click the ‘Next’button to continue.
8.
The directory for the drivers may now be entered or click the ‘Browse… ’button to
select the directory. Click the ‘OK’button to continue.
User’s Manual
9.
After system search the driver, click the ‘Next’button to continue upgrade driver.
10. After system install to drivers, the follow windows should appear, click the ‘Finish’
button to finish the driver installation.
11. To complete the driver installation, reboot the computer by clicking the ‘Yes’button in
the window shown below
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4.2
Driver Installation for Audio Adapter
4.2.1
Windows 9x
You could install the SiS 7012 Audio driver by Setup program or update the current driver
by Windows Update Device Driver Wizard.
The following steps show how to install the SiS 7012 audio driver by Setup program.
1. Click the ‘Start’ button on the task bar, select ‘Run’ and specify the location of SiS
7012 Audio driver setup program. This should start the SiS 7012 Audio driver setup
program as shown below:
User’s Manual
2. Select ‘SiS PCI Audio Driver’as shown below, Click ‘Next’to continue installation.
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The following steps will show you how to install the audio driver for the ‘SiS 7012 Audio ’
controller by Windows Update Device Driver Wizard.
1. Click the ‘Start’button on the task bar, select ‘Settings’ and ‘Control Panel’ from the submenu. This should start the Control Panel as shown below:
2. Double click the ‘System’icon and select the ‘Device Manager’tab as shown below.
User’s Manual
3. Select ‘PCI Multimedia Audio Device’. This will show the following window. Click the
‘Reinstall Driver’button.
4. Click the ‘Next’to update the audio driver.
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5. Click the ‘Next’to continue the audio driver installation.
6. Locate the path of Audio adapter driver and click the ‘Next’button.
User’s Manual
7. The driver files will now be read and the audio adapter is shown as the following. Click
the ‘Next’button to install the audio driver.
8. Click the ‘Finish’button.
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4.2.2
Windows 2000 Audio Installation
An audio driver for Windows 2000 is supplied with the system on the supporting CD-ROM.
1. Click the ‘Start’ button on the task bar, select ‘Run’ and specify the location of SiS 7012
Audio driver setup program. This should start the SiS 7012 Audio driver setup program
as shown below:
User’s Manual
2. Select ‘SiS PCI Audio Driver’as shown below, Click ‘Next’to continue installation.
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The following steps will show you how to install the audio driver for the ‘SiS 7012
Audio’controller by Windows Update Device Driver Wizard.
1. Start the control panel by clicking the ‘Start’ button, click‘Settings’ and ‘Control Panel’
2. On the System properties window, click the ‘Hardware’tab as shown below.
EBC-5710/5710V User’s Manual101
User’s Manual
3. Click the ‘Device Manager… ’button to show the Device Manager.
4. Double click ‘Multimedia Audio Controller’. This will show the following window. Click
the ‘Reinstall Driver’button.
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5. Click the ‘Next’button to run upgrade device driver wizard.
6. Click the ‘Next’button to continue the driver installation.
User’s Manual
7. Select the ‘Specify a location’check item, click the ‘Next’button to continue.
8. The directory for the drivers may now be entered or click the ‘Browse… ’button to select
the directory. Click the ‘OK’button to continue.
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9. After system search the driver, click the ‘Next’button to continue upgrade driver.
10. After system install to drivers, the follow windows should appear, click the ‘Finish’
User’s Manual
11. To complete the driver installation, reboot the computer by clicking the ‘Yes’ button in
the window shown below
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4.3
Driver Installation for Ethernet Adapter
4.3.1
Windows 9x
The best way to install the driver for the Ethernet controller is to use the plug and play
system of Windows 9x. The following procedures illustrate how the installation can be done.
1.
If a driver for the Ethernet controller is already installed this must be removed first. If
the Ethernet controller driver did not installed yet, it will show ‘PCI Ethernet Controller’
in System Properties. This can be done by the following steps shown below.
• Click the ‘Start’ button, click on ‘Settings’ and on ‘Control panel’ to open the
control panel.
Your display should now look as below (possibly with different size and icons):
• Double click the ‘System’icon (highlighted above).
• Select the ‘Device Manager’tab.
• If the ‘Network adapters’ line is present, expand the line and remove the PCI
Ethernet Controller adapters. This is done by selecting the line and clicking the
‘Remove’button. Or, clicking the ‘Properties’to reinstall/update driver.
User’s Manual
Before removal of the adapter(s), your screen might look like this:
• When all adapters are removed (or none were present), a new driver can be
installed.
2.
If you removed the old Network adapters, you could reboot the computer for install the
new adapter driver.
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3.
During the boot the network adapter should be detected and start to install driver
procedure or when you clicking the properties and run reinstall /update driver, system
will show as below;
User’s Manual
4.
Specify the location of network adapter and click ‘Next’(see below).
If your CPU board using Realtek RTL-8139C Network chip, the location of network
adapter are show as below.
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5.
Click the ‘Next’button.
or
User’s Manual
6.
Click the ‘Finish’button.
or
7.
Depending on the configuration, a request for the windows disks or CD-ROM may be
necessary. Insert the disk / CD-ROM and click the ‘OK’ button. An entry of the
directory for the files may then be required. After typing the path name, click the ‘OK’
button.
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8.
To complete the installation, reboot the computer by clicking the ‘Yes’ button in the
window shown below.
9.
After the system restarts, the network adapter should be installed. Protocols, clients
etc. may now be installed for the network in use.
Further configuration of the adapter may be made in the ‘Advanced’ section of the driver
properties. These options may be accessed through the ‘Network’ icon in the control panel
(Select the network adapter, click the ‘Properties’button and select the ‘Advanced’tab).
User’s Manual
4.3.2
Windows 2000 Ethernet Installation
A driver for the Intel-GD82559ER or Realtek Rtl-8139C PCI Fast Ethernet controller on
board is included in the attached supporting CD-ROM. The driver for this adapter is
denoted ’Intel GD82559ER PCI Adapter’’ or ’Realtek RTL8139(A/B/C) PCI Fast Ethernet
Adapter’.
1. Start the control panel by clicking the ‘Start’ button, click‘Settings’ and ‘Control Panel’
2.
On the System properties window, click the ‘Hardware’tab as shown below.
EBC-5710/5710V
3.
4.
Click the ‘Device Manager… ’button to show the Device Manager.
Double click ‘Ethernet Controller’. This will show the following window. Click the
‘Reinstall Driver’button.
User’s Manual
5.
6.
Click the ‘Next’button to run upgrade device driver wizard.
Click the ‘Next’button to continue the driver installation.
EBC-5710/5710V
7.
8.
Select the ‘Specify a location’check item, click the ‘Next’button to continue.
The directory for the drivers may now be entered or click the ‘Browse… ’ button to
select the directory. Click the ‘OK’button to continue.
User’s Manual
9.
10.
After system search the driver, click the ‘Next’button to continue upgrade driver.
After system install to drivers, the follow windows should appear, click the ‘Finish’
EBC-5710/5710V
11. After finish the driver installation, system will return to Properties windows as shown
below. Click the ‘Close’button to return the Device Manager.
User’s Manual
4.4
Driver Installation for SiS USB 2.0
The following steps show how to install the SiS PCI to USB Enhanced Host Controller driver.
1.
Click the ‘Start’button on the task bar, select ‘Run’ and specify the location of SiS PCI
to USB Enhanced Host Controller driver setup program. This should start the Intel
Chipset driver setup program as shown below:
2.
Press ‘Yes’to continue installation.
3.
Click the ‘Yes’button to complete the driver setup.
4.
To complete the driver installation and start the driver services, please reboot the
computer.
EBC-5710/5710V
5.
Measurement Drawing
User’s Manual
Appendix A: BIOS Revisions
BIOS Rev.
New Features
Bugs/Problems Solved
Known Problems
EBC-5710/5710V
Appendix B: System Resources
Memory Map
The following table indicates memory map of EBC - 5710/5710V. The address ranges
specif y the runtime code length.
Address Range
Description
00000000 - 0009FFFF
System board
000A0000 - 000BFFFF
PCI bus
000A0000 - 000BFFFF
SiS Accelerated Graphics Port
000A0000 - 000BFFFF
SiS 650_651_M650_740
000F0000 - 000F3FFF
System board
000F4000 - 000F7FFF
System board
000F8000 - 000FBFFF
System board
000FC000 - 000FFFFF
System board
00100000 - 1DFEFFFF
System board
1DFF0000 - 1DFFFFFF
System board
1E000000 - FEBFFFFF
PCI bus
E0000000 - E7FFFFFF
E0000000 - E7FFFFFF
SiS 650_651_M650_740
E8000000 - EBFFFFFF
EC000000 - EC0FFFFF
EC000000 - EC01FFFF
SiS 650_651_M650_740
EC100000 - EC100FFF
SiS 7001 PCI to USB Open Host Controller
EC101000 - EC101FFF
EC102000 - EC102FFF
EC103000 - EC103FFF
SiS PCI to USB Enhanced Host Controller A1
EC104000 - EC1040FF
Realtek RTL8139 Family PCI Fast Ethernet NIC
EC105000 - EC1050FF
FEC00000 - FECFFFFF
System board
FEE00000 - FEEFFFFF
System board
FFEE0000 - FFEFFFFF
System board
FFFE0000 - FFFEFFFF
System board
FFFF0000 - FFFFFFFF
System board
Note
Note:
The usage of these I/O addresses depends on the choices made in the BCM setup
screen. The I/O addresses are fully usable for PCI interface if the corresponding onboard unit is removed from the board.
User’s Manual
I/O – Map
Certain I/O addresses are subject to change during boot as PnP managers may relocate
devices or functions. The addresses shown in the table are typical locations.
I/O Port
00000000 - 0000047F
00000000 - 0000000F
00000010 - 0000001F
00000020 - 00000021
00000022 - 0000003F
00000040 - 00000043
00000044 - 0000005F
00000060 - 00000060
00000061 - 00000061
00000062 - 00000063
00000064 - 00000064
00000065 - 0000006F
00000070 - 00000073
00000074 - 0000007F
00000080 - 00000090
00000091 - 00000093
00000094 - 0000009F
000000A0 - 000000A1
000000A2 - 000000BF
000000C0 - 000000DF
000000E0 - 000000EF
000000F0 - 000000FF
00000170 - 00000177
000001F0 - 000001F7
00000274 - 00000277
00000279 - 00000279
00000294 - 00000297
000002F8 - 000002FF
00000376 - 00000376
00000378 - 0000037F
000003B0 - 000003BB
000003B0 - 000003BB
000003C0 - 000003DF
000003C0 - 000003DF
000003F2 - 000003F5
000003F6 - 000003F6
000003F7 - 000003F7
000003F8 - 000003FF
00000490 - 00000CF7
000004D0 - 000004D1
00000778 - 0000077B
Description
Note
PCI bus
Direct memory access controller
Motherboard resources
Programmable interrupt controller
System timer
Standard 101/102-Key or Microsoft Natural PS/2
System speaker
Standard 101/102-Key or Microsoft Natural PS/2
System CMOS/real time clock
Numeric data processor
Secondary IDE Channel
Primary IDE Channel
ISAPNP Read Data Port
Communications Port (COM2)
Printer Port (LPT1)
SiS 650_651_M650_740
SiS 650_651_M650_740
Standard floppy disk controller
Primary IDE Channel
Communications Port (COM1)
PCI bus
Printer Port (LPT1)
EBC-5710/5710V
I/O Port
00000A79 - 00000A79
00000D00 - 00000FFF
00001100 - 0000FFFF
00004000 - 0000400F
0000D000 - 0000DFFF
0000D000 - 0000D07F
0000E000 - 0000E0FF
0000E400 - 0000E47F
0000E800 - 0000E8FF
0000EC00 - 0000ECFF
Description
Note
PCI bus
PCI bus
SiS PCI IDE Controller
SiS 650_651_M650_740
SiS 7012 Audio Driver
Note:
The usage of these I/O addresses depends on the choices made in the BCM setup
screen. The I/O addresses are fully usable for PCI interface if the corresponding onboard unit is removed.
User’s Manual
Interrupt Usage
The actual interrupt settings depend on the PnP handler, the table below indicates the
typical settings.
Interrupt
Description
IRQ0
System timer
IRQ1
Standard 101/102-Key or Microsoft natural keyboard
IRQ2
IRQ3
Communications port (COM2)
IRQ4
Communications port (COM1)
IRQ6
IRQ8
IRQ9
System CMOS/Real time clock
Microsoft ACPI-Compliant System
IRQ12
PS/2 compatible mouse port
IRQ13
Numeric data processor
IRQ14
Primary IDE Channel
IRQ15
IRQ16
SiS 650_651_M650_740
IRQ18
IRQ18
IRQ19
Realtek RTL8139 Family PCI Fast Ethernet NIC #2
IRQ20
IRQ21
IRQ22
IRQ23
SiS PCI to USB Enhanced Host Controller A1
Note
Note:
1. The usage of these interrupts depends on the choices made in the BCM setup
screen. The interrupts are fully useable for PCI interface if the corresponding onboard unit is removed.
2. These interrupt lines are managed by the PnP handler and are subject to change
during system initialisation.
3. Disabling the hard disk controller in the BCM setup screen may not release the
interrupt line.
EBC-5710/5710V
DMA-channel Usage
The DMA circuitry incorporates the functionality of two 8237 DMA controllers with seven
programmable channels. The controllers are referenced DMA Controller 1 for channels 0-3
and DMA Controller 2 for channels 4-7. Channel 4 is by default used to cascade the two
controllers.
Channels 0-3 are hardwired to 8-bit count-by-bytes transfers and channels 5-7 to 16-bit
count-by-bytes transfers.
DMA-channel
Description
Note
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
Note:
The usage of these DMA-channels depends on the choices made in the BCM
setup screen. The DMA-channels are fully usable for PCI interface if the
corresponding on-board unit is disabled in the setup screen.
User’s Manual
Appendix C: AWARD BIOS Error Message
During the power-on self test (POST), the BIOS either sounds a beep code or displays a
message when it detects a correctable error.
Following is a list of POST messages for the ISA BIOS kernel. Specific chipset ports and
BIOS extensions may include additional messages. An error message may be followed by
a prompt to press F1 to continue or press DEL to enter Setup.
Beep
Currently the only beep code indicates that a video error has occurred and the BIOS cannot
initialize the video screen to display any additional information. This beep code consists of a
single long beep followed by two short beeps.
BIOS ROM Checksum Error – System Halted
The checksum of the BIOS code in the BIOS chip is incorrect, indicating the BIOS code
may have become corrupt. Contact your system dealer to replace the BIOS.
CMOS Battery Failed
CMOS battery is no longer functional. Contact your system dealer for a replacement
battery.
CMOS Checksum Error – Defaults Loaded
Checksum of CMOS is incorrect, so the system loads the default equipment configuration.
A checksum error may indicate that CMOS has become corrupt. This error may have been
caused by a weak battery. Check the battery and replace if necessary.
CPU at nnnn
Displays the running speed of the CPU.
Display Switch Is Set Incorrectly.
The display switch on the motherboard can be set to either monochrome or color. This
message indicates the switch is set to a different setting than indicated in Setup. Determine
which setting is correct, and then either turn off the system and change the jumper, or enter
Setup and change the VIDEO selection.
Press ESC to Skip Memory Test
The user may press Esc to skip the full memory test.
EBC-5710/5710V
Floppy Disk(s) Fail
Cannot find or initialize the floppy drive controller or the drive. Make sure the controller is
installed correctly. If no floppy drives are installed, be sure the Diskette Drive selection in
Setup is set to NONE or AUTO.
Hard Disk(s) Initializing; Please Wait a Moment...
Some hard drives require extra time to initialize.
Hard Disk(s) Install Failure
Cannot find or initialize the hard drive controller or the drive. Make sure the controller is
installed correctly. If no hard drives are installed, be sure the Hard Drive selection in Setup
is set to NONE.
Hard Disk(s) Diagnosis Fail
The system may run specific disk diagnostic routines. This message appears if one or more
hard disks return an error when the diagnostics run.
Keyboard Error or No Keyboard Present
Cannot initialize the keyboard. Make sure the keyboard is attached correctly and no keys
are pressed during POST. To purposely configure the system without a keyboard, set the
error halt condition in Setup to HALT ON ALL, BUT KEYBOARD. The BIOS then ignores
the missing keyboard during POST.
Keyboard Is Locked Out – Unlock The Key
This message usually indicates that one or more keys have been pressed during the
keyboard tests. Be sure no objects are resting on the keyboard.
Memory Test
This message displays during a full memory test, counting down the memory areas being
tested.
Memory Test Fail
If POST detects an error during memory testing, additional information appears giving
specifics about the type and location of the memory error.
Override Enabled – Defaults Loaded
If the system cannot boot using the current CMOS configuration, the BIOS can override the
current configuration is a set of BIOS defaults designed for the most stable, minimalperformance system operations.
User’s Manual
Press TAB to Show POST Screen
System OEMs may replace the Award BIOS POST display with their own proprietary
display. Including this message in the OEM display permits the operator to switch between
the OEM display and the default POST display.
Primary Master Hard Disk Fail
POST detects an error in the primary master IDE hard drive.
Primary Slave Hard Disk Fail
POST detects an error in the secondary master IDE hard drive.
Resuming from Disk, Press TAB to Show POST Screen
Award offers a save-to-disk feature for notebook computers. This message may appear
when the operator re-starts the system after a save-to-disk shut-down. See the Press
TAB ... message above for a description of this feature.
Secondary Master Hard Disk Fail
POST detects an error in the primary slave IDE hard drive.
Secondary Slave Hard Disk Fail
POST detects an error in the secondary slave IDE hard drive.
Proprietary Notice and Disclaimer
The information in this document is subject to change without notice, and should not be
considered as a commitment by Award. Although Award will make every effort to inform
users of substantive errors, Award disclaims all liability for any loss or damage resulting
from the use of this document or any hardware or software described herein, including
without limitation contingent, special, or incidental liability.
EBC-5710/5710V
Appendix D: AWARD BIOS POST Codes
Note: ISA POST codes are outputted to port address 80h
Code (Hex)
C0
Name
Description
Turn off Chipset Cache
OEM Specific-Cache control
1
Processor Test 1
Processor Status (1FLAGS) Verification. Tests the
following processor status flags: carry, zero, sign,
overflow.
The BIOS sets each flag, verifies they are set, then
turns each flagoff and verifies it is off.
2
Processor Test 2
Read/Write/Verify all CPU registers except SS, SP,
and BP with data pattern FF and 00.
3
Initialize Chips
Disable NMI, PIE, AIE, UEI, SQWV. Disable video,
parity checking, DMA. Reset math coprocessor.
Clear all page registers, CMOS shutdown byte.
Initialize timer 0, 1, and 2, including set EISA timer to
a known state. Initialize DMA controllers 0 and 1.
Initialize interrupt controllers 0 and 1. Initialize EISA
extended registers.
4
Test Memory
Refresh Toggle
RAM must be periodically refreshed to keep the
memory from decaying. This function ensures that
the memory refresh function is working properly.
5
Blank video, Initialize keyboard
Keyboard controller initialization.
6
Reserved
7
Test CMOS
Interface and Battery Status
Verifies CMOS is working correctly, detects bad
battery.
BE
Chipset Default Initialization
Program chipset registers with power on BIOS
defaults.
C1
Memory presence test
OEM Specific-Test to size on-board memory
C5
Early Shadow
OEM Specific-Early Shadow enable for fast boot.
C6
Cache presence test
External cache size detection
8
Setup low memory
Early chip set initialization.
Memory presence test.
OEM chip set routines.
Clear low 64K of memory.
Test first 64K memory.
9
EARLY CACHE INITIALIZATION
Cyrix CPU initialization.
Cache initialisation.
A
Setup Interrupt Vector Table
Initialize first 120 interrupt vectors with
SPURIOUS_INT_HDLR and initialize INT 00h-1Fh
according to INT_TBL.
User’s Manual
Code (Hex)
Name
Description
B
Test CMOS RAM Checksum
Test CMOS RAM Checksum, if bad, or insert key
pressed. Load defaults.
C
INITIALIZE KEYBOARD
DETECT TYPE OF KEYBOARD CONTROLLER
(OPTIONAL).
Set NUM_LOCK status.
D
INITIALIZE VIDEO INTERFACE
Detect CPU clock.
Read CMOS location 14h to find out type of video in
use.
Detect and initialize Video adapter.
E
Test Video memory
Test video memory, write sign-on message to
screen.
Setup shadow RAM – Enable shadow according to
Setup.
F
Test DMA Controller 0
BIOS Checksum test.
Keyboard detect and initialization.
10
Test DMA Controller 1
11
Test DMA Page Registers
12-13
TEST DMA PAGE REGISTERS.
Reserved
14
Test Timer Counter 2
Test 8254 Timer 0 Counter 2.
15
Test 8259-1 Mask Bits
Verify 8259 Channel 1 masked interrupts by
alternately turning off and on the interrupt lines.
16
Test 8259-2 Mask Bits
Verify 8259 Channel 2 masked interrupts by
alternately turning off and on the interrupt lines.
17
Test Stuck 8259’s Interrupt Bits
Turn off interrupts then verify no Interrupt mask
register is on.
18
Test 8259 Interrupt Functionality
Force an interrupt and verify the interrupt occurred.
19
Test Stuck NMI Bits (Parity / IO Check)
Verify NMI can be cleared.
1A
DISPLAY CPU CLOCK
1B-1E
RESERVED
1F
SET EISA MODE
If EISA non-volatile memory checksum is good,
execute EISA initialization. If not, execute ISA tests a
clear EISA mode flag.
Test EISA Configuration Memory Integrity
(checksum & communication interface).
20
Enable Slot 0
Initialize slot 0 (System Board).
Enable Slots 1-15
Initialize slot 1 through 15.
Size Base and Extended Memory
Size base memory from 256K to 640K and extended
memory above 1MB.
21-2F
30
EBC-5710/5710V
Code (Hex)
Name
Description
31
Test Base and Extended Memory
Test base memory from 256K to 640K Extended
Memory and extended memory above 1MB using
various patterns.
NOTE: This test is skipped in EISA mode and can be
skipped with ESC key in ISA mode.
32
Test EISA Extended Memory
If EISA Mode flag is set then test
EISA memory found in slots initialization.
NOTE: This test is skipped in ISA mode and can be
skipped with ESC key in EISA mode.
33-3B
Reserved
3C
Setup Enabled
3D
Initialize & Install Mouse
Detect if mouse is present, initialize mouse, install
interrupt vectors.
3E
Setup Cache Controller
Initialize cache controller.
3F
Reserved
BF
Chipset Initialization
40
PROGRAM CHIPSET REGISTERS WITH SETUP
VALUES.
Display virus protect disable or enable.
41
Initialize Floppy Drive & Controller
Initialize floppy disk drive controller and any drives.
42
Initialize Hard Drive & Controller
Initialize hard drive controller and any drives.
43
Detect & Initialize Serial / Parallel Ports
Initialize any serial and parallel ports (also game
port).
44
Reserved
45
Detect & Initialize Math Coprocessor
46
Reserved
47
Reserved
48-4D
Reserved
Initialize math coprocessor.
4E
Manufacturing POST Loop or Display
Messages
Reboot if Manufacturing POST Loop pin is set.
Otherwise display any messages (i.e., any non-fatal
errors that were detected during POST) and enter
Setup.
4F
Security Check
Ask password security (optional).
50
Write CMOS
Write all CMOS values back to RAM and clear
screen.
51
Pre-boot Enable
Enable parity checker.
Enable NMI, Enable cache before boot.
52
INITIALIZE OPTION ROMS
Initialize any option ROMs present from C8000h to
EFFFFh.
NOTE: When FSCAN option is enabled, ROMs
initialize from C8000h to F7FFFh.
53
Initialize Time Value
INITIALIZE TIME VALUE IN 40H: BIOS AREA.
User’s Manual
Code (Hex)
Name
Description
60
Setup Virus Setup
Setup Virus protect according to Setup.
61
SET BOOT SPEED
Set system speed for boot.
62
SETUP NUMLOCK
Setup Numlock status according to Setup.
63
BOOT ATTEMPT
Set low stack.
Boot via INT 19h.
B0
SPURIOUS
If interrupt occurs in protected mode.
B1
UNCLAIMED NMI
If unmasked NMI occurs, display Press F1 to disable
NMI, F2 reboot.
SETUP PAGES
E1 – Page 1, E2 – Page 2, etc.
E1-EF
FF
BOOT

ECM-5710 1st manual.DOC

Transcription

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