IC advanced packaging technology

IC advanced
packaging technology
Carl Chen
陳建安
Speaker introduction
學歷:
學歷
1. 英國Warwick 大學工商管理碩士.
2. 台北科技大學化學工程.
現任:
現任
1. 矽品精密公司前瞻科技中心副總經理
2. 台灣半導體產業協會IC設計委員會及生產設計
委員會副主任委員.
3. 東海大學教育諮詢委員
4. SEMI Taiwan committee委員
Contents
•
•
•
•
•
•
•
•
1. General.
2. Package mainstream 3D SiP.
3. Packaging materials.
4. TSV (through silicon via) technology.
5. Roadmap of packaging.
6. Material engineering JD.
7. High tech people characteristic.
8. Conclusions.
SPIL ASSEMBLY PLANT
TF Site
Pkg: P-DIP, SOJ, SOP & SSOP
Space: 72K SQ.FT
DF-A & DF-B
Pkg: PLCC, QFP, SO, TSOP, BGA
Space: 470K & 243K SQ.FT
CS-A & CS-B
Pkg: CSP, BGA , TCP , Bumping, Flip Chip,
Space: 831K SQ.FT
DF-C
Bumping, R&D , Administration
Space: 157K SQ.FT
CS-C
Pkg: BGA
Space: 605K SQ.FT
SPIL TESTING PLANT
Space:174k SQ FT
Tester: 86 sets
. HP83000 / HP93000
. ITS9000 / EXA3000
. J973 / Catalyst
HS-1
SQ FT
. Space:116k
J750
Tester: 49 sets
.Quartet
. HP93000
. SC312
. SC212
. J750
. VV
. Yokogawa
HS-2
CS-B
Marketing Demand
Portable / Communication / Storage
(light/thin/short/small)
Systems Integration in the Cell Phone
Source : H.Ueda JEITA
Small Form Factor
SiP for Flash Memory Cards
MMC
micro
Micro
SD
MS
micro
Standard Package (TSOP)
for CF / SD card etc.
Economic barrier
•GlobalFoundries CEO Doug Grose said「除了技
術挑戰，產業持續創新的最大障礙在於經濟學。」
•USD億
技術開發成本
Fab 廠成本
90/65nm
45/32nm
22/12nm
3~4
6~9
13
25~35
35~40
45~60
Note: GlobalFoundries本身已是IBM「晶圓廠俱樂部」的一員
Reasonable device (NIKKEI) (I)
先進國
高級品市場
先進國普及品,
新興國的高級品市場
新興國的
普及品市場
1998年期間的G7時代電子機器市場
現在的G20時代電子機器市場
Reasonable device (NIKKEI) (II)
今後的市場構造
從前的市場構造
新興國的普及品市場
市
場
規
模
先進國的
高級品市場
市
場
規
模
先進國的高級品市場
先進國的
高級品市場
價格
價格
Integrated fabless model (IFM)
•Jim Clifford, SVP and GM of Qualcomm said.
•"Fabless companies are good at development, not research,"
Thus, integrated ecosystem should involve the fabless,
foundry, test, packaging, IP, EDA and the final customer.
ITRS Semiconductors roadmap
18-inch (450mm) can shorten CT to 50% and cost down 30% per wafer, the
scale of manufacturing is double of 12 inch fab, this kind of huge capacity
should support by large volume products and large foundry firms, such as
Memory、CPU、partial Logic devices companies and foundry firms. may
only CPU-Intel、Memory-Samsung and Toshiba，Fab-tsmc can enter this
field.
Few IDMs can go to 32/22nm
•英特爾(Intel)創辦人Gordon Moore自1960年代提出摩爾定律至今，半導
體產業的技術演進可謂完全遵循摩爾定律的速度發展, 2014年後摩爾
定律可能失效. 現階段還能維持摩爾定律的業者只剩英特爾、三星電
子、東芝(Toshiba)、德儀(Texas Instruments)及意法半導體5家
Value Chain - Semiconductor
Design
Design House
IC Design
Test
Program
Bump
Wafer Sort
Assembly
Final Test
Fab.
Bumping
Probing
Assembly
Final Test
Wafer
Fab
Bumping
Fabrication
Materials
Fab
Wafer
Sort
Assembly
Board Assembly/EMS
B/L Assembly
Board
Final
Test
Insertion &
Assembly
Wafer
Die
Bin
Assembly / Test
ASE
Intel / IBM / Samsung / Toshiba
Board
Testing
Board
SPIL SERVICE
ASSEMBLY
• Substrate /
Leadframe
Design
Design &
Development
• Probe card
• Load board
• Test program
conversion
-- Sort
-- Final Test
TESTING
• Characterization
• Reliability
Validation
Prototype
• RDL
• Bumping
Wafer
Bumping
(Flip Chip)
• Hardware /
Software
optimization
• Yield enhancement
• SPC control
• Cycle time reduction
• Failure analysis
Wafer
Sort
Assembly
Final
Test
Drop
Ship
Level of packaging
• Level 1: Single chip IC or multi-chip
packaging (MCM).
• Level 2: Card or PCB.
• Level 3: Mother Board or System.
Traditional Package Portfolio
SO Family
SOJ
SOP
DDTSOP
LOC TSOP
TSOP
VSOP
QFP Family
QFP
EDHS-QFP
DHS-QFP
DPH-QFP
Stack Die QFP
L/T/VQFP
E-Pad L/TQFP
BGA Family
PBGA
EDHS-BGA
Stack Die BGA
EBGA
FCBGA
EHS-FCBGA
CSP Family
QFN
W/B CSP
Stack Die CSP
COS
FCCSP
UCSP
FCCSP
Memory Card
Family
MS/MS DUO
SD
MMC
XD
RSMMC
Mini SD
Transflash
Other Family
OLCC/CLCC for CIS
CIS Module
TCP
COF
IC Moore’s law
SIP vs. SOC
Source : Fraunhofer IZM
SOC/SiP/Packaged IC
Packaging
Packaged IC
SiP
Hybrid
IC
SOC
system
Wafer technology roadmap (ITRS )
• Wafer Technology node:
Tech node/Year
2009
2010
2011
2012
2013
Dram (nm)
50
45
40
--
32
Nand flash (nm)
40
--
32
28
--
Nor flash (nm)
65
45
40
--
32
MPU/ASIC (nm)
50
45
40
--
32
Wafer size (mm)
300
300
300
450
450
Enabling TSV tech. to products guide line
Source : Yole Developpment,2008
Core Competence
TSI
Pressure sensor
F2F BGA
u-Bump + RDL + WB
TSV
μ-bump
WL-MEMS
WB
Bump
& FC
RDL
FO-WLP
IPD
IPD
RF-Module
Future Products from ITRS
•SiP for Tera-scale computing
•Co-Design tools
•Optoelectronic Packaging
•RF and Millimeter wave packaging
•Medical and BioChip Packaging
•MEMS/MOEMS Device Packaging
•Printed Electronics
•Active Flexible Electronics
•Automotive Electronics
•Solar Cell Packaging
•Embedded and Integrated actives and passives
•Environmental Issues
•Equipments for emerging packaging
•RF/AMS Wireless
Packaging technology
mainstream
3D SiP
Category of SiP
RF/WLAN……
RF/WLAN……
MCM/MCP
SiP
Modules
(Active + Passive)
TSV
FC+WB
Wire Bonding
PoP/PiP
Stacked Die Packages
3D packaging
Chip / Component Configuration
Side by Side
Placement
Technology
Substrate:
organic laminate, ceramic, glas, silicon, leadframe
Chip Interconnection:
wire bond and/or flip chip
+ passive components
Stacked
Structure
PoP
PiP
stacked die
wire bond, WB +FC
chip to chip / wafer
Embedded
Structure
integrated into the substrate
discrete (CSP, SMD)
flip chip, face to face
through silicon
WL 3D stack
wafer to wafer (W2W)
Chip in PCB / polymer
single layer
multi-layer 3D stack
WL thin chip integration
single layer
stacked functional layers
Definition of SiP
• System in Package (SiP) :
A combination of multiple active electronic
components of different functionality,
assembled into a single unit, that provides
multiple functions associated with a system
or sub-system.
An SiP may optionally contain passives,
MEMS, optical components and other
packages and devices.
Pros for SiP
•
•
•
•
•
•
•
•
•
•
•
•
•
•
short time to market
different front-end technologies can be used (Si, GaAs etc.)
use of devices from different generations
re-use of common devices
trade-off between PoP, stacked die
reduced NRE relative to SoC
decreased size relative to other package types
embedded devices both active and passive can be incorporated
individual SiP components can be upgraded as soon as they are available it
allows individual system components to be in the best available technology
(with the cheapest mask set cost)
for the smaller chiplets the separate yields are better
it can be allowed for certain IP blocks (analog, RF) multiple design passes
to ensure functionality without to pay full overall mask set
the density and delay characteristics of interconnects could be better than of
on chip interconnects
it can have better noise isolation and smaller substrate coupling
SiP may incorporate one or more SoC devices
Development Flow
• 1. System design/SiP configuration.
a. System partition, function, consumable power
b. Cost, DFM, DFT.
c. Pin assignment, chip size, pad coordination.
• 3. SiP design.
a. Circuit design.
b. Structure design.(WB, FC, layout, H/V)
c. Thermal design.(DRAM temp. constrain)
d. Substrate (interposer) design.
e. Testing design(content optimization)
• 4. Trial run. (problems early finding and feedback)
• 5. Function check.
• 6. Reliability evaluation.
• 7. Ramp up
• 8. Mass production.
Conventional packaging flow
IQC
Back
Grinding
Die Saw
Die Bond
Plasma
clean
Wire Bond
Molding
OQC
Shipping
Singulation
Marking
Solder Ball
Placement
Post Mold
Cure
SPIL Leading
Wafer Thinning Technology
BG Tape
Laminator
Grinder
Polisher
DDAF : Dicing Die Attach Film
DDAF
Attach
Dicing
Frame
Mounter
BG Tape
Remove
Die
Dicer
Dicing Die Attach Film
Wafer
Saw
Blade
Heat Block
WBL
Tape
Bonder
Chip
Mount tape
Wafer thinning processes
Inline system
DGP
Grinding wheel
Back grinding
DFM
DP wheel
Dry Polishing
DAF
Laminating
Frame
Mounting
BG Tape
Peeling
BG machine
Dicing
Saw
Blade
Chip
WBL
Tape
Mount tape
Materials
• Tape and Blade
Structure
Tape
1.
2.
Blade
Feature
Base: Poly olefin. Before exposure:
T=100um
•
250g/25min
Adhesive 10um. •
20g/25min.
Bonder: Ni
Width:30~35um.
Diamond grain size:
2~6um.
Challenges of Low K
• Challenges of Low-k wafer in FC
packaging
– Mechanical properties of stacked dielectric
layers to resist external stress during
packaging
– Low stress underfill need to be selected to
prevent low-k layers from crack or
delamination.
• Engineering tasks need to be addressed
– Die saw : passivation/metal peeling …
– Materials combination: underfill …
Laser vs. conventional
Low-K Process
Street width
Si
Low-K layer
Laser trimming
Second step
Z1 blade
Z1 blade
Z2 blade
Si
Si
Tape
Tape
Full cut blade dicing
(Step cut )
(One pass cut )
Low k crack
*
Low k crack
Die Attach on metal L/F or Organic substrate
Die attach
• Die-attach film became popular as a die-attach adhesive
because of its uniform thickness, compatibility with the
existing assembly process, and bleed-free
characteristics.
• many dice are stacked each other, the thickness of the
die-attach adhesives are not negligible. The thickness of
the die-attach film is requested to be thinner but still
capable of filling the indented pattern surface of the
substrate.
• The die-attach film is capable of embedding bonding
wires in the film bulk during the die-attach process.
Concerns in die attach
• Concerns:
Thin wafer <50um
Chip strength downgrade
Thin package ~0.7mm
Chip warpage
Multi-die stack ~7 dies
Thin DB paste and
uneven
DB paste low corrosion
New tech node:
Cu wafer
Lead-free
260C reflow
Lower resistance
Why Film Over Wire ?
X, Y dimension issue
Z dimension issue
FOW X-section Photos
26um
27um
71um
250um
25um
71um
72um
Wirebond
Wire bond
• The requirements is lower loop control, less impact to the over hung
die.
• The lower loop-control by the reverse bonding technology. It is
composed of the stud-bump attach on a die as the first bond,
bonding on a finger as the second bond, and then bonding on the
stud bump as the third bond, it slows down the bonding throughput.
• New lower loop-control sequences are like the pad bond first and
then crashing the standing loop and force it to horizontal loop, then
bond on a finger as the second bond. This machine time is almost
equivalent to that of normal bonding, and the loop height is less than
that of the reverse bonding sequence.
• Insulation wires have been studied, but still unsuccessful to see
enough bondability and reliability to put into commercial base.
• For low k dielectric layer and over hang die, less impact bonding can
be achieved by the bonding conditions and the machine
performances.
Wire Bonding
Low-loop wire bonding technology :
Normal Bond
Loop Height :110~500 um
Reverse Bond
40~75 um
Ultra Low Loop
40~75 um
Low Loop Wire Bonding
9 dies package
Package: 9 Die (4GB/8GB) Micro SD / MS Micro
Die size : 265*528 * 1.8 mil ( Flash Memory die )
148*172* 1.8 mil ( Controller die )
Film thickness : 60um
Au wire : 0.8~1.0 mil
Substrate: 0.13 mm, 2L
Flip Chip =
Bumping +Substrate
FCBGA Process Flow
Wafer
receive
Wafer
bumping
Wafer
saw
Substrate
Loading
Marking
Lid
Attach
(option)
Ball
attach
FVI
Molding
& Curing
Packing
Flip Chip
Die bond
Flip chip interconnection
Good electrical performance, high speed and
density, and compact.
1.
2.
3.
4.
5.
6.
Au+solder Au-Sn alloy (Au stud bump + pre-coat
solder on substrate + UF--- small pitch <50um)
Solder alloy. (Solder bump --- High pin)
Ultrasonic.(Au bump, for low cost, chip on chip –
pitch 80um)
Polymer ACF (Au bump + anti-conductive film)
Copper column is used especially for fine pitch
applications
Underfill-applying methods: after flip-chip attach or
applying before flip-chip attach
Plating Bumping Flow
Process
PSV
Final
Pad
Silico
n
Wafer IQA
Ni / Solder Plating
Photoresist Strip
BCB/PI
photo
UBM Deposition
UBM Etching
Final Visual
Photoresist Photo
Flux Reflow & Flux
Clean
Pb Free Bumping
Bumping on Pure Cu Pad
Cu Pad Pretreatment
Pb Free Solder Bumping (SnAgCu & SnAg)
- Printing : (Sn/Ag/Cu, Sn/Ag)
Production:Sn/3.5Ag/0.75Cu, Sn/3Ag/0.5Cu Sn/3Ag/0.5Cu Sn/2.5Ag available
- Plating : (Sn/2.5Ag)
Cu post bump
*
<< Fine Pitch and High Power Solution >>
Bump Pitch -200um
Solder Bump
-150um
-100um
Cu Post Bump
Solder
(EU/LF)
Solder
Cu post
UBM
UBM
(Ti/Cu)
Ni
Pb-free Bump Challenges
• No “standard” Pb-free bump material defined yet.
– Sn-Ag-Cu and Sn-Ag bump were widely proposed by
bumping houses.
– Sn-Cu bump was proposed by Motorola due to lower
creep strength than Sn-Ag-Cu and Sn-Ag.
• Process: Flux and reflow profile need to be studied.
• Reliability:
– UBM consumption
– Solder bump fatigue life
– Delamination between UF and PI/BCB/die/sub
Pb-free Bump Meet Low-k….
• Challenges:
• Possible Solutions
– PI passivation/new UF/lower CTE sub
– Sn-Cu bump
– New package structure
Molding
Molding
• Thin-body molding, less wiring sweep, longer wiring, free from
void.
• Transfer molding: transferring mold compound from the gate
located at the center of the die, the melted mold compound flows
radiationally.
(to minimum package cost: maximize the number of devices on a
substrate strip is needed, then, gate molding is not appropriate for
SiP).
• Compression molding: places necessary amount of molding
compound in the cavity, heating up, placing the substrate strip on,
clamping and providing the pressure to the molding compound.
(This technology causes a little movement of the melted molding
compound, good for longer wire length, package body thinner,
accepting larger number of die on a strip).
Solder ball placement
Concerns:
• Height and coplanarity.(<30um).
• Variations come from
1. Substrate warpage.
2. Land dimension precision. (solder register
+-1um).
3. Solder volume. (φ+-10um)
Flux
• To activate the surface and hold solder
ball locate in the position temporary.
• With halogen flux + clean is general
process.
• Resin / water soluble and non-clean
type is option.
• The MP of Lead-free is higher, HT
resistant flux is prefer.
• Flux soluble solvent selection
• The volume of flux control.
Reflow
•
•
•
•
•
•
1. IR
2. Hot air
3. 6, 8 or 7 heat zone/2 cool zone.
4. Even temperature distribution.
5. Temperature profile control.
6. N2 gas surge, prevent oxidation.
Packaging materials
Semiconductor
•
•
•
•
•
•
•
1. Si (Graphene, Diamond).
2. Ge.
3. GaAs
4. GaSb
5. InP
6. InAs
7. InSb
IC Package Material Classification
Carrier Material
-Substrate
-Lead Frame
Polymer material
-Molding Compound
-Underfill
-Silver paste
-Die attach film
-Thermal interface
material(TIM)
IC package
material
Metal Material
-Gold Wire
-Solder Bump
-Solder Ball
IC packaging materials
•
•
•
•
•
•
•
•
1. Protection.
2. Interconnection.
3. Heat dissipation.
4. Reliability.
5. Structure.
6. Processing.
7. Supporting.
8. Indirect materials
Note: Good packaging is no packaging.
Carried Material
1.Lead frame
-Cu: C151, C194 and C7025
2.Substrate
-Ceramic
Cu
-Alloy: Fe-42Ni
-Plastic
Alloy
Function
-Redistribution between Chip and PCB
-Chip carrier
-Thermal dissipation
-Standard package size formation
Metal Material
1.Gold Wire(2N/4N)
3.Solder Ball(Sn-Ag-Cu)
Solder
ball
substrate
2.Solder Bump(Sn-Ag/Sn-Cu)
Function
-Interconnection between chip and L/F or
substrate
-Interconnection between package and
PCB
Polymer Material
-Gold wire protection
Molding compound
-Chip protection
-Solder bump protection
Underfill
Resin
+
• Epoxy
•Amine
• Phenol
• Anhydride
Filler
•Ag
•Teflon
•SiO2
•Al2O3
•Cu
Silver paste/Die attach film
-Chip protection
-Fix chip on substrate or L/F
-Thermal dissipation
Thermal interface material
-Fix heat sink on die
-Thermal dissipation
•Silver paste
•Molding compound
•Underfill
PGBA Substrate Material
Structure: 2 Layer
Ni/Au plated
Cu Plated
Cu Foil
BT Core
Solder mask
PTH
Structure: 4 Layer
Ni/Au plated
Cu Plated
Cu Foil
BT Core
Inner Cu foil
BT prepreg
Solder mask
PTH
PBGA Substrate Process
3.鍍銅
2.鑽孔
1.基材
BT樹脂
4.乾膜(曝光/顯影)
7.綠漆網印
銅箔
5.蝕刻
6.剝膜
8.鍍Ni/Au
Ni/Au層
Good material
•
•
•
•
•
•
1. Environmental friendly.
2. Compromised interface interaction.
3. Low stress and strain.
4. Functional as aspect.
4. Low cost.
5. Long life and reliable.
• Note: Good material is violate its nature.
Material vs. Process
•
•
•
•
•
1. Workability.
2. High throughput.
3. Friendly to processing environment.
4. Good health to human.
5. Safety.
• Note: Good transition without any impact.
Failure mechanisms
• 1. Stress and strain associated with CTE
mismatch
• 2. Interfacial delamination
• 3. Material (organic or metallic) coherent
crack
• 4. Intermetallic formation, diffusion and
delamination or coherent crack
• 5. Electromigration
• 6. Thermal migration
TSV
What is TSV
■ Through Silicon Vias (TSV)
◆ Create interconnections by
using vias, which go
through the silicon wafers
to form 3D IC
◆ Z-direction integration
Source: Intel , Samsung, University of Alberta.
Why TSV?
Source: Yole development
3D-TSV Technology Platform (2013)
Silicon interposer
Heterogeneous TSV Package
Yole (June 2008)
TSV-WLCIS
2013 for TSV technology platform
Heterogeneous TSV Package : 59%
WLCIS : 23%
Interposer : 18%
TSV Process Flow
Via etch
Over burden
removal
Via Isolation
Barrier/seed dep.
Wafer Thinning
Assembly
Micro bump
Formation
Via Filling.
Micro bump
Bonding
Micro Bump
Bump pitch = 25 um
Bump Diameter = 16 um
Sn 4 um
+
Cu 6 um
25um
Summary
• 1. Packaging innovation enables “more than
Moors”
a. 3D packaging technologies.
b. Scaling through functional diversity.
• 2. Consumer market demand drives innovation
in packaging. --- Size, weight, power, cost,
perfomance, time to market.
• 3. New materials and architectures are required
to meet today’s market demands, but, will
enable many future advanced packaging.
END
Thank you