Preliminary H7A36QP

Transcription

Preliminary H7A36QP

Preliminary
H7A36QP
OTP-256K Audio Codec Processor
Feature
 Built-in enhance 8 bits DSP Core (Jupiter-X instruction
set, improve 16 bits operatings).
 Internal operation frequency up to 48 MHz (Typical 40
MHz).
 Compatible with H244QP.
 Built-in 256K bits (32K bytes) OTP.
 Built-in 20.5K bytes SRAM.
 Built-in R/C trimming (1% Error) for base clock & digital
variable frequency control PLL circuit.
 Built-in VREF trimming for ADC.
 Built-in 32768 XTAL oscillator circuit. This function is
option with I/O pin.
 Built-in 4M Hz XTAL oscillator circuit. This function is
option with I/O pin.
 External clock source (4M – 32M Hz) for operation.
 Built-in 16 analog paths & internal VREF for 16 bits high
resolution ADC input select.
 Built-in 3 sets of 16 bits ADC converter for processing
microphone array (ADC accuracy 12bit) .
 Built-in 2 sets of 8-bit timer and 1 set of 16 bits timer,
and the 16-bit timer can be programmed as
Timer/Counter/Compare/Capture function with I/O pin.
 Built-in microphone differential input pre-amplifier
circuit, include AGC (Auto Gain Control) function.
 Built-in microphone 16 levels gain control function.
 Built-in 1 sets of 8/10 bits programmable PWM
generator.
 Built-in 16 bits Signed/Unsigned multiplier.
 Built-in ∑{ [(Xi ± Yi) * Zi]² } high performance arithmetic
block.
 Built-in 24 independent I/O, and there are16 I/O
containing interrupt function.
 Built-in 4 high sink I/O (40mA).
 Built-in low voltage reset function (LVR).
 Built-in watch dog timer function (WDT).
 Built-in NAND Flash interface.
 Built-in SBus Master/Slave serial interface.
 Built-in SPI Master/Slave serial interface.
 Built-in two 16-bits high resolution DAC( + 5-Bits
Multi-Level).
 Built-in EQ-OP for mixer or filter purpose design.
 Built-in class AB/D/PWM 8/0.5W circuit, direct drive
speaker or buzzer device with 16 levels control.
 Built-in Earphone/Speaker two type driving mode
function.
 Digital block operation voltage range in 2.4V-3.6V.
 Analog block operation voltage range in 2.4V-4.5V.
 Power down current < 3.0uA.
Description
The H7A36QP is compatible with H244QP, and
There are NAND interface and SPI bus for
provides more powerful analog device and digital
interfacing to the external storage, and 2-wire serial bus
mathematic circuit. It features the microphone input and
for linking with the other device or MCU.
differential amplifier for high quality audio input and high
For voice input, the H7A36QP also equips the
resolution ADC for analog sampling.
differential amplifier for microphone input and AGC (auto
The H7A36QP equips a math-processor (II) for
gain control) for good SNR voice signal input.
processing the mathematical algorithms that can be
Not only the good pre-amplifier is embedded but
implemented to a high-compressed speech encoder and
also the high-end delta-sigma DAC and class-AB speaker
decoder or the speech recognition …etc.
amplifier can drive and output the high-quality sound.
Block Diagram
1
Preliminary
H7A36QP
Pin Signal
Pin Signal Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Designation
EQ_I
L_DAC
R_DAC
GAIN_CO
GAIN_CI
AVCC
MIC_P
MIC_N
AGND
AGC_CTRL
DS_FI
DS_FO
PORT27
PORT26
PORT25
PORT24
VCC
GND
PORT23
PORT22
PORT21
PORT20
/RESET
PORT17
PORT16
PORT15
PORT14
PORT07
PORT06
PORT05
PORT04
GND
VCC
PORT03
PORT02
PORT01
PORT00
PORT13
PORT12
I/O
I
O
O
O
I
P
I
I
P
O
I
O
I/O
I/O
I/O
I/O
P
P
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
P
I/O
I/O
I/O
I/O
I/O
I/O
Description
OP-EQ N Input.
Left DAC.
Right DAC.
MIC Gain OP-O Output.
MIC Gain OP-N Input.
System Analog Power Supply.
MIC-P Input.
MIC-N Input.
System Analog Ground.
MIC AGC Control.
ADC Filter Input.
ADC Filter Output.
Port-2 I/O 7, 32768 XTAL_O.
Port-2 I/O 6, 32768 XTAL_I.
Port-2 I/O 5, 4M XTAL_O. Ext Clock In.
Port-2 I/O 4, 4M XTAL_I.
System Core Power Supply.
System Power Ground.
Port-2 I/O bit3, 40mA.
Port-2 I/O bit2, 40mA, NAND Flash CEB.
Port-2 I/O bit1, 40mA, CLKO.
Port-2 I/O bit0, 40mA, PWM.
System Reset.
Port-1 I/O bit7, NAND Flash REB.
Port-1 I/O bit6, NAND Flash WEB.
Port-1 I/O bit5, NAND Flash CLE.
Port-1 I/O bit4, NAND Flash ALE.
Port-0 I/O bit7, NAND D7.
Port-0 I/O bit6, NAND D6.
Port-0 I/O bit5, NAND D5, Motor-C L.
Port-0 I/O bit4, NAND D4, Motor-C H.
System Power Ground.
System Core Power Supply.
Port-0 I/O bit3, NAND D3, Motor-B L.
Port-0 I/O bit2, NAND D2, Motor-B H.
Port-0 I/O bit1, NAND D1, Motor-A L.
Port-0 I/O bit0, NAND D0, Motor-A H.
Port-1 I/O bit3, MISO/SPI Mode.
Port-1 I/O bit2, MOSI/SPI Mode.
2
Preliminary
H7A36QP
40
41
42
43
44
45
46
47
48
PORT11
PORT10
VPP
SPK_P
AGND
AVCC
SPK_N
AMP_IN
EQ_O
DC Characteristic
I/O
I/O
P
O
P
P
O
I
O
Port-1 I/O bit1, SSB/SPI Mode. SDA/SBus Mode.
Port-1 I/O bit0, SCK/SPI Mode. SCL/SBus Mode.
System OTP Power Supply.
Speaker P Connect.
Speaker Power Ground.
Speaker Power Supply.
Speaker N Connect.
AMP Input.
OP-EQ Output.
(VCC = 3.0V, VDD = 3.0V, GND = 0V, TA = 25℃)
Symbol
P00-P07
P10-P17
P20-P23
L_DAC
R_DAC
EQ_O
P24-P27
SPK_P
SPK_N
P00-P07
P10-P17
L_DAC
R_DAC
EQ_O
P20-P23
Parameter
P24-P27
SPK_P
SPK_N
I_STD
Min.
Typ.
Max.
Unit
Condition
Driving Current
4
mA
VOH=2.7
Driving Current
1
mA
VOH=2.7
Driving Current
250
mA
RL=8
Sink Current
4
mA
VOL=0.3
Sink Current
40
mA
VOH=2.7
Sink Current
1
mA
VOH=2.7
Sink Current
250
mA
RL=8
Standby Current
0.2
0.5
50
2
uA
Memory Map Allocate
000000H
000200H
000400H
009800H
00A000H
00B000H
010000H
–
–
–
–
–
–
–
0001FFH
0003FFH
0083FFH
009FFFH
00AFFFH
00FFFFH
FFFFFFH
: SRAM Data Space (Mapping 512B SRAM).
: Control Registers.
: OTP Program/Data Space.
: NAND Flash Access Space.
: SRAM Data Space(Mapping 20K SRAM).
: Reserved.
There are two modes for MTR setting.
CPU MTR Compatible Mode (compatible with H244QP):
000000H –
0001FFH
MTR[1:0] :
Mapping 512B SRAM Space.
MTR[4:2] :
OTP Space.
MTR[7:5] :
Mapping 20K SRAM/NAND Flash Space.
CPU MTR Advance Mode:
000020H –
0001FFH
MTR[0] : Mapping 512B SRAM Space.
MTR[1] : Mapping 20K SRAM Space.
MTR[4:2] :
OTP Space.
MTR[7:5] :
NAND Flash Space.
3
Preliminary
H7A36QP
Control Register Description
MSB
LSB
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
0010H
0011H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
001AH
001BH
001CH
001DH
001EH
001FH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Math-X Pointer Low-Byte
Math-X Pointer High-Byte
Math-Y Pointer Low-Byte
Math-Y Pointer High-Byte
Math-Z Pointer Low-Byte
Math-Z Pointer High-Byte
Math-i Pointer Low-Byte
Math-i Pointer High-Byte
Math Control Byte-0
Math Control Byte-1
Math Control Byte-2
Math-Item Low-Byte
Math-Item High-Byte
Math Result Byte-0
Math Result Byte-1
Math Result Byte-2
Math Result Byte-3
Math Result Byte-4
ADC-2 Low-Byte
ADC-2 High-Byte
Left-DAC Low-Byte
Left-DAC High-Byte
Right-DAC Low-Byte
Right-DAC High-Byte
X-Pointer Data Low-Byte
X-Pointer Data High-Byte
Y-Pointer Data Low-Byte
Y-Pointer Data High-Byte
ZY/Z-Pointer Data Low-Byte
ZY/Z-Pointer Data High-Byte
YX-Pointer Data Low-Byte
YX-Pointer Data High-Byte
0200H
0201H
0202H
0203H
0204H
0205H
0206H
0207H
0208H
0209H
020AH
020BH
020CH
020DH
020EH
020FH
0210H
0211H
0212H
0213H
0214H
0215H
0216H
0217H
0218H
0219H
021AH
021BH
021CH
021DH
021EH
021FH
0220H
0221H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
System Control
IRQ Enable
IRQ Status
DAC/PWM Control
Left-DAC Low Byte
Left-DAC High Byte
Right-DAC Low Byte
Right-DAC High Byte
Timer Control
Timer-0 Reload
Timer-0 Data
Timer-1 Reload
Timer-1 Data
Port-0 IRQ Mask
Port-0 IRQ Edge
Port-0 IRQ Status
Port-0 I/O Mode
Port-0 Pull-High Mode
Port-0 Data
Port-1 I/O Mode
Port-1 Data
Port-2 I/O Mode
Port-2 Data
Serial Control
Serial Mode-1
Serial Mode-2
Serial Status
Serial TX
Serial RX
Watch-Dog Control
Advance System Control
DPLL Control
4
Preliminary
H7A36QP
0222H
0223H
0224H
0225H
0226H
0227H
0228H
0229H
022AH
022BH
022CH
022DH
022EH
022FH
0230H
0231H
0232H
0233H
0234H
0235H
0236H
0237H
0238H
0239H
023AH
023BH
023CH
023DH
023EH
023FH
R/W
R/W
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC Control Low Byte
ADC Control High Byte
ADC0 Low Byte Data
ADC0 High Byte Data
ADC1 Low Byte Data
ADC1 High Byte Data
ADC2 Low Byte Data
ADC2 High Byte Data
Motor Control
Motor Mode
Motor Duty
Interpolation Control
Extra System Control
XControl Byte-0
XControl Byte-1
XControl Byte-2
Volume Control
Port-1 IRQ Mask
Port-1 IRQ Edge
Port-1 IRQ Status
Timer-2 Control Byte-0
Timer-2 Compare Low-Byte
Timer-2 Compare High-Byte
Timer-2 Data Low-Byte
Timer-2 Data High-Byte
PWM Control
PWM Duty
 ADC Control
0300H
0301H
0302H
0303H
0304H
0305H
0306H
0307H
0308H
0309H
030AH
030BH
030CH
030DH
030EH
030FH
0310H
0311H
0312H
0313H
0314H
0315H
0316H
0317H
0318H
0319H
031AH
031BH
031CH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Math Control
Multi/Divid Low
Multi/Divid High
Multied Low/Multi-Sum Byte-0
Multied LHighMulti-Sum Byte-1
Multi-Sum Byte-2
Multi-Sum Byte-3
Divided Byte-0/Quoation Low
Divided Byte-1/Quoation High
Divided Byte-2/Remain Low
Divided Byte-3/Remain High
Math-X Pointer Low-Byte
Math-X Pointer High-Byte
Math-Y Pointer Low-Byte
Math-Y Pointer High-Byte
Math-Z Pointer Low-Byte
Math-Z Pointer High-Byte
Math-i Pointer Low-Byte
Math-i Pointer High-Byte
Math Control Byte-0
Math Control Byte-1
Math Control Byte-2
Math-Item Low-Byte
Math-Item High-Byte
Math Result Byte-0
Math Result Byte-1
Math Result Byte-2
Math Result Byte-3
Math Result Byte-4
0380H
0381H
0382H
0383H
0384H
0385H
0386H
0387H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X-Pointer Data Low-Byte
X-Pointer Data High-Byte
Y-Pointer Data Low-Byte
Y-Pointer Data High-Byte
ZY/Z-Pointer Data Low-Byte
ZY/Z-Pointer Data High-Byte
YX-Pointer Data Low-Byte
YX-Pointer Data High-Byte
9800H R/W
0
0
0
0
0
0
0
0
NAND Flash Data
5
Preliminary
H7A36QP
9900H
9A00H
9C00H
9D00H
9E00H
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
系統預設值0
1
系統預設值1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NAND Flash Command
NAND Flash Address
NAND Flash Data (Hold)
NAND Flash Command (Hold)
NAND Flash Address (Hold)
系統預設值
系統使用到此位元但沒有預設值
系統保留(未使用)
0200H
System Control Register (SCR)
Bit No.
Bit Name
Read/Write
Reset
7
Base Clock
Oscillation
Control
R/W
1
0200H , System Control Register (SCR)
6
5
4
3
System Clock AMP Enable
SBUS/SP
16-bit DAC
Select
Interface
Output
Control
Control
R/W
R/W
R/W
R/W
1
0
0
0
2
PWM Output
Enable
1
Free-OP
Control
0
HVcc Enable/
Disable
R/W
0
R/W
0
R/W
0
[7] Base Clock Oscillation Control: This bit is used to enable/disable the R/C oscillation circuit.
 0 = R/C oscillation circuit is disabled in power_down mode, no base clock generated to save the power
 1 = Normal Condition, the R/C oscillation is enabled with generation of base clock
[6] System Clock Select: This bit is used to select the source of system clock.
 0 = Select base clock (typically 1.86 MHz) as the system clock
 1 = Select the DPLL clock (typically 40 MHz) as the system clock
[5] AMP Enable: This bit is used to enable/disable the embedded amplifier for speaker/buzzer output.
 0 = OP Amp is disabled.
 1 = OP Amp is enabled.
[4] SBUS/SP interface control: This bit is used to enable/disable the interface of Serial Mode & Serial/Parallel Mode.
 0 = SBUS/SP interface is in reset state.
 1 = SBUS/SP interface is enabled.
[3] 16-bit DAC output control: This bit is used to enable/disable the DAC output.
 0 = DAC output is disabled.
 1 = DAC output is enabled.
[2] PWM output enable: This bit is used to enable/disable the PWM output.
 0 = PWM output is disabled.
 1 = PWM output is enabled.
Note that this bit is only valid and PWM can be output correctly under the following condition:
-- Bit 1 “PWM Work Enable” of DPCR (0203H) is set.
-- PWM data should be written to LDACR register.
-- Bit 5 “AMP Enable” of SCR register is set. Control 0200H [5]”
[1] Free-OP Control: This bit is used to enable/disable the free operational amplifier.
 0 = Free-OP Amp is disabled for power-saving.
 1 = Free-OP Amp is enabled.
[0] HVcc Enable/Disable: This bit is used to enable the OP+ input of free OP-Amp to use the internal 1/2 Vcc
source.
 0 = half Vcc is not used as source of OP+.
 1 = half Vcc is used as source of OP+.
Interrupts Control
There are 6 kinds of interrupt sources to H244QP as listed below
(1) Timer0 interrupt
(2) Timer1 interrupt
(3) Port0 interrupts (external interrupts: may occur on Port0 [7:0], total 8 sets)
(4) SBUS/SPI interrupt (Serial Mode/SPI mode)
(5) ADC interrupt
6
Preliminary
H7A36QP
(6) Duty interrupt (Interrupt generated when motor duty cycle activated)
(7) Timer-2 interrupt (NOT compatible with H244QP)
(8) DAC-PWM synchronous interrupt (NOT compatible with H244QP)
The interrupt function diagram is shown as follows:
0201H
Interrupt Request Enable Register (IRQER)
0201H , Interrupt Request Enable Register (IRQER)
7
6
5
4
3
2
DAC-PWM
Timer-2 IRQ
Duty IRQ
ADC IRQ
SBUS/SPI IF Port-0 IRQ
IRQ
Enable/
Enable/
Enable/
IRQ Enable/
Enable/
Enable/Disable
Disable
Disable
Disable
Disable
Disable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
Bit No.
Bit Name
1
Timer-1 IRQ
Enable/
Disable
R/W
0
0
Timer-0 IRQ
Enable/
Disable
R/W
0
1
Timer-1 IRQ
Status
R/W
0
0
Timer-0 IRQ
Status
R/W
0
[7] DAC-PWM IRQ Enable/Disable
 0 = Disable.
 1 = Enable.
[6] Timer-2 IRQ Enable/Disable
 0 = Disable.
 1 = Enable.
[5] Duty IRQ Enable/Disable:
 0 = Disable.
 1 = Enable.
[4] ADC IRQ Enable/Disable:
 0 = Disable.
 1 = Enable.
[3] SBUS/SPI Interface IRQ Enable/Disable:
 0 = Disable.
 1 = Enable.
[2] Port-0 IRQ Enable/Disable:
 0 = Disable.
 1 = Enable.
[1] Timer-1 IRQ Enable/Disable:
 0 = Disable.
 1 = Enable.
[0] Timer-0 IRQ Enable/Disable:
 0 = Disable.
 1 = Enable.
0202H
Bit No.
Bit Name
Read/Write
Reset
Interrupt Status Register (IRQSR)
7
DAC-PWM
IRQ Status
R/W
0
6
Timer-2 IRQ
Status
R/W
0
0202H , Interrupt Status Register (IRQSR)
5
4
3
2
Duty IRQ
ADC IRQ
SBUS/SPI IF Port-0 IRQ
Status
Status
IRQ Status
Status
R/W
R/W
R/W
R/W
0
0
0
0
[7] DAC-PWM IRQ status (NOT compatible with H244QP)
[6] Timer-2 IRQ status (NOT compatible with H244QP)
[5] Duty IRQ status.
[4] ADC IRQ status.
[3] SBUS/SPI Interface IRQ status.
[2] Port-0 IRQ status.
[1] Timer-1 IRQ status.
[0] Timer-0 IRQ status.
Reading corresponding interrupt status bit:
 0 = no interrupt occurs.
 1 = corresponding interrupt occurs.
7
Preliminary
H7A36QP
Writing corresponding interrupt status bit:
 0 = Clear corresponding Interrupt (EOI, End of Interrupt).
 1 = no effect to corresponding interrupt.
Note that in order to clear the interrupt from port0-0, the bit 0 of PORT0_IRQ_STATUS should be set instead
of setting the bit 2 of this register.
0203H
Bit No.
Bit Name
Read/Write
Reset
DAC/PWM Control Register (DPCR)
0203H , DAC/PWM Control Register (DPCR)
7
6
5
4
3
2
DAC/PWM
DAC synchronous signal selection
DAC-PWM
DAC PWM
Frequency
11/12 bit
signed/unsigned
selection
selection
selection
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
1
PWM
Mode
0
Reserved
R/W
0
R/W
0
[7:5] DAC synchronous signal selection (NOT compatible with H244QP)
 0 = No Synchronous, always updates.
 1 = Synchronize with Timer-0 Reload (IRQ).
 4 = Synchronize with DAC-PWM Reload (IRQ).
 5 = Synchronize with Motor Duty Reload (IRQ).
DAC synchronous is better sound quality.
[4] DAC-PWM Frequency selection (NOT compatible with H244QP)
 0 = system clock
 1 = system clock x 2

[3] DAC-PWM resolution selection (NOT compatible with H244QP)
 0 =11 bit resolution.
 1 =12 bit resolution.
[2] DAC/PWM Signed/Unsigned selection:
 0 = Unsigned Number
 1 = Signed Number
[1] PWM Mode
 0 = Power-Down mode
 1 = Normally Working.
Note that this bit is only valid and PWM can be output correctly under the following condition:
-- Bit 2 “PWM Enable” of SCR (0200H) is set.
-- PWM data should be written to LDACR register.
-- Bit 5 “AMP Enable” of SCR register is set. Control 0200H [5]”
[0] Reserved
0204H Left DAC PCM Register Low Byte (LDACR)
Bit No.
7
6
R/W
0
R/W
0
0204H , Left DAC PCM Register Low Byte (LDACR)
5
4
3
2
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Left DAC PCM [7:0]
Bit Name
Read/Write
Reset
1
R/W
0
R/W
0
R/W
0
R/W
0
0205H Left DAC PCM Register High Byte (LDACR)
Bit No.
7
6
R/W
0
R/W
0
0205H , Left DAC PCM Register High Byte (LDACR)
5
4
3
2
Left DAC PCM [15:8]
Bit Name
Read/Write
Reset
R/W
0
R/W
0
8
R/W
0
R/W
0
Preliminary
H7A36QP
0206H Right DAC PCM Register Low Byte (RDACR)
Bit No.
7
6
0206H , Right DAC PCM Register Low Byte (RDACR)
5
4
3
2
Read/Write
Reset
1
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Right DAC PCM [7:0]
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0207H Right DAC PCM Register High Byte (RDACR)
Bit No.
7
6
0207H , Right DAC PCM Register High Byte (RDACR)
5
4
3
2
Right DAC PCM [15:8]
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
There are two sets of 16-bit ADC and one set of PWM provided as output by the system. If only low byte data
is written to either LDACR or RDACR, the DAC won’t use those data till high byte is written. Once high-byte data
register is written, the DAC will start to work and use the Left-DAC/ Right-DAC PCM data in turn separately. The
PWM duty is determined by Left DAC PCM data.
0208H Timer Control Register (TMCR)
Bit No.
Bit Name
7
Timer-1
Enable/
Disable
Read/Write
R/W
Reset
1
6
Timer-1 Clock
Source Select
R/W
1
0208H , Timer Control Register (TMCR)
5
4
3
2
1
0
Timer-1 Working Clock
Timer-0
Timer-0 Clock Timer-0 Base Working Clock
Select
Enable/
Source Select
Select
Disable
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
[7] Timer-1 Enable/Disable:
 0 = Disable.
 1 = Enable.
[6] Timer-1 Clock source:
 0 = Base Clock of 1.86 MHz (Typ.).
 1 = System DPLL Clock (High Frequency).
[5:4] Timer-1 working clock select: These bits are used to set various divided clock (up to 1/1024) from original
clock source.
 0 = Clock.
 1 = Clock / 8.
 2 = Clock / 64.
 3 = Clock / 1024.
[3] Timer-0 Enable/Disable:
 0= Disable.
 1= Enable.
[2:0] Timer-0 working clock select: These bits are used to set various divided clock (up to 1/16384) from original
clock source.
 0 = System Clock.
 1 = System Clock / 4.
9
Preliminary
H7A36QP
Timer 0 Data Register
SYSTEM CLOCK
SYSTEM CLOCK / 4
SYSTEM CLOCK / 16
SYSTEM CLOCK / 64
SYSTEM CLOCK / 256
SYSTEM CLOCK / 1024
SYSTEM CLOCK / 4096
SYSTEM CLOCK / 16384
0
1
2
Clear Timer Counter
Timer Clock
3
8-Bit Up-Counter
AND
4
5
6
CMP
8-Bit Reload Data
EQUAL
Timer 0 Interrupt
7
1 : Enable Timer Clock
Select Clock Source
0 : Disable Timer Clock
Timer 0 Reload Register
BIT[3]
BIT[2]
BIT[1]
BIT[0]
Timer Mode Register Bit 3~0
Timer 0 Block Diagram
0209H Timer-0 Reload Register (TM0RR)
Bit No.
7
6
0209H , Timer 0 Reload Register (T0RR)
5
4
3
Read/Write
Reset
2
1
0
R/W
1
R/W
1
R/W
1
Timer 0 counter reload value
Bit Name
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Timer-0 counter reload value: These bits are used to set the value of the pre-scale. The counter in Timer 0 is
an up-counter. When the value of counter is equivalent to the value of TM0DR data, Timer-0 interrupt will be
generated and the counter will be reset to 0. The default of TM0RR is FFH.
020AH Timer-0 Data Register (TM0DR)
Bit No.
7
6
R/W
0
R/W
0
020AH , Timer 0 Reload Register (T0RR)
5
4
3
1
0
R/W
0
R/W
0
R/W
0
Timer 0 Data
Bit Name
Read/Write
Reset
2
R/W
0
R/W
0
R/W
0
Timer-0 Data: These bits are used to set the value of counter in Timer-0. The up-counter will start to count at
this value. The default value is 00H.
10
Preliminary
H7A36QP
Timer 1 Data Register
Clear Timer Counter
0
/8
/64
/1024
Timer Clock
1
2
8-Bit Up-Counter
AND
3
CMP
8-Bit Reload Data
System Clock
Base Clock
0
EQUAL
Timer 1 Interrupt
1 : Enable Timer Clock
1
0 : Disable Timer Clock
Timer 1 Reload Register
BIT[7]
BIT[6]
BIT[5]
BIT[4]
Timer Mode Register Bit 7~4
Timer 1 Block Diagram
020BH Timer-1 Reload Register (TM1RR)
Bit No.
7
6
020BH , Timer-1 Reload Register (TM1RR)
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
Timer 1 counter reload value
Bit Name
Read/Write
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Timer-1 counter reload value: These bits are used to set the value of the pre-scale. The counter in Timer-1 is
an up-counter. When the value of counter is equivalent to the value of TM1DR data, Timer-1 interrupt will be
generated and the counter will be reset to 0. The default of TM1RR is FFH.
020CH Timer-1 Data Register (TM1DR)
Bit No.
7
6
R/W
0
R/W
0
020CH , Timer-1 Data Register (TM1DR)
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
Timer 1 counter data
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
Timer-0 Data: These bits are used to set the value of counter in Timer-1. The up-counter will start to count at
this value. The default value is 00H.
Port-0 IRQ
Port-0 Interrupt
Mask Register
P0.X Interrupt Enable
0 : P0.X Falling
Port-0 Interrupt
Polarity Register
1 : P0.X Rising
Port-0 Interrupt
Status Register
P0.X INT Status
P0.0 INT Status
P0.1 INT Status
P0.2 INT Status
0
P0.X IN
1
P0.3 INT Status
trigger
P0.4 INT Status
P0.5 INT Status
P0.6 INT Status
P0.7 INT Status
Port-0 Interrupt Function Diagram
11
OR
Port-0 Interrupt Status
Preliminary
H7A36QP
020DH Port-0 IRQ Mask
Bit No.
7
Register (P0IMR)
6
020DH , Port-0 IRQ Mask Register (P0IMR)
5
4
3
Read/Write
Reset
2
1
0
R/W
0
R/W
0
R/W
0
Port0 IRQ Mask
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Port-0 IRQ Mask: These bits are used to disable/enable the IRQ of corresponding bits of Port-0 in input mode.
 0 = Disable. Note that default value of P0IMR is “00H”. All Port-0 IRQ are masked.
 1 = Enable.
020EH Port-0 IRQ Polarity Register (P0IPR)
Bit No.
7
6
R/W
0
R/W
0
020EH , Port-0 IRQ Polarity Register (P0IPR)
5
4
3
1
0
R/W
0
R/W
0
R/W
0
Port-0 IRQ Polarity
Bit Name
Read/Write
Reset
2
R/W
0
R/W
0
R/W
0
Port-0 IRQ Polarity: These bits are used to select the polarity of IRQ generation of corresponding bits of Port-0 in
input mode. The IRQ polarity is “0” for falling edge and “1” for rising edge.
 0 = Falling Edge.
 1 = Rising Edge.
020FH Port-0 IRQ Status Register (P0ISR)
Bit No.
7
6
R/W
0
R/W
0
020FH , Port-0 IRQ Status Register (P0ISR)
5
4
3
1
0
R/W
0
R/W
0
R/W
0
Port-0 IRQ Status
Bit Name
Read/Write
Reset
2
R/W
0
R/W
0
R/W
0
Port-0 IRQ Status: After interrupt generation, the IRQ status bits can be read out to determine the IRQ source
of corresponding bit of Port-0. Write “0” to the bit of interrupt source will clear the interrupt (End of Interrupt EOI).
Note if the interrupt source comes from Port0, then the interrupt will be cleared by writing “0” to bits of P0ISR
register instead of IRQSR register
0210H Port-0 I/O Mode Register (P0MR)
Bit No.
7
6
0210H , Port-0 I/O Mode Register (P0MR)
5
4
3
Read/Write
Reset
2
1
0
R/W
1
R/W
1
R/W
1
Port-0 I/O Mode Register
Bit Name
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Port-0 I/O Mode bits are used to select the I/O mode to be either input or output. The default mode for port-0 is all
inputs
 0 = Output.
 1 = Input.
0211H Port-0 Pull-High Register (P0PR)
Bit No.
7
6
0211H , Port-0 Pull-High Register (P0PR)
5
4
3
Read/Write
Reset
2
1
0
R/W
1
R/W
1
R/W
1
Port-0 Pull-High
Bit Name
R/W
1
R/W
1
R/W
1
R/W
1
12
R/W
1
Preliminary
H7A36QP
Port-0Pull-High: Those bits can be set to enable the internal pull-high resistor (approximately10kΩ) to
corresponding pins of port-0.
Note that the default value of P0PR is “FFH”. All Port-1 pins are pull-high enabled as default.
 0 = Pull-High Resistor Disabled.
 1 = Pull-High Resistor Enabled
0212H Port-0 Data Register (P0DR)
Bit No.
7
0212H , Port-0 Data Register (P0DR)
5
4
3
6
Read/Write
Reset
2
1
0
R/W
0
R/W
0
R/W
0
Port-0 Data
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Port-0 Data: The bits can be used to set the values of corresponding pins of port-0 in output mode. The values of
pins of port-0 can be read as well. Note that the values to be read at P0DR reflect the current status of port0 pins,
not the values written previously. In port-0 input mode, the inputs will go through Schmitt Trigger first then into the
system.
0213H Port-1 I/O Mode
Bit No.
Register (P1MR)
7
6
R/W
1
R/W
1
0213H , Port-1 I/O Mode Register (P1MR)
5
4
3
1
0
R/W
1
R/W
1
R/W
1
Port-1 I/O Mode
Bit Name
Read/Write
Reset
2
R/W
1
R/W
1
R/W
1
Port-1 I/O Mode bits are used to select the I/O mode to be either input or output. The default mode for port-1 is all
input
 0 = Output.
 1 = Input.
0214H Port-1 Pull-High Register (P1PR)
Bit No.
7
6
0214H , Port-1 Pull-High Register (P1RR)
5
4
3
Read/Write
Reset
2
1
0
R/W
0
R/W
0
R/W
0
Port1 Pull-High
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Port-1Pull-High: Those bits can be set to enable the internal pull-high resistor (approximately10kΩ) to
corresponding pins of port-1.
Note that the default value “00H” of P1PR is different from P0PR. All Port-1 pins are pull-high disabled as default.
 0 = Pull-High Disable.
 1 = Pull-High Enable.
0215H Port-1 Data Register (P1DR)
Bit No.
7
6
0215H , Port-1 Data Register (P1DR)
5
4
3
Read/Write
Reset
2
1
0
R/W
0
R/W
0
R/W
0
Port-1 Data
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Port-1 Data: These bits can be used to set the values of corresponding pins of port-0 in output mode. The
values of pins of port-0 can be read as well. Note that the values to be read at P1DR reflect the current status of
port1 pins, not the values written previously.
In port-1 input mode, the inputs won’t go through Schmitt Trigger and directly into the system. That is different
from port-0 input data that go through Schmitt Trigger first.
13
Preliminary
H7A36QP
0216H~0218H Reserved
0219H Serial I/F Control
Bit No.
Bit Name
7
Read/Write
Reset
R
0
Register (SIFCR)
6
Reserved
R
0
0219H , Serial I/F Control Register (SIFCR)
5
4
3
SBUS Bus Serial Interface Modes Select
Idle Detection
Enable
R/W
R/W
R/W
0
0
0
2
1
0
Master Mode Clock Select
R/W
0
R/W
0
R/W
0
[7:6] Reserved
[5] SBUS Bus Idle Detection Enable: This bit is set to enable Bus Idle Detection in SBUS mode
 0 = Disable.
 1 = Enable
(Note that the interrupt will be generated if serial bus is occupied by other master and “STOP” signal
appears on the serial bus.
[4:3] Serial Interface Mode Select: These two bits are used to determine the mode of serial interface as follows:
 00 = Serial Bus Block Reset.
 01 = SBUS Mode: use proprietary serial mode in serial interface
 10 = SPI Mode: use SPI mode in serial interface
 11 = Serial Bus Block Reset.
[2:0] Slave Mode Clock Select: these three bits are used to set the clock frequency that determines the data
transfer rate in bit per second.
Serial Bus Port will use PORT1 [3:0] and the corresponding relationship is shown below:
SBUS Mode
SPI Mode
Port-1 [0]
SCL
SCK
Port-1 [1]
SDA
SSB
Port-1 [2]
MOSI(MOMI)
Port-1 [3]
MISO(SISO)
021AH Serial Mode-1 Register (SMOD1)
Bit No.
7
6
021AH , Serial mode-1 Register (SMOD1)
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
SBUS Address
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
When serial interface is set to SBUS Mode and slave mode:
[7:0] SBUS Address: Set the system device address (ID). The system can use either 7-bit device address or 10device address. In the case of 10-bit device address, the extended bits in SMOD2 will be used as the MSB bits.
When serial interface is set to SPI Mode: this register is not used.
14
Preliminary
H7A36QP
021BH Serial Mode-2 Register (SMOD2)
Bit No.
Bit Name
Read/Write
Reset
7
SBUS Start
6
SBUS Stop
R/W
0
R/W
0
021BH , Serial Mode-2 Register (SMOD2)
5
4
3
2
Master/Slave Master/Slave General-Call ACK/ NACK
Mode Select
Switch
IRQ enable Select
R/W
R/W
R/W
R/W
0
0
0
0
1
0
SBUS Extended Address
R/W
0
R/W
0
When serial interface is set to SBUS Mode:
[7] SBUS Start: This bit is set to generate a “START” signal to the serial interface. This bit is automatically cleared
after that and interrupt is generated as well.
 0 = No effect.
 1 = generate START signal
[6] SBUS Stop: This bit is set to generate a “STOP” signal to the serial interface. This bit is automatically cleared
and created interrupt after that.
 0= Disable.
 1 = generate STOP signal.
[5] Master/Slave Mode Select: It is used to select the system to be in master or slave mode.
 0 = Slave Mode.
 1 = Master Mode.
[4] Master to Slave Mode Switch: This bit provide an alternative for the system to switch the interface to slave mode
if there is any arbitration error occurring during transmission in SBUS master mode.
 0 = Disable.
 1 = Enable. Enable switching between the master/slave in SBUS mode
[3] General-Call IRQ enable: This bit is set to enable the system to respond the IRQ when there is a general-call on
the serial interface.
 0 = Disable.
 1 = Enable.
[2] ACK/NACK select: This bit is used to set the acknowledge/ non-acknowledge back to master.
 0 = NACK, .set the device non-acknowledge to the serial bus of data transmission.
 1 = ACK, set the device acknowledge to the serial bus of data transmission.
[1:0] SBUS extended address: this bit is used to set the device address [9:8]. The 10-bit device address is
implemented by combining SMOD2 [1:2] & SMOD1 [7:0].
When serial is set to SPI Mode:
Bit No.
Bit Name
7
Read/Write
Reset
R
0
6
Reserved
R
0
021BH , Serial Mode-2 Register (SMOD2)
5
4
3
2
Master/Slave SSB Control Duplex Data Duplex Data
Mode Select
Enable
I/O Control Flow Control
R/W
R/W
R/W
R/W
0
0
0
0
1
Clock Phase
R/W
0
0
Clock
Polarization
R/W
0
[7:6] Reserved
[5] Master/Slave Mode Select: It is used to select the system to be in master or slave mode.
 0 = Slave Mode.
 1 = Master Mode.
[4] SSB control enable: this bit is set to enable SSB to be controlled by system firmware. SSB is set from low to
high once with each data transmit/receive.
 0 = Disable..
 1 = Enable.
[3] Duplex Data I/O control: It is used to set input or output direction for duplex data flow.
 0 = Input – The serial interface data will be recorded to RX register.
 1 = Output – The TX register data will be sent to the serial interface.
[2] Duplex Data Flow Control
15
Preliminary
H7A36QP
 0 = Normal mode, MOSI & MISO are used to complete the data transmission.
 1 = Master changes MOSI to MOMI, Slave changes MISO to SISO. The data transmission will
implemented by one bit signal.
[1] Clock Phase: This bit is used to determine SDA is valid on either the first or the second edge (rising/falling) of
SCK.
SDA is valid when the bit is
 0 = on the first edge of SCK, rising or falling.
 1 = on the second edge of SCK, rising or falling.
Please refer to the diagram as below.
[0] Clock Polarization: This bit is used to determine the high/low voltage status of SCK when it is idle.
When SCK is Idle:
 0 = The SCK keeps low voltage.
 1 = The SCK keeps high voltage.
Please refer to the diagram as below..
16
Preliminary
H7A36QP
021CH Serial Status Register (SSTS)
Bit No.
Bit Name
7
Complete
Read/Write
Reset
R
0
6
SBUS Bus
Status
R
0
021CH , Serial Status Register (SSTS)
5
4
3
Arbitration
Master Busy ACK Status
Error
R
R
R
0
0
0
2
General Call
Flag
R
0
1
0
First Data
Data Transfer
Transfer Flag Direction Flag
R
R
0
0
Serial interface in SBUS Mode:
[7] Complete:
When the action of transmission is completed or some error occurs, this bit will be asserted no matter IRQ of
SBUS/SPI serial interface is enabled or not. This flag is used to indicate the transmission status as below and to
be polled by firmware. Serial EOI (end of interrupt) is used to clear this IRQ
The interrupt happens when
Slave Mode:
1. Direction of transmission is from Slave to Master and Master finishes sending
the address.
2. Direction of transmission if from Master to Slave and Master has completed the address.
3. Idle Detection is set and STOP signal appears on bus.
4. Data transmission is completed.
Master Mode:
1. START signal completed
2. STOP signal completed.
3. Transmission is done.
4. Arbitration Error.
[6] SBUS Bus Status: This bit is used to represent the bus status in SBUS mode.
 0 = Idle.
 1 = Busy.
[5] Arbitration Error: This bit is the flag of arbitration error during master mode. The system can use SMOD2 to
define whether the mode will be automatically switched to slave mode (by setting bit of Serial_Mode2[4]).
 0 = no arbitration error.
 1 = arbitration error occurs.
[4] Master Busy: This bit is used to indicate whether the BUS is being driven (in master mode only).
 0 = Bus is not driven.
 1 = Bus is driven.
[3] ACK Flag: This bit represents the Acknowledge/non-Acknowledge from external Host master.
 0 = non-Acknowledge (NACK). The host responds the NACK after SBUS TX data transmission is completed
 1 = Acknowledge (ACK). The host responds the ACK after the SBUS TX data transmission is completed. It
can be known by checking this bit whether host read stage is completed or not. If the host acknowledges the
data transmission, the device (H7A36QP) has to set next transmitting data to the SBUS TX for host’s next
reading. Otherwise, the host set none-acknowledge, that means the stage of host read is completed.
[2] General Call Flag: The general call ID is 0001111b, and the device can be configured to process general call if it
is necessary. This bit is used to show the general call status.
 0 = the received ID (Address) is not a general call.
 1 = the received ID (address) is a general call.
[1] First Data Transfer Flag: This bit indicates whether the data is the first received data or not after receiving the
device address.
 0 = the data received is the first byte of data after receiving device address.
 1 = the data received is not the first byte of data after receiving device address.
Note that in master mode if there is any arbitration error generated to switch the mode to slave mode, the first
data may not be recorded. The mode can be identified by checking bit 5 of Serial_Mode2 register. If it is in slave
mode, then this bit SMOD[5] should be set to “0”
[0] Data Transfer Direction Flag
 0 = Master Trans Write Direction (Master to Slave).
 1 = Master Trans Read Direction (Slave to Master).
17
Preliminary
H7A36QP
Bit No.
Bit Name
Read/Write
Reset
7
Complete
6
SPI Bus
Status
R
0
R
0
021CH , Serial Status Register (SSTS)
5
4
3
Mode Fault
R
0
R
0
R
0
2
Reserved
1
0
R
0
R
0
R
0
Serial SPI Mode:
[7] Complete:
When the action of transmission is completed or some error occurs, this bit will be asserted no matter IRQ of
SBUS/SPI serial interface is enabled or not. This flag is used to indicate the transmission status as below and to
be polled by firmware. Serial EOI (end of interrupt) is used to clear this IRQ
 0 = not completed.
 1 = completed.
[6] SPI Bus Status: This bit indicates that the bus is idle or busy.
 0 = Idle.
 1 = Busy.
[5] Mode Fault: This is the flag showing the status that there is other Master is using the bus. The mode fault flag
occurs with companion of an interrupt when SSB is “0” in SPI master mode.
 0 = non-Fault.
 1 = Fault.
[4:0] Reserved
021DH Serial TX (Transmit) Register (STXR)
Bit No.
7
6
021DH Serial TX Register
4
3
5
Read/Write
Reset
2
1
0
W
0
W
0
W
0
Serial TX Data
Bit Name
W
0
W
0
W
0
W
0
W
0
The data to be transmitted to the external host can be written to this register. When the serial TX bits are all
transferred, an interrupt will be generated and sent to the MCU.
021EH Serial RX (Receive) Register (SRXR)
Bit No.
021EH Serial RX Register
4
3
7
6
5
R
0
R
0
R
0
1
0
R
0
R
0
R
0
Serial RX Data
Bit Name
Read/Write
Reset
2
R
0
R
0
These bits represent the data received via serial interface and can be read only. This register won’t be
updated until the data transmission is finished.
Serial interface in SBUS mode: Note that it is required to write any arbitrary value to Serial TX or Serial RX
register first to generate the SCK clock. Then the content of this register is valid and can be read out.
Serial interface in SPI mode: Note that it is required to write any arbitrary value to Serial TX register first to
generate the SCK clock. Then the content of this register is valid and can be read out.
021FH Watch-Dog Timer Control Register (WDCR)
Bit No.
Bit Name
7
Read/Write
Reset
W
1
021FH Watch-Dog Timer Control Register, (WDCR)
6
5
4
3
2
1
Watch-Dog Timer Clock Prescaler
Watch-Dog Control Mode
W
1
W
1
W
1
W
1
W
1
W
1
0
W
1
[7:4] Watch-Dog Timer Clock Prescaler: These bits are used to set the value of prescaler that divides the R/C base
Block as below:
18
Preliminary
H7A36QP
R/C Base-Clock / (prescaler + 1)
Watch-Dog Timer will reset the CPU if watch-dog timer is not cleared within 65536 Watch-Dog Timer clock
cycles. The system control registers is not affected by this watch-dog timer reset and keep the same values.
[3:0] Watch-Dog Control Mode: These bit are used to control the watch-dog timer as below:
 0 = Disable.
 5 = Clear.
 F = Enable.
Base-Clock
(D[7..4] + 1)
16 bit
Counter
Clear
Watch-Doge Control
D[3] D[2] D[1] D[0]
CK
“1”
Carry
ResetB
Enable
Q
D
Clear
Watch-Doge Control Functional Block Diagram
0220H Advanced Control Register (ACR)
Bit No.
Bit Name
Read/Write
Reset
7
Motor Duty
High/Low
6
Low Voltage
Reset
R/W
0
R/W
0
0200H , Advanced Control Register (ACR)
5
4
3
2
1
0
ADC 1/0
ADC1/0 Sync ADC 2 Source ADC 1 Source
Reserved ADC Enable
Resolution
Select
Control
Control
Select
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
[7] Motor Duty Active High/Low: This bit is used to select the duty cycle of motor PWM to be active high or active
low.
 0 = Duty Active Low.
 1 = Duty Active High.
[6] Low Voltage Reset: This bit is set to enable the low voltage reset function. Default value is “0”– disabled.
 0 = Disable
 1 = Enable
NOTE: THIS BIT MUST BE SET TO 1 FOR ENABLING THE LVR AND LET POWER ON RESTING STABLY.
[5] Reserved.
[4] ADC Enable: This bit is set to enable the ADC (Analog-Digital Converter) function. Default value is “0”– disabled.
 0 = Disable.
 1 = Enable.
[3] ADC 1/0 resolution select: This bit is used to select the resolution in both ADC-0 and ADC-1:
 0 = 16-bit ADC resolution.
 1 = 8-bit ADC resolution.
[2] ADC 1/0 Sync Select: This bit is used to set the ADC to be synchronous or asynchronous. The description of
these two modes is depicted at the end of register definition.
 0 = asynchronous mode.
 1 = synchronous mode.
[1] ADC-2 Source Select: This bit is used to select the source of ADC-2 as follows:
 0 = Select signal defined in ADC Control Register.
 1 = Select internal VREF as the source.
19
Preliminary
H7A36QP
[0] ADC-1 Source Select: This bit is used to select the source of ADC-1 as follows:
 0 = Select signal defined in ADC Control Register.
 1 = Select internal VREF as the source.
The difference between asynchronous and synchronous mode of ADC lies in whether the ADC will lock the
action of conversion circuit when it reads the H/L bytes of conversion results of ADC-0 and ADC-1 or not. Under
synchronous mode, any register reading of either ADC-0 or ADC-1 may lock another ADC and prohibit its
conversion of source signal. Thus the firmware can get all ADC conversion result at one time then continue the
next conversion of all ADCs. Here is the synchronous mode lock restriction as below
In 8Bit mode:
Reading ADC-0 High Byte, ADC-1 Low Byte or ADC-1 High Byte: the other ADC will be locked.
Reading ADC-0 Low Byte: this will unlock the ADC.
In 16bit mode:
Reading ADC-0 Low Byte or ADC-1 will lock both ADC-0/ADC-1.
Reading ADC-0 High Byte will unlock both ADCs.
ADC-0& ADC-1 supports 2 modes of structure of different bit resolution that is either 8-bit or 16-bit.
In 16-bit mode, ADC-0 High/Low Byte is made up with 16bits conversion data. ADC-1 High/Low byte registers
are the same.
In 8-bit mode, both ADC-0/1 has two sets of conversion data. And the ADC-0/1 High/Low bytes are made up
of those conversion data separately. The high/low bytes of them represent different conversion results of signal
sources.
In ADC mode of 8-bit resolution, the analog source inputs is fixed at Port-1[7:4] as follows
ADC-0 Low Byte = AD conversion value of Port-1[4] .
ADC-0 High Byte = AD conversion value of Port-1[5] .
ADC-1 Low Byte = AD conversion value of Port-1[6] .
ADC-1 High Byte = AD conversion value of Port-1[7] .
0221H DPLL Control Register (DPLLR)
Bit No.
Bit Name
Read/Write
Reset
7
6
FDIV
R/W
1
R/W
0
0221H, DPLL Control Register (DPLLR)
5
4
3
FMUL
R/W
0
R/W
0
R/W
1
2
1
0
R/W
0
R/W
1
R/W
1
[7:6] FDIV: This bit is used to set the value of denominator FMUL in DPLL equation of base clock to generate system
clock
[5:0] FMUL: This bit is used to set the numerator FDIV in DPLL equation of base clock to generate system clock.
System Clock = Base Clock * (FMUL + 129) / (FDIV + 5).
The initial value is 10001011b (8BH) so the system clock is 20 x base clock.
Typically: base clock = 2.00MHz , Vcc = 3.3V
After power-on, system clock = 20.00 x 2.00MHz = 40.00 MHz.
20
Preliminary
H7A36QP
16
ADC0_DATA
16
ADC1_DATA
16
Select Source
ADC2_DATA
System Clock / 2
System Clock / 4
System Clock / 6
System Clock / 28
System Clock / 30
System Clock / 32
Select Clock Source
15
14
13
12
11
10
9
8
7
Select ADC2 Source
6
5
4
3
Select ADC1 Source
2
1
0
Select ADC0 Source
0222H ADC Control Low Byte Register (ACLR)
Bit No.
Bit Name
7
Read/Write
Reset
R/W
0
0222H , ADC Control Low Byte Register (ACLR)
6
5
4
3
ADC-1 Input select
2
1
ADC-0 Input Select
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
R/W
0
Analog Input Selection:
[7:4] = ADC-1 input select: These bits are used to select the input source of ADC-1, the default value is 0 that will
use PORT0 [0] as the source of ADC-1.
0223H ADC Control High Byte Register (ACHR)
Bit No.
Bit Name
Read/Write
Reset
7
R/W
0
0223H , ADC Control High Byte Register (ACHR)
6
5
4
3
2
1
ADC Prescaler
ADC-2 input select
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
R/W
0
[7:4] = ADC Prescaler: These bits are used to set the value of prescaler of ADC Clock, default is 0 (System Clock /
2).
Note that prescaler should be set between 03H to 0FH to get better result of AD conversion.
The AD Conversion Clock = System Clock / (([7:4] + 1) * 2). It needs 16/8 (depending on the AD resolution)
plus 8 conversion clock cycles to convert one bit analog data.
0224H ADC-0 Data Low Byte Register
Bit No.
7
6
R
0
R
0
0224H, ADC-0 Data Low Byte Register (AD0DL)
5
4
3
1
0
R
0
R
0
R
0
ADC-0 Data Low Byte
Bit Name
Read/Write
Reset
2
R
0
R
0
21
R
0
Preliminary
H7A36QP
0225H ADC-0 Data High Byte Register (AD0DH)
Bit No.
7
6
0225H, ADC-0 Data High Byte Register (AD0DH)
5
4
3
Read/Write
Reset
2
1
0
R
0
R
0
R
0
ADC-0 Data High Byte
Bit Name
R
0
R
0
R
0
R
0
R
0
These two bytes represents the AD conversion result of either one 16-bit resolution or two 8-bit
resolution channels.
0226H ADC-1 Data Low Byte Register (AD1DL)
Bit No.
7
6
R
0
R
0
5
4
3
1
0
R
0
R
0
R
0
2
1
0
R
0
R
0
R
0
ADC-1 Data Low Byte
Bit Name
Read/Write
Reset
2
R
0
R
0
R
0
Bit No.
7
6
0227H, ADC-1 Data High Byte Register (AD1DH)
5
4
3
Bit Name
Read/Write
Reset
R
0
R
0
R
0
R
0
R
0
These two bytes represents the AD conversion result of either one 16-bit resolution or two 8-bit
resolution channels.
0228H ADC-2 Data Low Byte Register (AD2DL)
Bit No.
7
6
R
0
R
0
5
4
3
1
0
R
0
R
0
R
0
2
1
0
R
0
R
0
R
0
ADC-2 Data Low Byte
Bit Name
Read/Write
Reset
2
R
0
R
0
R
0
Bit No.
7
6
R
0
R
0
0229H, ADC-2 High Byte Register (AD2DH)
5
4
3
Bit Name
Read/Write
Reset
R
0
R
0
R
0
These two bytes represents the AD conversion result of one 16-bit resolution channel.
Note that the ADC-0, ADC-1, ADC-2 supports the following:
3 bits AD conversion, each of them is of 16 bit resolution
5 bits AD conversion, 4 bits with 8-bit resolution and 1 bit with 16-bit resolution
022AH Motor Control Register (MCR)
Bit No.
Bit Name
Read/Write
Reset
7
Motor Enable
R/W
0
6
Motor Port0
Output
Select1
R/W
0
020AH , Motor Control Register (MCR)
5
4
3
Motor Port0
Motor Port0
Full Duty
Output
Output
Enable
Select2
Select3
R/W
R/W
R/W
0
0
0
2
1
0
PWM Clock Source Select
R/W
0
R/W
0
[7] Motor Enable:
 0 = Disable.
 1 = Enable.
[6] Motor Port0 Output Select1: This bit is used to select the output source of port-0 [5:4] as below:
22
R/W
0
Preliminary
H7A36QP
 0 = Port0 Data Output.
 1 = Motor Control Signal Output.
[5] Motor Port0 Output Select2: This bit is used to select the output source of port-0 [3:2] as below:
[4] Motor Port0 Output Select1: This bit is used to select the output source of port-0 [1:0] as below
[3] Full Duty Enable: This bit is set to use the full duty. The default “0” uses PWM duty cycle for motor, read this bit
to get active duty.
 0 = PWM Duty Cycle.
 1 = Full Duty.
[2:0] PWM Clock Source Select: The PWM clock source can be switched by changing these three bits as below:
022BH Motor Mode Register (MMR)
Bit No.
Bit Name
Read/Write
Reset
7
H_NMOS
6
L_NMOS
R/W
0
R/W
0
020BH, Motor Mode Register (MMR)
5
4
3
2
Output Mode & Pin Map 2
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
R/W
0
[7] H_NMOS: This bit is used to determine the type of transistor of external application circuit that links to high
channel of PWM.
 0 = PMOS Transistor.
 1 = NMOS Transistor.
[6] L_NMOS: This bit is used to determine the type of transistor of external application circuit that links to low
channel of PWM.
 0 = PMOS Transistor.
 1 = NMOS Transistor.
[5:4] Output Mode & Pin Map 2: They are used to set the mode of port0 pins that are mapped to Port-0 [5:4]. The
control modes are shown as below.
[3:2] Output Mode & Pin Map 2: They are used to set the mode of port0 pins that are mapped to Port 0[3:2]. The
[1:0] Output Mode & Pin Map 2: They are used to set the mode of port0 pins that are mapped to Port 0[1:0]. The
 0 = Floating.
 1 = Drive High.
 2 = Drive Low
 3 = don’t use this mode.
022CH Motor Duty Register (MDR)
Bit No.
7
6
022CH, Motor Duty Register (MDR)
5
4
3
Read/Write
Reset
2
1
0
R/W
0
R/W
0
R/W
0
Motor Duty
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
[7:0] Motor Duty: these bits are used to set high duty cycle of PWM ranging from 00H to FFH.
022DH Interpolation Control
(NOT compatible with H244QP)
23
Preliminary
H7A36QP
Bit No.
Bit Name
Read/Write
Reset
7
Interpolation
Enable/Disable
R/W
0
6
ADC/DAC
Interpolation
Select
R/W
0
022DH , Interpolation Control Register
5
4
3
2
Interpolation Mode
R/W
0
1
0
Interpolation Clock Select
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D[2:0] Interpolation Clock Rate.
 Clock = System Clock / (4*(n + 1)).
Define the interpolation clock.
D[5:3] ADC/DAC Interpolation Sample Number, System default 0:
 0 = 32 samples.
 1 = 64 samples.
 2 = 128 samples.
 3 = 256 samples.
 4 = Reserved.
 5 = Reserved.
 6 = Reserved.
 7 = Initial.
Define the number of samples for interpolation.
Example of 128 samples interpolation, top is without interpolation, bottom is with interpolation.
D[6] Select ADC or DAC for Interpolation, Default is 0:
 0 = ADC2.
 1 = DAC.
There is only one interpolation block function, the programmer can set this bit to assign the interpolation
to ADC or DAC.
D[7] Interpolation Enable/Disable, Default is 0:
 0 = Disable.
 1 = Enable.
022EH Extra System Control
Bit No.
Bit Name
Read/Write
Reset
7
Multi-ADC
Enable/Disable
R/W
0
(NOT compatible with H244QP)
022EH , Math Control Register (MTHCR)
6
5
4
3
2
Compatible Mode / Advance Mode
NAND I/F
NAND I/O
Enable/Disable Sharing mode
R/W
0
R/W
0
R/W
0
D[0] 32768 clock source selection:
 0 = Select from internal RC with divider.
 1 = Select from external XTAL 32768.
D[1] Selection of analog input source for channel 7:
 0 = Microphone pre-amplifier input source.
 1 = Select Port-0[7].
D[2] NAND I/O sharing mode:
 0 = Port-0[0~7] are always NAND data I/O.
24
R/W
0
R/W
0
1
ANA-7
Source
Selection
R/W
0
0
32768 Source
Selection
R/W
0
Preliminary
H7A36QP
 1 = Port-0[0~7] are general I/O function and shared with NAND data I/O.
D[3] NAND Flash Interface Enable or Disable:
 0 = Disable.
 1 = Enable.
When enable NAND interface, the following I/Os are optioned for NAND I/F control signals:
P17 :
REB
P16 :
WEB
P15 :
CLE
P14 :
ALE
P22 :
CEB
Set this bit to 0 for NAND Flash interface:
The NAND interface can be controlled by accessing the address space between 9800H to 9FFFH.
9800H-9BFFH
:
CEB, CLE, ALE is auto completed within 1 system clock cycle.
9C00H-9FFFH
:
CEB, CLE, ALE is latched until accessing 9800H~9BFFH.
Command Latch Cycle :
MOVE
[9D00H], CMD_CODE
Address Latch Cycle
MOVEW
MOVEW
MOVE
:
[9E00H], A15_A00
[9E00H], A31_A16
[9A00H], A39_A32
; Command Code, Hold CEB
; Address 15-00, Hold CEB & ALE
; Address 31-16, Hold CEB & ALE
; Address 39-32, Release CEB & ALE
D[6:4] Set compatible mode (compatible with H244QP) or advance mode :
 010b = Enable advance mode.
 other = H244QP compatible mode .
In H244QP compatible mode, the H7A36QP works with most functions and controls that are compatible
with H244QP.
When write 010 to these 3 bits, the H7A36QP works in advance mode, and the following are important
features for advance mode:
(1) MTR definition is different with compatible mode (please refer to the memory map description)
(2) ADC result can be configured to signed or unsigned value.
(3) The AMP (speaker amplifier) device are controlled by setting the “X-Control Byte-1”(0230H).
(4) The system memory decoder is different, the decode space from 00H~1FH is mapped to the
specified control registers. Especially, 18H~1FH are for Math-Processor that will speed up the
instruction operations.
D[7] Multi-ADC enable or disable:
 0 = Disable.
 1 = Enable (need entering advance mode).
You have to enter advance mode for controlling the Multi-ADC enable or disable.
If the system is H244QP compatible mode, the Multi-ADC function is controlled by hardware option code.
022FH X-Control Byte-0
Bit No.
Bit Name
Read/Write
Reset
7
6
PLL-Clock
Base-Clock
Enable/Disable Enable/Disable
R/W
R/W
0
0
(Advance Mode Only)
022FH ,X-Control Register – Byte-0
5
4
3
XTAL 4M
XTAL-32K
Select
CPU Clock
R/W
R/W
R/W
0
0
0
2
OTP
Enable/Disable
R/W
0
1
Select
Base Clock
R/W
0
D[0] System Low-Frequency source select. System default 0:
 0 = Select 4MHz (2M Hz R/C Base-Clock * 2).
 1 = Select 65536Hz (32768 Hz * 2).
D[1] Select Base-Clock source. Default is 0:
 0 = RC-Clock (Internal Base-Clock).
 1 = XTAL-4M (External Base-Clock).
Internal base-clock is RC clock (or called VCO clock) and it operates about 2MHz.
25
0
Select
Slow Clock
R/W
0
Preliminary
H7A36QP
External base-clock is from the XTAL that is enabled by bit 5 of this register and the Port-2[1..0] are
connected to the XTAL component. Besides, the external clock is scaled by controlling the bit 3~0 of
“System Control Byte-2” for scaling to 2MHz for external base-clock. If not use XTAL, the Port-2[1] can
input by other clock source.
D[2] OTP control, Default is1:
 0 = Disable.
 1 = Enable.
This bit is used to control the OTP power (OTP enable or disable), and the control program code should
be load to SRAM space to control this bit. When program codes are running in the SRAM and the OTP is
disabled, the system can save the power current.
The programmers have to wait 50 uS for OTP stabling after setting this bit to 1 from 0 (power on OPT).
However, when system enters the power down mode, the OTP is disabled.
The followings are power down conditions:
CPU clock is selected to PLL-Clock (bit-3 is 1), then disable PLL-Clock (bit-7 is set to 0).
CPU clock is selected to Slow-Clock (bit-3 is 0) and Low-Clock is selected to 65536(2x XTAL-32K), then
disable XTAL 32K (bit-4 is set to 0).
CPU clock is selected to Slow-Clock (bit-3 is 0) and Low-Clock is selected to 4MHz (2x RC-Clock), then
disable RC-Clock (bit-6 is set to 0).
D[3] Select CPU-Clock, Default is 1:
 0 = Select Slow-Clock.
 1 = Select PLL-Clock (High-speed).
Change CPU clock speed to slow for saving system power, and high-speed for processing high-loading
tasks.
D[4] XTAL-32K Enable/Disable, Default is 1:
 0 = Disable.
 1 = Enable.
If the hardware (Port-2[3..2]) is optioned to XTAL-32K, control this bit to start or stop the XTAL-32K
oscillating.
D[5] XTAL-4M Enable/Disable, Default is 1:
 0 = Disable.
 1 = Enable.
XTAL-4M is also called external base clock.
If the hardware (Port-2[1..0]) is optioned to XTAL-4M, control this bit to start or stop the XTAL-4M
oscillating.
D[6] Base-Clock Enable/Disable, Default is 1:
 0 = Disable.
 1 = Enable.
If the Base-Clock is select from RC-Clock, there are two conditions to starting the RC-Clock oscillating
and it is stable for system after 11’s warm-up-counter (2048 unstable clocks).
Change the bit from 0 to 1 when CPU runs in XTAL-32K.
Wake up from power down when CPU clock is set to Slow-Clock and Slow-Clock is selected to 4MHz.
If the Base-Clock is select from XTAL-4M, this bit is set to 1 for enabling the warm-up of XTAL-4M.
D[7] PLL-Clock Enable/Disable, Default is 1:
 0 = Disable.
 1 = Enable.
Set this bit is to enable the PLL circuit, and the Base-Clock have to be enabled together.
Note: switch to another clock source before disabling PLL-clock
0230H X-Control Byte-1
Bit No.
Bit Name
Read/Write
Reset
7
AMP
Dual Drives
R/W
0
(Advance Mode Only)
6
0230H , X-Control Register – Byte-1
5
4
3
AMP Drive Mode
R/W
0
R/W
0
2
DAC Over sampling
R/W
0
D[2:0] External Clock Pre-scale.
26
R/W
0
1
0
External Clock pre-scale
R/W
0
R/W
0
R/W
0
Preliminary
H7A36QP
 Base Clock = External Clock / 2*(n + 1).
These 3 bit are for controlling the external clock speed if the external clock is enabled.
D[4:3] DAC Over Sampling Control, Default is 00.
 Clock = System Clock / (n + 1).
The DAC of H7A36QP is based on DAC architecture, and controlling the over sampling can get the
result in good SNR. Set the converting-rate of DAC to 12~24 MHz is recommended.
For example, the play-back-rate of the sound is 16 KHz, and the system clock is set to 49.152M Hz,
configuring the bit 4 and 3 of this register to 11 is for maximum over-sampling; therefore, the convertingrate of DAC is 49.152M / (3+1) ( ~= 12.288M Hz) and the over-sampling is 12.288M / 16k (~= 768).
D[6:5] SPK-AMP Mode, Default is 00:
 0 = Analog.
 1 = PWM.
 2 = Class D.
 3 = Digital-Drive Power Down.
Writing these 2 bit is for configuring SPK-AMP(SPK_P and SPK_N) to drive with analog signal ( analog
amplifier) or digital signal (digital amplifier).
Sometimes, to distinguish the amplifier to analog by traditional wave signal and digital signal by square
form.
But, Class-A/B and Class-D were input by analog signal from AMP_IN, and the PWM is direct form the
DAC register.
The followings are the SPK-AMP modes:
AMP Enable
1001H D[0]
0
0
0
0
1
1
1
1
AMP Mode
1002H D[6:5]
00
01
10
11
00
01
10
11
SPK_P
SPK_N
Mode
Floating
Floating
Floating
Floating
Analog
Duty
Duty
Floating
Floating
Floating
Floating
Floating
Analog
Duty
Duty
GND
Class A/B
PWM
Class D
Power Down
In Class-A/B and Class-D modes, the DAC is internally connected via a internal resistor (about 10K Ω) to
the negative input of EQ-OP for filtering, and the output of EQ-OP have to be connected a coupling
capacitor to the AMP-IN for amplifying the audio signal.
Additionally, there is a programmable volume control to define the gain value in Class-A/B and Class-D
modes.
In PWM mode, the PWM resolution can be configured to 12 or 13 bit (2048 or 4096 duty levels).
Besides, the PWM is acts as push-pull, and SPK-P is active output for positive side when the DAC value
is form 8000H to FFFFH, and the SPK-N is active output for negative side when DAC value is from 0000H
to 7FFFH. However, the 12 bit resolution mode of PWM only uses the higher 12 bit of DAC value, and the
13 bit mode uses the higher 13 bit of DAC value.
By the way, the PWM resolution is defined in the bit 5 of “Advance Control Byte-0” and the PWM clock
can be configured to double speed ( 2x system clock) by writing 1 to the bit 4 of “Advance Control Byte-0”.
D[7] SPK_P & SPK_N Dual-Drive mode, Default is 0:
 0 = Disable (for Headphone).
 1 = Enable (for Speaker).
In some applications, the audio is not only for driving the speaker but also for driving the headphone. And,
When the headphone is connected, the speaker can be configured to off or on by setting this bit.
Writing 1 to this bit for enabling the SPK-P and SPK-N to drive the speaker, and writing 0 to this bit for
setting the SPK-P to high-impedance and the SPK-N is kept for signal output to drive the headphone.
0231H X-Control Byte-2
Bit No.
Bit Name
Read/Write
Reset
7
(Advance Mode Only)
6
AMP Drive Current Selection
R/W
0
R/W
0
0231H , X-Control Register – Byte-2
5
4
3
Clock Out
Clock Out
Clock source
Enable/Disable
Selection
R/W
R/W
R/W
0
0
0
D[3:0] Clock Out pre-scale:
27
2
1
0
Clock Out pre-scale
R/W
0
R/W
0
R/W
0
Preliminary
H7A36QP
 Clock out clock = Clock out source clock/ (D[3:0]+1)
D[4] Clock out source clock selection:
 0 = CPU clock.
 1 = External XTAL.
D[5] Clock out enable / disable:
 0 = Disable
 1 = Enable.
When enable clock-out, the clock output on Port-2[1], and the Port-2[1] I/O direction and pull-up resistor
are all disable.
D[7:6] Speaker Amplifier (AMP) drive current selection:
 0 = 50 mA
 1 = 100 mA
 2 = 150 mA
 3 = 200 mA
0232H Volume Control
Bit No.
(Advance Mode Only)
7
0232H , Volume Control Register
5
4
3
6
Read/Write
Reset
2
MIC volume
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D[3:0] 16 levels AMP volume control, Default is 0:
 0 = AMP minimum volume.
 F = AMP maximum volume.
Cf 222
Ci 104
DAC_VO
104
Ri 10K
Rf 10K
EQ_I
1
0
R/W
0
R/W
0
AMP volume
EQ_O
AMP_IN
SPK_P
SPK_N
0  Mute , 8  Gain=8/8=1 , F  Gain=15/8=1.875
D[7:4] 16 levels microphone volume control , System default 0:
 0 = MIC minimum gain.
 F = MIC maximum gain.
222
GAIN_CI
GAIN_CO
20K
MIC_P
10K
MIC_N
MIC_AGC
0  Mute , 8  Gain=8/8=1 , F  Gain=15/8=1.875
When gain=1, the feedback resistor is near 10K , and the low pass cut-off frequency is
F=1 / (2PI * R * C) = 7.234 KHz
28
Preliminary
H7A36QP
0233H Port-1 IRQ Mask
Bit No.
Bit Name
Read/Write
Reset
7
6
P17 IRQ
P16 IRQ
R/W
R/W
0
0
0233H ,Port-1 IRQ Mask (Interrupt Enable) Register
5
4
3
2
P15 IRQ
P14 IRQ
P13 IRQ
P12 IRQ
Enable/Disable Enable/Disable Enable/Disable Enable/Disable
R/W
R/W
R/W
R/W
0
0
0
0
1
0
P11 IRQ
P10 IRQ
R/W
R/W
0
0
Port-1[7..0] Interrupt Enable/Disable. Default is 00H.
 0 = Disable.
 1 = Enable.
0234H Port-1 IRQ Edge
Bit No.
Bit Name
Read/Write
Reset
7
P17
IRQ Edge
R/W
0
6
P16
IRQ Edge
R/W
0
0234H , Port-1 IRQ Edge (Polarity) Register
5
4
3
P15
P14
P13
IRQ Edge
IRQ Edge
IRQ Edge
R/W
R/W
R/W
0
0
0
2
P12
IRQ Edge
R/W
0
1
P11
IRQ Edge
R/W
0
0
P10
IRQ Edge
R/W
0
2
P12
IRQ Status
R/W
0
1
P11
IRQ Status
R/W
0
0
P10
IRQ Status
R/W
0
Port-1[7..0] Interrupt by falling edge or rising edge (Polarity). Default is 00H.
 0 = Falling Edge.
 1 = Rising Edge.
0235H Port-1 IRQ Status
Bit No.
Bit Name
Read/Write
Reset
7
P17
IRQ Status
R/W
0
6
P16
IRQ Status
R/W
0
0235H ,Port 1 Interrupt Request Status
5
4
3
P15
P14
P13
IRQ Status
IRQ Status
IRQ Status
R/W
R/W
R/W
0
0
0
Port 1 interrupt statuses, read to check if the corresponding pin interrupted or not, write 0 for clearing status and
write 1 for affecting nothing.
0236H Timer-2 Control Byte-0
Bit No.
Bit Name
Read/Write
Reset
7
6
T2 Enable
Repeat Mode
R/W
0
R/W
0
0236H ,Timer-2 Control Register – Byte-0
5
4
3
2
T2 Output
T2 Function Mode
Capture Select
Polarity
R/W
R/W
R/W
R/W
0
0
0
0
1
0
T2 Clock Source
R/W
0
R/W
0
D[1:0] Select Timer-2 Clock Source, Default is 0:
 0 = CPU-Clock.
 1 = Base-Clock.
 2 = External Clock Rising.
 3 = External Clock Falling.
This bit is used to select the clock source for Timer-2, and in the external clock mode (2 and 3), the clock
input is defined by bit 3~0 of ”Timer-2 Control Byte-1”.
D[3:2] Timer-2 Function Mode, Default is 0:
 0 = Timer/Counter mode.
 1 = Compare Output mode.
 2 = Capture Rising mode.
 3 = Capture Falling mode.
 0: Timer/Counter Mode:
Set Timer-2 to counter mode, and it is a 16 bit up-counter. The timer-2 interrupt status is set to 1 when the
timer-2 up-counter reaches the compare value, and then the counter is cleared to 0.
29
Preliminary
H7A36QP
 1: Compare Output:
30
T2 Clock Select
T2 Function = 01
Compare Output
Capture Mode
T2 Output Polarity
One-shot / Repeat
T2 Enable/Disable
External Clock Select
Compare Output
Select
P1 Cells
P0 Cells
In this mode, the Timer-2 is also a 16 bit up-counter, and the counter function is same as counter mode,
and additionally, the counter reaching the compare value would output a clock pulse on the I/O pin that is
defined by the bit 7~4 of “Timer-2 Control Byte-1” and the active polarity is defined by bit 5 of this register.
Preliminary
H7A36QP
 2 : Capture Rising:
 3 : Capture Falling:
The Timer-2 is also a 16 bit up-counter. The counter always counts until the Capture-Event occurs, and
then the counter value is latched to the “Timer-2 Compare” register.
The Capture-event is defined to capture the external input by setting the bit 4 of this register to 0, or
capture the internal interrupt event by setting bit 4 to 1.
The external input for capture event is defined by setting the bit 3~0 of “Timer-2 Control Byte-1”, and the
internal interrupt event is defined by setting the bit 7~4 of “Timer-2 Control Byte-1”.
D[4] Capture Select, Default is 0:
 0 = Capture external input.
 1 = Capture internal IRQ.
In capture external input, the input source is defined by the bit 3~0 of “Timer-2 Control Byte-1”.
In capture internal IRQ, the interrupt source is defined by the bit 7~4 of “Timer-2 Control Byte-1”.
D[5] Timer-2 output polarity, Default is 0:
 0 = Low.
 1 = High.
In output compare mode, this bit is used to drive the output pulse in high or low.
D[6] One-shot/Repeat mode, Default is 0:
 0 = One-shot.
 1 = Repeat.
Writing 0 to this bit and enabling Timer-2 is for one-shot operating, in other word, the interrupt occurs one
time. So, one-shot mode can be re-started by writing this register again.
In repeat mode, the timer-2 counter is always operating, and the IRQ status is set to 1 when the event
occurs.
D[7] Timer-2 Enable/Disable, Default is 0:
 0 = Disable.
 1 = Enable.
Bit No.
Bit Name
7
6
5
4
3
Compare Output I/O Select
2
1
External Clock I/O Select
31
0
H7A36QP
Preliminary
R/W
0
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D[3:0] Select external clock source (input), Default is 0:
 7-0 = Port-0[7:0].
 15-8 = Port-1[7:0].
D[7:4] Select compare output, Default is 0:
 7-0 = Port-0[7:0].
 15-8 = Port-1[7:0].
In compare output mode, the I/O is fixed to output mode, but the resistive control is effective.
Bit No.
Bit Name
7
5
4
3
6
Capture Interrupt Select
R/W
0
Read/Write
Reset
R/W
0
R/W
0
2
1
0
Capture Clock Select
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D[3:0] Select capture input, Default is 0:
 7-0 = Port-0[7:0].
 15-8 = Port-1[7:0].
D[7:4] Select Capture IRQ, Default is 0:
 0 = Timer-0 IRQ.
 1 = Timer-1 IRQ.
 2 = Reserved.
 3 = Port-0 IRQ.
 4 = SBus IRQ.
 5 = SPI IRQ.
 6 = PWM-0 IRQ.
 7 = PWM-1 IRQ.
 15-8 = Port-1[7:0].
0239H Timer-2 Compare Low-Byte
023AH Timer-2 Compare High-Byte
Bit No.
15
14
0239H~023AH, Timer-2 Compare Data Register (16 bit)
023AH High Byte
0239H Low Byte
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16-bit Timer-2 Compare Data
Bit Name
R/W
0000H
Read/Write
Reset
In counter mode or compare output mode, these 16 bit are used to define the compare value, when
counter reaches this value, the counter would be cleared and set the Timer-2 IRQ status to 1.
In capture mode (rising or falling), the 16 bit are used to store (copy) the counter value while the event
occurs.
023BH Timer-2 Data Low-Byte
023CH Timer-2 Data High-Byte
Bit No.
15
14
023BH~023CH, Timer-2 Data Register (16 bit)
023CH High Byte
13
12
11
10
9
8
7
6
023BH Low Byte
5
4
3
2
1
0
16-bit Timer-2 Data (Counter value)
Bit Name
R/W
0000H
Read/Write
Reset
In counter mode or compare output mode, these 16 bit are used to define the compare value, when counter
reaches this value, the counter would be cleared and set the Timer-2 IRQ status to 1.
In capture mode (rising or falling), the counter are stopped while the event occurs.
023DH PWM Control
Bit No.
Bit Name
Read/Write
7
Resolution
Mode
R/W
6
Enable
PWM Output
R/W
023DH ,PWM Control Register
5
4
3
Active Duty
PWM Clock Pre-scale
Polarity
R/W
R/W
R/W
32
2
1
0
PWM Duty[9..8]
R/W
R/W
R/W
Preliminary
H7A36QP
Reset
0
0
0
0
0
0
0
0
2
1
0
R/W
0
R/W
0
R/W
0
D[1:0] PWM Duty [9..8], Default is 0.
D[4:2] PWM Pre-scale, Default is 0:
 PWM-0 Clock = System Clock / (D[4:2] + 1).
D[5] Polarity of Active duty, Default is 0:
 0 = Low.
 1 = High.
D[6] PWM Output (on Port-2[0]) Enable/Disable, Default is 0:
 0 = Disable.
 1 = Enable.
This bit is used to enable the PWM-0 and output PWM duty on the Port-2[0].
D[7] PWM Resolution, Default is 0:
 0 = 8 Bits.
 1 = 10 Bits.
023EH PWM Duty
Bit No.
Bit Name
Read/Write
Reset
7
6
5
023EH ,PWM Duty Register
4
3
PWM Duty[7..0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D[7:0] : PWM Duty [7..0], Default is 0.
In 8 bit mode, writing this register to change the active duty of PWM-0.
In 10 bit mode, writing “PWM control” register would not direct change the active duty, the 10 bit active duty are
updated together with writing the “PWM Duty”.
023FH  ADC Control
Bit No.
Bit Name
Read/Write
Reset
7
Delta-Sigma
Enable/Disable
R/W
0
6
Delta-Sigma
Read Mode
R/W
0
023DH , Delta-Sigma ADC Control
5
4
3
R/W
0
R/W
0
2
1
0
Delta-sigma ADC2 pre-scale
Delta-sigma ADC2 Decimation
R/W
0
R/W
0
R/W
0
R/W
0
D[3:0]Delta-sigma ADC2 pre-scale.
Delta-sigma ADC clock = System Clock / (D[3:0]+1)
Minimum setting is 3.
D[4:2] Delta-sigma ADC2 decimation selection:
 0 = 64 samples
 1 = 128 samples
 2 = 256 samples
 3 = 512 samples
Recommend setting is 256 or 512 samples. In 256 samples, the ADC resolution is 14bit accuracy.
D[5] Delta-sigma read mode:
 0 = ADC2 read delta-sigma.
 1 = ADC0 read delta-sigma.
D[6] Delta-sigma enable/disable:
 0 = Disable.
 1 =Enable.
When enable delta-sigma, you can read ADC0 or ADC2 to get the result of delta-sigma ADC.
0300H Math Control
Bit No.
7
Register (MTHCR)
6
0300H , Math Control Register (MTHCR)
5
4
3
33
2
1
0
Preliminary
H7A36QP
Reserved
Bit Name
R
0
Read/Write
Reset
R
0
Math
Math Division
Multiplication
Status
Status
R/W
R/W
0
0
Math Status
Reserved
Math Clock
Select
R/W
0
R/W
0
R/W
0
Unsigned/
Signed
Multiplication
R/W
0
[7:6] Reserved.
[5] Math Multiplication Status: This bit is used to represent the status of multiplication computation. It is asserted
during multiplication is processing and deasserted when multiplication is done.
 0 = Multiplication done/Idle.
 1 = Multiplication still going.
[4] Math Division Status: This bit is used to represent the status of division computation. It is asserted during
division is processing and deasserted when division is done.
 0 = Division done/Idle.
 1 = Division still going
.
[3] Math Status: This bit represents the status of math module. It is asserted when math computation is still
processing and deasserted when computation is done.
 0 = Computation is done/idle.
 1 = Busy (Still in computation).
[2] Reserved
[1] Math Clock Select: This bit is used to select the operating clock frequency for math computation.
 0 = Normal Mode with system clock frequency.
 1 = Turbo Mode with double system clock frequency.
[0] Unsigned/Signed Multiplication: This bit is used to choose either unsigned number or signed number for
multiplication.
 0 = using unsigned multiplication.
 1 = using signed multiplication.
0301H Multiplicator/Divisor Low Register (MDLR)
Bit No.
7
6
0301H, Multiplicator/Divisor Low Register (MDLR)
5
4
3
Read/Write
Reset
2
1
0
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Multiplicator/ Divisor Low Byte
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0302H Multiplicator/Divisor High Register (MDHR)
Bit No.
7
6
0302H, Multiplicator/Divisor High Register (MDHR)
5
4
3
2
Multiplicator/ Divisor High Byte
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
These two bytes are used to set the value of either 16-bit multiplicator or 16-bit divisor depending on the
MULT/DIV mode set in math control register (MTHCR)
0303H Multiplicand Low Byte /Multiplication Product Byte 0 Register (MHMP0)
Bit No.
7
0303H , Multiplicand Low Byte/ Multiplication Product Byte 0 Register (MHMP0)
6
5
4
3
2
1
Read/Write
Reset
0
Multiplicand Low Byte/ Multiplication Product Byte 0
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0304H Multiplicand High Byte /Multiplication Product Byte 1 Register (MHMP1)
Bit No.
7
0304H , Multiplicand High Byte/ Multiplication Product Byte 1 Register (MHMP1)
6
5
4
3
2
1
Read/Write
Reset
0
Multiplicand High Byte/ Multiplication Product Byte 1
Bit Name
R/W
0
R/W
0
R/W
0
R/W
0
34
R/W
0
R/W
0
R/W
0
R/W
0
Preliminary
H7A36QP
These two bytes can be used to write the value of 16-bit multiplicand for multiplication. The multiplication will
be triggered after High Byte data is written to MHMP1 register.
0305H Multiplication Product Byte 2 Register (MP2R)
Bit No.
7
6
0305H , Multiplication Product Byte 2 Register (MP2R)
5
4
3
2
1
0
R
0
R
0
R
0
0306H , Multiplication Product Byte 3 Register (MP3R)
5
4
3
2
1
0
R
0
R
0
Multiplication Product Byte 2
Bit Name
Read/Write
Reset
R
0
R
0
R
0
R
0
R
0
0306H Multiplication Product Byte 3 Register (MP3R)
Bit No.
7
6
Multiplication Product Byte 3
Bit Name
Read/Write
Reset
R
0
R
0
R
0
R
0
R
0
R
0
The 32-bit product of multiplication can be obtained by reading out the 4 registers from 0303H to 0305H.
0307H Dividend Byte-0/Quotient Low Byte Register (DIV0QL)
Bit No.
7
0307H , Dividend Byte 0/ Quotient Low Byte Register (DIV0QL)
6
5
4
3
2
1
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Dividend Byte 0/ Quotient Low Byte
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0308H Dividend Byte-1/Quotient High Byte Register (DIV1QH)
Bit No.
7
0308H , Dividend Byte 1/ Quotient Low Byte Register (DIV1QH)
6
5
4
3
2
Dividend Byte 1/ Quotient High Byte
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
These two bytes are used to set the byte 1 & byte0 of the 32-bit dividend for computation of division. They can
be also read out to get the 16-bits quotient of division after computation is finished.
0309H Dividend Byte-2/Remainder Low Byte Register (DIV2RL)
Bit No.
7
0309H , Dividend Byte 2/ Remainder Low Byte Register (DIV2RL)
6
5
4
3
2
1
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Dividend Byte2/ Remainder Low Byte
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
030AH Dividend Byte-3/Remainder High Byte Register (DIV3RH)
Bit No.
7
030AH , Dividend Byte 3/ Remainder High Byte Register (DIV3RH)
6
5
4
3
2
Dividend Byte3/ Remainder High Byte
Bit Name
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
These two bytes are used to set the byte 2 & byte3 of the 32-bit dividend for computation of division. They can
be also read out to get the 16-bits remainder of division after computation is finished.
Note that the computation of division is triggered after dividend byte 3 is written.
030BH/0000H Math X-PTR Low-Byte
030CH/0001H Math X-PTR High-Byte
35
Preliminary
H7A36QP
Bit No.
15
14
030BH~030CH or 0000H~0001H,X-Pointer Register
0001H High Byte
0000H Low Byte
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16-bit X-Pointer or 16-bit X data
Bit Name
R/W
0000H
Read/Write
Reset
This 16 bit register is defined to two modes:
Pointer Mode (or Address Mode)
If the bit 1~0 of “Math Control Byte-0” are set to 01 or 11, these 16 bit are defined to X-Pointer for output 16
bit address while the mathematical co-processor (also named math-processor) is operating.
Besides, the programmer can use these 16 bit to address the memory and access the data by reading or
writing the address of 20H~21H.
Data Mode
If the bit 0 of “Math Control Byte-0” is set to 0, these 16 bit are defined to data for free accessing or direct data
for X item by math-processor.
030DH/0002H Math Y-PTR Low-Byte
030EH/0003H Math Y-PTR High-Byte
Bit No.
15
14
030DH~030EH or 0002H~0003H,Y-Pointer Register
0003H High Byte
0002H Low Byte
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16-bit Y-Pointer or 16-bit Y data
Bit Name
R/W
0000H
Read/Write
Reset
If the bit 3~2 of “Math Control Byte-0” are set to 01 or 11, these 16 bit are defined to Y-Pointer for
output 16 bit address while the math-processor is operating.
Besides, the programmer can use these 16 bit to address the memory and access the data by reading or
writing the address of 22H~23H.
Data Mode
for Y item by math-processor.
030FH/0004H Math Z-PTR Low-Byte
0310H/0005H Math Z-PTR High-Byte
Bit No.
15
14
030FH~0310H or 0004H~0005H,Z-Pointer Register
0005H High Byte
13
12
11
10
9
8
7
6
0004H Low Byte
5
4
3
2
1
0
16-bit Z-Pointer or 16-bit Z data
Bit Name
R/W
0000H
Read/Write
Reset
If the bit 5~4 of “Math Control Byte-0” are set to 01 or 11, these 16 bit are defined to Z-Pointer for output 16 bit
address while the math-processor is operating.
In the program, the programmers can set bit 6 of “Math Control Byte-0” to 1 and use these 16 bit to address
the memory and access the data by reading or writing the address of 24H~25H. In additional, the programmers
can set bit 6 of “Math Control Byte-0” to 0 and use these 16 bit combined with high byte of Y-Pointer to form a 24
bit ZY-Pointer to access data from the register of 24H and 25H.
Data Mode
for Z item by math-processor.
0311H/0006H
0312H/0007H
Math i-PTR Low-Byte
Math i-PTR High-Byte
0311H~0312H or 0006H~0007H,i-Pointer Register
0003H High Byte
36
0002H Low Byte
H7A36QP
Preliminary
Bit No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16-bit i-Pointer or 16-bit Y data
Bit Name
R/W
0000H
Read/Write
Reset
The result pointer or start address of searching.
0313H/0008H
Bit No.
Bit Name
Read/Write
Reset
Math Control Byte-0
7
Accelerate
Mathprocessor
R/W
0
6
Signed
/Unsigned
R/W
0
0318H or 0008H ,Math Control Byte-0
5
4
3
Z-Pointer Mode
R/W
0
R/W
0
2
Y-Pointer Mode
R/W
0
R/W
0
1
0
X Pointer Mode
R/W
0
R/W
0
D[5:0] Data pointer (PTR) mode selection. Default is 0:
 D[1:0] = X-PTR mode.
 D[3:2] = Y-PTR mode.
 D[5:4] = Z-PTR mode.
Data pointer mode definition:
 00 = immediate data.
 01 = Data pointer.
 10 = Data pointer with auto-decrement.
 11 = Data pointer with auto-increment.
If the data pointer is set to auto-increment or auto-decrement, the data pointer will be increased or
decreased after accessing the associative data port, because the data width is 16bit (one word=2 bytes).
D[7:6] m operator mode selection. Default is 0:
 00 = ADD : ∑{│[│(Xi + Yi)│ * Zi]│²}.
 01 = SUB : ∑{│[│(Xi - Yi)│ * Zi]│²}.
 10 = MUL : ∑{│[│(Xi * Yi)│ * Zi]│²}.
 11 = Reserved.
0314H/0009H
Bit No.
Bit Name
Read/Write
Reset
Math Control Byte-1
0314H or 0009H , Math Control Byte-1
5
4
3
2
1
0
(YmY)*Z
Save result
XmY modulus Result bit width
Power 2
Array Calculating Function Mode
modulus
Enable/Disable
Selection
Enable/Disable
Enable/Disable
Enable/Disable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
D[0] Save result function enable/disable. Default is 0:
 0 = Disable.
 1 = Enable.
The result of array calculating can be stored to the memory by addressing of i_PTR, and it can use the
searching function to get the maximum or minimum result.
If enable this function, the math-processor will spend more 2 or 4 clocks in operation.
D[1] Result bit width selection. Default is 0:
 0 = 32-Bits.
 1 = 16-Bits.
When use the result restoring function, this bit is configured to store the result in 32-bits or 16-bits. If
select 16-bits, only the high 16-bit is effective.
D[2] (Xi m Yi) result is modulus. Default is 0:
 0 = Disable.
 1 = Enable.
When this function is enabled, the result is modulus.
D[3] [(Xi m Yi) * Zi] result is modulus. Default is 0:
 0 = Disable.
 1 = Enable.
37
Preliminary
H7A36QP
When this function is enabled, the result is modulus.
D[4] [ (Xi m Yi) * Zi]² function enable or disable:
 0 = Disable.
 1 = Enable.
Set this bit to enable the power 2 operation.
D[7:5] Array Calculating Function mode. Default is 0:
 000 = Array calculating.
 001 = Array moving.
 010 = 16 bit faster multiplier.
 011 = 32 bit divider.
 100 = 16 bit searching minimum value.
 101 = 16 bit searching maximum value.
 110 = 32 bit searching minimum value.
 111 = 32 bit searching maximum value.
D[7:5] = 000 :Calculate ∑{│[│(Xi m Yi)│ * Zi]│²}.
Write anything to ”Math-Item Low-Byte” to enable and start array operation of Math-processor. And, the
Math-processor is a DMA architecture, so the CPU will release the system bus for math-processor
operating, and continue executing after the math-processor completing the operation.
Executing array calculating needs 6n + 3 clock cycles, n is item number. For example, if the item is 27,
the array calculating spends 165 clock cycle to complete operation.
Example:
The given condition is bellow: ∑{│[│(Xi - Yi)│ * Zi]│²}
X_PTR -> A000H
X[0]:0123H:291
X[1]:1234H:4660
X[2]:2345H:9029
X[3]:3456H:13398
MOVEW
MOVEW
MOVEW
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
Y_PTR -> B000H
Y[0]:0246H:582
Y[1]:2468H:9320
Y[2]:468AH:18058
Y[3]:68ACH:26796
Z_PTR -> C000H
Z[0]:1357H:4951
Z[1]:3579H:13689
Z[2]:579BH:22427
Z[3]:79BDH:31165
[MATH_X_PTR], A000H
; Setting X_PTR to A000H
[MATH_Y_PTR], B000H
; Setting Y_PTR to B000H
[MATH_Z_PTR], C000H
; Setting Z_PTR to C000H
[MATH_CONTROL+0], 7FH
; m[1:0], Z_MODE[1:0], Y_MODE[1:0], X_MODE[1:0]
[MATH_CONTROL+1], 10H
; MODE[2:0], SQUARE, ABS_XYZ, ABS_XY, ITEM_16, SAVE_ITEM
; ADJ, SIGNED, PTR_XYZ, SHIFT, RIGHT, OSEL[2:0]
[MATH_ITEM+0], 03H ; 4 Element
AX, [MATH_RESULT+0]
; Will Get Byte1-0 B7FCH
AX, [MATH_RESULT+2]
; Will Get Byte3-2 030BH
A, [MATH_RESULT+4]
; Will Get Byte4 00H
Trace List :
X[0]:0123H:291
FEDDH:-291
FFEAH:-22
SUM 0000000000H
X[1]:1234H:4660
EDCCH:-4660
FC32H:-974
SUM 00000001E4H
X[2]:2345H:9029
DCBBH:-9029
F3EEH:-3090
SUM 00000E7BA8H
X[3]:3456H:13398
CBAAH:-13398
E71CH:-6372
SUM 0000A02CECH
*
^
+
*
^
+
*
^
+
*
^
+
Y[0]:0246H:582
Z[0]:1357H:4951
2
000001E4H
Y[1]:2468H:9320
Z[1]:3579H:13689
2
000E79C4H
Y[2]:468AH:18058
Z[2]:579BH:22427
2
0091B144H
Y[3]:68ACH:26796
Z[3]:79BDH:31165
2
026B8B10H
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
FEDDH:-291
FFEA041BH:-1440741
000001E4H:484
00000001E4H:484
EDCCH:-4660
FC32A16CH:-63790740
000E79C4H:948676
00000E7BA8H:949160
DCBBH:-9029
F3EE3239H:-202493383
0091B144H:9548100
0000A02CECH:10497260
CBAAH:-13398
E71CB682H:-417548670
026B8B10H:40602384
00030BB7FCH:51099644
If the operator m of X and Y is a multiply, the result is effective and stored the MSB 16 bit of result, the
LSB is abort. Then, the previous result is multiplied with the Z item, and the result is also stored the MSB
16bit. If you enable the power 2 operation, the result of power 2 is stored with 32 bit.
If the operator m of X and Y items is add or subtract, the array calculating will use the signed or unsigned
definition to get and clamp the maximum value of 16 bit in signed (7FFFH) or unsigned (8000H).
Given the item number of the array calculating to 4, this operation would spend 27 (4x6+3=27) clock
cycles, if the accelerator is enabled (double clock speed), this operation would spend 13.5 clock cycles,
and the result is 00030BB7FCH. After completing this operation, the X/Y/Z-PTR are all increased in 8,
because each item is 16 bit.
D[7:5] = 001 : block moving (copying).
Data length is 65536 (bytes) in maximum.
Before writing ”Math-Item High-Byte” to trigger block copying, setting the source address and destination
address and configure the bit-5 of ”Math-Control Byte-2”.
If interface the NAND flash, you can configure source PTR to auto-increment, and the destination address
is fixed.
D[7:5] = 010 : 16 bit fast multiplier.
38
Preliminary
H7A36QP
Move you multiplicand to X (16bit) and multiplier to Y(16bit), and D[6] is configured to signed or unsigned,
the result of multiplier can be direct get from “Result3-0” (0318H~031BH or 000DH~0010H).
D[7:5] = 011 : 32 bit divider.
When enabling the 32-bit divider, Math X-PTR is a 16-bit Divid, and Math Y-PTR and Math Z-PTR are
formed a 32-bit Divided. By writing Byte-3, the divider is triggered and completed after 16 clock cycles (if
the accelerator is enabled, it needs only 8 clock cycles).
D[7:5] = 100 : 16 bit minimum value searching in array.
D[7:5] = 101 : 16 bit maximum value searching in array.
D[7:5] = 110 : 32 bit minimum value searching in array.
D[7:5] = 111 : 32 bit maximum value searching in array.
The searching function can be used for finding the minimum or maximum 16 or 32 bits data, and the
searching length can be 65536 bytes in maximum. Before writing”Math-Item High-Byte” to trigger for
searching, you have to set and configured the start address by writing i-PTR.
After completing the searching, the X-PTR is pointing at the result address, and Y-PTR is a 16 bit
searching result in 16-bit searching mode, in the other, ZY-PTR is a 32 bit searching result in 32 bit
searching mode.
Searching will spend 2n clock cycles in 16 bit searching mode, and 4n clock cycles in 32 bit searching
mode.
0315H/000AH Math Control Byte-2
Bit No.
Bit Name
Read/Write
Reset
7
6
Overflow
Signed/Unsigned
adjust
Enable/Disable
R/W
R/W
0
0
0315H or 000AH ,Math Control Byte-2
5
4
3
2
1
PTR Mode
32 Bit PTR shift
Enable Disable
32 Bit PTR shift
direction
Result 3-0 selection
R/W
0
R/W
0
R/W
0
R/W
0
0
D[2:0] Adjust the Result3-0 of array calculating. Default is 0:
 000 = SUM[31:0].
 001 = SUM[32:1], data right-shift 1 bit.
The real result of array calculating is 40 bit data, you can select the effective bits of result by setting these
3 bits as above list. By the way, the D[7] (bit 7 of this control register) can be configured to adjust the
result while the overflow happening.
Reading Result[4] is always to get the bit 39~32 of the result.
D[3] 32 bit PTR data shift direction. Default is 0:
 0 = shift left.
 1 = shift right.
D[4] 32 bit PTR data shift function enable/disable. Default is 0:
 0 = Disable.
 1 = Enable.
The 32-bit data is formed by Z_PTR[15:0]:Y_PTR[15:0]. By setting D[6] (signed/unsigned) and D[2:0] shift
controlling that can shift left or right in 1 ~8 bit, and then you can read the specified result from Result[4:0].
Besides, you can specify D[7] to clamp the maximum signed or unsigned value that is stored on
Result[4:0].
Actually, the Z_PTR[15:0]:Y_PTR[15:0] would not be changed, the shift function only form the result and
can be read from Result[4:0].
D[4]=1 : Result[4:0] = Z_PTR[15:0]:Y_PTR[15:0] with shift operation.
D[4]=0 : Result[4:0] = Array calculating Result.
39
Preliminary
H7A36QP
Example:
MOVEW
MOVEW
[MATH_Y_PTR], 7654H
[MATH_Z_PTR], BA98H
; Setting Y_PTR as 7654H
; Setting Z_PTR as BA98H
MOVE
MOVE
MOVE
MOVE
AX, [MATH_RESULT+0]
AX, [MATH_RESULT+2]
A, [MATH_RESULT+4]
MOVE
[MATH_CONTROL+2], D9H
MOVE
MOVE
MOVE
AX, [MATH_RESULT+0]
AX, [MATH_RESULT+2]
A, [MATH_RESULT+4]
MOVE
MOVE
MOVE
MOVE
AX, [MATH_RESULT+0]
AX, [MATH_RESULT+2]
A, [MATH_RESULT+4]
MOVE
MOVE
MOVE
MOVE
AX, [MATH_RESULT+0]
AX, [MATH_RESULT+2]
A, [MATH_RESULT+4]
MOVE
MOVE
MOVE
MOVE
AX, [MATH_RESULT+0]
AX, [MATH_RESULT+2]
A, [MATH_RESULT+4]
MOVE
[MATH_CONTROL+2], D3H
MOVE
MOVE
MOVE
AX, [MATH_RESULT+0]
AX, [MATH_RESULT+2]
A, [MATH_RESULT+4]
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
ADJ, SIGNED, PTR_XYZ, SHIFT, RIGHT, OSEL[2:0]
BA987654 >> 2 = EEA61D95H <--- FFEEA61D95H Signed No-Adjust
AX = 1D95H
AX = EEA6H
A = FFH
-------------------------------------------------------ADJ, SIGNED, PTR_XYZ, SHIFT, RIGHT, OSEL[2:0]
BA987654 >> 2 = EEA61D95H <--- FFEEA61D95H Signed Adjust
AX = 1D95H
AX = EEA6H
A = FFH
BA987654 << 3 = D4C3B2A0H <--- 05D4C3B2A0H Unsigned No-Adjust
AX = B2A0H
AX = D4C3H
A = 05H
BA987654 << 3 = FFFFFFFFH <--- 05D4C3B2A0H Unsigned Adjust
AX = FFFFH
AX = FFFFH
A = 05H
BA987654 << 4 = A9876540H <--- FBA9876540H Signed No-Adjust
AX = 6540H
AX = A987H
A = FBH
BA987654 << 4 = 80000000H <--- FBA9876540H Signed Adjust
AX = 0000H
AX = 8000H
A = FBH
D[5] Data PTRs mode. Default is 0:
 0 = 001CH/0384H data port is addressed by Z-PTR[15:0]: Y[15:8] that is a 24 bit pointer.
 1 = 001CH/0384H data port is addressed by Z-PTR[15:0] that is a 16 bit pointer.
D[5] = 0 : 001CH/0384H data port is addressed by Z-PTR[15:0]: Y[15:8] that is a 24 bit pointer.
WORD
0018H
X-PTR[15:0]
WORD
001AH
Y-PTR[15:0]
WORD
001CH
Z-PTR[15:0]: Y[15:8]
WORD
001EH
Y-PTR[7:0]:X-PTR[15:0]
If Setting MATH_XYZ_PTR as Follow:
MOVEW
[MATH_X_PTR], 0123H
; Setting X_PTR to 0123H
MOVEW
[MATH_Y_PTR], 4567H
; Setting Y_PTR to 4567H
MOVEW
[MATH_Z_PTR], 89ABH
; Setting Z_PTR to 89ABH
Example
MOVE
MOVE
MOVE
MOVE
Code With D[5]=0:
AX, [18H]
AX, [1AH]
AX, [1CH]
AX, [1EH]
;
;
;
;
Will
Will
Will
Will
Read
Read
Read
Read
2
2
2
2
Bytes
Bytes
Bytes
Bytes
of
of
of
of
Address
Address
Address
Address
000123H
004567H
89AB45H
670123H
D[5] = 1 : 001CH/0384H data port is addressed by Z-PTR[15:0] that is a 16 bit pointer.
WORD
0018H
X-PTR[15:0]
WORD
001AH
Y-PTR[15:0]
WORD
001CH
Z-PTR[15:0]
WORD
001EH
Y-PTR[7:0]:X-PTR[15:0]
Example
MOVE
MOVE
MOVE
MOVE
Code With D[5]=1:
AX, [18H]
AX, [1AH]
AX, [1CH]
AX, [1EH]
;
;
;
;
Will
Will
Will
Will
Read
Read
Read
Read
2
2
2
2
Bytes
Bytes
Bytes
Bytes
of
of
of
of
Address
Address
Address
Address
000123H
004567H
0089ABH
670123H
D[5]=1
D[5]=0
16
16
16
16
16
24
24
24
0018H is addressed by X-PTR[15:0] (16 bit pointer).
001AH is addressed by Y-PTR[15:0] (16 bit pointer).
001EH is addressed by Y[7:0]:X-PTR[15:0] (24 bit pointer).
Reading these data port ( [0018H] ~ [001EH]) the data pointer may be increased or decreased by autoincrement/decrement setting.
D[6] Math-Processor’s data type (signed or unsigned). Default is 0:
 0 = signed.
 1 = unsigned.
40
Preliminary
H7A36QP
D[7] accelerator (double clock) enable disable / overflow clamp enable/disable. Default is 0:
 0 = system clock and not clamping when overflow.
 1 = 2 x system clock and clamping when overflow.
0316H/000BH Math-item Low-Byte
0317H/000CH Math-item Low-Byte
Bit No.
15
14
0316H~0317H or 000BH~000CH, Math-item
0317H/000CH High Byte
13
12
11
10
9
8
7
6
0316H/000BH Low Byte
5
4
3
2
1
0
16-bit item number
Bit Name
R/W
0000H
Read/Write
Reset
Item number = N+1.
(1) Array calculating function: The maximum item is 256, so you can just only write the low-byte to set the item
number and trigger the array calculating.
(2) Block moving (copying) function or searching function: The maximum item number is 65536, and write the lowbyte first, and then write the high-byte to trigger moving or searching function.
0318H/000DH
0319H/000EH
031AH/000FH
031BH/0010H
031CH/0011H
Bit No.
Math Result Byte-0
Math Result Byte-1
Math Result Byte-2
Math Result Byte-3
Math Result Byte-4
0008H~000BH,Math Result Register
031BH/0010H
031AH/000FH
0319H/000EH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
0318H/000DH
5 4 3 2
1
0
40 bits Result Data
Bit Name
R
0000H
Read/Write
Reset
0008H~000BH,Math Result Register
031CH/0011H
Bit No.
39 38 37 36 35 34 33 32
40 bits Result Data
Bit Name
R
0000H
Read/Write
Reset
Read these bytes to get the result of math-processor.
0380H/0018H
0381H/0019H
Bit No.
15
X-PTR Data Low-Byte
X-PTR Data High-Byte
14
0380H~0381H or 0018H~0019H, X-PTR Data Register (16 bit)
0381H/0019H High Byte
0380H/0018H Low Byte
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16-bit Data Register (X-PTR)
Bit Name
R/W
X
Read/Write
Reset
Reading/Writing this register is for reading/writing data that are addressed by X-pointer (16 bit address) register.
Besides, if the X-pointer is set to auto-increment mode, the X-pointer is auto increased by 2 after accessing one
word (two byte).
Because the pointer is designed to access word (16 bit), accessing the low byte only causes the X-pointer
increased by 1 (X-pointer+1), even the auto-increment is disable or enable.
And, accessing the high byte only causes the X-pointer decreased by 1 (X-pointer-1) while the auto-increment is
disable.
0382H/001AH Y-PTR Data Low-Byte
0383H/001BH Y-PTR Data High-Byte
Bit No.
Bit Name
15
14
0022H~0023H, Y-PTR Data Register (16 bit)
0023H High Byte
13
12
11
10
9
8
7
6
16-bit Data Register (Y-PTR)
41
0022H Low Byte
5
4
3
2
1
0
Preliminary
H7A36QP
R/W
X
Read/Write
Reset
The usage is same as X-pointer.
0384H/001CH Z-PTR Data Low-Byte
0385H/001DH Z-PTR Data High-Byte
Bit No.
15
14
0384H~0385H or 001CH~001DH, Z-PTR Data Register (16 bit)
0385H/001DH High Byte
0384H/001CH Low Byte
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
16-bit Data Register (Z-PTR)
Bit Name
R/W
X
Read/Write
Reset
The usage is same as X-pointer.
0386H/001EH ZY_PTR Data Low-Byte
0387H/001FH ZY_PTR Data High-Byte
Bit No.
15
14
0386H~0387H or 001EH~001FH, ZY-PTR Data Register (16 bit)
0387H/001FH High Byte
0386H/001EH Low Byte
13
12
11
10
9
8
7
6
5
4
3
16-bit Data Register (ZY-PTR)
Bit Name
R/W
X
Read/Write
Reset
This register is accessed by ZY-pointer, and ZY-pointer is 24 bit pointer.
NAND Flash Data Port
Bit No.
Bit Name
7
98XXH/9CXXH
6
R/W
98XXH ( or 9CXXH) , NAND Flash Data Port
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
NAND Flash Data [7..0]
Read/Write
Reset
R/W
0
R/W
0
NAND Flash Command Port
Bit No.
Bit Name
7
6
R/W
0
R/W
0
R/W
0
R/W
0
99XXH/9DXXH
R/W
0
R/W
99XXH ( or 9DXXH) , NAND Flash Command Port
5
4
3
NAND Flash Command [7..0]
Read/Write
Reset
NAND Flash Address Port
Bit No.
Bit Name
7
R/W
0
R/W
0
9AXXH/9EXXH
6
R/W
0
R/W
9AXXH ( or 9EXXH) , NAND Flash Address Port
5
4
3
NAND Flash Address [7..0]
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
If Address[10]=0(98XXH), NAND flash control pins (CEB, CLE, ALE) are only active within one memory accessing
cycle, and CEB returns to logical high level, the ALE and CLE return to logical low level.
If Address[10]=1(9CXXH), NAND flash control pins (CEB, CLE, ALE) are latched to active levels until the program
accesses the space between 9800H to 9BFFH, and the CEB returns to high, the ALE and CLE return to low.
Description of Serial Mode (SBUS)
System will initialize the serial interface after powered on and cannot accept any kind of data transmission on
the bus (no ACK status). The addressing ability of SBUS can support 7bit/10bit cases. There is limitation of minimum
data transmission rate and the maximum transfer rate is up to 4M Bit/s. The following diagram shows the transmission
packet flow and it relationship to the transmission command on SDA/SCL bus.
42
Preliminary
H7A36QP
SDA
SCL
(1)
(2)
(3)
(4)
(5)
(1) Start stage
(2) 7-bit ID (Address) + 1-bit direction (R/W) stage
(3) ACK/NACK acknowledge or none-acknowledge stage
(4) device hold SCL low , not ready for next data transaction.
(5) Stop stage
SDA
0
1
1
1
0
0
0
W
A
D7
D6
D5
D4
D3
D2
D1
D0
SCL
Device ID
7 bits
Start
1st Write Data
R/W Direction
STOP
ACK
D7
D6
D5
D4
D3
D2
D1
D0
A
D7
D6
D5
D4
D3
D2
D1
D0
A
Two-wire serial bus timming conditions
Basic data packet format are as follows:
Master writes data to Slave and issues ACK response.
Master reads data from Slave and the ACK response.
Note: The shadowed square represents the direction of transfer is from master to slave, the blank square
represents the direction of transfer is
43
Preliminary
H7A36QP
Master should read SDA when SCL is high. After data transmission of one packet of 8 bits is finished and the
ACK phase is done, slave device will set SCL to low and execute internal operation. When internal IRQ process
is done, the slave device is then able to receive other data and the SCL should become high again. The master
should monitor the SCL high status at any time of the data transfer in order to get the maximum transfer rate with
correct data.
The following diagram shows the data transfer packet format that master write to the slave:
Slave Address
Command Code
Command Data
Command Data
In case that the slave cannot receive the data, it will send the NACK to the bus as follows:
Slave Address
Command Code
Command Data
Command Data
This case may happen when slave buffer is full and master cannot write data to slave and needs to abort the
data transfer by sending “STOP” to the bus
The following diagram shows the data transfer packet format that master receive data from the slave:
Slave Address
Command Code
Slave Address
Command Data
Command Data
Master should replay Non-Acknowledge to slave to release the SDA bus. The protocol should be followed in
order to keep the 2-wired serial bus valid to be used.
[SR][Slave Address+R] is used to switch the data transfer direction, the direction is from slave to master.
44
Preliminary
H7A36QP
Application Circuit
EV-Board
1
3
4
6
5
P2
U1
I/O Port
R_DAC
GAIN_CO
GAIN_CI
VADC
MIC_P
MIC_N
U3
EN-BUSY
VCC
R8
10K
P11
1
2
EN-NAND
332
PORT0_7
PORT0_6
PORT0_5
PORT0_4
MIC_ALC
DS_FI
DS_FO
PORT2_0
PORT2_1
PORT2_2
PORT2_3
PORT2_4
PORT2_5
PORT2_6
PORT2_7
VCC
VCC
PORT1_7
PORT1_6
PORT1_5
PORT1_4
PORT0_7
PORT0_6
PORT0_3
PORT0_2
PORT0_1
PORT0_0
H7A36QEV
VCC
PORT1_1
PORT1_3
1
2
3
4
S
Q
W
GND
C27
104
VCC
HOLD
C
D
8
7
6
5
DAT A1
DAT A5
DAT A0
DAT A6
ADDR0
DAT A7
ADDR1
OTP_CEB
ADDR2
ADDR10
ADDR3
MRDB
ADDR4
ADDR11
ADDR5
ADDR9
ADDR6
ADDR8
ADDR7
ADDR13
ADDR12
ADDR14
ADDR15
C
H2A36QEV
NAND
NAND FLASH
U4
U6
B
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
DATA1
DATA5
DATA0
DATA6
ADDR0
DATA7
ADDR1
OTP_CE
ADDR2
ADDR10
ADDR3
MRD
ADDR4
ADDR11
ADDR5
ADDR9
ADDR6
ADDR8
ADDR7
ADDR13
ADDR12
ADDR14
ADDR15
ADDR19
ADDR18
ADDR16
ADDR17
2
C3
C9
4.7uF
CPU_CLK
P5
PORT2_3
1
NAND_BUSY
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O 7
I/O 6
I/O 5
I/O 4
NC
NC
NC
VCC
GND
NC
NC
NC
I/O 3
I/O 2
I/O 1
I/O 0
NC
NC
NC
NC
R_DAC
GAIN_CO
GAIN_CI
VADC
MIC_P
MIC_N
AGND
MIC_ALC
DS_FI
DS_FO
PORT20
PORT21
PORT22
PORT23
PORT24
PORT25
PORT26
PORT27
GND
VCC
PORT17
PORT16
PORT15
PORT14
PORT07
PORT06
P ORT05
P ORT04
P ORT03
P ORT02
P ORT01
P ORT00
P ORT13
P ORT12
P ORT11
P ORT10
VPP
C
NC
NC
NC
NC
NC
NC
BUSY
RE
CE
NC
NC
VCC
GND
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VCC
ADDR19
ADDR18
ADDR16
ADDR17
222
CPU_CLK
C8
1
2
3
4
5
6
NAND_BUSY 7
8
PORT1_7
NAND_CEB 9
10
11
VCC
12
C26
104
13
14
15
PORT1_5 16
PORT1_4 17
VCC PORT1_6 18
19
20
21
22
23
24
D
L_DAC
EQ_I
EQ_O
AMP _I N
S PK_N
AVCC
AGND
S PK_P
GND
BUS _REQ
F ORCE_TRAP
CPU_INT
BUS _ACK
OP_FETCH
CLOCK
MCE
MWR
ADDR22
ADDR23
ADDR20
ADDR21
EV_MODE
RES ET
GND
DATA3
DATA2
DATA4
27
25
23
21
19
17
15
13
11
9
7
5
3
1
EV_MODEB
ADDR20
ADDR22
MCEB
EXT _INTB
OP_FET CHB
CPU_INTB
BUS_REQB
EV-ICE
NAND_CEB
PORT2_2
VCC
28
26
24
22
20
18
16
14
12
10
8
6
4
2
PORT2_6
PORT2_4
PORT2_2
PORT2_0
PORT1_6
PORT1_4
PORT1_2
PORT1_0
PORT0_6
PORT0_4
PORT0_2
PORT0_0
PORT0_5
PORT0_4
PORT0_3
PORT0_2
PORT0_1
PORT0_0
PORT1_3
PORT1_2
PORT1_1
PORT1_0
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
PORT2_7
PORT2_5
PORT2_3
PORT2_1
PORT1_7
PORT1_5
PORT1_3
PORT1_1
PORT0_7
PORT0_5
PORT0_3
PORT0_1
RESET B
102
101
100
99
98
97 L_DAC
96 EQ_I
95 EQ_O
94 AMP_IN
93 SPK_N
92 VCC
91
90 SPK_P
89
88 BUS_REQB
87 FORCE_TRAPB
86 CPU_INTB
85 BUS_ACKB
84 OP_FETCHB
83 CLOCK
82 MCEB
81 MWRB
80 ADDR22
79 ADDR23
78 ADDR20
77 ADDR21
76 EV_MODEB
75 RESETB
74
73 DATA3
72 DATA2
71 DATA4
70
69
68
67
66
65
ADDR18
3
ADDR17
5
ADDR14
7
ADDR13
9
ADDR8
11
ADDR9
13
ADDR11
15
MRDB
17
ADDR10
19
OTP_CEB
21
DAT A7
23
DAT A6
25
DAT A5
27
DAT A4
29
DAT A3
31
RESET B
33
ADDR21
35
ADDR23
37
MWRB
39
EXT _REGB
41
CLOCK
43
BUS_ACKB
45
FORCE_T RAPB
ADDR19
ADDR16
ADDR15
ADDR12
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
DAT A0
DAT A1
DAT A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
D
2
P1
VCC
B
VCC
L_DAC
C6
104
R_DAC
C13
104
PORT1_0
PORT1_2
VCC
R6
10K
R7
EQ_I
C24
222
R4
EQ_O C1
104 AMP_IN
10K
10K
SPI-FLASH
C10
VCC
RESET B
C15
R1
P4
X1
VADC
51
102
XP2_4
R2 220uF
4.7K
M+C4
104 MIC_P
PORT2_4
XP2_4
XP2_5
4MHz
C20
12pF
1
2
XP24
P7
C21
12pF
PORT2_5
XP2_5
+ MIC1
VCC
C17
10uF
XP25
M- C5
PORT2_6
XP2_6
X2
XP2_6
XP2_7
SPK
32768
C22
12pF
Title
XP26
P9
C23
12pF
PORT2_7
XP2_7
Size
1
2
3
Number
Revision
B
XP27
2
C12
104
A
1
2
SPK_N
1
C18
10uF
P8
R3
4.7K
A
C11
104
104 MIC_N
SPK1
SPK_P
VCC
1
2
MIC
Date:
File:
4
11-Dec-2008
Sheet of
D:\Project\PCB-Board\H7A36QP EV-Board.DDB
Drawn By:
5
6
Demo-Board
1
2
4
3
VCC
VCC
R1
EQ_O
AMP_IN
SPK_N
48
47
46
45
44
43
42
41
40
39
38
37
EQ_O
AMP _I N
S PK_N
AVCC
AGND
S PK_P
VPP
P ORT10
P ORT11
P ORT12
P ORT13
P ORT00
PORT12
C8
222
NAND
NAND FLASH
S
Q
W
GND
C3
104
VCC
HOLD
C
D
8
7
6
5
GND
PORT10
PORT12
VPP
1
2
3
4
5
6
7
SPK_P
SPK1
SPK_N
PIN-7
C11
104
L_DAC
R6
EQ_I
10K
B
36
35
34
33
32
31
30
29
28
27
26
25
PORT01
PORT02
PORT03
VCC
PORT04
PORT05
PORT06
PORT07
PORT14
PORT15
PORT16
C
H7A36QP LQFP48
SPK
SD
SPI-FLASH
H7A36QPL
PORT01
PORT02
PORT03
VCC
GND
PORT04
PORT05
PORT06
PORT07
PORT14
PORT15
PORT16
R2
C24
222
EQ_O C1
PORT23
PORT22
PORT21
PORT20
RESETB
PORT17
1
2
3
4
C9
4.7uF
P3
RESET B
GND
VCC
PORT00
GND
PORT01
VPP
EQ_I
L_DAC
R_DAC
GAIN_CO
GAIN_CI
AVCC
MIC_P
MIC_N
AGND
MIC_AGC
DS_FI
DS_FO
13
14
15
16
17
18
19
20
21
22
23
24
VCC
PORT11
PORT13
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
MIC_ALC 10
11
12
C7 222
PORT27
PORT26
PORT25
PORT24
VCC
J1
RESET B
GND
VCC
U2
U3
EQ_I
L_DAC
R_DAC
GAIN_CO
GAIN_CI
VADC
MIC_P
MIC_N
P ORT27
P ORT26
P ORT25
P ORT24
VCC
GND
P ORT23
P ORT22
P ORT21
P ORT20
RES ET
P ORT17
VR
SW2
KEY P 12
VR
SW1
KEY P 13
PORT13
PORT00
PORT01
PORT14
PORT15
DIE1
VR1
VR2
VR
SPK_P
VPP
PORT10
PORT11
PORT12
PORT13
PORT00
D
R8
220
VR3
C
R7
220
VCC
PORT03
PORT02
PORT01
PORT00
LED1
LED P02
PORT20
PORT15
PORT14
VCC PORT16
PORT07
PORT06
PORT05
PORT04
LED2
LED P03
PORT23
VCC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O 7
I/O 6
I/O 5
I/O 4
NC
NC
NC
VCC
GND
NC
NC
NC
I/O 3
I/O 2
I/O 1
I/O 0
NC
NC
NC
NC
PORT16
PORT17
PORT22
NC
NC
NC
NC
NC
NC
BUSY
RE
CE
NC
NC
VCC
GND
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
PORT17
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
100
U1
104 AMP_IN
B
10K
VCC
VCC
102 C14
RESET B
R3
C16
51
SW3
RESET
C21
10uF
C6
104
X1
PORT24
VADC
R4 220uF
4.7K
M+C4
PORT25
4MHz
C17
12pF
C18
12pF
104 MIC_P
+ MIC1
MIC
R_DAC
C10
104
R9
10K
M- C5
104 MIC_N
X2
R5
4.7K
PORT26
A
PORT27
32768
C19
12pF
PORT23
C20
12pF
Title
Size
A
Number
Revision
A4
Date:
File:
1
2
3
45
11-Dec-2008
Sheet of
D:\Project\PCB-Board\H2A36QP EV-Board.DDB
Drawn By:
4
Preliminary
H7A36QP
EQ Gain:
Gain (EQ-R) = -Rf (1/Ri)
EQ Low Pass:
FLpass(R) = 1 / (2 x  x Rf x Cf)
EQ High Pass:
FHpass(R) = 1 / (2 x  x Ri x Ci)
46
Preliminary
H7A36QP
Revision History
Version No.
Date
Description
1.0
2009/3/16
Initial release.
47

Preliminary H7A36QP

Transcription

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