3.MVinet Leti Workshop IEDM2014 (2)

Transcription

CoolCube™, a powerful approach
for further 3D VLSI scaling
Maud Vinet • Advanced CMOS Laboratory Manager • CEA-Leti
© CEA. All rights reserved
Common human sense,
when we miss space
M. Vinet| 14/12/2014 | 2
Common human sense,
…we pile up
M. Vinet| 14/12/2014 | 3
Motivations for 3D VLSI
Device scaling more and more difficult and
costly (lithography, material, architecture)
Global IC performance improvement without
device scaling
Natural opportunity for high-level integration
M. Vinet| 14/12/2014 | 4
CoolCubeTM technology
Outline
CoolCube™
unique
features
Opportunities
CoolCube™
enablers
M. Vinet| 14/12/2014 | 5
3D vias density
D = 100.000/mm 2 D = 10.000/mm 2
SOI TSV
Bulk TSV
D> 5.000.000/mm 2
CoolCubeTM
D> 100.000.000/mm 2
P. Batude et al, VLSI 2011
At 14nm node, CoolCubeTM 3D via density D > 100 million vias/mm2
M. Vinet| 14/12/2014 | 6
Power, performance, area, cost metric
Energy – delay – product
(pJ*ns)
CMOS/CMOS FPGA-based circuits benchmark
Area gain = 55%
Performance gain = 23%
Power gain = 12%
14nm
14nm
O. Turkylmaz et al., DATE 2014
= 10nm
M. Vinet| 14/12/2014 | 7
CoolCube™ for high mobility channel
Opportunities
P. Batude et al., VLSI 2009
Source: T. Irisawa et al., VLSI 2013 (AIST)
EU initiative “COMPOSE3”
Independently process high mobility materials
M. Vinet| 14/12/2014 | 8
CoolCube™ for heterogeneous co-integration
Opportunities
Highly miniaturized pixels
Gaz sensors (NEMS with CMOS)
P. Coudrain et al., IEDM 2008
Independent optimization of each level
Proximity between stacked functions (signal/noise ratio)
I.Ouerghi, paper 22.4 at this IEDM
First step to high level of integration for interconnectivity
M. Vinet| 14/12/2014 | 9
CoolCubeTM technology
Outline
CoolCube™
unique
features
Opportunities
CoolCube™
enablers
M. Vinet| 14/12/2014 | 10
CoolCube™ enablers
Low thermal
budget top layer
Bottom MOS FET
thermal stability
M. Vinet| 14/12/2014 | 11
Thermal budget management
• Active area
patterning
• Gate oxide
• Gate stack
• Dopant activation
• Epitaxy
• Spacer deposition
450
500
550
600
650
… 800
Bottom layer and interconnection stability
M. Vinet| 14/12/2014 | 12
C. Fenouillet-Beranger, ESSDERC 2014
C Fenouillet Beranger, paper 27.5 at this IEDM
• Active area
patterning
• Gate oxide
• Gate stack
• Epitaxy
450
500
550
600
650
… 800
M. Vinet| 14/12/2014 | 13
Harness the energy of the technology mainstream momentum
• Active area
patterning
• Gate oxide
EOT reduction
• Gate stack
• Epitaxy
Junction control
Thin film management
Low k
450
500
550
600
650
… 800
M. Vinet| 14/12/2014 | 14
Low thermal
budget top layer
High-quality
top film
Bottom MOS FET
thermal stability
M. Vinet| 14/12/2014 | 15
Molecular bonding for high quality films
Infrared characterization
Back side macroscopic
aspect of a 300mm wafer
L. Brunet, ECS 2014
Acoustic characterization
Front side macroscopic
aspect of a 300mm wafer
300mm blanket Si film on top of a CMOS layer
M. Vinet| 14/12/2014 | 16
Low-resistivity
3D connections
Low thermal
budget top layer
Local interconnect
Level
High-quality
top film
Bottom MOS FET
thermal stability
M. Vinet| 14/12/2014 | 17
Design tools
14CoolCube™ PDK available
Based on silicon CMOS/CMOS demonstration
M. Vinet| 14/12/2014 | 18
CoolCubeTM ecosystem
M. Vinet| 14/12/2014 | 19
INTERCONNECTIVITY
A. Kis, Nature
Nanotechnology 2012
2D functional
materials
Si-based sensors
and communication
Feasibility
Process selection
2007 - 2014
2014 - 2018
Perf. optimization
Repeatability
2018
Manufacturing
SCALING
M. Vinet| 14/12/2014 | 20
Key messages
• CoolCube TM is a powerful alternative to
2D scaling
• Path for high mobility materials co-integration
• Paves the way for heterogeneous integration
• Key technological steps are addressed in our programs
• Supporting ecosystem
From scaling
to interconnectivity and diversification
M. Vinet| 14/12/2014 | 14
Thank you for your attention!

3.MVinet Leti Workshop IEDM2014 (2)

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