SAQP - Sematech

Transcription

SAQP - Sematech

2011 International Symposium on Lithography Extensions
Sustainability of Double Patterning process
for Lithographic scaling
H. Yaegashi, K. Oyama, S.Yamauchi,
A. Hara, S. Natori
Tokyo Electron limited
Advanced patterning project
1
H.Yaegashi / 20th Oct 2011 / Miami Florida
Outline
 Lithography trend
 Applicability of Self-aligned DP
 Multiple patterning for line pattern
 Self-aligned DP for hole pattern
 Maturity of Multi-patterning
 CD error budget analysis
 Summary
2
Lithographic scaling
65nm rule
50nm rule
45nm rule
3
Paradigm shift to 1D layout design
intel 65nm node
(2005)
intel 45nm node
(2007)
intel 32nm node
(2009)
M.Bohr, intel, ISCC 2009
4
Complementary Lithography
Grid line
Cutting Litho
5
Complementary Lithography
Grid line
SADP~SAMP
Cutting Litho
Single expo : EUV
Multi-patterning : 193-i
Direct writing : EB
Other : innovative tech.
6
SADP on Resist-core scheme
Litho.
PR-Slim
SiO2 depo
SpacerEtch
HM Etch
Clean
Resist
Si-ARC
SOC
Hard mask
40nm hp
20nm hp
7
Spacer and Cutting process
1st Litho.
SADP
2nd Litho.
CD Shrink
Cutting Etch
1st Litho.
SADP
2nd Litho.
CD Shrink
Cutting Etch
8
SAQP : Pitch-Quadrupling
Litho.
PR-Slim
SiO2 depo
HM Etch
SiO2 depo
SpacerEtch
HM Etch
PR
Si-ARC
OPL
SiN
44nm hp
22nm hp
11nm hp
22nm pitch
9
CD Error Budget comparison
~ Calculation result ~
8
7
6
CD Deviation (nm)
SADP
Depo
Etch
Litho
SATP
SAQP
5
4
3
2
1
0
line
space
line
space
Single Expo. PR-core
line
space
HM-core
line
space
PR-core
line
space
HM-core
line
space
PR-core
line
space
HM-core
10
SAQP Patterning result
Litho.
PR-Slim
SiO2 depo
HM Etch
SiO2 depo
SpacerEtch
HM Etch
PR
Si-ARC
OPL
SiN
44nm hp
22nm hp
11nm hp
11
CDU Measurement result
on SAQP
5
Line CDU
Space CDU
LWR (nm)
CDU (nm)
4
3
2
1
0
PR-Slim SiO2 Depo
Spacer
Post Litho 1st Depo 1st Spacer
2nd Core
2nd Core
SiO2 Depo 2nd Spacer
2nd Depo 2nd Spacer
Process step
12
Pitch Tripling Scheme comparison
General scheme
Litho
Etch
Clean
Depo
Etch
Depo
Etch
Etch
Etch
Etch
Proposed scheme
Litho
Depo
Etch
Etch
Clean
Depo
13
CD Error Budget comparison
Calculation result vs practical CDU
8
CD Deviation (3sgm/nm)
7
S/E
SADP
SATP
SAQP
CD:40nm
CD:20nm
CD:14nm
CD:12nm
6
5
4
3
2
1
0
line
space
line
space
line
space
line
space
line
space
line
space
line
space
：Line CDU (Calculated)
：Line CDU (Actual)
：Space CDU (Calculated)
：Space CDU (Actual) 14
Hole pattern resolution
SE 193-i
Resolution
(theoretical)
80nm
Cross LLE
80nm
LELE
56nm
Cross-SADP
EKB
40nm
56nm
28nm
40nm hp
40nm hp
28nm hp
20nm hp
42nm hp
40nm hp
29nm hp
20nm hp
31nm hp
(44nm=>)
Demo.
Result
15
@ NA : 1.30
Pitch-doubling with S/E for dens hole
Litho
SiO2 Depo
Etch-back
TEOS etch
PR
16
Cutting mask formation in minimum step
1st PR (V-line)
3rd PR (Trim)
2nd PR (H-line)
LLLE
＋
＋
50nm hp (V)
40nmhp
50nm hp (H)
100nm hp (CH)
28nmhp
EKB+
17
PR-core X-SADP scheme
1st Litho.
PR-Slim
SiO2 depo.
SiO2 depo
Spacer Etch
HM Etch
SOC2 Etch
2nd Litho.
SOC1 Etch
TEOS ETch
18
X-SADP CD measurement result
①
PR core line
CDU R=3.0nm
PR core space
CDU R=3.2nm
④
Core space
CDU R=2.1nm
Gap space
CDU R=1.9nm
19
Extendable X-SADP
1st Litho
Spacer depo
Spacer etch
2nd Litho
Spacer depo
HM etch & Clean
hole
2nd Litho
Spacer depo
HM Etch
Clean
Pillar
20
Summary
 Self-aligned DP technique has wide applicability and
extendibility for
Down scaling on SATP,SAQP
Pitch splitting in both line and hole pattern
complementary lithography on 1D layout
 We introduced quite good CD controllability on
11nm hp line pattern on SAQP
20nm hp hole pattern on Cross-SADP
 Self-aligned multi-patterning with PR-core must be
Litho-friendly process
Cost conscious scheme
21
Fully coordinated by
TOKYO ELECTRON
TM
22

SAQP - Sematech

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