Unveiling the Next Generation in Substrate Technology

UNVEILING THE NEXT GENERATION IN SUBSTRATE TECHNOLOGY
Ron Huemoeller and Sukianto Rusli
Amkor Technology, Inc
Chandler, AZ, USA
Steve Chiang and Tsung Yuan Chen
Unimicron Technology Corporation
Taoyuan, Taiwan
Dave Baron, Lutz Brandt and Bernd Roelfs
Atotech GmbH
Berlin, Germany
ABSTRACT
The electronic packaging industry has been crippled by the
incremental technology advancement produced by the
substrate manufacturers over the past decade. While
semiconductors and related packaging technologies progress
at alarming rates, typically doubling in functionality every
couple of years, the substrate portion of the integrated
circuit (I.C.) packaging industry continues to fall further and
further behind. This has created a significant technology
gap, forcing the semiconductor manufacturers to
compensate their chip design by adding more redistribution
layers or even worse, additional size to the chip itself. Thus,
the I.C. industry is in dire need of a significant change at the
substrate level to remove the innovative barrier that exist
today and allow chip designers to continue their efforts in
reducing size and cost, while increasing the functionality.
A collaborative effort between Amkor Technology,
Unimicron and Atotech, has led to a significant new
breakthrough in substrate manufacturing techniques,
allowing both layer and format reduction (thus cost
reduction) versus currently available state of the art
technologies. The tremendous growth and need for a
disruptive technology in I.C. substrates, has helped to
facilitate the implementation of this new method that allows
the miniaturization of both design features and substrate
format. This innovative technology utilizes laser ablation
techniques, together with specially developed plating
processes, to form electrical paths for signal propagation
within the dielectric, as opposed to conventional
technologies that form signal paths above the dielectric.
A close look at this technology reveals benefits and
opportunity for significant gap closure to current needs in
the chip packaging industry today. The laser structured
approach offers a unique opportunity to simultaneously
improve upon traditionally incremental improvements in
design as well as optimize electrical performance at the
same time by reducing signal paths. Ultimately, this
approach addresses critical needs for the coming generations
of chip packaged substrates by not only driving
miniaturization in design, but also by improving the
electrical performance of the package as well. This paper
unveils the technology and benefits that the laser embedded
approach provides.
Key words: BGA, laser, embedded, excimer.
BACKGROUND
Substrate innovation continues to be paced by known
technologies in the substrate manufacturing industry,
limiting the ability of the manufacturers to close gaps that
currently exist between packaging technology and substrate
based technology.
Part of this is due to the reliance on
incremental approaches to roadmaps and part to limited
development budgets within the substrate industry today.
Margins at the substrate level have forced the manufacturers
to focus on business and roadmaps with visible demand,
rather than invest in future technologies that might offer
promise in better gap closure to the packaging industry.
Additionally, the incremental approach to technology has
been predicated on photolithographic techniques and
miniaturization of the through hole. Although this approach
has allowed the steady progression of geometries to just
under 20 m in signal width and 100 m in via diameter, the
primary issue of space utilization and electrical performance
still has not been fully addressed. Even with the full
adoption of laser blind vias through coreless concepts, the
basic problem remains, how to reduce the footprint of
substrate itself while maintaining or improving upon the
electrical performance.
A collaborative effort has brought forth a new method of
manufacturing substrates that allows not only the
miniaturization of signals to 10 m and below with padless
vias and reduction of layers from current design sets today,
while maintaining all electrical requirements of the package.
This paper discusses an overview of the technology, as well
as a portion of the findings and conclusions from the work
completed jointly between Atotech, Amkor and Unimicron
to date. The intent is to convey to the reader the overall
benefit of the laser embedded approach from both a cost and
a performance perspective, in addition to allowing the
reader to preview the beginning of a new era in substrate
manufacturing techniques.
THE LASER EMBEDDED APPROACH
The laser embedded technology is predicated upon the use
of a laser to create recesses within the dielectric material for
subsequent signal formation, as opposed to current
photolithographic techniques used today where the signals
are formed on the surface of the dielectric. In general, the
intent is to not only create much smaller patterned features
as a result, but to bypass the yield and cost sensitive
photolithography stages as well.
Through the work
completed to date, this has been accomplished with a
number of ablation techniques. In fact, multiple laser
choices have been tried and proven effective, including both
excimer and UV YAG systems, with each offering uniquely
different benefits.
For example, UV YAG ablation techniques offer flexibility
in that they can operate at a number of wavelengths and
integration methods. The UV YAG systems can be
operated in both vector and raster formats with power
ranging from 3 to 40 watts. The UV YAG systems also
provide ability to cluster beams to gain both efficiency in
available laser power and throughput of the working tool.
UV YAG systems also provide a broad choice of dielectric
materials by the manufacturer due to the higher ablation
wavelength (355nm typical) and higher energy density in
the spot created by the focused beam. UV YAG ablation
also allows for a maskless process, facilitating the creation
of trenches and blind microvias simultaneously. Figure 1
illustrates an example of UV YAG ablated signals paths
with 12um line/space in Ajinomoto GX-13 dielectric film.
Figure 1 - UV Ablated GX-13
Dielectric
Excimer ablation, on the other hand, allows for better
resolution and depth control, as well as higher throughput
when the pattern has larger features.
This can be of
significant consequence when considering the creation of
lands, ground planes or other larger features in the
patterning process. Figure 2 shows an example of excimer
ablated signals paths at 12 m line and space. Excimer
systems operate at typically 248nm or 308nm wavelengths,
providing a more incremental ablation approach to dielectric
removal and thus, providing high resolution and better depth
control. Excimer systems can operate in power ranges up to
300 watts, depending on configuration, and lens design.
The laser embedded format allows the formation of recessed
signals to below 10 m (4 m demonstrated) and the creation
of near padless vias to facilitate a reduction in both package
size and format. Resolution of designed in features to ±
1 m, with registration at better than 5 m, is realized with
the laser structuring approach. The registration is a direct
result of the simultaneous creation of microvias and the
completely recessed signal channels. Since the creation of
the vias and signals occur simultaneously, all patterned
features are precisely aligned, facilitating the landless
microvia structures. Thus, as a result, the laser embedded
approach enables significant layer reduction by availing
more routing space on each plane of the substrate.
Figure 2 - Excimer Ablated GX-13
Dielectric
Critical aspects of this approach also include the ability to
manage the ablation process with high panel throughput.
This, however, is greatly affected by the laser choice and
level of integration employed. In this respect, the laser
choice will have tremendous influence on the subsequent
substrate fabrication processes as well. This is especially
true when considering the performance and cost tradeoffs of
the ablation process chosen (UV YAG vs. Excimer).
Equipment cost, throughput, maintenance and consumables
are all varying factors affecting the cost equation of this
process. However, as is discussed in the following section
of this paper, the cost equation must be balanced with the
performance of the final product.
Laser machine technology is developing rapidly and
performance standards only a few years ago have been
replaced by equipment that will ablate the patterns required
in seconds rather than minutes. This improvement is the
result of not only advances in the laser sources, but also in
the software and control systems for the machines.
THE LASER STRUCTURING PROCESS
The laser structuring process is highly dependent upon laser
choice. For example, for a UV YAG system, the method of
ablation is one of direct writing and is performed real time.
In other words, a masking tool is not required and data, once
generated by the designer, can be input real time to the UV
YAG system for immediate use and ablation. This method
is preferred for small volumes and prototype applications
since it is a tool-less method and can also be performed in a
variety of dielectrics.
As previously indicated the
wavelength of the UV YAG system for these applications is
performed at 355nm and is able to ablate a multitude of
dielectric materials as a result, including both homogeneous
and composite materials (including with silica fillers). The
UV YAG systems are also able to ablate at various depths
simultaneously, with only a change in algorithms of the
software. This allows the simultaneous formation of both
signals and vias, enabling padless via formation.
without the need for lands or pads, thus enabling even UV
YAG approaches.
In Figure 4, is shown the profile of a UV YAG 12 m wide
trace ablated in ABF GX-3 dielectric, at 15 ms in depth.
The UV YAG systems employed to date have demonstrated
capability of resolutions and depth control of approximately
± 1.0µm and alignment capability at ± 2.5µm. Again, it is
important to highlight that the UV YAG systems do not
require a mask and are also more versatile in the number of
dielectric choices they can ablate. It is also important to
note that the UV YAG systems are solid state and are
considered reliable workhorse systems in the industry today.
Figure 3 - The Laser Embedded approach
demonstrated in ePTFE dielectric.
Although for UV YAG systems both the pulsed DPSS
355nm and pulsed 266nm wavelength 25 watt energy
sources are available for the laser embedded application,
only the 355nm energy sources are used in production today
in the larger substrate supply base. For this application, the
frequency, or pulsed repetition rate, generally operate from
50-250 KHz. The typical ablation efficiency is greater than
1 J/cm2 for dielectrics in use today (ABF and FR5
materials). It is important to note that the throughput is
highly dependent upon the area of ablation required as this
is a direct write application.
Typical area ablation
requirements for a single plane of a multilayer substrate,
with dense circuitry today, are roughly 6%. This equates to
a throughput of 18 panels per hour, depending on
configuration of the machine and depth of ablation. For
most of the applications tested to date, the depth
requirement is at 15 m. This, however, is going to be
dependent on desired overall copper requirements and
designed in electrical requirements.
Larger features adversely affect the direct write applications
(UV YAG) as the write time is significantly increased as a
result. The direct dependence on ablation area requirements
highlights a negative characteristic of the direct write
approach, since larger feature areas require more ablation
time to complete they also thus lower the throughput. If
large lands are required for subsequent via connections to
top side layers, the time required to crate these lands could
be prohibitive, depending on size. Therefore, careful design
consideration should be given when considering pad,
ground and other larger patterns. It is important to note that
the laser structured approach allows the creation of traces
Figure 4 - UV YAG Ablated GX-3
Dielectric
Excimer based systems on the other hand, require a mask.
The mask based system provides a unique advantage,
however. It enables mass ablation of the dielectric surface
area to create any feature size desired, across a large area,
without penalty for increased density. The precision with
which this is accomplished is much greater than the UV
YAG based systems, and is typically achieved at resolutions
of greater than ± 1.0µm with capability of high precision
alignment at ± 2.5 m. In addition, precise depth control at
less than 1µm is achieved in conjunction with seamless,
large-area patterning. In Figure 5 below, 12 m lines and
spaces have been ablated in an Aramid non woven fiber.
Figure 5 - Example of Excimer Ablation of
Aramid Dielectric
Excimer based systems on the other hand, require a mask.
The mask based system provides a unique advantage,
however. It enables mass ablation of the dielectric surface
area to create any feature size desired, across a large area,
without penalty for increased density. The precision with
which this is accomplished is much greater than the UV
YAG based systems, and is typically achieved at resolutions
of greater than ± 1.0µm with capability of high precision
alignment at ± 2.5 m. In addition, precise depth control at
less than 1µm is achieved in conjunction with seamless,
large-area patterning. In Figure 5 above, 12 m lines and
spaces have been ablated in an Aramid non woven fiber.
In Figure 6, the patterns were created with a 248nm excimer
system, at 15 m in depth, and subsequently copper plated to
fill both the traces and pads shown above. These features
include 12 m line and space, 60 m vias and 110 m flip
chip attach pads. Since the excimer system is a mass
ablation system based on mask technology, a multitude of
pattern sizes and shapes can be created at the same time.
This is exemplified, in Figure 6, where very large concentric
rings have been formed to create BGA lands (420 m).
Figure 6 - Example of 248nm Excimer Ablated
ePTFE Dielectric, followed by Copper Plating
ablate numerous materials while still maintain the same
resolution, precision and accuracy, the material of choice is
preferably a homogenous material (or one with limited silica
fillers) to maximize ablation speeds.
Figure 7 - 248nm Excimer Ablated Kapton
Below in Figure 8, is shown both Aramid and expanded
Teflon dielectrics with again, 12 m traces and spaces
demonstrated. Ultimately, the choice in ablation techniques
amounts to a series of tradeoffs. The Excimer system is
more costly upon initial purchase and requires more expense
in maintenance than the UV YAG system, but produces a
higher resolution product with much better depth control
and registration feature capability. Thus, if the need to go to
sub 10 m traces is present, the excimer should be the
system of choice. If the desire is to stay within a UV YAG
format, alternate variants of the laser structuring process
will be required to facilitate this. It is important to note,
these variants have been tested and proven effective in a UV
format but still remain in early development stages, and thus
cannot be disclosed completely.
With the ability of the excimer system to ablate large lands
and traces simultaneously, the throughput is also enhanced
as compared to the UV YAG systems. This is important
for products requiring large lands or ground planes on the
same plane as the trace signals. The ability to ablate both at
the same time without a throughput penalty is critical, as
large features require significant time to create in a direct
write system, making the UV YAG system all but
impractical in some cases. It is important to note that the
line resolution and depth is not compromised when ablating
large features adjacent to the signals, as shown in Figure 6
with the excimer systems.
Figure 8 - Examples of 248nm excimer ablated Aramid
& ePTFE dielectrics, with 12µm lines and padless vias.
This is again, demonstrated in Figure 7, with 12 m traces
connecting to 250 m lands in a Kapton dielectric, further
demonstrating the precise ability of the excimer system to
simultaneously control depth, registration and feature size
simultaneously. Depending upon integration techniques of
the lens systems, laser power and extreme know-how, the
panel throughput for an excimer system can be 15 panels or
more per hour, again depending on the depth of ablation and
dielectric choice. Although the excimer system is able to
SUPPLIER INFRASTRUCTURE
One of the benefits of the laser structuring approach is that it
would leverage existing infrastructure in the form of
equipment, materials, processing and engineering. The
infrastructure to manufacture substrates employing a laser
embedded approach exists in the supplier’s facilities today
already, with the exception of the laser structuring
equipment. All of the other processes follow standard
process flows, minus the photolithographic steps required to
create the patterned signals. As such, the addition of a laserstructuring device enables the laser embedded approach,
with minimal impact to the supplier. However, there is
great know-how in the ability to both structure dielectric
with a laser and subsequently metallize and fill the features.
The importance of all parts of the process sequence should
not be underestimated.
DIELECTRIC PREPARATION (DESMEAR)
After the bare dielectric panel has been ablated with the
relevant trenches, pads and blind microvias, the next step is
to metallize the entire surface of the dielectric material. This
is achieved in two process sequences already well known in
the industry, namely “Desmear” and “Metallization” using
electroless copper.
The “Desmear” process is applied in order to remove
ablation debris, provide uniform surface roughening and
therefore ensure maximum adhesion of the subsequently
applied electroless copper layer. The “Desmear” process
consists of three steps; resin softening with a high boiling
“sweller” solvent, followed by an alkaline permanganate
resin etch and a final step that removes residual
permanganate and MnO2 from the dielectric surface. The
chemical contribution to adhesion in this type of wet
processing is thought to be relatively minor; therefore,
uniform surface roughening is critical for mechanical
anchoring of the electroless copper to the bare laminate.
Without some level of surface roughness, sufficient
adhesion is not possible.
Average roughness (Ra) in typical Flip Chip substrate SAP
applications has been in the order of 0.4 to 1.0 microns with
maximum roughness Rt of 3-10 microns! Roughness is not
only dictated by how aggressive the desmear chemistry is,
but also by the filler particle size. Popular SAP BU
dielectrics such as Ajinomoto ABF resins are highly filled
with spherical silica particles to provide dimensional
stability and improved CTE performance. Fillers are in the
order of 5 microns for resins such as ABF SH9K, and still
have sizes as large as 5 microns for newer resins such as
ABF GX3 and GX13. From this perspective fillers not only
dictate the surface roughness on desmeared dielectric, but
also determine the smallest possible feature size in the case
of the embedded conductor technology.
Figure 10 - GX3 after Laser Ablation and Desmear
Currently conductors formed by standard SAP BU
processes on the surface of flip chip substrate dielectrics are
in the order of 20 microns. The surface roughness quoted
above, while not desired, is accepted currently. However in
order to address 10-micron and smaller features and at the
same smoother conductors, for reasons of signal integrity,
maximum roughness Rt and the corresponding filler
particles will have to reduce to < 1 micron. This particle size
reduction will be required irrespective of the type of
production process utilized.
Figure 9 -GX3 after Laser Ablation
Adhesion of the subsequent copper layer is of the utmost
importance in the traditionally used Semi-Additive Build
Up Process (SAP BU), because only one side of the
conductor is attached to the dielectric during the
construction of the substrate. Although important for the
laser embedded process sequence, the absolute adhesion
value can be less because of increased surface area (three
sides are attached to the dielectric). Tests have proven that
the minimum required adhesion, as measured by surface
peel strength, is probably in the order of 3-5 N/cm. For
comparison the minimum peel strength requirement for
current Flip Chip substrates is currently 6-8 N/cm.
Figure 11 - Sumitomo after Laser Ablation and
desmear.
Many different types of material have been tested for
suitability for laser and chemical processing. Key points for
desmear conditions have been surface roughness, adhesion
and trench definition. Materials from two well-known
dielectric material suppliers show the most suitable
performance. Laser ablation results, with subsequent
desmear and copper deposition (for cross-section
preparation) can be seen in Figures 9–13. While the results
from these materials are acceptable, specially developed
materials would enhance the performance of embedded
conductors significantly.
method for Flip Chip substrate production, where ionic
activation is thought to provide a larger operating window
and therefore higher process safety compared to Pd/Sn
based activation systems, with respect to electrical shorts
and subsequent Ni/Au plating. Below, in Figure 14, a
generalized desmear/metallization process is shown.
Process Step
Sweller
Permanganate Etch
Neutralizer
Cleaner
Soft-etch
Pre Dip
Ionic Activator
Reducer
Electroless copper
Baking
Time
3 min
6 min
4 min
4 min
1 min
1 min
4 min
3 min
20 min
60 min
A
65-80 °C
75-80 °C
50 C°
60 C°
RT
RT
40 °C
30 °C
34 °C
120 °C
Figure 14 - Desmear/Metallization Process Steps
Figure 12 - GX3 Ablated features filled with
Copper for cross-section reinforcement
Another major issue with bare laminate desmearing is the
degree and consistency of resin curing and hardness, which
is a consequence of customer specific lamination conditions.
Roughness and adhesion can therefore vary significantly
from lot to lot or even on a single panel. Constructing panels
using materials with significantly different chemical
behaviour is also problematic, resulting in compromises on
the uniformity of the surface roughness.
Figure 13 - Sumitomo ablated features filled
with Copper for cross-section reinforcement
METALLIZATION PROCESSES
The main points for consideration in the metallization part
of the process are ionic activation and an electroless copper
with low internal stress (fewer tendencies for blistering).
Ionic activation consists of Pd2+ ion seeding of the
desmeared surface, followed by a reduction step. This
results in finely divided Pd being adsorbed on the dielectric,
which in turn catalyzes the deposition of copper from the
electroless copper solution. This is also the standard
During the development of the laser embedded conductor
process, chemistry utilized in the traditional SAP-BU
process was used for early work. However, superior results
have been obtained using Via2 chemistry, specially
developed for use with laser ablated features.
ELECTROLYTIC COPPER FILLING PROCESSES
Vertical Methodology
At a first glance the requirements for the electrolytic copperplating step seemed to be similar to those of the traditional
HDI and IC Substrate technology. It involves the filling of
blind microvias (BMV) and trenches, with the exception
that the plating is done using panel plate methodology
instead of pattern plate mode. The dimensions of BMV’s
and trenches are in the same order of magnitude. Standard
technology for substrate plating is typically traditional
vertical copper plating technology using specially adapted
electrolytes, which have a strong levelling effect. Typical
current densities are 0.8-1.5 ASD DC with plating times of
60-90 min. This is shown in Figure 15.
Although the small BMV like structure are sufficiently
filled with copper using the standard HDI approach for laser
ablated structures, two fundamental issues were revealed:
the surface distribution of such a plated panel is
significantly worse than ± 10 % and larger pad like
structures were not evenly filled with copper. Since the next
process step involves removal of any excess copper on the
surface to facilitate the isolation of the conductor pattern,
plating thick Cu layers (> 30 µm Cu) onto the panel, to
ensure minimum dimple in large features (pads), was
counter productive. These two points have made it
necessary to invent and apply a new plating technology.
The approach adopted in this case was the use of horizontal
conveyorized inert anode plating equipment with
‘SuperFilling’ technology.
time and increases the amount of copper to be removed in
the next step. In both cases costs and the risk of yield loss
increase.
Figure 15 – Typical results from vertical DC - BMV
plated with standard technology: 100x75µm with
~25µm Cu plated at 1.0 ASD with a dimple of ~10µm.
Horizontal Methodology
Horizontal conveyorized plating systems are not new, but
the use of inert anodes with specifically developed additives
and aggressive pulse/periodic reverse conditions is new. As
with all conveyorised systems horizontal plating has an
inherent advantage over traditional hoist type vertical
plating lines - every panel passes exactly the same anode
sequence, thus has exactly the same surface distribution.
Moreover, the latest technology is equipped with
sophisticated pulse technology, foil transportation system,
electrolyte flow control and 112 individually controlled
anodes to optimize surface distribution. The individual
anodes are not only placed in a series but also parallel so
that the copper deposition can also be individually
controlled over 4 segments for one panel. This generates an
unrivaled surface distribution of <±10% min/max of Cu on
a panel within a minimum edge frame. Figure 16 shows the
inert anode segments.
Figure 17 – 90µm x 60µm BMV filled with
SuperFilling technology. Only 12µm Cu is plated
in 22 minutes horizontally (2 Cu layers visible).
A process that deposits the minimum amount of Copper on
the surface and the maximum in the recesses is what is
required for embedded conductor production. SuperFilling
technology improves the Cu distribution ratio significantly.
It is predicated on the combination of both plating and
etching in one step. The horizontal inert anode plating
technology coupled with SuperFilling technology, can
simultaneously plate inside a hole (or trench) while etching
the copper from the surface in one electrolyte! An example
of a filled BMV is given in Figure 17 above, while in Figure
18 below, an example of a partially plated blind via pad
1.
Segment
2.
Segment
3.
Segment
4.
Segment
Figure 16 - Segmented anodes over the width of a
panel. Panel transport direction is indicated by
the arrow. Panels are contacted on the left side.
The anode sequence described above can also equalize
potential drops over the panel, which may occur if a very
thin and thus high resistance copper starting layer is present.
As was stated earlier BMV and trench filling can be
achieved with a lot of available electrolytes, but not without
the need to plate significant amounts of copper on the
surface, to ensure dimple free results, which takes a lot of
Figure 18 – 120 x 40µm BMV - SuperFilling
technology. Intermediate step only 4-5µm Cu
is plated on the surface for 28µm in the BMV.
In comparison with most of the traditional BMV filling
processes, SuperFilling technology reduces the amount of
surface Cu by about 40%. Although the SuperFilling
technology is better suited to structures without through
holes, development is currently underway to widen the
operating window to include the through holes as well.
UNIQUE ATTRIBUTES OF APPROACH
The laser embedded approach not only addresses the need to
reduce the overall layer count to improve upon both cost
and yield concerns, but also addresses the need to improve
upon the electrical performance by use of improved routing
techniques and reduced signal length. Part of the ability to
reduce the number of layers comes directly from the ability
to create 10µm signal traces in conjunction with padless
microvias.
Due to the ability to ablate the vias and the
signal traces simultaneously, the need for registration
tolerances has been removed with respect to the formation
of each feature, or at the minimum, significantly reduced.
With the excimer system registration accuracy of the laser
systems is well within 5µm of fiducials and exact on a
feature-to-feature basis.
Figure 19 - Landless (near landless) Vias
after ablation.
Figure 20 – Ablated pattern in Figure 19, after
copper plating.
Thus, the laser structuring approach allows for precisely
aligned trace signals to ground signals by means of adjacent
proximity, thus providing extremely accurate impedance
control and matching. This is significant as it allows for
less stringent requirements on the dielectric material choice
with respect to loss (Dk~0.01) for high-speed applications.
As the speed increases signal integrity is increasingly
affected by interconnect between semiconductor die and
board. When a signal exits the die it has to travel through
the wirebond or flip chip attach, the interposer routing and
out through the solder ball connecting the package to board.
The signal flight time through the package substrate and out
into the board, is of the order of rise time for modern bus
speeds, i.e. about 100ps, or less. This creates a timing delay
and the substrate is therefore potentially the source of
significant crosstalk, skew and impedance mismatches. The
addition of ground layers between signal layers to improve
electrical performance for long transmission delay lines is
adding costs back into FC packaging and reversing the
conventional direction of this sector.
Earlier it was suggested that the laser embedded approach
allows for a coplanar approach to electrical management.
As a result of this innovative approach to managing the
electrical requirements on a planar basis as opposed to a
coplanar basis, the signal-ground trace coupling has enabled
ground plane reduction to be achieved, allowing further
reduction in layer count of the overall substrate. With the
laser structuring approach, reductions in designs from 2
buildup layers per side over a core have been reduced to
only 1 buildup layer per side instead. Further, current high
running production designs today with both 3 and 4 buildup
layers per side over core have also been redesigned into
only 2 buildup layers per side over core. This path is
diametrically opposed to the current trend of layer addition
that we currently witness today, in an effort to address
electrical concerns. However, with the laser embedded
approach, layer reduction is now a reality. In each case, the
designs have electrically modeled, ensuring all electrical
requirements are maintained.
Since this technology ultimately provides for embedded
circuitry within the signal layers (see Figure 20), subsequent
dielectrics when attached, demonstrate tremendous surface
planarity allowing improved yield performance at both flip
chip attach and underfill processes of assembly. The ability
to use reinforced dielectrics during this process also
provides for improved rigidity, again improving assembly
processing. This also allows for the thickness reduction in
both the core and the overall package.
An additional benefit of the laser embedded approach is the
improvement of adhesion of the circuits to the dielectric.
With standard techniques used today, the copper binds on
only one side to the dielectric, creating processing problems
and resultant opens or trace cracking under stress. With the
laser embedded approach, the copper binds to the dielectric
on three sides, thus removing opportunity for separation of
the circuit from the dielectric material as a result. This is
demonstrated in Figure 21, on the following page.
It is also important to note that in high speed applications,
the length of interconnect from the die pad to the I/O can be
more important than the dielectric itself. With the reduction
in the number of layers and shortened signal paths by means
of the laser embedded techniques, electrical performance is
no longer compromised. Additionally, the surface profile of
the copper trace also has an affect on the signal integrity at
higher speeds as well. At higher speeds the signal travels
more along the surface of the trace rather than in the bulk
metal itself. With adhesion of the copper trace to the
surface dielectric being of concern in standard processing
today to assure a high yield process and a reliable product
under stress, a degree of copper surface roughness is
required, typically at or near 2 m. The laser embedded
approach addresses the adhesion to dielectric without having
to roughen the copper by binding on three sides, as
previously discussed. The issue of adhesion and copper
roughness becomes exacerbated in standard SAP as trace
signals continue to reduce to below 15 m. This issue is
easily overcome with the laser embedded approach.
15u
8u
15u
8u
Not Capable
Limited
Figure 21 – Cu Adhesion to dielectric (laser
embedded vs. traditional processing)
Future - maybe
Capable
Figure 23 – Current SAP Design Rules
ULTIMATE IN DENISTY
As the laser embedded approach allows for much smaller
trace signals due to resolution and manufacturing techniques
(see Figure 22), it provides ability to route many more
channels on a given plane. This is significantly enhanced by
the ability to create landless vias for blind via applications
through V-OUT (via – over/under trace) concepts. This
ultimately enables the layer reduction needed for improved
electrical performance and cost reduction. In Figures 23
and 24 is shown the design density enabled by virtue of the
laser structuring approach. It is clear that by reducing the
signal width, more signals can be routed between pads.
However, it is probably more important to note the density
is significantly improved by reducing the pad sizes of the
through holes and blind vias. Note in Figure 24 that the
density is doubled by reducing the blind via pads to near
padless structures.
Limited
Figure 24 – Laser Design Rules
Figure 22 - Excimer Ablation of Aramid
Capable
COMPETIVE SOLUTIONS?
Embossing and very advanced photolithographic techniques
have been tried, or are being contemplated, that attempt to
create miniaturized features as well. Embossing requires the
use of a tool plate and ability to release this tool from
specialized materials to form recessed features. The
embossing technique forms a pattern into the surface of the
dielectric by use of a hot press, simultaneously curing the
dielectric. Tool cost, lead times and the need to inventory a
large number of tools for each design can make this
approach prohibitive. In addition, challenges of tool release
from the dielectric as well as dielectric limitations due to
embossing affinity, have limited this application.
Extremely advanced photolithographic techniques are
littered across every substrate suppliers’ roadmap today.
Fabricating smaller features in substrates is driving most
I.C. substrate suppliers to expensive equipment and
materials in an attempt to create sub 15 m circuits.
Steppers, expensive glass tooling, specialized resists and
handling are all required to allow the formation of these
circuits. As the circuits go to 12 m, the challenge becomes
even greater with severe yield implications. Additionally,
this still does not address the registration issues involved
with aligning the vias to preformed circuitry.
Transfer solutions provide an additional approach to
embedding circuits, using standard photolithographic
techniques on advanced resists that have been applied to
various carriers. Once the resist has been patterned through
the standard (or advanced) photolithographic processing, the
patterns are subsequently plated. This image is then
laminated (pressed) into the dielectric to embed the circuit.
This technology has attributes, but also has drawbacks as
well. Primarily, it has registration limitations within the
transfer process. While registration tolerance to 40µm is
achievable, tolerance to sub 20µm still requires significant
development. To generate features less than 15µm will
also require very advanced photolithographic techniques
and materials.
Each of the above techniques has severe limitations in the
ability to provide a volume manufacturing solution that
addresses total cost, flexibility and registration requirements.
Each provides some merit, but none provide the full
package of benefits that has been discussed with the laser
embedded approach.
CONCLUSION
Flip chip (FC) substrate technology involves the most
advanced set of materials and design rules used in the
industry today for substrates. Increasing IC functionality
continues to drive the addition of layers and, subsequently,
cost. Material costs can be as high as 60-80% of the total
FC package cost. Layer counts as high as 16 layers are
found today for advanced application specific integrated
circuits (ASICs). In fact, the addition of layers is continuing
to purvey in the industry as the ultimate desire by end users
is to provide a device with improved electrical performance.
As the end users strive for better electrical integrity, they
continue to pressure the substrate manufacturers to improve
electrical performance of the substrate as well. The general
desire is for the elimination or the core layer(s) and redesign
into what the industry has termed ‘coreless’ structures. To
do this however, requires very advanced and costly
manufacturing techniques at the substrate supplier and also
causes great concern at assembly due to lack of rigidity of
the substrate, resulting in assembly defects.
Looking to the future, the key issues for substrates and the
substrate suppliers for next generation devices will be signal
integrity and latency, which will need to be optimized
through minimized matched pair routing distances from die
to motherboard, surface planarity, cost and reliability [1].
The laser embedded technology addresses all of these
nicely. Reduced signal path lengths by virtue of feature size
reduction, improved planarity by virtue of recessed features
and cost reduction by virtue of layer reduction, will
ultimately enable these new devices. This is good news for
an industry seeking innovation.
SPECIAL ACKNOWLEDGEMENTS
The authors would like to acknowledge the significant
contributions of Anvik Corporation. Specifically, we would
like to acknowledge the following individuals whose tireless
work over the past few years has proven invaluable in
enabling this technology:
• Kanti Jain (President) and Krishna Kuchibhotla
(Director of Engineering)
Additionally, we would like to thank the following
individuals at Amkor for their efforts and exceptional
guidance in the electrical design of each test vehicle:
• Nozad Karim, Mike Devita and Harry McCaleb
Finally, we would like to acknowledge the Executive
Management of each company involved in this collaborative
effort for their continuous support:
Amkor Technology:
• Oleg Khaykin (CEO), Mike Barrow (Sr. VP, FC) and
Robert Darveaux (Sr. VP, Adv. Products).
Atotech:
• Reinhard Schneider (President) and Uwe Hauf, (VP
Electronics).
Unimicron Corporation:
• David Cheng (President) & T.J. Tseng (Chairman)
REFERENCES
[1] BPA Consulting (2006), “Worldwide High-Speed
Electronics Technology and Market Trends for the
Years 2006-2016,” Executive Market and Technology
Forum, pp. 59, 64-65, Sept. 2006.