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SPADIC-Susibo communication CBMnet
SPADIC-Susibo communication using CBMnet Michael Krieger SuS Meeting, 26.02.2013 Michael Krieger SPADIC-Susibo communication using CBMnet 1 Introduction SPADIC-Susibo communication so far Limitations: SPADIC unreliable (connection breaks down at high data rates) register file cannot read data from group B cannot read register values channel group A “CBMnet” epoch channels need DLMs (CBMnet feature) Susibo needs to “speak CBMnet” channel group B Michael Krieger SPADIC-Susibo communication using CBMnet 2 Introduction “CBMnet” in more detail SPADIC CBMnet SERDES clk, reset start/stop, sync, trigger RF 4 16 4× LVDS DLM data ctrl 16+2 16+2 group A group B 16 data 16+2 data 16 “ports” Michael Krieger “links” SPADIC-Susibo communication using CBMnet 3 Introduction CBMnet routing Susibo connector HDMI connector Michael Krieger SPADIC-Susibo communication using CBMnet 4 CBMnet Susibo implementation Susibo point of view SERDES clk root Susibo CBMnet clk, reset DLM data 16+2 ctrl 4 16 16+2 16+2 data 16 data CBMnet block provided (should be generic enough) SERDES block: SP605 implementation provided—not generic enough → need to adapt for Susibo 16 Michael Krieger SPADIC-Susibo communication using CBMnet 5 CBMnet Susibo implementation Signal delays SERDES SERDES ensure correct clock/data alignment ? clk root on both sides automatically (independent of PCB routing, cable length, bitfile, ...) ? ? Virtex 5 provides ? IDELAY (variable) ODELAY (fixed) SPADIC Susibo DCM (variable) 250 MHz bit clk, DDR → 2 ns/bit Michael Krieger SPADIC-Susibo communication using CBMnet 6 CBMnet Susibo implementation SERDES building blocks receiver module: control input control input 20 IBUFDS IDDR IDELAY 20 16+2 barrel shifter deserialiser 8b/10b decoder word clk bit clk Michael Krieger SPADIC-Susibo communication using CBMnet 7 CBMnet Susibo implementation SERDES building blocks transmitter module: serialiser override encoder override 20 OBUFDS ODDR serialiser 16+2 8b/10b encoder word clk bit clk bit clk Michael Krieger SPADIC-Susibo communication using CBMnet 8 CBMnet Susibo implementation SERDES building blocks clock root: phase shift control 200 MHz clk source IBUFGDS OBUFDS to FPGA logic LVDS DCM_ADV DCM_ADV currently: 200 MHz bit clock, 20 MHz word clock Michael Krieger SPADIC-Susibo communication using CBMnet 9 CBMnet Susibo implementation clock phase shift adjustment send pattern to SPADIC is the pattern received? can we receive the answer? Susibo SPADIC phase shift control clk root clk root serialiser override RX send pattern TX delay, barrel shifter control TX A pattern detected? TX B RX A yes/no/? RX B Michael Krieger SPADIC-Susibo communication using CBMnet 10 CBMnet Susibo implementation clock phase shift adjustment target scan yes no ? scan for yes/no border go to center how to stay inside (slope)? Michael Krieger SPADIC-Susibo communication using CBMnet 11 CBMnet Susibo implementation side note: LVDS signal quality almost 50% 10% flaw in SPADIC LVDS output buffer measurement artefact Michael Krieger SPADIC-Susibo communication using CBMnet 12 CBMnet Susibo implementation clock phase shift adjustment store value store value IDELAY wraps around! relatively simple and fail-safe algorithm: go right/down until outside “yes”/“no” independent of slope (no need to even know the slope) DCM phase shift range only scanned once (does not wrap around → rewind logic saved) scan completely → end position known Michael Krieger SPADIC-Susibo communication using CBMnet 13 CBMnet Susibo implementation input delay adjustment send pattern to SPADIC the pattern should now be received can we receive the answer? SPADIC Susibo clk root clk root serialiser override RX send pattern TX delay, barrel shifter control TX A pattern detected! RX A yes/? delay, barrel shifter control TX B pattern detected! Michael Krieger RX B yes/? SPADIC-Susibo communication using CBMnet 14 CBMnet Susibo implementation SERDES handshake SPADIC Susibo clk root clk root encoder override RX TX A TX B ready0, ready1 TX ready0, ready1 ready0, ready1 RX A ready0/ready1? RX B ready0/ready1? send ready0 → SPADIC stops sending “yes”/“no” wait for incoming ready0 characters send ready1, wait for ready1 → finish Michael Krieger SPADIC-Susibo communication using CBMnet 15 CBMnet Susibo implementation CBMnet initialization CBMnet SPADIC Susibo SERDES SERDES ACK? CBMnet “ready” after SERDES is ready (LED), CBMnet can use it again handshake SPADIC-side handshake FSM often stuck in infinite loop: waiting for “ACK” Susibo FSM assumed “ACK” was sent, but it wasn’t handshake specification? cannot decide if wrong concept or wrong implementation → hack: send some more “ACK”s. . . Michael Krieger SPADIC-Susibo communication using CBMnet 16 CBMnet Susibo implementation Status CBMnet SPADIC Susibo SERDES SERDES CBMnet SPADIC signals “CBMnet ready” most of the time (LED) first experiment: write register file works almost always (why not always?) correct control characters are sent (at least they enter the 8b/10b encoder), but register is not written ACK01, ACK03 are returned, ACK00, ACK02 not Michael Krieger SPADIC-Susibo communication using CBMnet 17
