docAn 81Gb/s, 1.2V TIALA An 81Gb/s, 1.2V TIALA
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An 81Gb/s, 1.2V TIALA An 81Gb/s, 1.2V TIALA
An 81Gb/s, 1.2V TIALATIALA-Retimer in St d d 65nm Standard 65 CMOS Technology T h l Shahriar Shahramian1 Anthony Chan Carusone1 Peter Schvan2 Sorin P. Voinigescu1 1 Universityy of Toronto,, 2 Nortel Networks University of Toronto 1 Motivation Emerging nanoscale CMOS with fT and fMAX beyond 200GHz Low voltage operation and high levels of integration Wireline, serial 110Gb/s applications in a single chip solution High g speed p retimers Wireline transceivers, equalizers, ADCs and CML memory Static frequency dividers up to 100GHz in 65nm SOI CMOS Retimer speeds lag behind SiGe and InP technologies University of Toronto 2 Goal and Design Methodology Demonstrate a record speed TIALA-retimer in a standard 65nm GPLP process Low-voltage nanoscale CMOS topologies Optimally y sizing g and biasing g devices Optimized circuit cell layout University of Toronto 3 TIALA--Retimer Block Diagram TIALA University of Toronto 4 TIALA FrontFront-end University of Toronto 5 TIALA Schematics CMOS TIA 4‐stage pseudo differential LA g p Low-noise, broadband front-end C bi ti off SVT & HVT d Combination devices i TIA: 7dB gain and 3dB BW of 80GHz TIALA: > 20dB of gain and 45GHz BW Overcome latch metastability University of Toronto 6 Single--ended to Differential Conversion Single University of Toronto 7 Differential Buffers Schematics Single-ended to differential conversion O Operates t in i full f ll switching it hi mode d Series-shunt peaking between stages University of Toronto 8 Clock Distribution University of Toronto 9 Clock Distribution Schematics 1.2V 26x1.6µm SVT 150Ω 450pH Clkin 55fF 4mA 1.2V 0.8V 1.2V 2kΩ 150fF 150pH 55pH 55pH 25pH OutA OutB 450pH 150Ω 26x0.8µm SVT 85pH IB 26x0.8µm HVT 26x0.8µm HVT 125pH IT = 8mA XFMR Input CMOS TIA IT = 8mA Tuned amplifier chain Transformer for differential conversion CMOS TIA used in the 81GHz clock path Tuned differential amplifier chain > 6dB differential gain from 50G-85GHz University of Toronto 10 Flip--Flop (Retiming Block) Flip University of Toronto 11 Flip--Flop Schematics Flip Combination of HVT & LVT devices No current sources are used Operation from a 1.2V supply Layout is critical for 81Gb/s operation University of Toronto 12 400mV In n 50Ω 400mV V TIALA--Retimer Signal Flow TIALA University of Toronto 13 Layout Considerations Layout optimized by interdigitating and merging transistors with common sources or drains in a single well Latch example: OutB ClkA 0.8µ µ InB B 1.6µ InA OutA ClkB University of Toronto 14 Chip Micrograph DC and Biasing DC and Biasing Clock distributiion TIALA Differential pairs iff i l i Outpu ut Input Flip‐flop Output Driver Clock Standard 65nm GPLP CMOS process Measure fT and fMAX of an 80x1um x 60nm n-MOSFET is 170GHz and 250GHz respectively measured at VDS = 0.6V Chip p area is 0.56mm x 1.2mm including gp pads University of Toronto 15 S-Parameter Measurement Results ‐5 S‐Param meters (dB B) ‐10 10 ‐15 15 ‐20 ‐25 TIA Measured SP Return Loss TIA Simulated SP Return Loss DRV Measured SP Return Loss DRV Simulated SP Return Loss ‐30 ‐35 0 20 40 60 Frequency (GHz) Frequency (GHz) University of Toronto 80 100 16 S-Parameter Measurement Results 0 S‐Param meters (dB B) ‐5 5 ‐10 ‐15 ‐20 ‐25 CLK Measured SP Return Loss CLK Simulated SP Return Loss ‐30 ‐35 0 20 40 60 Frequency (GHz) Frequency (GHz) University of Toronto 80 100 17 Transient Test Setup Block Diagram University of Toronto 18 Transient Test Setup Photograph 81Gb/s TIALA‐Retimer Channel (24 i h 50G C bl ) (24‐inch 50G Cable) 81Gb/s (2 81Gb/s (27 – 1) PRBS 1) PRBS Transmitter University of Toronto 19 Outp put Input Measurement Results: 75Gb/s τJRMS ≈ 2.5ps 2.5ps ≈5mV τJRMS ≈ 380fs ≈315mV Input eye amplitude is 40mVpp, single single-ended ended University of Toronto 20 Pattern Verification: 75Gb/s University of Toronto 21 Outp put Input Measurement Results: 78Gb/s τJRMS ≈ 1.0ps p ≈12mV τJRMS ≈ 370fs Input eye amplitude is 60mVpp, single single-ended ended University of Toronto 22 Outp put Input Measurement Results: 81Gb/s τJRMS ≈ 1.1ps 1.1ps ≈15mV τJRMS ≈ 380fs ≈320mV Input eye amplitude is 80mVpp, single single-ended ended University of Toronto 23 Pattern Verification: 81Gb/s University of Toronto 24 Table of Comparison Ref Ref. Technology Rate (Gb/s) Supply (V) PLATCH (mW) PTotal (mW) [[2]] InP HEMT fT = 245GHz 80 -5.7 N/A 1200 [3] SiGe BiCMOS fT = 150GHz 48 2.5 23 288 [4] 90nm CMOS Process fT = 120GHz 40 1.2 10.8 130 This 65nm GPLP CMOS Process Work fT = 170GHz 81 1.2 9.6 200 University of Toronto 25 Conclusions Fastest TIALA-retimer in any technology, operating at 81Gb/s Latch power consumption is 9 9.6mW 6mW TIA FoM is 118.5µW/Gb/s in differential operation Combination of LVT, SVT and HVT CMOS from 1.2V supply Low voltage CMOS nanoscale topologies Optimized transistor layouts and compact latch layout Combining low-noise, broadband CMOS TIA and high gain LA Optimized transistor sizing and biasing Series-shunt p peaking g techniques q University of Toronto 26 Acknowledgments We wish to acknowledge Nortel for funding and chip fabrication University of Toronto 27 Backup ac up S Slides des University of Toronto 28 Simulated Clock Tree (Single(Single-ended) 10 Simulated d AC Gain (dB) 5 0 ‐5 ‐10 ‐15 ‐20 XFMR AC Gain Clock Tree AC Gain ‐25 35 45 55 65 75 Frequency (GHz) Frequency (GHz) University of Toronto 85 95 29 Simulated TIALA AC Response 25 Simulated d AC Gain (dB) 20 15 10 5 TIA AC Gain LA1 AC Gain LA2 AC Gain LA3 AC Gain LA4 AC Gain 0 ‐5 ‐10 0 20 40 60 Frequency (GHz) Frequency (GHz) University of Toronto 80 100 30 Outp put Input Measurement Results: 81Gb/s τJRMS ≈ 750fs 750fs τJRMS ≈ 350fs Input eye amplitude is ~ 300mVpp, single single-ended ended University of Toronto 31
