AC`97 Audio Codec: ALC200/ALC200P

AC'97 Audio Codec: ALC200/ALC200P
Avance ALC200/ALC200P
AC’97 Audio CODEC
Revision 1.21
April 19, 2000
AC'97 Audio Codec: ALC200/ALC200P
1. Features :
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Single chip audio CODEC with high S/N
ratio(>90dB)
18-bit ADC and DAC resolution
Compliant with AC’ 97 2.1 specification
18-bit stereo full-duplex CODEC with
independent and variable sampling rate
4 analog line-level stereo inputs with 5bit volume control: LINE_IN,CD,VIDEO
& AUX
2 analog line-level mono inputs:
PC_BEEP & PHONE_IN
Mono output with 5-bit volume control
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Stereo output with 5-bit volume control
2 MIC inputs : Software selectable
Power management
3D Stereo Enhancement
True Line-Level output
Multiple CODEC extension
External Amplifier power down
capability
Dual power support : Digital :5V/3.3V
Analog : 5V
Standard 48-Pin LQFP Package
ALC200/ALC200P Overview
The ALC200 codec family is designed based
on all requirements of the Audio Codec '97
Specification, Revision 2.1. The digital
section includes the AC-Link registers,
power management, Sync detection and
AC-Link serial interface logic. The analog
section includes analog input MUX, stereo
output mixer, analog volume controls. With
independent variable sampling rate, the
ALC200 family of codecs is an analog front
end for high performance PC audio or DSP
application. It has low power consumption
and flexible power-down modes. The
ALC200 codec family requires minimal
external component cost, provides greater
design flexibility and pairs with DC'97 digital
controller(ALC200P) as well as custom logic
acceleration or host baseline audio(ALC200)
solution such as Intel810/820 chipset.
Note: ALC200 supports host/baseline
audio and will bundle with host WDM
driver and application utilities, whereas
ALC200P is specifically for card or audio
on board design and will not have any
driver utilities.
Power Management
16 bit
A/D
Convert.
Sync
Input
Mux
Volume
& Mute
Control
CD_L/R
Line_L/R
Aux_L/R
Video_L/R
Mic1
Mic2
Phone
PC-Beep
SDATA_
Out
SDATA_
AC-Link
Interface
AC'97
Registers
Mono
Volume
Mono_Out
In
16 bit
D/A
Convert
Bit_Clk
Output
Mixer
Reset#
Volume
& Mute
Control
EAPD
Line_OutL/R
LNLVL_L/R
XTL_In
OSC.
3D Stereo Enhancement
True Line
Level
IDO#
XTL
ID1#
Block Diagram
AC'97 Audio Codec: ALC200/ALC200P
of ALC200/ALC200P. The mono output mix
is sent to the MONO-Out output pin.
ALC200/ALC200P
Analog Inputs & Mixing
The codec incorporates a pair of stereo
ADCs. Inputs to the ADC include the
following signals: Phone, Mic1&2,
Line_L/R, Aux_L/R, CD_L/R, and Video_L/R.
Phone, MIC1 or 2, Line_L/R, CD_L/R and
Video_L/R can be mixed in the analog
domain with the stereo output for the DACs.
The input mux controls which one of the
analog inputs is sent to the ADCs. The
output of input mux is converted to
stereodigital PCM data and sent to the
AC'97 controller chip.
Outputs & Mixing
The ALC200 codec family is a pair of DACs
of output mixers. The stereo output mixer
sums together the analog inputs to the
ALC200/ALC100P according to the settings
from the volume control registers.
Note:The mono output mixer does not
include the PC_Beep & phone signals which
are included in the stereo output mix. The
stereo output mix is sent to the Line_Out L/R
Power Management
The ALC200 family provides various power
down modes. They are accessible through
Mx26H of the ALC200/ALC200P register
interface. Please refer to the Power
Management section of this data sheet.
AC'97 and AC-Link
The ALC200 family of codecs implements
the AC'97 register according to the AC'97
Specification. The AC-Link consists of the
five following digital interface signals to the
AC'97 controller chip: Bit_Clk, SDATA_IN,
SDATA_OUT, Reset# & Sync. Both Bit_Clk
and the SDATA_IN signals are generated
from the ALC200/ALC200P and the AC'97
controller chip will drive the Sync,
SDATA_OUT & Reset# signals. The Sync
signal is synchronized with the Bit_Clk, and
it is used to align the data within the frame.
Please refer to the AC_Link section of this
data sheet for details.
2- Pin Description :
2.1
Digital I/O pins : 10 pins
Name
RESET#
XTL-IN
I
I
Pin
No
11
2
XTL-OUT
SYNC
BIT-CLK
SDATAOUT
SDATA-IN
ID0#
ID1#
EAPD
O
I
IO
I
3
10
6
5
O
I
I
O
8
45
46
47
2.2
Type
Description
Characteristic Definition
AC'97 master H/W reset
Crystal input pad
(24.576Mhz)
Crystal output pad
Sample Sync (48Khz)
Bit clock output (12.288Mhz)
Serial TDM AC97 output
CMOS input,Vt=0.35Vdd
Crystal input pad
Serial TDM AC97 input
ID strap 0
ID strap 1
External Amplifier power
down control
CMOS output (Refer 6.2.5)
CMOS input Vt=0.35Vdd
CMOS input Vt=0.35Vdd
2mA CMOS output
Crystal output pad
Schmitt input, Vl=0.3 Vdd, Vh=0.4Vdd
CMOS input/output Vt=0.35Vdd (Refer 6.2.5)
Schmitt input, Vl=0.3 Vdd, Vh=0.4Vdd
Analog I/O Pins : 18 pins
Name
PC-BEEP
PHONE
AUX-L
AUX-R
VIDEO-L
VIDEO-R
CD-L
CD-GND
CD-R
MIC1
MIC2
LINE-L
LINE-R
LINE-OUTL
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
Pin
No
12
13
14
15
16
17
18
19
20
21
22
23
24
35
Description
PC speaker input
Speakerphone input
AUX Left channel
AUX Right channel
Video audio Left channel
Video audio Right channel
CD audio Left channel
CD audio analog GND
CD audio Right channel
First Mic input
Second Mic input
Line input Left channel
Line input Right channel
Line-Out Left channel
Characteristic Definition
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog output (1Vrms)
AC'97 Audio Codec: ALC200/ALC200P
LINEOUTR
LNLVL-L
LNLVL-R
MONOOUT
2.3
O
36
Line-Out Right channel
Analog output (1Vrms)
O
O
O
39
41
37
True Line Level output-Left
True Line Level output-Right
SpeakerPhone output
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Filter/References : 12 pins
Name
Type
VREF
VREFOUT
O
O
AFILT1
AFILT2
VRAD
VRDA
CAP1
TEST1
TEST2
NC
O
O
O
O
O
O
O
2.4
Name
AVDD1
AVDD2
AVSS1
AVSS2
VDD1
VDD2
VSS1
VSS2
Pin
No
27
28
29
30
31
32
33
43
44
34,40,
48
Description
Reference voltage
Reference voltage out with
5mA drive
ADC anti-aliasing filter cap
ADC anti-aliasing filter cap
Vref for ADC
Vref for DAC
Band gap filter
Test Pin
Test Pin
No Connect
Characteristic Definition
Analog output (2.25~2.75V)
Analog output (2.25~2.75V)
Analog output, 1nf cap to AVSS
Analog output, 1nf cap to AVSS
Analog output, +4.7uf and 0.1 uf cap to AVSS
Analog output, +4.7uf and 0.1uf cap to AVSS
1uf cap to AVSS(used to improve performance)
Digital output
Digital output
Power/Ground : 8 pins
Type
I
I
I
I
I
I
I
I
Pin
No
25
38
26
42
1
9
4
7
Description
Analog VDD (5.0V)
Analog VDD (5.0V)
Analog GND
Analog GND
Digital VDD (5.0V or 3.3V)
Digital VDD (5.0V or 3.3V)
Digital GND
Digital GND
Characteristic Definition
AC'97 Audio Codec: ALC200/ALC200P
3- ALC200/ALC200P Pin-Out Diagram :
ID0#
TEST2
TEST1
Avss2
LnLVL_Out_R
NC
LNLVL_Out_L
Avdd2
Mono_Out
47
ID1#
EAPD
NC
48
46
45
44
43
42
41
40
39
38
37
DVdd1
1
36
Line_Out_R
XTL_In
2
35
Line_Out_L
XTL_Out
3
34
NC
DVss1
4
33
CAP1
SDATA_Out
5
32
VRDA
Bit_Clk
6
31
VRAD
DVss2
7
30
AFILT2
SDATA_In
8
29
AFILT1
DVdd2
9
28
Vrefout
10
27
Vref
Reset#
11
26
AVss1
PC_Beep
12
25
Avdd1
SYNC
ALC200/ALC200P
22
23
24
Mic2
Line_In_L
Line_In_R
19
21
Mic1
18
20
CD_R
17
CD_GND
AUX_R
AUX_L
Phone
16
CD_L
15
Video_R
14
Video_L
13
Pinout Diagram of ALC200/ALC200P
AC'97 Audio Codec: ALC200/ALC200P
4- Mixer Register :
All mixer register access with odd-number will return with 0.
Reading unimplemented registers will return 0.
REG.
(HEX)
00h
02h
NAME
Reset
Master
Volume
04h
True-Line
Out Volume
06h Mono-Out
Volume
0Ah PC_BEEP
Volume
0Ch
PHONE
Volume
0Eh
MIC
Volume
10h
Line-In
Volume
12h CD Volume
14h
16h
18h
1Ah
1Ch
20h
22h
26h
28h
2Ah
2Ch
2Eh
30h
32h
7Ch
7Eh
D15 D14 D13 D12 D11 D10 D9
X
Mut
e
Mut
e
Mut
e
Mut
e
Mut
e
Mut
e
Mut
e
Mut
e
Video
Mut
Volume
e
Aux
Mut
Volume
e
PCM Out Mut
Volume
e
Record
X
Select
Record Mut
Gain
e
General Post
Purpose
3D
3D Control X
Power
EAP
Down
D
Ctrl/Status
Extended ID1
Audio ID
Extended
X
Audio
Status
PCM front FSR
Out Sample 15
Rate
PCM Surr. SSR
Out Sample 15
Rate
PCM LFE LSR
Out Sample 15
Rate
PCM Input ISR
Sample
15
Rate
Vendor ID1 0
Vendor ID2 0
X: reserved bit
D8
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
1
X
0
X
1
1
0
0
1
ML4 ML3 ML2 ML1 ML0
0
X
1
X
0
X
1
0
0
0
0 5950h
MR4 MR3 MR2 MR1 MR0 8000h
X
X
X
X
X
X
X
LNL LNL LNL LNL LNL
4
3
3
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LNR LNR LNR LNR LNR 8000h
4
3
2
1
0
MM MM MM MM MM 8000h
4
3
2
1
0
PB3 PB2 PB1 PB0 X 0000h
X
X
X
X
X
X
X
X
X
X
PH4 PH3 PH2 PH1 PH0 8008h
X
X
X
X
X
X
X
X
X
MI4 MI3 MI2 MI1 MI0 8008h
X
X
NL4 NL3 NL2 NL1 NL0
X
20d
B
X
X
NR4 NR3 NR2 NR1 NR0 8808h
X
X
CL4 CL3 CL2 CL1 CL0
X
X
X
CR4 CR3 CR2 CR1 CR0 8808h
X
X
VL4 VL3 VL2 VL1 VL0
X
X
X
VR4 VR3 VR2 VR1 VR0 8808h
X
X
AL4 AL3 AL2 AL1 AL0
X
X
X
AR4 AR3 AR2 AR1 AR0 8808h
X
X
PL4 PL3 PL2 PL1 PL0
X
X
X
PR4 PR3 PR2 PR1 PR0 8808h
X
X
X
X
X
X
X
X
X
X
X
X
X
3D
X
X
X
X
RRS RRS RRS 0000h
2
1
0
RR RR RR RR 8000h
G3 G2 G1 G0
X
X
X
X 0000h
X
X DP1 DP0 0000h
REF ANL DAC ADC 000Fh
X
LRS LRS LRS X
2
1
0
LRG LRG LRG LRG X
3
2
1
0
X
X MIX MS LBK
X
X
X
X
X
X
X
X
PR6 PR5 PR4 PR3 PR2 PR1 PR0
X
X
X
X
X
X
X
X
ID0
X
X
X
X
X
X
X
X
X
X
X
X
VRA 0201h
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA 0000h
AM
AP
X
FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR BB80
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
h
SSR SSR SSR SSR SSR SSR SSR SSR SSR SSR SSR SSR SSR SSR SSR BB80
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
h
LSR LSR LSR LSR LSR LSR LSR LSR LSR LSR LSR LSR LSR LSR LSR BB80
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
h
ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR BB80
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
h
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
0
0
1
1
V3
1
V2
0
V1
0 414Ch
V0 471Xh
AC'97 Audio Codec: ALC200/ALC200P
MX00
Reset
Default : 5950h
Bit
Type
Function
15
Reserved
14:10
R
return 10110 b
9
R
Read as 0 (No support 20-bit ADC)
8
R
Read as 0 (No support 18-bit ADC)
7
R
Read as 0 (No support 20-bit DAC)
6
R
Read as 1 (No support 18-bit DAC)
5
R
Read as 0 (No support for Loudness)
4
R
Read as 1(True Line Level output support)
3
R
Read as 0 (No simulated stereo ,for analog 3D block use)
2
R
Read as 0 (No Bass & Treble Control)
1
R
Reserved, Read as 0
0
R
Read as 0 (No Dedicated Mic PCM input)
ΠWrite to this register will reset all mixer registe2r to their default value. The write data is
ignored.
MX02
Master Volume
Default : 8000h
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:13
Reserved
12:8
R/W Master Left Volume (MLV[4..0]) in 1.5 dB step
7:5
Reserved
4:0
R/W Master Right Volume (MRV[4..0]) in 1.5 dB step
ΠFor MRV/MLV,
00h 0 dB attenuation
1Fh 46.5 dB attenuation
• MRV/MLV are 5-bit R/W variables. The 6th bit implementation is optional. For this reason,
when 6th bit is written by 1,it is equivalent to writing low 5-bit with 1. For example, writing
1xxxxx will read back 01111.
MX04
Line Level Output Volume
Default : 8000h
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:13
Reserved
12:8
R/W Line Level Output Left Volume (LNLV[4..0]) in 1.5 dB step
7:5
Reserved
4:0
R/W Line Level Output Right Volume (LNRV[4..0]) in 1.5 dB step
ΠFor LNRV/LNLV,
00h 0 dB attenuation
1Fh 46.5 dB attenuation
•Implement 5-bit volume control only. Writing 1xxxxx will be interpreted as x11111 and
response when read with x11111 too.
MX06
MONO_OUT Volume
Default : 8000H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:5
Reserved
4:0
R/W Mono Master Volume (MMV[4..0]) in 1.5 dB step
ΠFor MMV,
00h 0 dB attenuation
1Fh 46.5 dB attenuation
•Implement 5-bit volume control only. Writing 1xxxxx will be interpreted as x11111 and
response when read with x11111 too.
AC'97 Audio Codec: ALC200/ALC200P
MX0A
PC BEEP Volume
Default : 0000H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:5
Reserved
4:1
R/W PC Beep Volume (PBV[3..0]) in 3 dB step
0
Reserved
ΠFor PBV,
00h 0 dB attenuation
0Fh 45 dB attenuation
MX0C
PHONE Volume
Default : 8008H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:5
Reserved
4:0
R/W Phone Volume (PV[4..0]) in 1.5 dB step
ΠFor PV,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
MX0E
MIC Volume
Default : 8008H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:7
Reserved
6
R/W 20 dB boost control 0 : Normal
1: 20 dB boost
5
Reserved
4:0
R/W Mic Volume (MV[4..0]) in 1.5 dB step
ΠFor MV,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
MX10
LINE_IN Volume
Default : 8808H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:13
Reserved
12:8
R/W Line-In Left Volume (NLV[4..0]) in 1.5 dB step
7:5
Reserved
4:0
R/W Line-In Right Volume (NRV[4..0]) in 1.5 dB step
ΠFor NLV/NRV,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
MX12
CD Volume
Default : 8808H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:13
Reserved
12:8
R/W CD Left Volume (CLV[4..0]) in 1.5 dB step
7:5
Reserved
4:0
R/W CD Right Volume (CRV[4..0]) in 1.5 dB step
ΠFor CLV/CRV,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
AC'97 Audio Codec: ALC200/ALC200P
MX14
VIDEO Volume
Default : 8808H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:13
Reserved
12:8
R/W Video Left Volume (VLV[4..0]) in 1.5 dB step
7:5
Reserved
4:0
R/W Video Right Volume (VRV[4..0]) in 1.5 dB step
ΠFor VLV/VRV,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
MX16
AUX Volume
Default : 8808H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:13
Reserved
12:8
R/W AUX Left Volume (ALV[4..0]) in 1.5 dB step
7:5
Reserved
4:0
R/W AUX Right Volume (ARV[4..0]) in 1.5 dB step
ΠFor ALV/ARV,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
MX18
PCM_OUT Volume
Default 8808H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:13
Reserved
12:8
R/W PCM Volume (PLV[4..0]) in 1.5 dB step
7:5
Reserved
4:0
R/W PCM Right Volume (PRV[4..0]) in 1.5 dB step
ΠFor PLV/PRV,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
MX1A
Record Select
Default : 0000H
Bit
Type
Function
15:11
Reserved
10:8
R/W Left record source select (LRS[2..0])
7:3
Reserved
2:0
R/W Right record source select (RRS[2..0])
ΠFor LRS
0
1
2
3
4
5
6
7
MIC
CD LEFT
VIDEO LEFT
AUX LEFT
LINE LEFT
STEREO MIXER OUTPUT LEFT
MONO MIXER OUTPUT
PHONE
0
1
2
3
4
5
6
MIC
CD RIGHT
VIDEO RIGHT
AUX RIGHT
LINE RIGHT
STEREO MIXER OUTPUT RIGHT
MONO MIXER OUTPUT
PHONE
• For RRS
7
AC'97 Audio Codec: ALC200/ALC200P
MX1C
Record Gain
Default : 8000H
Bit
Type
Function
15
R/W Mute Control 0 : Normal
1 : Mute (-∞ dB)
14:12
Reserved
11:8
R/W Left Record Gain Select (LRG[3..0]) in 1.5 dB step
7:4
Reserved
3:0
R/W Right Record Gain Select (RRG[3..0]) in 1.5 dB step
ΠFor LRG/RRG
0Fh +22.5dB
00h 0 dB (No Gain)
MX20
General Purpose Register
Default : 0000H
Bit
Type
Function
15
R/W PCM output path & mute, 0 : pre 3D, 1 : post 3D
14
Reserved, Read as 0
13
R/W 3D Control
1 : On
0 : Off
12:10
Reserved, Read as 0
9
R/W Mono output select 0 : MIX
1 : MIC
8
R/W Mic select 0 : Mic 1
1 : Mic 2
7
R/W AD to DA loop-back control
0 : Disable
1 : Enable
6:0
Reserved
MX22
3D Control
Default : 0000H
Bit
Type
Function
15: 2
Reserved ,Read as 0
1:0
R/W Depth control (DP[1..0])
Œ3D effect control
DP[1..0]
Function
00
0%(Off)
01
50%
10
75%
11
100%
In our design,3D block output is enabled only when (MX20.13=1)
MX26
Power-down Control/Status
Default : 0000H
Bit
Type
Function
15
R/W PR7 External Amplifier Power Down (EAPD) 0 : normal 1 : Power down
14
R/W PR6
0 : Normal
1 : Power down LNLVL_OUT
13
R/W PR5
0 : Normal
1 : Disable internal clock
12
R/W PR4
0 : Normal
1 : Power down AC-Link
11
R/W PR3
0 : Normal
1 : Power down Mixer (Vref off)
10
R/W PR2
0 : Normal
1 : Power down Mixer (Vref still on)
9
R/W PR1
0 : Normal
1 : Power down PCM DAC
8
R/W PR0
0 : Normal
1 : Power down PCM ADC and input MUX
7:4
Reserved, Read as 0
3
R
Vref status
1 : Vref is up to normal level
0 : Not yet
2
R
Analog Mixer status
1 : Ready
0 : Not yet
1
R
DAC status
1 : Ready 0 : Not yet
0
R
ADC status
1 : Ready 0 : Not yet
ÊTrue table for power down mode
ADC
DAC
Mixder
PR0=1
PD
PR1=1
PD
PR2=1
PD
PR3=1
PD
PD
PD
PR4=1
PD
PD
Vref
ACLINK Int CLK
LNLVL
PD
PD
PD
PD
EAPD
AC'97 Audio Codec: ALC200/ALC200P
PR5=1
PD
PD
PD
PR6=1
PD
PR7=1
PD
PD : Power Down
Blank : Don’t Care
MX28
Extended Audio ID
Default : 0000H
Bit
Type
Function
15
R
ID1
14
R
ID0
13:10
Reserved, Read as 0
9
R
AMAP read as 1 (DAC mapping base on Codec ID)
8:0
Reserved, Read as 0
0
R
VRA read as 1 (Variable sample rate support)
ÊID1 is latched inversely from pin 46 when system reset. ID0 is latched inversely from pin 45
when system reset.
ËALC200/ALC200P maps DAC slot according to the following table
ID[1..0] PCM Left DAC slot # PCM Right DAC slot # Comment
00
3
4
Primary
01
3
4
Secondary (Docking)
10
7
8
Secondary (Surround)
11
6
9
Secondary
(Center/LFE)
MX2A
Extended Audio Status and control register
Default : 0000H
Bit
Type
Function
15:1
Reserved
0
R/W VRA 1 : enable 0 : disable
ÊIf VRA = 0, ALC200/ALC200P AD/DA operate fixed 48KHz sampling rate. Otherwise, it
operate with variable sampling rate defined in MX2C and MX32.
MX2C
PCM front output sampling rate
Default : BB80H
Bit
Type
Function
:150
R/W FOSR[15:0]Output sampling rate (in 100Hz resolution)
ÊALC200/ALC200P support the following sampling rate required in PC99 design guide.
Sampling rate
FOSR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
If the value written is not support, the closest value is returned (higher in case of a tie).
ËThis register control slot 3,4 and is accessible when CODEC ID = 00 ,01. For other
configuration, this register is reserved and return 0000h when read.
MX2E
PCM surround output sampling rate
Default : BB80H
Bit
Type
Function
:150
R/W SOSR[15:0]Output sampling rate (in 100Hz resolution)
ÊThis register control slot 7,8 and is effective when CODEC ID = 10. For other configuration,
this register is reserved and return 0000h when read.
ËFor SOSR, please refer MX2C for detail.
AC'97 Audio Codec: ALC200/ALC200P
MX30
PCM LFE output sampling rate
Default : BB80H
Bit
Type
Function
:150
R/W LOSR[15:0]Output sampling rate (in 100Hz resolution)
ÊThis register control slot 6,9 and is effective when CODEC ID = 11. For other
configuration, this register is reserved and return 0000h when read.
ËFor LOSR, please refer MX2C for detail.
MX32
PCM input sampling rate
Default : BB80H
Bit
Type
Function
:150
R/W ISR[15:0]Output sampling rate (in 100Hz resolution)
ÊALC200/ALC200P support the following sampling rate are required in PC99 design guide.
Sampling rate
ISR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
If the value written is not support, the closest value is returned (higher in case of a tie).
MX7C
Bit
15:0
VENDOR ID1
Type
R
Vendor ID “AL”
Default : 414CH
Function
MX7E
VENDOR ID2
Default : 471XH
Bit
Type
Function
15:8
R
Vendor ID “G”
7:4
R
Chip ID 0001
3:0
R
Version number
00 : version A
ÊChip ID
0001: ALC200
5- Design Suggestions :
5.1 Clocking :
The clock source of different configuration is listed below :
CODEC ID[1..0]
BIT-CLK
Clock source
00
Output
Crystal or external clock (XTAL-IN)
01
Input
external clock (XTAL-IN)
10
Input
external clock (XTAL-IN)
11
Input
external clock (XTAL-IN)
5.2 AC-Link :
When ALC200/ALC200P takes serial data from AC97 controller, it samples SDATA_OUT on
the falling edge of BIT_CLK .When ALC200 sends serial data to AC97 controller, it starts to
AC'97 Audio Codec: ALC200/ALC200P
drive SDATA_IN on the rising edge of BIT_CLK.
ALC200/ALC200P will return any uninstalled bits or registers with 0 for read operation..
ALC200 also stuffs the unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is
MSB-justified.
Refer to “Audio CODEC ’97 Component Specification Revision 2.1” for detail.
Slot#
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA-OUT
SDATA-IN
TAG
CMD DATA PCML PCM
R
TAG ADD
R
DATA PCML PCM
R
Fig5.2-1 ALC200/ALC200P slot arrangement – CODEC ID = 00 or 01
Slot#
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA-OUT
SDATA-IN
TAG
CMD DATA
TAG ADD
R
PCML PCM
R
DATA PCML PCM
R
Fig5.2-2 ALC200/ALC200P slot arrangement – CODEC ID = 10
Slot#
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA-OUT
SDATA-IN
TAG
CMD DATA
TAG ADD
R
PCML
PCM
R
DATA PCML PCM
R
Fig5.2-3 ALC200/ALC200P slot arrangement – CODEC ID = 11
5.3 Reset :
There are 3 kinds of reset operation: Cold, Warm and Register resets which are listed below :
Reset Type
Cold
Register
Warm
Trigger condition
Assert RESET# for a specified
period
Write register indexed 00h
Driven SYNC high for specified
period without BIT_CLK
CODEC response
Resets all hardware logic and all
registers to it’ s default value.
Resets all registers to it’ s default
value.
Reactivates AC-LINK, no change to
register values.
The AC97 controller should drive SYNC and SDATA-OUT low during the period of RESET# assertion to guarantee
ALC200/ALC200P to reset successfully.
AC'97 Audio Codec: ALC200/ALC200P
5.4 CD Input :
Pay attention to differential CD input. Below is an example of differential CD input.
Fig 5.4-1 Example of differential CD input
5.5 Odd Addressed Register Access :
ALC200/ALC200P will not respond to odd-addressed register access for future compatibility.
5.6 Power-down Mode :
Pay special attention to power-down control register (index 26h),especially PR4 (powering
down the AC-link).
PR0=1
PR1=1
PR0=0
PR1=0
PR4=1
Mixer off
Vref on/off
DACs off
ADCs off
Normal
PR2=1
PR3=1
Shut off
AC-LINK
PR2=0
PR3=1
Codec Ready
Fig. 5.6:
Digital I/F
off
Warm Reset
Default
Cold Reset
An example of ALC200/ALC200P power-down/power-up flow
5.7 Test Mode :
5.7.1
ATE In Circuit Test Mode :
SDATA_OUT is sampled high at the trailing edge of RESET#. At this mode
ALC200/ALC200P will drive BIT_CLK and SDATA_IN to high impedance state.
AC'97 Audio Codec: ALC200/ALC200P
5.7.2
Vendor Specific Test Mode :
SYNC is sampled high at the trailing edge of RESET#.
and SDATA_IN to high impedance state in this mode.
ALC200/ALC200P will drive BIT_CLK
6- Electrical Characteristics :
6.1 DC Characteristics :
Dvdd= 5.0V or 3.3V±5%, Tambient=250C, with 50pF external load.
Parameter
Symb
Min
Typ
Max
ol
Input voltage range
Vin
-0.30
Dvdd+0.30
Low level input voltage
1.2 / 0.7
SYNC,SDATA_OUT,RESET#
VIL
1.7 / 1.0
XTAL_IN,BIT_CLK
ID1#,ID0#
High level input voltage
-
2.0 / 1.2
-
Units
V
V
SYNC,SDATA_OUT,RESET#
XTAL_IN,BIT_CLK
ID1#,ID0#
VIH
-
2.1 / 1.7
3.2 / 2.2
2.5 / 1.7
-
High level output voltage
Low level output voltage
Pull up resistance
Input leakage current
Output leakage current
(Hi-Z)
Output buffer drive
current
VOH
VOL
-
0.5DVdd
50K
-10
-10
100K
-
0.2DVdd
200K
10
10
V
V
Ohm
uA
uA
-
-
5
-
mA
V
6.2 AC Timing Characteristics :
6.2.1
Cold Reset :
Parameter
Symb
ol
Trst_low
RESET# active low pulse
width
RESET# inactive to BIT_CLK Trst2clk
Startup delay
Fig 6.2.1-1
6.2.2
Warm Reset :
Min
Typ
Max
Units
1.0
-
-
us
162.8
-
-
ns
Cold reset timing diagram
AC'97 Audio Codec: ALC200/ALC200P
Fig 6.2.2-1
Cold reset timing diagram
Parameter
Symb
ol
SYNC active high pulse width Tsynchigh
SYNC inactive to BIT_CLK
Tsync2clk
Startup delay
6.2.3
Min
Typ
Max
Units
1.0
162.8
-
-
us
ns
AC-Link Clocks :
Fig 6.2.3-1
BIT_CLK and SYNC timing diagram
Parameter
Symbol Min
Typ
BIT_CLK frequency
12.288
BIT_CLK period
Tclk_period
81.4
BIT_CLK output jitter
BIT_CLK high pulse width(note1) Tclk_high
36
40.7
BIT_CLK low pulse width (note1) Tclk_low
36
40.7
SYNC frequency
48.0
SYNC period
Tsync_period
20.8
SYNC high pulse width
Tsync_high
1.3
SYNC low pulse width
Tsync_low
19.5
Note 1 : Worse case duty cycle is restricted to 45/55
6.2.4
Max
750
45
45
-
Units
MHz
ns
ps
ns
ns
KHz
us
us
us
Data Output and Input Times :
Fig 6.2.4-1
Data Output and Input timing diagram
Parameter
Symbol Min
Typ
Max Units
Output Valid Delay from rising edge of
tco
15
ns
BIT_CLK
Note 1 : Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the
Device driving the output.
Note 2 : 50pF external load
Parameter
Input Setup to falling edge of
BIT_CLK
Symbol
tsetup
Min
10
Typ
-
Max
-
Units
ns
AC'97 Audio Codec: ALC200/ALC200P
Input Hold from falling edge of
thold
10
ns
BIT_CLK
Note : Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the
device driving the output.
Parameter
Symbol Min
Typ
Max Units
BIT_CLK combined rise or fall plus
7
ns
flight time
SDATA combined rise or fall plus
7
ns
flight time
Note : Combined rise or fall plus flight times are provided for worst case
scenario modeling purpose.
6.2.5
Signal Rise and Fall Times :
Fig 6.2.5-1
Signal Rise and Fall timing diagram
Parameter
Symbol Min
Typ
BIT_CLK rise time
Triseclk
2
BIT_CLK fall time
Tfallclk
2
SYNC rise time
Trisesync
2
SYNC fall time
Tfallsync
2
SDATA_IN rise time
Trisedin
2
SDATA_IN fall time
Tfalldin
2
SDATA_OUT rise time
Trisedout
2
SDATA_OUT fall time
Tfalldout
2
Note 1 : 50pF external load
Note 2 : rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3 : fall is from 90% to 10% of Vdd (Voh to Vol)
6.2.6
Max
6
6
6
6
6
6
6
6
AC-Link Low Power Mode Timing :
Fig 6.2.6-1
AC-Link low power mode timing diagram
Units
ns
ns
ns
ns
ns
ns
ns
ns
AC'97 Audio Codec: ALC200/ALC200P
Parameter
End of slot 2 to BIT_CLK,
SDATA_IN low
6.2.7
Symbol
Ts2_pdown
Min
-
Typ
-
Units
us
Max
-
Units
ns
25.0
ns
ATE Test Mode :
Fig 6.2.6-1 ATE test mode timing diagram
Parameter
Symbol Min
Typ
Setup to trailing edge of
Tsetup2rst
15.0
RESET# (also applies to
SYNC)
Rising edge of RESET# to
Toff
Hi-Z delay
6.2.8
Max
1.0
AC-Link IO Pin Capacitance and Loading :
Output Pin
1 Codec 2 Codec 3 Codec 4 Codec
55pF
62pF
70pF
BIT_CLK (must support ≥ 2 Codecs) 55pF
SDATA_IN
47.5pF
47.5pF
47.5pF
47.5pF
7- Analog Performance Characteristics :
Standard test condition : Tambient=250C, Dvdd=5.0 or 3.3V ±5%,Avdd=5.0V±5%
Input Voltage Level : Logic Low=0.35*Vdd, Logic High=0.65Vdd
1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms
10KΩ/50pF load; Testbench Characterization BW :20Hz~20KHz
0dB attenuation; tone and 3D disabled
Parameter
Min
Typ
Max
Units
Full scale input voltage
1.7
Vrms
Mixer (except for MIC)
1.7
Mic input (gain=0dB)
0.17
Mic input (gain=20dB)
1.1
ADC
Full scale output voltage
DAC
1.0
1.41
Vrms
S/N (A weighted)
CD to LINE_OUT
101
dB
Other to LINE_OUT
94
ADC
86
DAC
86
S/(N+D)
ADC
80
dB
DAC
80
frequency response
Mixers
20
20,000
Hz
ADC & DAC
20
19,200
Power Supply Rejection (DAC,ADC)
-68
dB
Total Out-of-Band Noise
-63
dB
(28.8K~100KHz)
Mic 20dB gain is selected
18
20
22
dB
Crosstalk between inputs channels
-70
dB
AC'97 Audio Codec: ALC200/ALC200P
Attenuation, Gain Step Size
Input impedance (gain=0dB)
PC_BEEP only
Others
(PHONE,LINE,CD,AUX,VIDEO)
MIC1 and MIC2
Power Supply Current (nornal
operation)
VA=5v
VD=5v
Power Supply Current (power down
mode)
VA=5v
VD=5v
Vrefout
Digital Filter Characteristics
ADC Lowpass Filter
Passband
Stopband
Stopband Rejection
Passband Frequency Response
DAC Lowpass Filter
Passband
Stopband
Stopband Rejection
Passband Frequency Response
-
1.5
-
dB
-
32
32
16
-
KΩ
-
40
30
-
mA
-
5
10
-
mA
2.25
2.5
2.75
V
0
28.8
-
-76.0
+- 0.15
19.2
-
KHz
KHz
dB
dB
0
28.8
-
-78.5
+- 0.15
19.2
-
KHz
KHz
dB
dB
AC'97 Audio Codec: ALC200/ALC200P
8- ALC200/ALC200P Application Circuits:
8.1
Multiple Codec Connection :
For multiple codec connection, the primary and secondary codec use a
common external 24.576MHz clock source. The bit clock(BCLK) is provided by
the primary codec.
24.576MHz
SYNC,SDOUT,RESET#
Controller
BCLK
Primary
AC97
1st_SDIN
24.576MHz
SYNC,SDOUT,RESET#
BCLK
2nd_SDIN
Secondary
AC97
ID1#
R
ID0#
R
AC'97 Audio Codec: ALC200/ALC200P
8.1
2-Channel Application :
AC'97 Audio Codec: ALC200/ALC200P
8.2
4-Channel Application :
AC'97 Audio Codec: ALC200/ALC200P
AC'97 Audio Codec: ALC200/ALC200P
8.3
6-Channel Application :
The primary codec circuit is the same as in 4-channel application. The
secondary and third codec circuits as followed:
AC'97 Audio Codec: ALC200/ALC200P
AC'97 Audio Codec: ALC200/ALC200P
9- ALC200/ALC200P Mechanical Dimensions in Inches(mm):
48-Pin LQFP
0.339-0.371(8.6-9.4)
0.272-0.279(6.9-7.1)
36
25
37
24
48-Pin LQFP
13
48
1
12
0.020
(0.5)
0.052-0.059
(1.3-1.5)
0.399-0.371(8.6-9.4)
0.272-0.279(6.9-7.1)
ALC200/
ALC200P
0.006-0.011
(0.13-0.28)
70
0.008(0.2)
0.008(0.2)
0.066
(1.7)
0.004-0.006(0.1-0.175)
00-100
0.012-0.027(0.3-0.7)
0.004
(0.1)
0.020(0.5)
40
0.039(1.0)
AC'97 Audio Codec: ALC200/ALC200P
APPENDIX A
Performance Measured by Audio Precision System II:
The following diagrams are analog performance measured by AudioPrecision system II. The methodology is based on WHQL PC99 definition
released by Microsoft.
1. Analog Input to Analog Output (SNR spectrum, frequency response)
Fig.1 Mixer S/N ratio spectrum
AC'97 Audio Codec: ALC200/ALC200P
Fig.2 Mixer frequency response
AC'97 Audio Codec: ALC200/ALC200P
2. Digital to Analog Output (DAC)
Fig.3 DAC S/N ratio spectrum
AC'97 Audio Codec: ALC200/ALC200P
3. Analog Input to Digital (ADC)
Fig.4
ADC-to-DAC S/N ratio spectrum
AC'97 Audio Codec: ALC200/ALC200P
Fig.5
ADC-to-DAC frequency response
AC'97 Audio Codec: ALC200/ALC200P
Fig.6
ADC-to-DAC S/N ratio for multi-tone audio