MSP430 Teaching Materials

Transcription

15/01/2013
UBI
Capítulo 7
Comunicaciones
Introducción
Texas Instruments Incorporated
University of Beira Interior (PT)
Pedro Dinis Gaspar, António Espírito Santo, Bruno Ribeiro, Humberto Santos
University of Beira Interior, Electromechanical Engineering Department
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Copyright 2009 Texas Instruments
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Contents
UBI
Introduction
Communications system model
Transmission mode
Serial communications
Synchronous and asynchronous serial communications
Peripheral Interface Serial (SPI) protocol
I2C (Inter-Integrated Circuit) protocol
MSP430 communications interfaces
Quiz
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Introduction
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Una característica importante de los sistemas
basados en microprocesadores modernos es su
capacidad de comunicación, es decir, su capacidad para
intercambiar información con otros sistemas en el medio
ambiente circundante;
A bajo nivel, las interfaces de comunicación se utilizan
para descargar una actualización de firmware o para
establecer las configuraciones locales (por ejemplo,
características encender o apagar), entre otras tareas;
En un nivel superior, interfaces de comunicación se
utilizan para intercambiar información en aplicaciones
distribuidas.
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Communications system model (1/2)
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Dispositivos de comunicación digital:
Transmisor: Tiene la tarea de poner la información en el
formato adecuado para su posterior transmisión;
Receptor: Es el encargado de recoger el mensaje que se
ha enviado y extraer la información original;
Medio de comunicación: El medio físico a través del cual
fluye la información y se implementa habitualmente como:
• Par de cable trenzado;
• Cable de fibra óptica;
• Transmisión por radiofrecuencia.
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Communications system model (2/2)
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Dispositivos de un sistema de comunicación digital:
DTE: Data Terminal Equipment;
DCE: Data Communications Equipment.
Transmitter
Receiver
Transmission
medium
DTE
DCE
DCE
Receiver
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DTE
Transmitter
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Transmission mode (1/5)
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La comunicaciones entre dispositivos digitales pueden
ser divididos en dos tiempos:
Comunicaciones paralelas;
Comunicaciones seriales.
Comunicaciones paralelas:
El medio físico de transmisión tiene líneas independientes de
señal en un número igual a los bits de la palabra digital
transmitida;
La información transmitida en cualquier instante dado, es la
palabra de datos formada por los niveles lógicos en las
líneas de señal diferentes.
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Comunicaciones paralelas:
Ejemplo: Carácter ASCII “W” en una transmisión paralela.
Flujo de la información
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Comunicación serial:
El medio físico de transmisión sólo necesita una línea de
señal;
La información transmitida es proporcionada por el
transmisor como una secuencia de bits, enviado a la razón
establecida entre el transmisor y el receptor;
Se necesita información adicional para permitir la
sincronización entre el receptor y el transmisor:
• Bit de inicio: se añade al inicio de la información
transmitida, de modo que el receptor puede identificar el
inicio de una nueva transmisión;
• Bit de paro(s): Añadido a la final de la información
transmitida para indicar que el valor de los datos se ha
completado.
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Comunicación serial:
Ejemplo: Carácter ASCII “W” de transmisión serial:
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Ventajas y desventajas de las comunicaciones seriales y
paralelas:
Característica
Bus line
Sequence
Transmission
rate
Paralela
Serial
One line per bit
All
bits of one
simultaneously
One line
word
High
Sequence of bits
Low
Bus length
Short distances
Short and long distances
Cost
High
Low
Asynchronous transmission
Synchronisation between
needs start and stop bits
Critical
the different bits is Synchronous transmission
characteristics
demanding
needs some other
synchronisation
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Serial communications (1/3)
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El bit de inicio identifica el inicio de una transferencia de
datos y se genera una transición de alto a bajo en el
bus;
Tras el bit de inicio son los bits de datos. En este
ejemplo, el código ASCII para la transferencia de texto
utiliza siete bits de datos;
La comprobación de errores de bit (bit de paridad) se
envía después de los bits de datos;
Para finalizar la transmisión, uno o dos bits de parada se
emiten;
A partir de siete bits de datos, el mensaje completo
puede utilizar uno o dos bits de paro. Si se usan ocho
bits de datos, un bit de paro sólo está disponible para la
transmisión.
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Bit de paridad:
Se utiliza para verificar la integridad de la información
transmitida;
El bit se agrega por el transmisor e indica si la suma total
de los números "1" en el mensaje de datos es par o impar;
Las transmisiones pueden ser configurados para paridad par
o impar.
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Ejemplo de baud rate:
La transmisión de la “W”:
• El caracter usa siete bits de datos;
• Cuatro bits son usados para control, haciendo un total
de 11 bits.
• Esto corresponde a 11 bauds;
• Si los caracteres son transmitidos a una razón de 10
caracteres por segundo, el baud rate sería:
10x11 = 1100 baud/s.
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Synchronous and asynchronous serial
communications (1/2)
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Las comunicaciones seriales pueden ser:
Asíncrono: donde la tasa de transmisión (baud rate) está
fijado por el transmisor y el receptor funcionan en la mismo
baud rate de transmisión, utilizando el bit de inicio de
transmisión para sincronizar el inicio de un nuevo mensaje;
Síncrono: donde hay una señal de sincronización de reloj
independiente conectado entre el receptor y el transmisor.
Síncrono: donde hay una señal de sincronización de reloj
independiente conectado entre el receptor y el transmisor.
Comunicaciones síncronas:
Normalmente una unidad asume el papel de maestro y uno
o más de las otras unidades tomar el papel de esclavos;
La señal de reloj generada por el maestro es utilizado por
las unidades esclavas para transferir datos en /hacia los
registros TX y RX;
Es posible que un dispositivo para transmita y reciba
simultáneamente.
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Synchronous and asynchronous serial
communications (2/2)
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Comunicaciones asíncronas:
Caracterizada por la ausencia de cualquier señal de reloj de
sincronización entre las unidades;
La transmisión en este modo no permite la transmisión y
recepción simultáneas, es decir, cuando un dispositivo
transmite los otros dispositivos sólo escuchan.
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Serial Peripheral Interface (SPI) protocol
(1/2)
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El bus de Interfaz Serial de Periféricos (Serial Peripheral
Interface SPI) es un estándar para la comunicación
serial síncrona.
Desarrollado por Motorola;
Funciona en mod full duplex;
Relación Maestro / esclavo;
Las comunicaciones son
Siempre iniciadas por el maestro.
Bajo costo.
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Peripheral Interface Serial (SPI) protocol
(2/2)
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Soporta un solo maestro;
Puede soportar más de un esclavo;
A corta distancia entre dispositivos, por ejemplo, en una
placa de circuito impreso (PCB);
Se observa especial atención en la polaridad y la fase de
la señal de reloj;
El maestro envía los datos en un filo de reloj y lee los
datos en el otro filo. Por lo tanto, se puede enviar /
recibir al mismo tiempo.
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I2C (Inter-Integrated Circuit) protocol (1/3)
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Bus serial síncrono de computadora multi maestro;
Inventado por Philips semiconductores;
Desarrollado con el objetivo principal de establecer
vínculos entre los circuitos integrados y para conectar
periféricos de baja velocidad;
Basado en un dos líneas bidireccionales con compuertas
de colector abierto conectadas con resistores:
• SDA: Serial Data;
• SCL: Serial clock.
Los voltajes típicos usados son de +5.0 V o +3.3 V, sin
embargo otros voltajes son posibles.
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Las comunicaciones son siempre iniciados y
completados por el maestro, el cual es responsable de
generar la señal de reloj;
En aplicaciones más complejas, I2C puede funcionar en
modo de multi maestro;
La selección del esclavo por el maestro es realizado
usando la dirección de 7 bits del esclavo destino;
El maestro (en modo de transmisión) envía:
Bit de inicio;
La dirección de 7-bits del esclavo con el que se desea
comunicar;
Con un bit se determina
Con un solo bit representa si desea escribir (0) o para leer
(1) desde el esclavo;
El esclavo de destino responde con su dirección.
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Ejemplo de un sistema de comunicación I2C:
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MSP430 communications interfaces (1/2)
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Equipado con tres interfaces seriales:
USART (Universal Synchronous/Asynchronous
Receiver/Transmitter):
• UART mode;
• SPI mode;
• I2C (on ‘F15x/’F16x only).
USCI (Universal Serial Communication Interface):
• UART with Lin/IrDA support;
• SPI (Master/Slave, 3 and 4 wire modes);
• I2C (Master/Slave, up to 400 kHz).
USI (Universal Serial Interface):
• SPI (Master/Slave, 3 & 4 wire mode);
• I2C (Master/Slave, up to 400 kHz).
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MSP430 communications interfaces (2/2)
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Comparación entre los módulos de comunicaciones
USART
USCI
USI
UART:
- Only one modulator
- n/a
- n/a
- n/a
UART:
- Two modulators support
n/16 timings
- Auto baud rate detection
- IrDA encoder & decoder
- Simultaneous USCI_A and
USCI_B (2 channels)
SPI:
- Only one SPI available
- Master and Slave Modes
- 3 and 4 Wire Modes
SPI:
- Two SPI (one on each
USCI_A and USCI_B)
- 3 and 4 Wire Modes
SPI:
- Only one SPI available
I2C: (on ‘15x/’16x only)
- up to 400kbps
I2C:
- Simplified interrupt usage
- up to 400kbps
I2C:
- SW state machine needed
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Quiz (1/6)
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1. In the parallel communication transmission mode:
(a) The data is transferred more slowly;
(b) Each bit of the data has its own line;
(c) All of above;
(d) None of above.
2. In the serial communication transmission mode:
(a) The data bits arrive sequentially;
(b) The digital data is transferred faster;
(c) All of above;
(d) None of above.
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Quiz (2/6)
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3. The serial transmission mode is the most popular
digital data communications method because:
(a) Higher bit transfer rates are achieved;
(b) It is cheaper to implement than parallel transmission mode;
(c) All of above;
(d) None of above.
4. In asynchronous serial transmission communications,
the frame must include:
(a) Start and stop bits.
(b) Parity bit.
(c) All of above;
(d) None of above.
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Quiz (3/6)
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5. Even parity means that an additional bit is:
(a) Added to the data to make the sum of the “1” bits even;
(b) Subtracted from the data to make the sum of the “1” bits
even;
(c) All of above;
(d) None of above.
6. A USART is used:
(a) Only for asynchronous transmissions;
(b) Only for synchronous transmissions;
(c) In parallel transmission communications;
(d) In serial transmission communications.
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Quiz (4/6)
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7. Synchronous communication performed between two
USART requires:
(a) A common clock either in the transmitter or the receiver;
(b) No common clock;
(c) An independent clock in the transmitter;
(d) An independent clock in the receiver.
8. Asynchronous communication between two USARTs
requires:
(a) A common clock in the transmitter and the receiver;
(b) An independent clock in the transmitter and the receiver;
(c) A common clock in the transmitter or the receiver;
(d) An independent clock in the transmitter or the receiver.
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Quiz (5/6)
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9. I2C is a bus:
(a) Synchronous with a master and a slave where both can be
the transmitter or receiver;
(b) Where the master generates the clock;
(c) All of above;
(d) None of above.
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Quiz (6/6)
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Answers:
1. (b) Each bit of the data has its own line.
2. (a) The data bits arrive sequentially.
3. (c) All of above.
5. (a) Added to the data to make the sum of the “1” bits even.
6. (d) In serial transmission communications.
7. (a) A common clock either in the transmitter or the receiver.
8. (b) An independent clock in the transmitter and the receiver.
9. (d) None of above.
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UBI
Capítulo 7
Comunicaciones
Módulo USART
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Contents
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USART module introduction
USART operation: UART mode
USART operation: SPI mode
USART registers (UART and SPI modes)
Quiz
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USART module introduction (1/2)
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The USART (Universal Synchronous/Asynchronous
Receiver/Transmitter) este módulo esta basado para
comunicaciones seriales soportando comunicaciones
(RS232) y asíncronas (SPI).
El módulo USART esta disponible en los dispositivos 4xx:
MSP430x42x y MSP430x43x: un módulo;
MSP430x44x y MSP430FG461x: Dos módulos.
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USART module introduction (2/2)
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El soporte del USART:
• Modos de operación baja potencia (con auto inicio);
• Modo UART o SPI (I2C solo en ‘F15x/’F16x);
• Buffer doble TX/RX;
• Generador de baud rate;
• Habilita DMA;
• Detección de errores.
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USART operation: UART mode (1/13)
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Transmite y recibe caracteres de forma asíncrona;
La sincronización de cada carácter se basa en la
selección de baud rate seleccionada;
El transmisor y el receptor usa la misma frecuencia de
reloj que llevan el mismo baud rate;
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Proceso de Inicialización / reconfiguración
recomendada:
Poner SWRST (BIS.B #SWRST,&UxCTL);
Inicializa todos los registros del USART con SWRST = 1
(incluyendo UxCTL);
Habilita el modo USART vía los SFRs Mex (URXEx y/o
UTXEx);
Limpia por software SWRST (BIC.B #SWRST,&UxCTL);
Habilita las interrupciones (opcional) vía los SFRs Iex
(URXIEx y/o UTXIEx);
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El
formato del carácter se especifica como sigue:
Bit de inicio;
Siete u ocho bits de datos;
Bit de paridad impar/par;
Bit de dirección (modo de bit de dirección);
Uno o dos bits de paro.
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Detección de error automático:
El supresor de Glitch previene que la USART se inicie
accidentalmente;
Cualquier pulso corto en UCxRXC menor al tiempo de glitch
(aproximadamente 30 ns).
Error de trama FE: Se activa si el bit de paro es omitido de la
trama recibida;
Error de paridad PE: Se pone si la paridad es diferente de la trama
recibida;
Error de desbordamiento OE: Se pone si UxRXBUF es sobrescrita;
Condición de ruptura BRK: Se pone si todos los bits en la trama
recibida =0;
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Habilitado el receptor de la USART se activa el bit
URXEx:
El buffer del datos recibidos, UxRXBUF, contiene el carácter
movido del registro de corrimiento RX después de que el
carácter ha sido recibido.
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Habilitado el transmisor de la USART con el bit UTXEx:
La transmisión es iniciado por escribir el dato a UxTXBUF;
El valor del dato se mueve al registro de corrimiento del
transmisor en el siguiente pulso de reloj después que éste
se vacía.
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Generación del Baud rate del USART :
El baud rate estándar se genera con generadores de
frecuencia no convencionales.
El módulo USART utiliza un pre-escalador / divisor y un
modulador;
El bit de temporización (BITCLK) de este módulo se permite
que sea más pequeño que 1/3 de la señal de reloj, BRCLK.
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Generación del Baud rate del USART(continuación):
Bits de temporización:
• Implementación en dos etapas:
– Par el divisor BRCLK, el factor N esta dado por:
BRCLK
N=
baudrate
– Su parte entera es la primera fase del bit de tiempo;
– Su parte fraccionaria de este factor es el modulador;
– La nueva definición de N esta dado por:
1 n −1
N = UxBR +
mi
n i =0
∑
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Interrupción de la USART:
Un vector de interrupciones para la transmisión y un vector
para la recepción:
Interrupción de la UART por transmisión:
• La bandera de interrupción UTXIFGx se pone el
transmisor para indicar que UxTXBUF está listo para
aceptar otro carácter;
• Una petición de interrupción también se genera si UTXIEx
y GIE se activan;
• El bit UTXIFGx se reinicia automáticamente si la solicitud
de interrupción es atendida o si un carácter se escribe en
UxTXBUF.
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Interrupción de la USART(continuación):
Interrupción de la UART por recepción:
• La bandera de interrupción URXIFGx se pone cada vez
que se recibe un carácter y se cargan en UxRXBUF;
• Una petición de interrupción también se genera si URXIEx
y GIE se activan;
• URXIFGx y URXIEx se restablecen por una señal de
reinicio del sistema o cuando SWRST PUC = 1;
• URXIFGx se reinicia automáticamente si la interrupción
pendiente es atendida (cuando URXSE = 0) o cuando se
lee UxRXBUF.
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La facilidad de la detección del filo de inicio del receptor
(URXSE bit). Deberá usarse cuando:
BRCLK es la fuente del DCO;
DCO esta apagado debido al modo de operación de bajo
consumo.
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Ejemplo de comunicaciones seriales
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//***************************************************************
// MSP430G2xx3 Demo - USCI_A0, 9600 UART Echo ISR, DCO SMCLK
//
// Description: Echo a received character, RX ISR used. Normal mode is LPM0.
// USCI_A0 RX interrupt triggers TX Echo.
// Baud rate divider with 1MHz = 1MHz/9600 = ~104.2
// ACLK = n/a, MCLK = SMCLK = CALxxx_1MHZ = 1MHz
//
//
MSP430G2xx3
//
----------------//
/|\|
XIN|//
||
|
//
--|RST
XOUT|//
|
|
//
|
P1.2/UCA0TXD|------------>
//
|
| 9600 - 8N1
//
|
P1.1/UCA0RXD|<-----------//
// D. Dang
// Texas Instruments Inc.
// February 2011
// Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10
//*************************************************************
All Rights Reserved
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Ejemplo de comunicaciones seriales
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#include "msp430g2553.h"
void main(void)
{
WDTCTL = WDTPW + WDTHOLD;
// Stop WDT
BCSCTL1 = CALBC1_1MHZ;
// Set DCO
DCOCTL = CALDCO_1MHZ;
P1SEL = BIT1 + BIT2 ;
//
P1.1 = RXD, P1.2=TXD
P1SEL2 = BIT1 + BIT2 ;
//
P1.1 = RXD, P1.2=TXD
UCA0CTL1 |= UCSSEL_2;
//
SMCLK
UCA0BR0 = 104;
//
1MHz 9600
UCA0BR1 = 0;
//
1MHz 9600
UCA0MCTL = UCBRS0;
//
Modulation UCBRSx = 1
UCA0CTL1 &= ~UCSWRST;
//
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**Initialize USCI state machine**
IE2 |= UCA0RXIE;
//
Enable USCI_A0 RX interrupt
_BIS_SR(GIE);
while(1);
}
// Echo back RXed character, confirm
TX buffer is ready first
#pragma vector=USCIAB0RX_VECTOR
__interrupt void USCI0RX_ISR(void)
{
while (!(IFG2&UCA0TXIFG));
// USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF;
// TX -> RXed character
}
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USART operation: SPI mode (1/8)
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Serial data transmitted and received by multiple devices
using a shared clock provided by the master;
Three or four signals are used for SPI data exchange:
SIMO: Slave In, Master Out;
SOMI Slave Out, Master In;
UCLK USART SPI clock;
STE slave transmit enable (controlled by the master).
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USART initialization/re-configuration process:
Set SWRST (BIS.B #SWRST,&UxCTL);
Initialize all USART registers with SWRST = 1 (including
UxCTL);
Enable USART module via the MEx SFRs (URXEx and/or
UTXEx);
Clear SWRST via software (BIC.B #SWRST,&UxCTL);
Enable interrupts (optional) via the IEx SFRs (URXIEx and/or
UTXIEx);
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Define mode: Master or Slave;
Enable SPI transmit/receive, USPIEx;
State diagram of transmit enable for SPI master mode:
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State diagram of transmit enable for SPI slave mode:
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State diagram of receive enable for SPI master mode:
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UBI
State diagram of receive enable for SPI slave mode:
>> Contents
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Define serial clock control:
UCLK is provided by the master on the SPI bus.
• MM = 1: BITCLK is provided by the USART baud rate
generator on the UCLK;
• MM = 0: USART clock is provided on the UCLK pin by the
master (baud rate generator disable);
• The SPI receiver and transmitter operate in parallel and
use the same clock source for data transfer.
Define serial clock polarity (CKPL bit) and phase (CKPH
bit);
All Rights Reserved
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UBI
USART interrupts:
One interrupt vector for transmission and one interrupt
vector for reception:
UART transmit interrupt operation:
• UTXIFGx interrupt flag is set by the transmitter to
indicate that UxTXBUF is ready to accept another
character;
• An interrupt request is generated if UTXIEx and GIE are
also set;
• UTXIFGx is automatically reset if the interrupt request is
serviced or if a character is written to UxTXBUF.
>> Contents
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UBI
In this section, the register bit definitions are provided
for both USART peripheral interfaces:
Asynchronous UART mode;
Synchronous SPI mode.
The registers common to both modes are described
simultaneously, taking into account that some of them
are represented by the same mnemonic, only
differentiated by the register number (“UART” for UART
mode and “SPI” for SPI mode);
The registers used exclusively for one mode are
presented separately.
All Rights Reserved
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UBI
UxCTL, USART Control Register
Mode
7
6
5
4
3
2
1
0
UART
SPI
PENA
Unused
PEV
Unused
SPB
I2C(1)
CHAR
CHAR
LISTEN
LISTEN
SYNC
SYNC
MM
MM
SWRST
SWRST
Bit
UART mode description
SPI mode description
7
PENA
Parity enable when PENA = 1
Parity bit is generated (UTXDx) and expected (URXDx).
6
PEV
Parity select:
PEV = 0 ⇒ Odd parity
PEV = 1 ⇒ Even parity
5
SPB
Stop bit select:
SPB = 0 ⇒ One stop bit
SPB = 1 ⇒ Two stop bits
I
I2C or SPI mode select when SYNC = 1.
I2C2= 0 ⇒ SPI mode
I2CC= 1 ⇒ I2C mode
4
CHAR
Character length:
CHAR = 0 ⇒ 7-bit data
CHAR = 1 ⇒ 8-bit data
C
As UART mode
3
LISTEN
Listen enable when LISTEN = 1. The transmit signal is internally
fed back to the receiver.
L
As UART mode
2
SYNC
Synchronous mode enable:
SYNC = 0 ⇒ UART mode
SYNC = 1 ⇒ SPI Mode
S
As UART mode
N
C
1
MM
Multiprocessor mode select
MM = 0 ⇒ Idle-line multiprocessor protocol
MM = 1 ⇒ Address-bit multiprocessor protocol
M Master mode:
MM
M= 0 ⇒ USART is slave
MM = 1 ⇒ USART is master
0
SWRST
Software reset enable:
SWRST = 0 ⇒ Disabled. USART reset released for operation
SWRST = 1 ⇒ Enabled. USART logic held in reset state
S
>> Contents
U
Unused
Unused
As UART mode
W
R
S
T
All Rights Reserved
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UxTCTL, USART Transmit Control Register
Mode
7
6
3
2
1
0
UART
Unused
CKPL
SSELx
URXSE
TXWAKE
Unused
TXEPT
SPI
CKPH
CKPL
SSELx
Unused
Unused
STC
TXEPT
Bit
5
4
7
Unused
CKPH
6
CKPL
Clock polarity select:
CKPL = 0 ⇒ UCLKI = UCLK
CKPL = 1 ⇒ UCLKI = inverted UCLK
CKPL
CKPL = 0 ⇒ UCLKI = The inactive state is low.
CKPL = 1 ⇒ UCLKI = The inactive state is high.
5-4
SSELx
BRCLK source clock:
SSEL1 SSEL0 = 00 ⇒
SSELx
BRCLK source clock:
UCLKI
ACLK
SMCLK
SMCLK
3
URXSE
UART receive start-edge enable when URXSE = 1
Unused
2
TXWAKE
Transmitter wake:
TXWAKE = 0 ⇒ Next frame transmitted is data
TXWAKE = 1 ⇒ Next frame transmitted is an address
Unused
1
Unused
0
TXEPT
Transmitter empty flag:
TXEPT = 0 ⇒ UART is transmitting data and/or data is
waiting in UxTXBUF
TXEPT = 1 ⇒ Transmitter shift register and UxTXBUF are
empty or SWRST=1
External UCLK (slave mode only)
ACLK (master mode only)
SMCLK (master mode only)
SMCLK (master mode only)
STC
Slave transmit control:
STC = 0 ⇒ 4-pin SPI mode: STE enabled.
STC = 1 ⇒ 3-pin SPI mode: STE disabled.
TXEPT
Transmitter empty flag:
TXEPT = 0 ⇒ UART is transmitting data and/or data is
waiting in UxTXBUF
TXEPT = 1 ⇒ UxTXBUF and TX shift register are empty
All Rights Reserved
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UBI
UxRCTL, USART Receive Control Register
Mode
7
6
3
2
1
0
UART
FE
PE
OE
BRK
URXEIE
URXWIE
RXWAKE
RXERR
SPI
FE
Unused
OE
Unused
Unused
Unused
Unused
Unused
Bit
5
4
7
FE
Framing error flag:
= 0 ⇒ No error
= 1 ⇒ Character received with low stop bit
FE
6
PE
Parity error flag:
= 0 ⇒ No error
= 1 ⇒ Character received with parity error
Unused
5
OE
Overrun error flag:
= 0 ⇒ No error
= 1 ⇒ A character was transferred into UxRXBUF before the
previous character was read.
OE
4
BRK
Break detect flag:
= 0 ⇒ No break condition
= 1 ⇒ Break condition occurred
Unused
3
URXEIE
Receive erroneous-character interrupt-enable:
= 0 ⇒ Err. characters rejected
= 1 ⇒ Err. characters received
Unused
2
URXWIE
Receive wake-up interrupt-enable:
= 0 ⇒ All received characters set IFG
= 1 ⇒ Received address characters set IFG
Unused
1
RXWAKE
Receive wake-up flag:
= 0 ⇒ Received character is data
= 1 ⇒ Received character is an address
Unused
0
RXERR
Receive error flag:
= 0 ⇒ No receive errors detected
= 1 ⇒ Receive error detected
Unused
>> Contents
All Rights Reserved
Master mode framing error flag: (MM = 1, STC = 0)
= 0 ⇒ No conflict detected
= 1 ⇒ Bus conflict (STE’s negative edge)
As UART mode
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UxBR0, USART Baud Rate Control Register 0
Mode
7
6
UART / SPI
27
26
5
4
25
24
3
2
1
0
23
22
21
20
UxBR1, USART Baud Rate Control Register 1
Mode
7
6
UART / SPI
215
214
Bit
5
4
213
212
3
2
1
0
211
210
29
28
7
The valid baud-rate control range is 3 ≤
UxBR < 0FFFFh, where UxBR =
{UxBR1+UxBR0}.
Unpredictable receive/transmit timing
occurs if UxBR < 3.
UxBRx
UxBRx
The baud-rate generator uses the content of
{UxBR1+UxBR0} to set the baud rate.
Unpredictable SPI operation occurs if UxBR
< 2.
All Rights Reserved
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UBI
UxMCTL, USART Modulation Control Register
Mode
7
6
UART / SPI
m7
m6
Bit
7
5
4
m5
m4
3
2
1
0
m3
m2
m1
m0
UxMCTL
x
Selects the modulation for BRCLK.
UxMCTLx
Not used in SPI mode and should be set
to 00h.
UxRXBUF, USART Receive Buffer Register
Mode
7
6
UART / SPI
27
26
Bit
7
5
4
25
24
3
2
1
0
23
22
21
20
UxRXBUFx
>> Contents
The receive-data buffer is user
accessible and contains the last
received character from the receive
shift register.
Reading UxRXBUF resets the receiveerror bits, the RXWAKE bit, and
URXIFGx.
In 7-bit data mode, UxRXBUF is LSB
justified and the MSB is always cleared.
UxRXBUFx
All Rights Reserved
The receive-data buffer is user
accessible and contains the last received
character from the receive shift register.
Reading UxRXBUF resets the OE bit and
URXIFGx flag.
In 7-bit data mode, UxRXBUF is LSB
justified and the MSB is always cleared.
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UBI
UxTXBUF, USART Transmit Buffer Register
Mode
7
6
UART / SPI
27
26
Bit
5
4
25
24
3
2
1
0
23
22
21
20
7
UxTXBUFx
UxTXBUFx
The
transmit data buffer is user
accessible and holds the data
waiting to be moved into the
transmit
shift
register
and
transmitted on UTXDx.
Writing to the transmit data buffer
clears UTXIFGx.
The MSB of UxTXBUF is not used for
7-bit data and is cleared.
The
transmit data buffer is user
accessible and contains current data
to be transmitted.
When seven-bit character-length is
used, the data should be MSB
justified before being moved into
UxTXBUF.
Data is transmitted MSB first.
Writing to UxTXBUF clears UTXIFGx.
All Rights Reserved
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UBI
ME1, Module Enable Register 1
Mode
7
6
UART
UTXE0
URXE0
SPI
5
4
3
2
1
0
USPIE0
Bit
7
UTXE0
USART0 transmit enable:
UTXE0 = 0 ⇒ Module not enabled
UTXE0 = 1 ⇒ Module enabled
6
URXE0
USART0 receive enable:
URXE0 = 0 ⇒ Module not enabled
URXE0 = 1 ⇒ Module enabled
USPIE0
USART0 SPI enable:
USPIE0 = 0 ⇒ Module not enabled
USPIE0 = 1 ⇒ Module enabled
ME2, Module Enable Register 2
Mode
7
UART
6
5
4
UTXE1
URXE1
SPI
3
2
1
0
USPIE1
Bit
5
UTXE1
USART1 transmit enable:
UTXE1 = 0 ⇒ Module not enabled
UTXE1 = 1 ⇒ Module enabled
4
URXE1
USART1 receive enable:
URXE1 = 0 ⇒ Module not enabled
URXE1 = 1 ⇒ Module enabled
>> Contents
USPIE1
All Rights Reserved
USART1 SPI enable:
USPIE1 = 0 ⇒ Module not enabled
USPIE1 = 1 ⇒ Module enabled
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UBI
IE1, Interrupt Enable Register 1
Mode
7
6
UART / SPI
UTXIE0
URXIE0
Bit
5
4
3
2
1
0
7
UTXIE0
USART0 UTXIFG0 transmit interrupt enable:
UTXIE0 = 0 ⇒ Interrupt not enabled
UTXIE0 = 1 ⇒ Interrupt enabled
UTXIE0
As UART mode
6
URXIE0
USART0 URXIFG0 receive interrupt enable:
URXIE0 = 0 ⇒ Interrupt not enabled
URXIE0 = 1 ⇒ Interrupt enabled
URXIE0
As UART mode
IE2, Interrupt Enable Register 2
Mode
7
6
UART / SPI
5
4
UTXIE1
Bit
3
2
1
7
UTXIE1
USART1 UTXIFG1 transmit interrupt enable:
UTXIE1 = 0 ⇒ Interrupt not enabled
UTXIE1 = 1 ⇒ Interrupt enabled
UTXIE1
As UART mode
6
URXIE1
USART1 URXIFG1 receive interrupt enable:
URXIE1 = 0 ⇒ Interrupt not enabled
URXIE1 = 1 ⇒ Interrupt enabled
URXIE1
As UART mode
All Rights Reserved
>> Contents
0
URXIE1
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UBI
IFG1, Interrupt Flag Register 1
Mode
7
6
UART / SPI
UTXIFG0
URXIFG0
Bit
5
4
3
2
0
7
UTXIFG0
USART0 transmit interrupt flag. UTXIFG0 is
set when U0TXBUF is empty.
UTXIFG0 = 0 ⇒ No interrupt pending
UTXIFG0 = 1 ⇒ Interrupt pending
UTXIFG0
As UART mode
6
URXIFG0
USART0 receive interrupt flag. URXIFG0 is set
when U0RXBUF has received a complete
character.
URXIFG0 = 0 ⇒ No interrupt pending
URXIFG0 = 1 ⇒ Interrupt pending
URXIFG0
As UART mode
>> Contents
1
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UBI
IFG2, Interrupt Flag Register 2
Mode
UART / SPI
Bit
7
6
5
UTXIFG1
4
3
2
0
7
UTXIFG1
USART1 transmit interrupt flag. UTXIFG1
is set when U1TXBUF is empty.
UTXIFG1 = 0 ⇒ No interrupt pending
UTXIFG1 = 1 ⇒ Interrupt pending
UTXIFG1
As UART mode
6
URXIFG1
USART1 receive interrupt flag. URXIFG1
is set when U1RXBUF has received a
complete character.
URXIFG1 = 0 ⇒ No interrupt pending
URXIFG1 = 1 ⇒ Interrupt pending
URXIFG1
As UART mode
>> Contents
1
URXIFG1
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Quiz (1/5)
UBI
1. The USART supports the following communication
modes:
(a) UART and I2C;
(b) SPI and I2C;
(c) UART and SPI;
(d) None of above.
2. The USART module has:
(a) One SPI module;
(b) Two SPI modules;
(c) Three SPI modules;
(d) None of the above.
>> Contents
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Quiz (2/5)
UBI
3. The USART:
(a) Transmits and receives characters synchronously;
(b) Transmits characters synchronously and receives characters
asynchronously;
(c) Transmits characters asynchronously and receives
characters synchronously;
(d) Transmits and receives characters asynchronously.
4. The USART character format is composed of:
(a) {Start bit, Seven data bits, Parity bit, Stop bit};
(b) {Start bit, Eight data bits, Parity bit, Stop bits};
(c) {Start bit, Seven data bits, Parity bit, Address bit; Stop
bit};
(d) Each of the above is possible.
>> Contents
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Quiz (3/5)
UBI
5. The asynchronous communication formats available to
the USART module are:
(a) Idle-line multiprocessor communication protocol;
(b) Address bit multiprocessor communication protocol;
(c) All of above;
(d) None of above.
6. The automatic error detection recognizes:
(a) Framing, Parity, Receive Overrun and Break condition
errors;
(b) Framing and Parity errors;
(c) Receive Overrun and Break condition errors;
(d) Framing, Parity, Receive Overrun errors.
>> Contents
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Quiz (4/5)
UBI
7. The serial clock control in SPI mode when MM = 1 is
provided by the:
(a) UCLK pin on the master;
(b) BITCLK USART baud rate generator on the UCLK;
(c) All of above;
(d) None of above.
>> Contents
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Quiz (5/5)
UBI
Answers
1. (c) UART and SPI.
2. (a) One SPI module.
3. (d) Transmits and receives characters asynchronously.
4. (d) Each of the above is possible.
6. (a) Framing, Parity, Receive Overrun and Break condition
errors.
7. (b) BITCLK USART baud rate generator on the UCLK.
>> Contents
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UBI
Capítulo 7
Comunicaciones
Módulo USCI
www.msp430.ubi.pt
>> Contents
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Contents
UBI
USCI module introduction
USCI operation: UART mode
USCI operation: SPI mode
USCI operation: I2C mode
USCI registers: UART, SPI and I2C modes
Lab10b: USCI echo test
Quiz
>> Contents
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USCI module introduction (1/3)
UBI
Although supporting UART, SPI and I2C, the USCI
(Universal Serial Communication Interface) module is a
communications interface specially designed to
interconnect with high-speed industrial protocols:
LIN (Local interconnect Network), used for low-cost modules
in cars e.g. door modules, alarms, rain-sensors;
IrDA (Infrared Data Association).
The USCI module is available in the following devices:
• MSP430F5xx;
• MSP430F4xx and MSP430FG41xx;
• MSP430F2xx.
All Rights Reserved
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UBI
The USCI module supports:
Low power operating modes (with auto-start);
Two individual blocks:
• USCI_A: UART and SPI;
• USCI_B: SPI and I2C.
Double buffered TX/RX;
Baud rate/bit clock generator:
• With auto-baud rate detect;
• Flexible clock source.
RX glitch suppression;
DMA enabled;
Error detection.
>> Contents
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UBI
USCI block diagram:
All Rights Reserved
>> Contents
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USCI operation: SPI mode (1/9)
UBI
Flexible interface:
3- or 4-pin SPI;
7- or 8-bit data length;
Master or slave;
LSB or MSB first.
S/W configurable clock phase and polarity;
Programmable SPI master clock;
Double buffered TX/RX;
Interrupt driven TX/RX (USCI_A and USCI_B share TX
and RX vector);
Direct Memory Address ( DMA) enabled;
LPMx operation.
>> Contents
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UBI
USCI module: SPI mode block diagram:
>> Contents
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UBI
USCI module: SPI connections:
>> Contents
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UBI
Serial data transmitted and received by multiple devices
using a shared clock provided by the master;
Three or four signals are used for SPI data exchange:
UCxSIMO: Slave in, master out;
UCxSOMI: Slave out, master in;
UCxCLK: USCI SPI clock;
UCxSTE: Slave transmit enable:
• Enables a device to receive and transmit data and is
controlled by the master;
• 4 wire master, senses conflicts with other master(s);
• In 4 wire slave, externally controls TX and RX.
All Rights Reserved
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UBI
USCI initialization/re-configuration process:
Set UCSWRST (BIS.B #UCSWRST,&UCAxCTL1);
Initialize all USCI registers with UCSWRST = 1 (including
UCxCTL1);
Configure ports;
Clear UCSWRST via software (BIC.B
#UCSWRST,&UCxCTL1);
Enable interrupts (optional) via UCxRXIE and/or UCxTXIE.
>> Contents
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UBI
Define the character format as presented earlier;
Define mode: Master or Slave;
Enable SPI transmit/receive clearing the UCSWRST bit;
Define serial clock control:
UCxCLK is provided by the master on the SPI bus;
Configure serial clock polarity and phase (UCCKPL and
UCCKPH bits).
All Rights Reserved
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UBI
USCI interrupts:
vector for reception:
SPI transmit interrupt operation:
• UCxTXIFG interrupt flag is set by the transmitter to
indicate that UCxTXBUF is ready to accept another
character;
• An interrupt request is generated if UCxTXIE and GIE are
also set;
• UCxTXIFG is automatically reset if the interrupt request is
serviced or if a character is written to UCxTXBUF.
>> Contents
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UBI
USCI interrupts (continued):
USCI receive interrupt operation:
• UCxRXIFG interrupt flag is set each time a character is
received and loaded into UCxRXBUF;
• An interrupt request is also generated if UCxRXIE and GIE
are set;
• UCxRXIFG and UCxRXIE are reset by a system reset PUC
signal or when SWRST = 1;
• UCxRXIFG is automatically reset if the pending interrupt
is serviced (when UCSWRST = 1) or when UCxRXBUF is
read.
All Rights Reserved
>> Contents
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UBI
USCI interrupts (continued):
SPI TX interrupt:
>> Contents
SPI RX interrupt:
All Rights Reserved
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USCI operation: I2C mode (1/11)
UBI
The I2C mode supports any master or slave I2Ccompatible device (Specification v2.1);
Each I2C device is recognized by a unique address and
can operate as either a transmitter or a receiver, as well
as either the master or the slave;
A master initiates a data transfer and generates the clock
signal SCL;
Any device addressed by a master is considered a slave;
Communication using the bi-directional serial data (SDA)
and serial clock (SCL) pins;
>> Contents
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UBI
I2C mode block diagram:
>> Contents
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UBI
I2C mode block diagram:
>> Contents
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UBI
Initialized using the sequence given earlier;
I2C serial data:
One clock pulse is generated by the master for each data bit
transferred;
Operates with byte data (MSB transferred first);
The first byte after a START condition consists of a 7-bit
slave address and the R/W bit:
• R/W = 0: Master transmits data to a slave;
• R/W = 1: Master receives data from a slave.
The ACK bit is sent from the receiver after each byte on the
9th SCL clock.
>> Contents
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UBI
I2C addressing modes (7-bit and 10-bit addressing
modes);
I2C module operating modes:
Master transmitter;
Master receiver;
Slave transmitter;
Slave receiver.
Arbitration procedure is invoked if two or more master
transmitters simultaneously start a transmission on the
bus;
>> Contents
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UBI
I2C Clock generation and synchronization:
SCL is provided by the master on the I2C bus;
Master mode: BITCLK is provided by the USCI bit clock
generator;
Slave mode: the bit clock generator is not used.
>> Contents
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UBI
I2C interrupts:
vector for reception;
I2C transmit interrupt operation:
• UCBxTXIFG interrupt flag is set by the transmitter to
indicate that UCBxTXBUF is ready to accept another
character;
• An interrupt request is also generated if UCBxTXIE and
GIE are set;
• UCBxTXIFG is automatically reset if a character is written
to UCBxTXBUF or a NACK is received.
>> Contents
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UBI
I2C interrupts (continued):
I2C receive interrupt operation:
• UCBxRXIFG interrupt flag is set each time a character is
received and loaded into UCxRXBUF;
• An interrupt request is also generated if UCBxRXIE and
GIE are set;
• UCBxRXIFG and UCBxRXIE are reset by a system reset
PUC signal or when SWRST = 1;
• UCxRXIFG is automatically reset when UCBxRXBUF is
read.
>> Contents
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UBI
I2C transmit/receive interrupt operation:
>> Contents
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UBI
I2C state change interrupt flags:
• Arbitration-lost, UCALIFG: Flag is set when two or
more transmitters start a transmission simultaneously, or
operates as master but is addressed as a slave by
another master;
• Not-acknowledge interrupt, UCNACKIFG: Flag set
when an acknowledge is expected but is not received;
• Start condition detected interrupt, UCSTTIFG: Flag
set when the I2C module detects a START condition
together with its own address while in slave mode;
• Stop condition detected interrupt, UCSTPIFG: Flag
set when the I2C module detects a STOP condition while
in slave mode.
>> Contents
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UBI
I2C TX interrupt:
I2C RX interrupt:
All Rights Reserved
>> Contents
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USCI registers (UART, SPI and I2C modes)
(1/20)
UBI
UCAxCTL0, USCI_Ax Control Register 0 (UART, SPI)
UCBxCTL0, USCI_Bx Control Register 0 (SPI, I2C)
Mode
7
6
5
4
3
UART
UCPEN
UCPAR
UCMSB
UC7BIT
UCSPB
SPI
UCCKPH
UCCKPL
UCMSB
UC7BIT
I2C
UCA10
UCSLA10
UCMM
Unused
Bit
2
1
0
UCMODEx
UCSYNC=0
UCMST
UCMODEx
UCSYNC=1
UCMST
UCMODEx=11
UCSYNC=1
I2C mode description
7
UCPEN
Parity
enable
UCPEN = 1
when
UCCKPH
Clock phase select:
UCCKPH = 0 ⇒ Data is changed
on the 1st UCLK edge and
captured on the next one.
UCCKPH = 1 ⇒ Data is captured
on the 1st UCLK edge and
changed on the next one.
UCA10
Own addressing mode select:
UCA10= 0 ⇒ 7-bit address
UCA10= 1 ⇒ 10-bit address
6
UCPAR
Parity select:
UCPAR = 0 ⇒ Odd parity
UCPAR = 1 ⇒ Even
parity
UCCKPL
Clock polarity select.
UCCKPL = 0 ⇒ Inactive state: low.
UCCKPL = 1 ⇒ Inactive state:
high.
UCSLA10
Slave addressing mode
select:
UCSLA10= 0 ⇒ 7-bit
address
address
5
UCMSB
MSB first select:
UCMSB = 0 ⇒ LSB first
UCMSB = 1 ⇒ MSB first
UCMSB
As UART mode
UCMM
Multi-master environment
select:
UCMM= 0 ⇒ Single master
UCMM= 1 ⇒ Multi master
>> Contents
All Rights Reserved
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UBI
Mode
7
6
5
4
3
UART
UCPEN
UCPAR
UCMSB
UC7BIT
UCSPB
SPI
UCCKPH
UCCKPL
UCMSB
UC7BIT
I 2C
UCA10
UCSLA10
UCMM
Unused
Bit
2
1
0
UCMODEx
UCSYNC=0
UCMST
UCMODEx
UCSYNC=1
UCMST
UCMODEx=11
UCSYNC=1
4
UC7BIT
Character length:
= 0 ⇒ 8-bit data
= 1 ⇒ 7-bit data
UC7BIT
As UART mode
Unused
3
UCSPB
Stop bit select:
= 0 ⇒ One stop bit
= 1 ⇒ Two stop bits
UCMST
Master mode:
= 0 ⇒ USART is slave
= 1 ⇒ USART is master
UCMST
Master mode select.
= 0 ⇒ Slave mode
= 1 ⇒ Master mode
2-1
UCMODEx
USCI asynchronous mode:
= 00 ⇒ UART
= 01 ⇒ Idle-Line Multiproc.
= 10 ⇒ Address-Bit Multiproc.
= 11 ⇒ UART with ABR.
UCMODEx
USCI synchronous mode:
= 00 ⇒ 3-Pin SPI
= 01 ⇒ 4-Pin SPI (slave
enabled when UCxSTE=1)
= 10 ⇒ 4-Pin SPI (slave
enabled when UCxSTE=0)
= 11 ⇒ I2C
UCMODEx=11
USCI Mode:
= 00 ⇒ 3-Pin SPI
= 01 ⇒ 4-Pin SPI
(master/slave enabled if
STE = 1)
= 10 ⇒ 4-Pin SPI
(master/slave enabled if
STE = 0)
= 11 ⇒ I2C
0
UCSYNC=0
Synchronous mode enable:
= 0 ⇒ Asynchronous
= 1 ⇒ Synchronous
UCSYNC=1
As UART mode
UCSYNC=1
As UART mode
All Rights Reserved
>> Contents
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UBI
Mode
UART
7
6
UCSSELx
5
4
3
2
1
0
UCRXEIE
UCBRKIE
UCDORM
UCTXADDR
UCTXBRK
UCSWRST
SPI
UCSSELx
Unused
Unused
Unused
Unused
Unused
UCSWRST
I 2C
UCSSELx
Unused
UCTR
UCTXNACK
UCTXSTP
UCTXSTT
UCSWRST
Bit
7-6
UCSSELx
BRCLK source clock:
= 00 ⇒ UCLK
= 01 ⇒ ACLK
= 10 ⇒ SMCLK
= 11 ⇒ SMCLK
UCSSELx
5
UCRXEIE
Receive erroneous-character IE:
= 0 ⇒ Rejected (UCAxRXIFG not set)
= 1 ⇒ Received (UCAxRXIFG set)
4
UCBRKIE
Receive break character IE:
= 0 ⇒ Not set UCAxRXIFG.
= 1 ⇒ Set UCAxRXIFG.
>> Contents
BRCLK source clock:
= 00 ⇒ N/A
= 01 ⇒ ACLK
= 10 ⇒ SMCLK
= 11 ⇒ SMCLK
UCSSELx
BRCLK source clock:
= 00 ⇒ UCLKI
= 01 ⇒ ACLK
= 10 ⇒ SMCLK
= 11 ⇒ SMCLK
Unused
Unused
Slave addressing mode select:
address
address
Unused
UCTR
Transmitter/Receiver select:
= 0 ⇒ Receiver
= 1 ⇒ Transmitter
All Rights Reserved
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UBI
Mode
7
UART
6
UCSSELx
5
4
3
2
1
0
UCRXEIE
UCBRKIE
UCDORM
UCTXADDR
UCTXBRK
UCSWRST
SPI
UCSSELx
Unused
Unused
Unused
Unused
Unused
UCSWRST
I 2C
UCSSELx
Unused
UCTR
UCTXNACK
UCTXSTP
UCTXSTT
UCSWRST
Bit
SPI mode
description
3
UCDORM
Dormant. Puts USCI into sleep mode:
= 0 ⇒ Not dormant
= 1 ⇒ Dormant
Unused
UCTXNACK
Transmit a NACK:
= 0 ⇒ Acknowledge normally
= 1 ⇒ Generate NACK
2
UCTXADDR
Transmit address:
= 0 ⇒ Next frame transmitted is data
= 1 ⇒ Next frame transmitted is
address
Unused
UCTXSTP
Transmit STOP condition in master
mode:
= 0 ⇒ No STOP generated
= 1 ⇒ Generate STOP
1
UCTXBRK
Transmit break:
= 0 ⇒ Next frame transmitted is not a
break
= 1 ⇒ Next frame transmitted is a break
or a break/synch
Unused
UCTXSTT
Transmit START condition in master
mode:
= 0 ⇒ No START generated
= 1 ⇒ Generate START
0
UCSWRST
Software reset enable
=0 ⇒ Disabled. USCI reset released for
operation
1 ⇒ Enabled. USCI logic held in reset
state
UCSWRST
UCSWRST
As UART mode
As UART mode
All Rights Reserved
>> Contents
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UBI
UCAxBR0, USCI_Ax Baud Rate Control Register 0 (UART, SPI)
UCBxBR0, USCI_Bx Bit Rate Control Register 0 (SPI, I2C)
Mode
7
6
5
4
UART / SPI / I2C
3
2
1
0
UCBRx – low byte
UCAxBR1, USCI_Ax Baud Rate Control Register 1 (UART, SPI)
UCBxBR1, USCI_Bx Bit Rate Control Register 1 (SPI, I2C)
Mode
7
6
5
4
UART / SPI / I2C
Bit
7-6
UCBRx
>> Contents
3
2
1
0
UCBRx – high byte
I2C mode
description
Clock prescaler setting of
the baud rate generator:
Prescaler value (16-bit
value) =
{UCAxBR0+UCAxBR1x256}
UCBRx
Bit clock prescaler setting:
Prescaler value (16-bit
value) =
{UCAxBR0+UCAxBR1×256}
All Rights Reserved
UCBRx
As SPI mode
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UBI
UCAxSTAT, USCI_Ax Status Register (UART, SPI)
UCBxSTAT, USCI_Bx Status Register (SPI, I2C)
Mode
7
6
5
4
3
2
1
0
UART
UCLISTEN
UCFE
UCOE
UCPE
UCBRK
UCRXERR
UCADDR
UCIDLE
UCBUSY
SPI
UCLISTEN
UCFE
UCOE
Unused
Unused
Unused
Unused
UCBUSY
I 2C
Unused
UCSCLLOW
UCGC
UCBBUSY
UCNACKIFG
UCSTPIFG
UCSTTIFG
UCALIFG
Bit
7
UCLISTEN
Listen enable:
= 0 ⇒ Disabled
= 1 ⇒ UCAxTXD is internally
fed back to receiver
UCLISTEN
Listen enable:
= 0 ⇒ Disabled
= 1 ⇒ The transmitter
output is internally fed
back to receiver
Unused
6
UCFE
Framing error flag:
= 0 ⇒ No error
= 1 ⇒ Character with low stop
bit
UCFE
Framing error flag:
= 0 ⇒ No error
= 1 ⇒ Bus conflict (4w
master)
UCSCLLOW
SCL low:
= 0 ⇒ SCL is not held
low
= 1 ⇒ SCL is held low
5
UCOE
Overrun error flag:
= 0 ⇒ No error
= 1 ⇒ Overrun error
UCOE
As UART mode
UCGC
General call address
received:
= 0 ⇒ No general call
address
= 1 ⇒ General call
address
All Rights Reserved
>> Contents
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UBI
UCAxSTAT, USCI_Ax Status Register (UART, SPI)
UCBxSTAT, USCI_Bx Status Register (SPI, I2C)
Mode
7
6
5
4
3
2
1
0
UART
UCLISTEN
UCFE
UCOE
UCPE
UCBRK
UCRXERR
UCADDR
UCIDLE
UCBUSY
SPI
UCLISTEN
UCFE
UCOE
Unused
Unused
Unused
Unused
UCBUSY
I 2C
Unused
UCSCLLOW
UCGC
UCBBUSY
UCNACKIFG
UCSTPIFG
UCSTTIFG
UCALIFG
Bit
4
UCPE
Parity error flag:
= 0 ⇒ No error
= 1 ⇒ Character with parity error
Unused
UCBBUSY
Bus busy:
= 0 ⇒ Bus inactive
= 1 ⇒ Bus busy
3
UCBRK
Break detect flag:
= 0 ⇒ No break condition
= 1 ⇒ Break condition occurred
Unused
UCNACKIFG
NACK received interrupt flag:
= 0 ⇒ No interrupt pending
= 1 ⇒ Interrupt pending
2
UCRXERR
Receive error flag.
= 0 ⇒ No receive errors detected
= 1 ⇒ Receive error detected
Unused
UCSTPIFG
Stop condition interrupt flag:
1
UCADDR
UCIDLE
Address-bit multiproc. mode:
= 0 ⇒ Received character is data
= 1 ⇒ Received character is an
address
Idle-line multiproc. mode:
= 0 ⇒ No idle line detected
= 1 ⇒ Idle line detected
Unused
UCSTTIFG
Start condition interrupt flag:
0
UCBUSY
USCI busy:
= 0 ⇒ USCI inactive
= 1 ⇒ USCI transmit/receive
UCBUSY
UCALIFG
Arbitration lost interrupt flag:
>> Contents
All Rights Reserved
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UBI
UCAxRXBUF, USCI_Ax Receive Buffer Register (UART, SPI)
UCBxRXBUF, USCI_Bx Receive Buffer Register (SPI, I2C)
Mode
7
6
5
4
UART / SPI / I2C
Bit
7-0
UART mode
description
UCRXBUFx
3
2
1
0
UCRXBUFx
The receive-data buffer
is user accessible and
contains the last
received character
from the receive shift
register.
Reading UCxRXBUF
resets receive-error
bits, UCADDR/UCIDLE
bit and UCAxRXIFG.
In 7-bit data mode,
UCAxRXBUF is LSB
justified and the MSB
is always cleared.
I2C mode
description
SPI mode
description
UCRXBUFx
As UART mode
Reading UCxRXBUF
resets the
receive-error bits,
and UCxRXIFG
UCRXBUFx
As SPI mode
All Rights Reserved
>> Contents
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UBI
UCAxTXBUF, USCI_Ax Transmit Buffer Register (UART, SPI)
UCBxTXBUF, USCI_Bx Transmit Buffer Register (SPI, I2C)
Mode
7
6
5
4
UART / SPI / I2C
Bit
7-0
UART mode
description
UCTXBUFx
>> Contents
3
2
1
0
UCTXBUFx
The transmit data
buffer is user
accessible and holds
the data waiting to be
moved into the
transmit shift register
and transmitted on
UCAxTXD.
Writing to the transmit
data buffer clears
UCAxTXIFG.
I2C mode
description
SPI mode
description
UCTXBUFx
The transmit data
buffer is user
accessible and
holds the data
waiting to be
moved into the
transmit shift
register and
transmitted.
Writing to the
transmit data
buffer clears
UCxTXIFG.
All Rights Reserved
UCTXBUFx
As SPI mode
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UBI
IE2, Interrupt Enable Register 2 (UART, SPI, I2C)
Mode
7
6
5
4
3
2
UART
SPI
UCB0TXIE
UCB0RXIE
I 2C
UCB0TXIE
UCB0RXIE
Bit
UART mode
description
1
0
UCA0TXIE
UCA0RXIE
UCA0TXIE
UCA0RXIE
I2C mode
description
SPI mode
description
3
UCB0TXIE
USCI_B0 transmit
interrupt enable:
= 0 ⇒ Disabled
= 1 ⇒ Enabled
UCB0TXIE
As SPI mode
2
UCB0RXIE
USCI_B0 receive
interrupt enable:
= 0 ⇒ Disabled
= 1 ⇒ Enabled
UCB0RXIE
As SPI mode
1
UCA0TXIE
USCI_A0 transmit
interrupt enable:
= 0 ⇒ Disabled
= 1 ⇒ Enabled
UCA0TXIE
As UART mode
0
UCA0RXIE
USCI_A0 receive
interrupt enable:
= 0 ⇒ Disabled
= 1 ⇒ Enabled
UCA0RXIE
As UART mode
All Rights Reserved
>> Contents
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UBI
IFG2, Interrupt Flag Register 2 (UART, SPI, I2C)
Mode
7
6
5
4
3
2
UART
SPI
UCB0TXIFG
UCB0RXIFG
I 2C
UCB0TXIFG
UCB0RXIFG
Bit
1
UCA0TXIFG
UCA0TXIFG
0
UCA0RXIFG
UCA0RXIFG
I2C mode
description
3
UCB0TXIFG
USCI_B0 transmit interrupt flag:
UCB0TXIFG
As SPI mode
2
UCB0RXIFG
USCI_B0 receive interrupt flag:
UCB0RXIFG
As SPI mode
1
UCA0TXIFG
USCI_A0 transmit interrupt flag:
UCA0TXIFG
As UART mode
0
UCA0RXIFG
USCI_A0 receive interrupt flag:
UCA0RXIFG
As UART mode
>> Contents
All Rights Reserved
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UBI
UC1IE, USCI_A1 Interrupt Enable Register (UART, SPI)
UC1IE, USCI_B1 Interrupt Enable Register (SPI, I2C)
Mode
7
6
UART
Unused
Unused
5
4
Unused
Unused
3
2
SPI
Unused
Unused
Unused
Unused
UCB1TXIE
UCB1RXIE
I 2C
Unused
Unused
Unused
Unused
UCB1TXIE
UCB1RXIE
Bit
1
0
UCA1TXIE
UCA1RXIE
UCA1TXIE
UCA1RXIE
3
UCB1TXIE
USCI_B1 transmit interrupt
enable:
UTXIE1 = 0 ⇒ Disabled
UTXIE1 = 1 ⇒ Enabled
UCB1TXIE
As SPI mode
2
UCB1RXIE
USCI_B1 receive interrupt enable:
URXIE1 = 0 ⇒ Disabled
URXIE1 = 1 ⇒ Enabled
UCB1RXIE
As SPI mode
1
UCA1TXIE
USCI_A1 transmit interrupt
enable:
UTXIE1 = 0 ⇒ Disabled
UTXIE1 = 1 ⇒ Enabled
UCA1TXIE
As UART mode
0
UCA1RXIE
USCI_A1 receive interrupt
enable:
URXIE1 = 0 ⇒ Disabled
URXIE1 = 1 ⇒ Enabled
UCA1RXIE
As UART mode
All Rights Reserved
>> Contents
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UBI
UC1IFG, USCI_A1 Interrupt Flag Register (UART, SPI)
UC1IFG, USCI_B1 Interrupt Flag Register (SPI, I2C)
Mode
7
6
5
4
3
2
UART
SPI
UCB1TXIFG
UCB1RXIFG
I 2C
UCB1TXIFG
UCB1RXIFG
Bit
1
UCA1TXIFG
UCA1TXIFG
3
UCB1TXIFG
USCI_B1 transmit interrupt flag:
UCB1TXIFG
As SPI mode
2
UCB1RXIFG
USCI_B1 receive interrupt flag:
UCB1RXIFG
As SPI mode
UCA1TXIFG
USCI_A1 transmit interrupt flag:
UCA1TXIFG
As UART mode
0
UCA1RXIFG
USCI_A1 receive interrupt flag:
UCA1RXIFG
As UART mode
>> Contents
All Rights Reserved
UCA1RXIFG
1
0
UCA1RXIFG
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UBI
UCAxMCTL, USCI_Ax Modulation Control Register (UART)
7
6
5
4
3
2
UCBRFx
Bit
1
UCBRSx
0
UCOS16
7-4
UCBRFx
First modulation pattern for BITCLK16 when UCOS16 = 1
(See Table 19-3 of the MSP430x4xx User’s Guide)
3-1
UCBRSx
Second modulation pattern for BITCLK
(See Table 19-2 of the MSP430x4xx User’s Guide)
0
UCOS16
Oversampling mode enabled when UCOS16 = 1
All Rights Reserved
>> Contents
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UBI
UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register (UART)
7
6
5
4
3
2
UCIRTXPLx
Bit
0
UCIREN
7-2
UCIRTXPLx
Transmit pulse length:
tPULSE = (UCIRTXPLx + 1) / (2 x fIRTXCLK)
1
UCIRTXCLK
IrDA transmit pulse
UCIRTXCLK = 0 ⇒
UCIRTXCLK = 1 ⇒
⇒
0
1
UCIRTXCLK
UCIREN
>> Contents
clock select:
BRCLK
BITCLK16,
BRCLK,
when UCOS16 = 1
otherwise
IrDA encoder/decoder enable:
UCIREN = 0 ⇒ IrDA encoder/decoder disabled
UCIREN = 1 ⇒ IrDA encoder/decoder enabled
All Rights Reserved
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UBI
UCAxIRRCTL, USCI_Ax IrDA Receive Control Register (UART)
7
6
5
4
3
2
UCIRRXFLx
Bit
1
0
UCIRRXPL
UCIRRXFE
7-2
UCIRRXFLx
Receive filter length (minimum pulse length):
tMIN = (UCIRRXFLx + 4) / (2 × fIRTXCLK)
1
UCIRRXPL
IrDA receive input UCAxRXD polarity. When a light pulse is seen:
UCIRRXPL = 0 ⇒ IrDA transceiver delivers a high pulse
UCIRRXPL = 1 ⇒ IrDA transceiver delivers a low pulse
0
UCIRRXFE
IrDA receive filter enabled:
UCIRRXFE = 0 ⇒ Disabled
UCIRRXFE = 1 ⇒ Enabled
All Rights Reserved
>> Contents
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UBI
UCAxABCTL, USCI_Ax Auto Baud Rate Control Register (UART)
7
6
Reserved
Bit
5-4
5
4
UCDELIMx
3
2
1
0
UCSTOE
UCBTOE
Reserved
UCABDEN
UCDELIMx
Break/synch delimiter length:
UCDELIM1 UCDELIM0 = 00 ⇒
1
2
3
4
bit
bit
bit
bit
time
times
times
times
3
UCSTOE
Synch field time out error:
UCSTOE = 0 ⇒ No error
UCSTOE = 1 ⇒ Length of synch field exceeded measurable time
2
UCBTOE
Break time out error:
UCBTOE = 0 ⇒ No error
UCBTOE = 1 ⇒ Length of break field exceeded 22 bit times.
0
UCABDEN
Automatic baud rate detect enable:
UCABDEN = 0 ⇒ Baud rate detection disabled
UCABDEN = 1 ⇒ Baud rate detection enabled
>> Contents
All Rights Reserved
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UBI
UCBxI2COA, USCIBx I2C Own Address Register (I2C)
15
14
13
12
11
10
UCGCEN
0
0
0
0
0
7
6
5
4
3
2
9
8
I2COAx
1
0
I2COAx
Bit
15
UCGCEN
General call response enable:
UCGCEN = 0 ⇒ Do not respond to a general call
UCGCEN = 1 ⇒ Respond to a general call
9-0
I2COAx
I2C own address (local address of the USCI_Bx I2C controller)
⇒ Right-justified address
⇒ 7-bit address ⇒ Bit 6 is the MSB, Bits 9-7 are ignored.
⇒ 10-bit address ⇒ Bit 9 is the MSB.
All Rights Reserved
>> Contents
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UBI
UCBxI2CSA, USCI_Bx I2C Slave Address Register (I2C)
15
14
13
12
11
10
0
0
0
0
0
0
7
6
5
4
3
2
9
8
I2CSAx
1
0
I2CSAx
Bit
9-0
I2CSAx
>> Contents
I2C slave address (slave address of the external device to be addressed
by the USCI_Bx module)
⇒ Only used in master mode
⇒ Right-justified address
⇒ 7-bit address ⇒ Bit 6 is the MSB, Bits 9-7 are ignored.
⇒ 10-bit address ⇒ Bit 9 is the MSB.
All Rights Reserved
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UBI
UCBxI2CIE, USCI_Bx I2C Interrupt Enable Register (I2C)
7
6
5
4
Reserved
Bit
3
3
2
1
0
UCNACKIE
UCSTPIE
UCSTTIE
UCALIE
UCNACKIE
2
Not-acknowledge interrupt enable:
UCNACKIE = 0 ⇒ Interrupt disabled
UCNACKIE = 1 ⇒ Interrupt enabled
UCSTPIE
Stop condition interrupt enable:
UCSTPIE = 0 ⇒ Interrupt disabled
UCSTPIE = 1 ⇒ Interrupt enabled
UCSTTIE
Start condition interrupt enable:
UCSTTIE = 0 ⇒ Interrupt disabled
UCSTTIE = 1 ⇒ Interrupt enabled
UCALIE
Arbitration lost interrupt enable:
UCALIE = 0 ⇒ Interrupt disabled
UCALIE = 1 ⇒ Interrupt enabled
1
0
>> Contents
All Rights Reserved
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Quiz (1/6)
UBI
1. The USCI module has:
(a) One module;
(b) Two modules;
(c) Three modules;
(d) None.
2. The USCI module in UART mode supports:
(a) LIN;
(b) IrDA;
(c) All of above;
(d) None of above.
>> Contents
All Rights Reserved
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Quiz (2/6)
UBI
3. The UCMSB bit controls:
(a) The direction of the data transfer;
(b) Selects LSB or MSB first;
(c) All of above;
(d) None of above.
4. The automatic baud rate detection uses a “break”
which is:
(a) Detected when 11 or more continuous “0”s are received;
(b) Detected when 4 or more continuous “0”s are received;
(c) Detected when 8 or more continuous “0”s are received;
(d) None.
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Quiz (3/6)
UBI
5. The automatic baud rate detection uses a synch field
which is represented by:
(a) Data 022h inside a byte field;
(b) Data 055h inside a byte field;
(c) Data 044h inside a byte field;
(d) None.
6. The USCI module in UART mode for IrDA decoding
detects:
(a) Low pulse;
(b) High pulse;
(c) All of above;
(d) None.
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Quiz (4/6)
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7. The baud rate can be generated using:
(a) A low frequency;
(b) Oversampling;
(c) All of above;
(d) None of above.
8. In USCI I2C communication, the ACK bit is sent from
the receiver after:
(a) Each bit on the 9th SCL clock;
(b) Each byte on the 2th SCL clock;
(c) Each bit on the 2th SCL clock;
(d) Each byte on the 9th SCL clock.
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Quiz (5/6)
UBI
9. The operating modes provided by the I2C mode are:
(a) Master transmitter and Slave receiver;
(b) Slave transmitter and Master receiver;
(c) All of above;
(d) None of above.
10. The I2C state change interrupt flags are:
(a) Arbitration-lost and Not-acknowledge;
(b) Start and stop conditions;
(c) All of above;
(d) None of above.
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Quiz (6/6)
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Answers:
1. (b) Two modules.
4. (a) Detected when 11 or more continuous “0”s are received.
5. (b) Data 055h inside a byte field.
8. (d) Each byte on the 9th SCL clock.
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Chapter 7
Communicaciones
USI Module
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Contents
UBI
USI module introduction
USI operation: SPI mode
USI operation: I2C mode
USI registers (SPI and I2C modes)
Lab10b: Echo test using SPI
Lab10c: Echo test using I2C
Quiz
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USI module introduction (1/2)
UBI
The USI (Universal Serial Interface) module supports
basic SPI and I2C synchronous serial communications;
It is available in the MSP430x20xx family of devices;
The USI module supports:
SPI or I2C modes;
Interrupt driven;
Reduces CPU load;
Flexible clock source selection.
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USI module introduction (2/2)
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USI block diagram:
SPI mode:
• Programmable data length (8/16-bit shift register);
• MSB/LSB first.
I2C mode:
• START/STOP detection;
• Arbitration lost detection.
Interrupt driven;
Reduces CPU load;
Flexible clock source.
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USI operation: SPI and I2C modes (1/5)
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Shift register and bit counter that include logic to
support SPI and I2C communication;
USISR shift register (up to 16 bits supported):
Directly accessible by software;
Contains the data to be transmitted/received
(simultaneously);
MSB or LSB first.
Bit counter:
Controls the number of bits transmitted/received;
Counts the number of sampled bits;
Sets USIIFG when the USICNTx = 0 (decrementing or
writing zero to USICNTx bits);
Writing USICNTx > 0 automatically clears USIIFG when
USIIFGCC = 0 (automatically stops clocking after last bit).
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USI initialization:
Reset USISWRST;
Set USIPEx bits (USI function for the pin and maintains the
PxIN and PxIFG functions for the pin):
• Port input levels can be read via the PxIN register by
software;
• Incoming data stream can generate port interrupts on
data transitions.
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Recommended USI initialization process:
Set the USIPEx bits in the USI control register (USI function
for the pin and set up the PxIN and PxIFG functions for the
pin as well);
Set the direction of the RX and TX shift register (MSB or LSB
first) by USILSB bit;
Select the mode (master or slave) by USIMTS bit;
Enable or disable output data by USIOE bit;
Enable USI interrupts by setting USIIE bit;
Set up USI clock by configuring the USICKCTL control
register;
Enable USI by setting USISWRST bit;
Read port input levels via the PxIN register by software;
Incoming data stream will generate port interrupts on data
transitions.
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USI clock generation:
Clock selection multiplexer:
• Internal clocks ACLK or SMCLK;
• External clock SCLK;
• USISWCLK (software clock input bit);
• Timer_A CAP/COM outputs.
Configurable divider;
Auto-stop on interrupt: USIIFG;
Selectable phase and polarity.
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USICKPL: Selects the inactive level of the SPI clock (data
latching on rising or falling edge);
USICKPH: Selects the clock edge on which SDO is
updated and SDI is sampled (idle high or low support).
USIIFG automatically cleared and set by USICNTx;
Clock stop on IFG: USIIFG and USISTTIFG.
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USI operation: SPI mode (1/2)
UBI
Configure SPI mode:
SPI master:
• USIMST = 1;
• USII2C = 0;
• Select clock source;
• SCLK -> output.
SPI slave:
• USIMST = 0;
• USII2C = 0;
• SCLK -> input;
• Receives the clock externally from the master.
USIPEx bits enable data and clock pins;
Port logic functions, including interrupts as normal;
Data output latched on shift clock.
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USI operation: SPI mode (2/2)
UBI
SPI interrupts:
One interrupt vector associated with the USI module;
One interrupt flag, USIIFG:
• Set when bit counter counts to zero;
• Generates an interrupt request when USIIE = 1;
• Cleared when USICNTx > 0 (USIIFGCC = 0), or directly
by software;
• Stops clock when set.
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USI operation: I2C mode (1/10)
UBI
Configure USI module in I2C mode:
USII2C =1;
USICKPL = 1;
USICKPH = 0;
I2C data compatibility:
USILSB = 0;
USI16B = 0;
Enable SCL and SDA
port functions:
Set USIPE6 and USIPE7.
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I2C master:
USIMST = 1 and USII2C = 1;
Select clock source (output to SCL line while USIIFG = 0).
I2C slave:
USIMST = 0;
SCL is held low if USIIFG=1, USISTTIFG=1 or if USICNTx=0.
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I2C transmitter:
Data value is first loaded into USISRL;
USIOE= 1: Enable output and start transmission (writes 8
into USICNTx);
Send Start (or repeated Start);
Define address and set R/W;
Slave ACK: (Data TX/RX + ACK for N bytes);
SCL is generated in master mode or released from being
held low in slave mode;
USIIFG is set after the transmission of all 8 bits (stops clock
signal on SCL in master mode or held low at the next low
phase in slave mode);
Stop (or repeated Start).
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I2C receiver:
Clear USIOE (disable output);
Enable reception by writing 8 into USICNTx (USIIFG = 0);
SCL is generated in master mode or released from being
held low in slave mode;
USIIFG is set after 8 clocks (stops the clock signal on SCL in
master mode or holds SCL low at the next low phase in
slave mode).
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SDA configuration:
Direction;
Used for TX/RX, ACK/NACK handling and START/STOP
generation;
USIGE: Output latch control;
USIOE: Data output enable.
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START condition:
(high-to-low transition on SDA while SCL is high);
Clear MSB of the shift register;
USISTTIFG set on start (Sources USI interrupt).
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STOP condition:
(low-to-high transition on SDA while SCL is high):
Clear the MSB in the shift register and loads 1 into USICNTx
(finishes the acknowledgment bit and pulls SDA low);
USISTP set on stop (CPU-accessible flag).
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Receiver ACK/NACK generation:
After address/data reception;
SDA = output;
Output 1 data bit: 0 = ACK, 1 = NACK.
Transmitter ACK/NACK Detection:
After address/data transmission;
SDA = input;
Receive 1 data bit: 0 = ACK, 1 = NACK.
Arbitration procedure (in multi-master I2C systems);
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I2C Interrupts:
One interrupt vector associated with the USI;
Two interrupt flags, USIIFG and USISTTIFG;
Each interrupt flag has its own interrupt enable bit, USIIE
and USISTTIE;
When an interrupt is enabled and the GIE bit is set, a set
interrupt flag will generate an interrupt request;
USIIFG is set (USICNTx = 0);
USISTTIFG is set (START condition detection).
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Example:
Procedure for I2C communication between a Master TX and a
Slave RX.
Master TX
Slave RX
1: Send Start, Address and R/W bit 1: Detect Start, receive address and
R/W
2: Receive (N)ACK
2: Transmit (N)ACK
3: Test (N)ACK and handle TX data
3: Data RX
4: Receive (N)ACK
4: Transmit (N)ACK
5: Test (N)ACK and prepare Stop
5: Reset for next Start
6: Send Stop
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USI registers (SPI and I2C modes) (1/8)
UBI
USICTL0, USI Control Register 0
7
6
5
4
3
2
1
0
USIPE7
USIPE6
USIPE5
USILSB
USIMST
USIGE
USIOE
USIWRST
Bit
7
USIPE7
6
USIPE6
5
USIPE5
Description
USI SDI/SDA port enable:
⇒ SPI mode ⇒ Input
⇒ I2C mode ⇒ Input or open drain output
USIPE7 = 0 ⇒ USI function disabled
USIPE7 = 1 ⇒ USI function enabled
USI SDO/SCL port enable:
⇒ SPI mode ⇒ Output
⇒ I2C mode ⇒ Input or open drain output
USI SCLK port enable:
⇒ SPI slave mode ⇒ Input
⇒ SPI master mode ⇒ Output
⇒ I2C mode ⇒ Input
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USICTL0, USI Control Register 0 (continued)
7
6
5
4
3
2
1
0
USIPE7
USIPE6
USIPE5
USILSB
USIMST
USIGE
USIOE
USIWRST
4
USILSB
3
USIMST
2
USIGE
1
USIOE
0
USIWRST
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LSB first select (direction of the receive and transmit shift
register):
USILSB = 0 ⇒ MSB first
USILSB = 1 ⇒ LSB first
Master select:
USIMST = 0 ⇒ Slave mode
USIMST = 1 ⇒ Master mode
Output latch control:
USIGE = 0 ⇒ Output latch enable depends on shift clock
USIGE = 1 ⇒ Output latch always enabled and transparent
Data output enable:
USIOE = 0 ⇒ Output disabled
USIOE = 1 ⇒ Output enabled
USI software reset:
USIWRST = 0 ⇒ USI released for operation
USIWRST = 1 ⇒ USI logic held in reset state
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USICTL1, USI Control Register 1
7
6
5
4
3
2
USICKPH
USII2C
USISTTIE
USIIE
USIAL
USISTP
Bit
7
USICKPH
6
USII2C
5
USISTTIE
4
USIIE
1
USISTTIFG
0
USIIFG
Description
Clock phase select:
USICKPH = 0 ⇒ Data is changed on the first SCLK edge and
captured on the following edge
USICKPH = 1 ⇒ Data is captured on the first SCLK edge and
changed on the following edge
I2C mode enable:
USII2C = 0 ⇒ I2C mode disabled
USII2C = 1 ⇒ I2C mode enabled
START condition interrupt-enable:
USISTTIE = 0 ⇒ Interrupt on START condition disabled
USISTTIE = 1 ⇒ Interrupt on START condition enabled
USI counter interrupt enable:
USIIE = 0 ⇒ Interrupt disabled
USIIE = 1 ⇒ Interrupt enabled
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USICTL1, USI Control Register 1 (continued)
7
6
5
4
3
2
USICKPH
USII2C
USISTTIE
USIIE
USIAL
USISTP
3
USIAL
2
USISTP
1
USISTTIFG
0
USIIFG
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1
USISTTIFG
0
USIIFG
Arbitration lost:
USIAL = 0 ⇒ No arbitration lost condition
USIAL = 1 ⇒ Arbitration lost
STOP condition received:
USISTP = 0 ⇒ No STOP condition received
USISTP = 1 ⇒ STOP condition received
START condition interrupt flag:
USISTTIFG = 0 ⇒ No interrupt pending
USISTTIFG = 1 ⇒ Interrupt pending
USI counter interrupt flag:
USIIFG = 0 ⇒ No interrupt pending
USIIFG = 1 ⇒ Interrupt pending
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USICKCTL, USI Clock Control Register
7
6
5
4
USIDIVx
Bit
7-5
USIDIVx
4-2
USISSELx
3
2
USISSELx
1
USICKPL
0
USISWCLK
Description
Clock divider select:
USIDIV2 USIDIV1 USIDIV0 = 000 ⇒ Divide by 1
Clock source select. Not used in slave mode.
USISSEL2 USISSEL1 USISSEL0 = 000 ⇒ SCLK (1)
USISSEL2 USISSEL1 USISSEL0 = 001 ⇒ ACLK
USISSEL2 USISSEL1 USISSEL0 = 010 ⇒ SMCLK
USISSEL2 USISSEL1 USISSEL0 = 011 ⇒ SMCLK
USISSEL2 USISSEL1 USISSEL0 = 100 ⇒ USISWCLK bit
USISSEL2 USISSEL1 USISSEL0 = 101 ⇒ TACCR0
USISSEL2 USISSEL1 USISSEL0 = 110 ⇒ TACCR1
USISSEL2 USISSEL1 USISSEL0 = 111 ⇒ TACCR2 (2)
(1)
Not used in SPI mode
(2)
Reserved on MSP430F20xx devices
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USICKCTL, USI Clock Control Register (continued)
7
6
USIDIVx
1
USICKPL
0
USISWCLK
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5
4
3
USISSELx
2
1
USICKPL
0
USISWCLK
USICKPL = 0 ⇒ Inactive state is low
USICKPL = 1 ⇒ Inactive state is high
Software clock:
USISWCLK = 0 ⇒ Input clock is low
USISWCLK = 1 ⇒ Input clock is high
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USICNT, USI Bit Counter Register
7
USISCLREL
6
5
USI16B
USIIFGCC
Bit
7
USISCLREL
6
USI16B
5
USIIFGCC
4-0
USICNTx
4
3
2
1
0
USICNTx
Description
SCL line release from low to idle:
USISCLREL = 0 ⇒ SCL line is held low if USIIFG is set
USISCLREL = 1 ⇒ SCL line is released
16-bit shift register enable:
USI16B = 0 ⇒ 8-bit shift register mode. (Uses USISRL low byte)
USI16B = 1 ⇒ 16-bit shift register mode (Uses both USISRx bytes)
USI interrupt flag clear control:
USIIFGCC = 0 ⇒ USIIFG automatically cleared on USICNTx update
USIIFGCC = 1 ⇒ USIIFG is not cleared automatically
USI bit count (Number of bits to be received or transmitted)
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USISRL, USI Low Byte Shift Register
7
6
5
4
3
2
1
0
1
0
USISRLx
Bit
7-0
USISRLx
Description
Contents of the USI low byte shift register
USISRH, USI High Byte Shift Register
7
6
5
4
3
2
USISRHx
Bit
7-0
USISRHx
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Description
Contents of the USI high byte shift register
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Lab10b: Echo test using SPI mode (1/17)
UBI
Project files:
C source files: Chapter
Chapter
Solution files: Chapter
Chapter
14
14
14
14
>
>
>
>
Lab10
Lab10
Lab10
Lab10
>
>
>
>
Lab10b1_student.
Lab10b2_student.c
Lab10b1_solution.c
Lab10b2_solution.c
Overview:
This laboratory explores the USCI and USI communication
interfaces in SPI mode;
The MSP430 devices supported by the Experimenter’s board
will exchange messages between themselves;
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Overview (continued):
MSP430FG4618: Master reads the current state of the slave,
and drives it to the new desired state;
MSP430F2013: Slave commanded by the Master.
A.
Resources:
USCI module: MSP430FG4618;
USI module: MSP430F2013;
Both units operate in SPI mode;
Basic Timer1 of the master device is programmed to switch
the status of the slave device once every 2 seconds;
The slave is notified of the arrival of information through the
end of counting interrupt of the USI module.
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A. Resources (continued):
The resources used are:
• USCI module;
• USI module;
• Basic Timer1;
• Interrupts;
• I/O ports.
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B. Software application organization:
MASTER
SLAVE
SOMI
RX
USCI
SPI
SIMO
USI
ISR
USI
SPI
SCLK
Main
Master Task
TX
RX
TX
P3.0
2s
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Basic Timer
ISR
Slave Status
Basic
Timer
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P1.4
Main
Slave Task
LED3
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The master unit is composed of two software
modules:
• The "Main master task" module contains the operational
algorithm of the master unit;
• The "ISR Basic Timer" module wakes the "Main master
task" with a rate of once every 2 seconds.
Similarly, the slave unit is composed of two modules:
• The "Main slave task" module contains the operational
algorithm of the slave unit;
• The "USI ISR" module reads the data received, prepares
the USI module for reception of a new command and
wakes the "Main slave task" to execute the algorithm
associated with the reception of the new command.
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C. Configuration:
Configure the control registers USCI_B (master):
• The SPI connection will operate as follows:
– Clock phase -> Data bits are sent on the first UCLK
edge and captured on the following edge;
– Clock polarity -> the inactive state is low;
– MSB first;
– 8-bit data;
– Master mode;
– 3-Pin SPI;
– Source clock -> SMCLK.
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C. Configuration (continued):
• Configure the following control registers based on these
characteristics:
UCB0CTL0 = _______________;
UCB0CTL1 = _______________;
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Data rate USCI_B (master):
• The system clock is configured to operate with a
frequency of ~ 1048 kHz from the DCO;
• This frequency will be the working base of the USCI
module;
• The connection operates at a clock frequency of ~ 500
kHz. Configure the following registers:
UCB0BR0= _______________;
UCB0BR1= _______________;
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Ports configuration USCI_B (master):
• In order to set the external interfaces of the USCI
module, it is necessary to configure the I/O ports;
• Select the USCI peripheral in SPI mode following the
connections provided at the Experimenter’s board:
P3SEL = __________________;
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Configure the control registers USI (slave):
• The SPI connection will operate in the following mode:
– MSB first;
– 8-bit data;
– Slave mode;
– Clock phase -> Data bits are sent on the first SCLK
edge and captured on the following edge;
– USI counter interrupt enable.
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characteristics:
USICTL0 = _______________;
USICTL1 = _______________;
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D. Analysis of operation:
Once the USCI module is configured in accordance with the
previous steps, to initiate the experiment, complete the files
Lab10b1_student.c (master – MSP430FG4618) and
Lab10b2_student.c (slave – MSP430F2013), compile them
and run them on the Experimenter’s board;
The finished solution can be found in the files
Lab10b1_solution.c and Lab10b2_soluction.c.
For this laboratory, the following jumper settings are
required:
• PWR1/2, BATT, LCL1/2, JP2;
• SPI: H1- 1&2, 3&4, 5&6, 7&8.
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Verification:
• Once the program code is running in the two
microcontrollers, monitor LED3 of the Experimenter’s
board. It will blink at a rate of 4 flashes per second.
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MSP-EXP430FG4618
(master)
SOLUTION
Using USCI module in SPI mode included in the FG4618 (configured as master) of the
Experimenter’s board, establish a connection to the F2013 by its USI module in SPI
mode. The data exchanged is displayed by the LED blinking.
Control registers USCI_B (master):
UCB0CTL0 = 0x29;
//UCB0CTL0 = UCCKPH|UCCKPL|UCMSB|UC7BIT|UCMST|UCMODEx|UCSYNC
//UCCKPH (Clock phase) = 0b
-> Data is changed on the
//
first UCLK edge and captured on the following edge.
//UCCKPL (Clock polarity) = 0b -> Inactive state is low
//UCMSB (MSB first select) = 1b
-> MSB first
//UC7BIT (Character length) = 0b
-> 8-bit data
//UCMST (Master mode) = 1b
-> Master mode
//UCMODEx (USCI mode) = 00b
-> 3-Pin SPI
//UCSYNC (Synch. mode enable) = 1b -> Synchronous mode
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Control registers USCI_B (master):
UCB0CTL1 = 0x81;
//UCB0CTL1 = UCSSELx |
Unused
//UCSSELx (USCI clock source select)= 10b
-> SMCLK
//UCSWRST (Software reset) = 1b -> normally set by a PUC
|UCSWRST|
UCB0BR0 = 0x02;
UCB0BR1 = 0x00;
// Data rate = SMCLK/2 ~= 500kHz
// UCB0BR1 = 0x00 & UCB0BR0 = 0x02
Configure I/O ports:
P3SEL |= 0x0E;
// P3.1,P3.2,P3.3 option select
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MSP-EXP430F2013
(slave)
SOLUTION
Using the USCI module in SPI mode included in the FG4618 (configured as
master) of the Experimenter’s board, establish a connection to the F2013 by
its USI module in SPI mode. The data exchanged is displayed by the LED
blinking.
USI (slave) control registers:
USICTL0 = 0xE3;
//USICTL0 = USIPE7|USIPE6|USIPE5|USILSB|USIMST|USIGE|USIOE|USISWRST
//USIPE7 (USI SDI/SDA port enable) = 1b
-> USI enabled
//USIPE6 (USI SDO/SCL port enable) = 1b
-> USI enabled
//USIPE5 (USI SCLK port enable) = 1b
-> USI enabled
//USILSB (LSB first) = 0b
-> MSB first
//USIMST (Master) = 0b
-> Slave mode
//USIGE (Output latch control) = 0b
-> Output latch enable
//USIOE (Serial data output enable) = 1b
-> Output enabled
//USISWRST (USI software reset) = 1b
-> Software reset
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USICTL1 = 0x10;
//USICTL1= USICKPH|USII2C|USISTTIE|USIIE|USIAL|USISTP|USISTTIFG|USIIFG
//USICKPH (Clock phase select) = 0b -> Data is changed on the first
//
SCLK edge and captured on the following edge
//USII2C (I2C mode enable) = 0b
-> I2C mode disabled
//USISTTIE (START condition interrupt) = 0b
-> Not used
//USIIE (USI counter) = 1b
-> Interrupt enabled
//USIAL (Arbitration lost) = 0b
-> Not used
//USISTP (STOP condition received) = 0b
-> Not used
//USISTTIFG (START condition int. flag) = 0b
-> Not used
//USIIFG (USI counter int. flag) = 0b
-> No int. pending
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Lab10c: Echo test using I2C mode (1/21)
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Project files:
C source files: Chapter
Chapter
Solution files: Chapter
Chapter
14
14
14
14
>
>
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>
Lab10
Lab10
Lab10
Lab10
>
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Lab10c1_student.c
Lab10c2_student.c
Lab10c1_solution.c
Lab10c2_solution.c
Overview:
This laboratory explores the USCI and USI communication
interfaces in I2C mode;
It uses the two MSP430 devices included on the
Experimenter’s board: MSP430FG4618 as the master and
the MSP430F2013 as slave;
The master receives a single byte from the slave as soon as
a button connected to P1.0 is pressed.
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A. Resources:
This laboratory uses the USCI module of the MSP430FG4618
device and the USI module included in the MSP430F2013.
Both units operate in I2C mode;
The interrupts on the slave unit are generated exclusively by
the USI module. They are:
• START condition on the I2C bus;
• Data reception and transmission.
The interrupts in the master unit are provided by the USCI
module. They are:
• Data reception;
• Logic level change on Port1.
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A. Resources:
The resources used are:
• USCI module;
• USI module;
• Interrupts;
• I/O ports.
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Software architecture:
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The master task is composed of two interrupt service
routines:
• The S1 switch service routine is used to control the way
the master receives a new data frame from the slave;
• The USCI module interrupt service routine ensures that
the data sent by the slave is read by the master .
A state machine has been implemented for the USI module
of the slave unit;
It is important to note that the states “RX Address” and “RX
(N)ACK" are transient states that ensure the USI module is
ready for the next activity.
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Slave state machine:
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C. Configuration:
• The connection via I2C bus is to operate as follows:
– Address slave with 7-bit address;
– Master mode;
– Single master;
– USCI clock source is SMCLK.
characteristics:
UCB0CTL0 = _______________;
UCB0CTL1 = _______________;
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• The system clock is configured to operate with a
frequency of ~ 1048 kHz from the DCO;
• This frequency will be the working base for the USCI
module;
• The connection operates at a clock frequency of
~ 95.3kHz. Configure the following registers:
UCB0BR0= _______________;
UCB0BR1= _______________;
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Ports configuration USCI_B (master):
• In order to set the external interfaces for the USCI
module, it is necessary to configure the I/O ports;
• Select the USCI peripheral in I2C mode to be compatible
with the connections on the Experimenter’s board:
P3SEL = __________________;
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• The connection via I2C bus is to operate as follows:
– Slave mode;
– USI counter interrupt enable (RX and TX);
– START condition interrupt-enable;
– USIIFG is not cleared automatically.
• Configure the following control registers:
USICTL0 = _______________;
USICTL1 = _______________;
USICNT = ________________;
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• The slave unit interrupt service routine is not yet
complete. The portion related to the “I2C_TX” state needs
to be completed:
– Configure the USI module as an output;
– Insert the value to transmit in the transmit register;
– Configure the bit counter.
USICTL0 |=________________;
USISRL =_________________;
USICNT |=________________;
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Once the USCI module is configured in accordance with the
previous steps, to initiate the experiment, complete the files:
• Lab10c1_student.c (master – MSP430FG4618)
• Lab10c2_student.c (slave – MSP430F2013)
Compile them and run them on the Experimenter’s board;
The completed solution can be found in the files
Lab10c1_solution.c and Lab10c2_soluction.c.
For this laboratory it is necessary to set up the following
jumper settings:
• PWR1/2, BATT, LCL1/2, JP2;
• SPI: H1- 1&2, 3&4.
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Verification:
• The slave data values are sent and incremented from
0x00 with each transmitted byte, and are verified by the
Master;
• The LED is off for address/data Acknowledge and the LED
turns on for address/data Not Acknowledge;
• The LED3 blinks at each data request:
– It is turned on by a START condition;
– It is turned off by the data transmit acknowledge by
the slave;
(Note: the I2C bus is not released by the master
because the successive START conditions are
interpreted as “repeated START”).
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Verification:
• Verify the value received by setting a breakpoint in the
line of code “RxBuffer = UCB0RXBUF;” of the USCI
interrupt.
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SOLUTION
MSP-EXP430FG4618
(master)
Using USCI module in I2C mode included in the FG4618 (configured as
its USI module in I2C mode. The master receives a single byte from the slave
as soon as a button connected on P1.0 is pressed.
USCI (master) control registers:
UCB0CTL0 = 0x0F;
//UCB0CTL0 =
//UCA10|UCSLA10|UCMM|Unused|UCMST|UCMODEx|UCSYNC|
//UCA10 (Own address) = 0b
-> Own address (7-bit)
//UCSLA10 (Slave address) = 0b
-> 7-bit slave address
//UCMM (Multi-master) = 0b
-> Single master
//Unused
//UCMST (Master mode) = 1b
-> Master mode
//UCMODEx (USCI mode) = 11b ->
I2C Mode
//UCSYNC (Synchronous mode enable) = 1b ->
Synchronous
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USCI (master) control registers:
UCB0CTL1 = 0x81;
//UCB0CTL1 =
//UCSSELx|Unused|UCTR|UCTXNACK|UCTXSTP|UCTXSTT|UCSWRST|
//UCSSELx (USCI clock source select) = 10b
-> SMCLK
//Unused
//UCTR (Transmitter/Receiver) = 0b
-> Receiver
//UCTXNACK (Transmit a NACK) = 0b
-> Ack normally
//UCTXSTP (Transmit STOP condition) = 0b
-> No STOP
//UCTXSTT (Transmit START condition) = 0b
-> No START
//UCSWRST (Software reset) = 1b
-> Enabled
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Data rate:
// DATA RATE
// data rate -> fSCL = SMCLK/11 = 95.3 kHz
UCB0BR0 = 0x0B; // fSCL = SMCLK/11 = 95.3 kHz
UCB0BR1 = 0x00;
Configure ports:
P3SEL |=0x06; // Assign I2C pins to USCI_B0
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SOLUTION
MSP-EXP430F2013
(slave)
Using USCI module in I2C mode included in the FG4618 (configured as
its USI module in I2C mode. The master receives a single byte from the slave
as soon as a button connected on P1.0 is pressed.
USICTL0 = 0XC1;
//USICTL0 =|USIPE7|USIPE6|USIPE5|USILSB|USIMST|USIGE|USIOE|USISWRST|
//USIPE7 (USI SDI/SDA port enable) = 1b
-> USI function enabled
//USIPE6 (USI SDO/SCL port enable) = 1b
-> USI function enabled
//USIPE5 (USI SCLK port enable) = 0b
-> USI function disable
//USILSB (LSB first) = 0b
-> MSB first
//USIMST (Master) = 0b
-> Slave mode
//USIGE (Output latch control) = 0b
-> Depends on shift clock
//USIOE (Serial data output enable) = 0b
-> Output
enabled
//USISWRST (USI software reset) = 1b
-> Software reset
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USICTL1 = 0x70;
//USICTL1 =
//|USICKPH|USII2C|USISTTIE|USIIE|USIAL|USISTP|USISTTIFG|USIIFG|
//USICKPH (Clock phase select) = 0b
-> Data is changed
// on the first SCLK edge and captured on the following edge.
//USII2C (I2C mode enable) = 1b
-> I2C mode enabled
//USISTTIE = 1b
-> Interrupt on START condition enabled
//USIIE = 1b
-> USI counter interrupt enable
//USIAL (Arbitration lost) = 0b
-> Not used
//USISTP (STOP condition received) = 0b
-> Not used
//USISTTIFG (START condition int. flag) = 0b
-> Not used
//USIIFG (USI counter int. flag) = 0b
-> No int. pending
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USI Bit Counter Register:
USICNT |= 0x20;
//USICNT =
//USISCLREL| USI16B |USIIFGCC |USICNTx|
//USISCLREL (SCL release) = 0b
-> SCL line is held low
//
if USIIFG is set
//USI16B (16-bit shift register enable) = 0b
-> 8-bit
//
shift register mode
//USIIFGCC (USI int. flag clear control) = 1b -> USIIFG
//
is not cleared automatically
//USICNTx (USI bit count) = 00000b (not relevant)
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I2C state machine:
USICTL0 |= USIOE;
USISRL = SlaveData;
USICNT |= 0x08;
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// SDA = output
// Send data byte
// Bit counter = 8, TX data
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Quiz (1/4)
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1. The USI module has:
(a) A SPI interface;
(b) An I2C interface;
(c) All of above;
(d) None of above.
2. The internal USI clock generation can use:
(a) ACLK and SMCLK;
(b) ACLK and MCLK;
(c) SMCLK and MCLK;
(d) None of above.
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Quiz (2/4)
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3. The USISR shift register supports:
(a) 8 bits;
(b) 16 bits;
(c) All of above;
(d) None of above.
4. The USIIFG is set when:
(a) Bit counter counts to 0xFF;
(b) Bit counter counts to 0x00;
(c) Bit counter counts to 0x80;
(d) Bit counter counts to 0x08.
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Quiz (3/4)
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5. After address/data reception, the receiver ACK/NACK
is:
(a) SDA = input: 0 = ACK, 1 = NACK;
(b) SDA = output: 0 = ACK, 1 = NACK;
(c) SDA = input: 1 = ACK, 0 = NACK;
(d) SDA = output: 1 = ACK, 0 = NACK.
6. After address/data transmission the transmitter
ACK/NACK is:
(a) SDA = input: 0 = ACK, 1 = NACK;
(b) SDA = output: 0 = ACK, 1 = NACK;
(c) SDA = input: 1 = ACK, 0 = NACK;
(d) SDA = output: 1 = ACK, 0 = NACK.
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Quiz (4/4)
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Answers:
2. (a) ACLK and SMCLK.
4. (b) Bit counter counts to 0x00.
5. (b) SDA = output: 0 = ACK, 1 = NACK.
6. (a) SDA = input: 0 = ACK, 1 = NACK.
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MSP430 Teaching Materials

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