Through the Looking Glass - International Solid

Kenneth C. Smith, Alice Wang,
and Laura C. Fujino
Through the
Looking Glass
Trend tracking for ISSCC 2012
t the IEEE International Solid-State Circuits Conference (ISSCC),
there is a long tradition of working to maintain the conference’s role as the foremost global forum for the presentation of
advances in solid-state circuits and systems on a chip (SOCs). But
this implies a great deal of effort on the part of many people. One
of the most important elements of this effort is the structuring and organization
of the Program Committee, including its subdivision into ten subcommittees focusing on diverse technical areas and its dynamic growth and adaptation through the
selection of world-renowned specialists. One of the many techniques used by the
subcommittees to remain at the forefront of evolving technology is the identification and maintenance of trend information, on the basis of which new developments become startlingly clear.
The intent of the present article is to share with IEEE Solid-State Circuits Society
(SSCS) membership a sampling of the views held by the diverse group of experts represented by the Program Committee, which for ISSCC 2012 is composed of 159 members. These members are divided into ten subcommittees whose size ranges from
12 to 18 people. This year, the subcommittees are focusing on the following areas:
analog; data converters; energy-efficient digital; high-performance digital; imagers,
microelectromechanical systems (MEMS), medical, and displays; memory; radio frequency; technology directions; wireless; and wireline.
What follows is a sampling of recent analyses and predictions from each of the ten
subcomittees.
A
Analog
Analog circuits continue to play a key role in modern technology. For example, analog
signal amplification is fundamental to interfacing with antennas, microphones, speakers, headphones, and image sensors. Analog circuits are bridges between the digital
world and the analog real world. Just as with the bridges on our roads, analog circuits
often become bottlenecks, and their design is critical to overall performance, efficiency, and robustness. Nevertheless, digital circuits such as microprocessors drive
the market, and therefore semiconductor technology has been relentlessly optimized
over the past 40 years to reduce the size, cost, and power consumption of digital circuits. Analog circuitry, however, has proven increasingly difficult to implement using
these modern IC technologies. For example, as the size of transistors has decreased,
Digital Object Identifier 10.1109/MSSC.2011.2177577
Date of publication: 14 February 2012
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the range of analog voltage they can
handle has also decreased, and the
variation observed in their analog
performance has increased.
These aspects of semiconductor technology explain two key
divergent trends in analog circuits:
One is to forgo the latest digital IC
manufacturing technologies, and
instead fabricate analog circuits in
older technologies, which can be
augmented to accommodate the
high voltages demanded by medical,
automotive, lighting, and industrial
applications. Other applications dictate a second trend: accepting full
integration of analog and digital
circuits in the most modern digital
semiconductor technology. In such
applications, advances in analog
interfaces are needed to realize the
full potential of digital processing.
THE 2012 ISSCC PROGRAM COMMITTEE
FRONT ROW, FROM LEFT: DAVID SU, TZI-DAR CHIEUH,
BRAM NAUTA, LAURA FUJINO, HIDETO HIDAKA,
HOI-JUN YOO, AND KEVIN ZHANG. BACK ROW,
FROM LEFT: ROLAND THEWES, BILL REDMAN-WHITE,
AARNO PARSSINEN, ANANTHA CHANDRAKSAN,
VENU GOPINATHAN, ANDREIA CATHELIN, STEFAN RUSU,
DAVID FRIEDMAN, MAKOTO IKEDA. NOT PICTURED IS
SUBCOMMITTEE CHAIR SIVA NARENDRA.
For example, mobile systems with
multicore digital processors routinely have their battery life limited by the power consumption of
traditional analog audio-playback
circuits. Modern analog circuits
have embedded within them digital
signal-processing elements that help
overcome analog-circuit limitations;
moreover, low-power analog circuits
are being embedded within digital
ICs to monitor their performance
and manage their power consumption. Hence, the distinction between
analog and digital circuit design is
blurring, spawning new advances in
the state of the art for both.
The efficient control, storage, and
distribution of energy are worldwide
challenges and an increasing focus of
research in analog circuits. Whereas
the manipulation and storage of
information is efficiently performed
digitally, the manipulation and storage of energy must fundamentally be
performed using analog systems. As a
result, the key technologies for power
management are predominantly analog. Consequently, there is a great deal
of activity in architectures for dc-dc
converters for many applications,
such as lighting, multiple-outputvoltage generation, and inductorless
fully integrated power conversion.
There is also an increase in the use
of circuits that harvest energy from
many sources, such as ambient light,
heat, and motion, and then store it
and convert it into usable voltages
and currents. Currently, much effort
is being directed to simultaneously
increasing the energy efficiency and
power density (power-handling ability per unit of size) of power management circuits, as shown in Figure 1.
Future power management systems
will begin to make use of sources
with voltages well below 100 mV. At
the same time, the power consumption of analog circuits is being aggressively scaled down in order to enable
these low-power systems. Micropower
instrumentation amplifiers and oscillators and highly efficient audio power
amplifiers are two examples of this
trend. Together, these technologies
will permit devices to be powered
indefinitely from sustainable sources,
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5
95.0
Trench Capacitors
2
90.0
ISSCC’12
90 nm
Peak Efficiency (%)
85.0
3
SOI + 32 nm
80.0
Eff
icie
75.0
ncy
70.0
<->
Po
we
65.0
rD
5
32 nm
CMOS
60.0
ens
ity
55.0
50.0
0.1
1
10
100
1,000
10,000
Power Density (mW/mm2)
FIGURE 1: Trends in integrated power conversion. Each year, more and more is integrated
in standard CMOS technologies, optimizing efficiency versus power density. At ISSCC 2012,
these trends are evident in a shift to higher performance, as shown by the arrow.
opening the door to ubiquitous sensing, environmental monitoring, and
diverse medical applications.
Data Converters
The march of progress in converter
designs involves exploiting the
inherent trade-offs between signalto-noise ratio (SNR), bandwidth,
sampling frequency, and power efficiency, especially when all need to be
improved. This year, at ISSCC 2012,
new and improved design combinations are being presented.
Figure 2 shows power efficiency
in terms of power dissipation per
Hertz at the Nyquist frequency versus signal-to-noise-and-distortion
ratio (SNDR). Since higher SNDR
requires more power, constant
figure-of-merit (FoM) trend lines in
the plot are proportional to SNDR.
The small dots in the graph are
previously published ISSCC results,
1E + 06
P/fsnyq (pJ)
1E + 05
1E + 04
1E + 03
1E + 02
1E + 01
1E + 00
1E – 01
20
30
40
50
60
70
SNDR (dB)
FoM = 100 f/Conversion Step
FoM = 10 f/Conversion Step
Pipeline
BP Delta Sigma
80
90
100
ISSCC 1997–2011
LP Delta Sigma
SAR
FIGURE 2: Power efficiency versus SNR, highlighting ISSCC 2012 results.
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while the ISSCC 2012 contributions
are indicated by the large triangles, squares, and circles. As the
plot indicates, ISSCC 2012 data converters have once again extended
the state-of-the-art.
Figure 3 shows bandwidth versus
SNDR. Generally speaking, bandwidth is lower at higher SNDR, as is
indicated in the figure. The trend
lines correspond to two values of
clock jitter, 0.1 and 1 ps root mean
square (psrms). In this figure, it can
be seen that bandpass delta-sigma
converters are especially pushing
the state of the art.
Figure 4 shows the FoM versus
Nyquist-bandwidth. At low frequencies, the FoM is optimal (low FoM is
better), but as the graph shows, the
FoM is deteriorating at higher frequencies. This is primarily caused
by the speed limitation of presently available technology. As can
be noted, designs presented at ISSCC
2012 show good progress, with a
successive-approximation register (SAR) pushing the state of the art
at lower frequencies and a pipeline
design breaking the barrier at higher
frequencies.
Energy-Efficient Digital
The energy efficiency of digital circuits becomes increasingly important as larger and larger numbers of
transistors are integrated on a single
chip. This is particularly important
for mobile applications in multimedia and communications.
Multimedia and communication
technologies have enhanced the lives
of mobile consumers by increasing
productivity, enhancing the social
networking experience, and delivering improved visual and audio
quality for communication links
and entertainment. In this development, the performance of embedded
CPUs has increased to meet the rising
demands of general-purpose computations. At the same time, dedicated
multimedia accelerators provide a
solution for well-defined, energy-efficient signal processing constrained by
the physical limitations of advanced
1E + 05
1E + 11
FoM (fJ/Conversion Step)
1E + 10
BW (Hz)
1E + 09
1E + 08
1E + 07
1E + 06
1E + 05
1E + 04
1E + 03
20
30
50 60 70
SNDR (dB)
40
Jitter = 0.1 psrms
Jitter = 1 psrms
BP Delta Sigma
80
1E + 04
1E + 03
1E + 02
1E + 01
1E + 00
1.0E + 04
90 100 110
ISSCC 1997–2011
LP Delta Sigma
Pipeline
SAR
1.0E + 06
1.0E + 08
fsnyq (Hz)
1.0E + 10
ISSCC 1997–2011
Pipeline
LP Delta Sigma
BP Delta Sigma
SAR
FIGURE 4: FoM (energy per conversion step) versus Nyquist-bandwidth
for various converters.
FIGURE 3: Bandwidth versus SNDR.
process technologies. But consumer
expectations for increasing mobile
functionality will continue unabated
into the foreseeable future. This fact
necessitates advances in low-voltage
technologies coupled with progress
in architectures and designs.
Figure 5 illustrates the energy
efficiency of the main CPU in a smart
phone application processor. As can
be seen, CPU performance has continually increased in both heterogeneous and homogeneous SOCs. But
because of the thermal and power
limitations of handsets, the energy
efficiency of the CPU has also had
to increase in order to sustain the
thermal and power envelopes. There
is still room for further increases in
CPU frequency, number of cores, and
memory capacity. Additional power
Application Processor Trends in Smart Phone
CPU Performance (GOPS/W)
100
Production
Conference
Heterogeneous
10
Homogeneous
1
2004
Graphics
Camera
2005
2006
2007
Image/Video
JPEG,
MPEG-4
Audio
MP3
2009
OpenGL
(ES1.1)
2-D, 3-D
1~2M
2008
3M
5~8M
AAC
2011
OpenGL/VG/M
AX (ES2.0)
10M
H.264/AVC
(VGA)
2010
H.264/AVC
(D1)
AAC Plus
16M
2012
2013
AR
(Augmented Reality)
Dual
Camera
H.264/MVC
H.264/SVC
Dolby
TrueHD/Digital+
20M
H.264/AVC
(Full HD)
WMA
Dolby 5.1
FIGURE 5: Trends in application processors for smart phones.
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Distance
Wireless Network Trends
2.5G/3G
WCDMA
UMTS
CDMA1x, 2000
Cell Phone
3.5G
LTE/LTE-A
HSDPA, Etc.
WiMAX
GSM
GPRS, EDGE
3.9/4G
WLAN
100 m
10 m
Bluetooth
802.15.1
Zigbee
802.15.4
802.11ac/ad
802.11n
802.11a/b/g
WPAN
mm-Wave
802.15.3c
UWB
PAN/Sensor Network
RF-ID
100k
1M
10M
100M
1G
10G
Downlink Data Rate (b/s)
FIGURE 6: Trends in wireless networks.
efficiency from technology, along with
circuit and architectural improvements, must be incorporated, however,
so as to offset the higher CPU clock
frequencies, additional cores, and
greater amounts of memory.
Historically, many multimedia
applications were first implemented
in general-purpose CPUs or other
programmable processors. The multimedia computational requirements
have increased faster than the ability
of programmable devices to reasonably address them, however. Originally this occurred with graphics,
imaging, and video. Semiprogrammable and hard-wired cores are now
required to remain within thermal
limits and meet economic considerations. There will be a continued
need for circuit, architectural, and
system innovations to maintain this
growth trend. New areas in which
dedicated processors are particularly
needed include gesture-based user
interfaces and computational imaging, to name only two.
Figure 6 presents current trends
in the wireless-communication standards that are employed to achieve
various link lengths and data rates.
Wireless-networking standards can
be roughly segmented into four categories: cell phones, with the greatest
link distance; wireless LANs (WLANs),
with just over 100 m in link distance;
Video/DTV Trends
Video Codec
(Standard)
MPEG-2
Application
DVD Recorder
Pixel Format
480i
Bit Rate (b/s)
~10M
Memory
MPEG2(HD)
H.264/AVC(VGA)
~20M
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2005
90n
2006
2007
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H.265/HEVC
Digital
Cinema
Holographic
Recorder
4kx2k
~50M
~300M
DDR3-1333/Wide IO
DRAM
DDR2-667~800
FIGURE 7: Trends in digital TV and video.
8
H.264/MVC
H.264/SVC
1080i/720P/480P
130n
2004
Blu-Ray
Recorder
DTV
DDR-333
Technology
H.264/AVC
(D1/Full HD)
45n
2008
2009
28n
2010
2011
2012
2013
Chip Complexity
Transistor Count (Millions)
10,000
1,000
100
10
1
1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012
Year
FIGURE 8: Chip complexity.
products continues to drive applications of high-performance digital
technology.
At ISSCC 2012, the continuing
progress in CMOS technology provides us with the first 22-nm commercial microprocessor featuring
new vertical device architectures
with triple gates. These developments enable further improvements
in area and energy efficiency.
The chip complexity chart in
Figure 8 shows the trend in transistor integration on a single chip over
the past two decades. While the 1 bil-
Clock Frequency
1,000
100
10
1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012
High-Performance Digital
Rapid progress in the reduction of
CMOS feature size in commercial
lion–transistor integration level was
first achieved five years ago, last
year marked the first commercial
product exceeding 3 billion transistors on a single die. This trend persists: Average complexity continues
to increase, with 1.4 billion transistors on the first 22-nm commercial
microprocessor chip.
As power reduction becomes
mandatory in every application, the
trend toward lower clock frequencies
also continues, as shown in the frequency trends chart in Figure 9. This is
driven by decreased supply voltages,
10,000
Clock Frequency (MHz)
personal area networks (PANs), with
up to 10 m of range at data rates of
up to 10 Mb/s; and wideband PANs
(WPANs), with up to 10 m of range at
data rates of up to 10 Gb/s. In each
of these categories, the data rate has
increased over time, typically providing an increased computational
load, so as to move closer and closer
to the theoretical channel capacity of
the system.
Figure 7 presents video and digitaltelevision trends. Generally speaking,
modern video requires a very large
number of computations to keep
up with increasing video bit rates,
increasing resolution and frame rates,
increasing complexity of the standards for video compression, and new
applications such as 3-D and multiview video that demand higher
resolution and greater numbers of
concurrent streams. Dedicated highperformance and low-power video
processor architectures and highbandwidth external dynamic randomaccess memory (DRAM) interfaces are
essential to meet these dramatically
increasing performance requirements. Mobile video also requires
energy efficiency in implementing
video streaming, encoding, and decoding for high-definition video. Both lowpower video engines and low-power
memory architectures leveraging new
technology such as wide-I/O, lowcapacitance direct interfaces to DRAM
are paramount.
As process technology continues
to advance, enabling integration on
a massive scale, this year at ISSCC
2012 we are seeing processors originate from a wide variety of technological backgrounds. New ground
is being broken in the key areas of
transistor integration, performanceper-unit power, and functional integration. This is being accomplished
across varied process technologies
(65-nm, 45-nm, 40-nm, and 32-nm)
and for bulk and silicon on insulator
(SOI) CMOS technologies.
Year
FIGURE 9: Clock frequency.
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Core Count
70
60
Core Count
50
40
30
20
10
0
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
Year
FIGURE 10: Core count.
with processors operating in the nearthreshold or even the subthreshold
voltage domain. The performance
loss resulting from reduced voltages and clock frequencies is compensated for by further increased
parallelism. Leveraging sophisticated strategies to lower leakage and
manage voltage, variability, and aging
has bolstered the continuing reduction in total power dissipation. This is
helping to rein in the immense power
demands from PCs, servers, and similar systems. Consequently, it yields
solutions with less cost and reduced
cooling requirements, resulting in
greener products.
In addition to the trend toward
integrating more cores on a single
chip, shown in the core trend chart
in Figure 10, additional dedicated
coprocessing units for graphics and
communications are now commonly
integrated on these complex SOCs. It
is worth noting that the design of such
SOCs requires broad collaboration
across multiple disciplines, including circuits, architecture, graphics,
process technology, system design,
energy efficiency, and software.
High-performance and power-efficient computing techniques continue
to be introduced for targeted critical
applications, such as floating-point
Total Power Consumption
Power Consumption (W)
250
200
150
100
and single-instruction, multiple-data
(SIMD) processors. As a result, we
can see a downward trend in power
consumption, as shown in the power
trend chart in Figure 11.
ISSCC 2012 marks the wider
introduction of massively parallel,
3-D-integrated systems. In such systems, a third dimension of integration becomes available by stacking
monolithically integrated dies and
interconnecting them by applying
innovative TSV technologies. The
result of this integration is a new
level of performance in a powerefficient package.
Another trend evident this year is
the continued emergence of all-digital phase-locked loops (PLLs) and
delay-locked loops (DLLs) to better
exploit deep-submicron-feature-size
scaling, thereby reducing power and
area costs. Due to the application of
highly innovative architectural and
circuit-design techniques, the features of these all-digital PLLs and
DLLs have improved significantly
over the past several years. The
rms-jitter-versus-power diagram in
Figure 12 shows the improvement
of the widely accepted FoM for PLLs
and multiplying delay-locked loops
(MDLLs).
Clearly, the rapid downward reduction of feature size continues to
force the replacement of traditionally analog techniques.
Imagers, MEMS, Medical,
and Displays (IMMD)
The common thread that unites
the constituents of IMMD is a concern for interfaces with the physical
world—both the human body and
its environment. Conventionally, we
consider this broad area in terms of
both task and tool: imagers, MEMS,
medical, and displays, as discussed
in the following subsections.
50
Imagers
0
1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012
Year
FIGURE 11: Total power consumption.
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The CMOS image sensor business
remains one of the fastest-growing segments of the semiconductor industry,
due to the proliferation of cell phone
cameras and other digital-imaging
PLL and MDLL Trends
100
FoM
= –2
20 d
Jitter RMS (ps)
applications. The intense adoption
of cell phone cameras led to approximately 90% market penetration in
2009. Currently, 3G mobile technology is accelerating the utilization of
multiple cameras in each cell phone.
Of course, other emerging digitalimaging markets include traditional
digital still cameras (DSCs) and camcorders. But other potentially highvolume markets are emerging: Web
cameras, security cameras, automotive cameras, digital-cinema cameras, and gaming cameras.
For all cameras, the resolution and
miniaturization races are ongoing;
while the performance requirements
remain constant, pixel size continues to scale down. Pixel resolutions
of more than 20 million are commercially available, employing enhanced
small-size pixels. A column-parallel
approach based on pipelined and
multiple-sampling implementations
is emerging for low-power, highspeed, low-noise analog-to-digital
converters (ADCs) for high-resolution
DSC and video applications.
In this race, innovative new technologies are under constant development. These include advanced
sub-100-nm CMOS image-sensor fabrication processes, backside illumination, and wafer-level imaging. Backside
illumination is now a mainstream
technology for mobile imaging. Most
producers rely on bulk silicon rather
than the more expensive SOI approach
for back-side thinning.
The importance of digital-signalprocessing technology in cameras
continues to grow in order to mitigate sensor imperfections and noise
and compensate for optical limitations. The level of sensor computation is increasing to thousands
of operations per pixel, requiring
high-performance and low-power
digital-signal-processing solutions.
In parallel with these efforts, there
is a trend throughout the image sensor industry toward higher levels of
integration, in order to reduce system costs.
High dynamic range (HDR) is now
well established in low-cost con-
10
FoM
= –2
B
30 d
FoM
B
= –2
40 d
1
FoM
B
= –2
50 d
FoM
= –2
B
60 d
0.1
0.1
B
1
10
100
Power (mW)
2012
2011
2010
2009
2008
2007
FIGURE 12: Trends in PLL and MDLL technology.
sumer imaging. High-speed, lowpower, low-noise, column-parallel
ADCs are becoming a key technology for
high-definition video imagers. But many
barriers must be overcome in order to
maintain market growth in the image
sensor industry. These challenges
include better image quality, higher
sensitivity, higher sensor resolution,
lower cost, higher data-transfer rate,
higher system-level integration, lower
power consumption, and “consumerpriced” integrated 3-D imaging. Socalled sensor-plus-companion-chip
solutions are replacing SOCs except
for the most compact camera modules, where back-side imaging is
combined with 3-D integration.
More developers are demonstrating subelectron readout noise
performance for low-light imaging applications. For nonconsumer
low-light-level applications, imager
arrays based on 2-D single-photon-avalanche diodes (SPAD) with
increased resolution and smaller
pixel size are beginning to compete with electron-multiplying CCD
(EMCCD) technology. These deepsubmicron CMOS SPADs are now
capable of meeting the requirements
for high resolution and high timing
accuracy using highly parallel implementations of time-to-digital converters (TDCs) with small pixel pitch
and better fill factor.
Trends in emerging digital camera markets include lower-bandwidth
communication for surveillance
cameras, wider dynamic range and
optical-communication functions for
automotive cameras, faster read-out
for digital-cinema cameras, and 3-D
imaging for gaming. These markets
are placing ever increasing functionality and performance demands on
today’s image sensors, which are in
turn delivering an exponential rate
of growth in both complexity and
performance to ensure that they can
keep pace.
One very hot R&D topic is 3-D
imagers, given the current push
toward 3-D entertainment, security, and automotive applications.
Rapid increases in integrated logic
functionality are driving a dramatic
increase in imager functions and
features. Such possibilities include
merging 2-D with 3-D imaging by
interlacing 3-D time-of-flight pixels
with a standard RGGB pixel architecture as a path toward simultaneous
color and depth imaging.
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The market share for CCDs continues to shrink in machine vision,
compact DSC, and security applications. Only within top-end broadcast and top-end digital cameras
do CCDs still maintain a significant
market share.
Sensors and MEMS
CMOS temperature sensors continue
to improve, reaching higher temperatures (200 8C), with finer resolution
(100µ 8C/!Hz), in shorter conversion times (10 µs), with simpler calibration (using voltage rather than
temperature), and using smaller die
sizes (0.006 mm2).
New technologies for temperature sensors are maturing; in particular, thermal diffusivity is proving to
be a valuable sensing phenomenon,
reaching both high temperatures
and good accuracy. Small-area, highspeed temperature sensors in highly
scaled 22-nm CMOS technology will
be important for microprocessors
so as to limit die temperatures to
safe values.
MEMS oscillators are improving.
Phase noise is now low enough for
demanding RF applications; 12-kHz–
20-MHz jitter is now below 1 ps; and
frequency accuracy is now better
than 0.5 ppm. MEMS microphones,
accelerometers, and pressure sensors continue to improve as they
become common in consumer and
automotive applications.
Biomedical
There is an increasing interest in
neural applications, with significant
R&D activity in the field of biopotential sensors for neural recording and stimulation. Such activity
includes the following trends:
■ Closed-loop systems are being
commercialized: a closed-loop, acceleration-sensor-enabled neurostimulation device is CE-marked
in Europe, and a closed-loop epilepsy device has completed clinical trials. The latter is a major innovation that leverages the latest
sensor and circuit technology for
neural interfacing, allowing for
Bit Cell Trend
1.4
1.4
90, 1.2
65, 1.2
1.2
1.2
90, 1
90, 1
28, 1
65, 1
1
90, 0.999
Bit Cell Size (µm2)
20, 0.95
1
20, 0.85
0.8
40, 0.9
0.8
28, 0.85
65, 0.57
0.6
0.6
65, 0.525
0.4
0.4
45, 0.346
0.2
40, 0.242
32, 0.171
28, 0.127
0.2
20, 0.081
22, 0.092
0
90
65
45
40
32
28
22
Technology Node (nm)
Intel Cell
TSMC Cell
VDD_LP
FIGURE 13: Trends for SRAM bit cells.
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0
20
VDD_LP, VDD_G (V)
40, 1.1
novel diagnostics based on chronic recording.
■ Brain-machine interface systems
are now transferring into pilot
clinical trials, although there continues to be some debate about
“best methods.” While acute human testing shows that only a low
degree of freedom is needed to
control robotic arms in paralyzed
patients, methods are being extended for a broader range of neural applications.
■ Continuing efforts are enabling
high-spatial-resolution, multichannel neural stimulators (such as
those for retinal stimulation) and
stimulators with recorders (such
as those used in brain research).
For example, a retinal implant with
60 pixels has received a CE mark,
a step forward in the design of a
sophisticated prosthesis. Work to
increase complexity by another order of magnitude is ongoing.
The demand for telemedicine, remote
sensing, and economical design is
expanding as the population ages
and cost pressures increase. These
pressures are growing significantly
with health care reform; the economic value of technical solutions
is now being considered along with
safety and efficacy.
Silicon technology is enabling
new paradigms for biological signal
processing. Examples include:
■ Along with 32-bit processing cores,
0.13-µm foundry-based CMOS
technology is stabilizing as a lowpower process for biomedical purposes. The partitioning of signal
processing between the analog and
digital domains is still being debated, with both modalities reaching
levels that allow for chronic monitoring with minimal energy drain.
■ Silicon-based arrays are emerging
for analyzing genomes and immunoassays. Multiple paradigms
are being explored to eliminate the
need for expensive optical components. It is being proposed not
only to perform hybridization assays on-chip but to allow direct
DNA sequencing as well.
Displays
SRAM
Single-chip sensing and driving
for touch-integrated liquid-crystal
display (LCD) panels is one of the
display-technology trends for much
thinner and lower-cost realizations.
Advanced 3-D LCD TV technologies
are opening up a new era of 3-D home
theater. The current focus is on how
to make more realistic views that are
comfortable to the eye. Technologies for 3-D realization that do not
require glasses and their driving
electronics are emerging for mobile
and notebook applications.
Embedded SRAM continues to be
an important element in a wide
range of very large scale integration (VLSI) applications, from
high-performance processors to
handheld devices. Historically, the
SRAM bit cell has followed Moore’s
law, shrinking in area by about
50% with each new generation, as
shown in Figure 13. This reduction
has enabled designers to put more
SRAM bits on each die, improving
performance. Another key performance metric for SRAM design is the
lowest reliable operating voltage. A
low value lets memory blocks operate reliably with the same (or better)
power envelope, as compared with
the previous generation. As the transistor feature size marches below
20 nm, device variation has made it
very difficult to shrink the bit-cell
area at the 50 % rate while maintaining or lowering VCCmin between
generations. Starting at 45 nm, the
introduction of high-K metal gates
has reduced the Vt mismatch and
enabled further device scaling by
significantly reducing the equivalent
Memory
100,000
Storage Capacity (Mb)
10,000
Condition 1 Mb
ISSCC, VLSI Circuits, ASSCC
IEDM, VLSI Technology
128 Gb
NAND Flash
8 Gb
1,000
PRAM
128 Mb
FeRAM
100
64 Mb
64 Mb
RRAM
MRAM
10
1
2000
2002
2004
2006
2008
2010
2012
Year
FIGURE 14: Trends in emerging NVM memory capacity.
10,000
Write Bandwidth (MB/s)
Development of mainstream memory
technologies continues unabated.
The major thrust concerns embedded memories, i.e., static randomaccess memory (SRAM), DRAM, and
floating-gate-based flash, for very
broad applications. As processes continue to shrink in an effort to follow
Moore’s law, however, each incumbent technology is encountering
difficulty in maintaining the trend
line. Cells in SRAM, DRAM, and flash
are becoming ever more difficult to
scale. In response to the challenges,
we see logic processes adopting
trigate/3-D devices, along with assist
circuits for SRAM read and write.
Meanwhile, certain emerging memory technologies are making rapid
progress toward product introduction, including phase-change
RAM (PCRAM) and magnetoresistive
RAM (MRAM), while resistance RAM
(ReRAM or RRAM) is gaining ground
for future applications.
Current state-of-the-art results
from ISSCC 2012 include:
■ the first SRAM using FinFETs operating at 4.6 GHz using trigate
devices with assist circuits for
lower VCCmin
■ a density-record-beating 19-nm,
128-Gb TLC NAND flash memory
■ a new DDR4 3.2-Gb/s/pin, 4-Gb,
30-nm SDRAM with PVT-tolerant
data fetch
■ a
high-speed 443-MB/s–write–
throughput, multilayered, crosspoint ReRAM macro.
Condition ≥ 1 Mb
ISSCC, VLSl Circuit
ASSCC 2001–2011
Emerging NVRAMs
FeRAM (ISSCC’09)
1,000
100
eMRAM (ASSCC’07)
MRAM (ASSCC’06)
FeRAM, MRAM
(ISSCC’06)
RRAM (ISSCC’11)
NAND (ISSCC’08)
10
PRAM
(ISSCC’07,’10)
Flash
1
100
r
tte
Be
PRAM (ISSCC’11)
NOR
(ISSCC’07’05)
eNOR (ISSCC’07)
1,000
10,000
Read Bandwith (Mb/s)
FIGURE 15: Trends in read/write bandwidth for NVMs.
IEEE SOLID-STATE CIRCUITS MAGAZINE
W I N T E R 2 0 12
13
als. The emerging NVMs, such as
PCRAM, ferroelectric RAM (FeRAM),
MRAM, and ReRAM, all have excellent read/write and endurance performance, as well as low power
requirements as compared with
flash memory. These new NVMs offer
the potential to open up new markets and applications. Commercial
uses have been very slow to appear
because of the rapid reduction of
per-bit costs of conventional flash
memory technologies already on
the market, as shown in Figure 14.
But the new technologies seem set
to capture some specific markets by
taking advantage of merits such as
high read/write bandwidth (in the
hundreds of megabytes per second),
as shown in Figure 15. This year,
ISSCC 2012 will report on a number of high-density 20-nm and sub20-nm designs.
Memory Density (MB/mm)
100
10
x3/year
1
4b/Cell (16 LC)
3b/Cell (TLC)
2b/Cell (MLC)
1b/Cell (SLC)
0.1
0.01
1994 1996 1998 2000 2002 2004 2006 2008 2010 2012
Year
FIGURE 16: Trends in NAND flash memory.
DDRx Data Rate - DRAM Core Freq Gap
ISSCC 2012
3,200
3,200
Prefetch n = 8 with
Bank interleaving
2,400
2,000
2,133
2.5 V
2.5
n=8
VDD
Data Rate
1,600
1,200
2,400
2.0
1.8 V
n =
1,600
(Data Rate)
1.5 V
1,066
(Core Frequency)
=> (Prefetch Size)
1.2 V
n=4
800
n=2
400
400
200
400
200
0 100
1.0
800
Core Frequency
266
266
100
DDR1
1.5
VDD (V)
Data Rate (Mb/s), Core Frequency (MHz)
NAND Flash Logic
2,800
100
100
DDR2
200
DDR3
DDR4
FIGURE 17: Trends for DRAM and high-speed I/O for DDRx.
oxide thickness. Design solutions
such as read/write assist circuitry
have been used to improve the VCCmin
performance at the memory-macro
level for 32 nm and beyond. New
transistor structures such as FinFET and FD-SOI are emerging as the
replacement for planar devices to
14
W I N T E R 2 0 12
enable further area reduction and
VCCmin scaling of SRAM bit cells.
Nonvolatile Memories
In recent years, technological and
chip development for emerging nonvolatile memories (NVMs) has been
intensified, using advanced materi-
IEEE SOLID-STATE CIRCUITS MAGAZINE
Over the past few years, significant developments in NAND flash
memory have resulted in high-density, low-power, and low-cost storage solutions that are enabling the
replacement of traditional hard disk
drives by solid-state disks (SSDs).
With physical scaling, accompanied
by advancing multilevel storage cell
concepts, a 128-Gb/die capacity is
being demonstrated at ISSCC 2012,
using 19-nm technology with 3-b/
cell operation. Figure 16 shows the
observed trend in NAND flash capacities presented at ISSCC over the past
17 years. As process feature size
shrinks, error rates rise, requiring
system designers to develop moresophisticated controllers to compensate, some of which are utilized
outside the NAND silicon, in the system-memory controller.
DRAM and High-Speed I/O
The gap between on-chip memory
and processor frequencies and
external data rates continues to
increase as conventional high-speed
wired interface schemes [such as
DDRx and graphics DDRx (GDDRx)
for DRAM and NAND flash memory]
GDDRx I/F - DRAM Core FREQ GAP
7,000
6,000
Prefetch n = 8 with
Bank interleaving
2.5 V
2.5
VDD
5,000
Data Rate
1.5 V
4,000
3,000
2.0
1.8 V
(Data Rate)
n=
(Core Frequency)
=> (Prefetch size)
VDD (V)
Date Rate (Mb/s), Core Frequency (MHz)
evolve, as shown in Figures 17 and
18. This leads to the need for a larger
prefetch size, which is emerging as a
major problem in modern memory
systems. Alternatives that accommodate high data rates through the use
of wider or differential interfaces
will, however, face the problems of
increased pin counts and enlarged
silicon areas. Combined with 3-D
integration of memory and memory logic in near-future commercial
products, new interface technologies with more memory stacking will
yield lower-power and higher-bandwidth interfaces. This year, at ISSCC
2012, the first implementations of
new standards of LPDDR3 and DDR4
enabled by through-silicon via (TSV)
technologies for 3-D ICs will be
described.
1.5
n=8
n=4
2,000
n=4
1,000
Core Frequency
2
0
GDDR1
GDDR2
GDDR3
GDDR4
GDDR5
FIGURE 18: Trends in DRAM and high-speed I/O for GDDRx.
Radio Frequency (RF)
On the horizon for RF, there are three
trends that are converging, driven by
their applications. The first concerns
the well-established cellular market, where the demand is focused
on high-mobility terminals providing high data rates, such as LTEdedicated devices. The second trend
addresses the connectivity sector,
where the demand of extremely high
data rates (equal to or above 1 Gb/s)
is essential in devices incorporating several coexisting standards. At
the end of May 2011, a press release
announced the first product on the
market with extended connectivity
features such as dual Wi-Fi, Bluetooth, and 60-GHz WiGig standard
compliance. Finally, the third application-driven trend concerns sensor
networks, where the major features
are low data rates and, above all,
ultralow power (including devices
using self-contained power).
The implementation of all these
product families relies on two technology trends. First of all, transceiver
integration performed either monolithically or using a 3-D heterogeneous scheme pushes toward the
ultimate air interface. Hence, a large
majority of current devices show full
integration up to the antenna(s), as
well as the absence of bulky external
SAW or BAW filters at the RF interface.
Second, there is a consolidating trend
toward using multiradio SOCs in an
increasing majority of products.
In emerging applications, the
most advanced sub-nm CMOS technology has opened some application fields reserved thus far for
III-V electronics. Over the past few
years, more and more academic and
research institutions have investigated fully integrated CMOS ICs for
THz imaging and sensing. Furthermore, carrier frequencies above
100 GHz are well placed for veryhigh-data-rate communications (10–
20 Gb/s), an application formerly
reserved for wireline technology.
ISSCC 2012 is highlighting the
following critical building blocks
addressing these applications.
Cellular Voltage-Controlled
Oscillators (VCOs)
The VCO and its digital counterpart,
the digitally controlled oscillator
(DCO), form a traditional bottleneck
in radio design, where they provide
the RF reference frequency needed
in all transceivers. The key features
of VCOs and DCOs are oscillation
frequency, frequency-tuning range,
spectral purity (usually quoted in
terms of phase noise), and power
consumption. A typical trade-off in
VCO and DCO design involves phase
noise, power consumption, and tuning range. Achieving the phase noise
performance mandated by the 2G,
3G, and 4G cellular radio standards
requires a VCO/DCO power consumption that is often a significant part of
the total power budget, especially if a
large tuning range is needed in order
to cover many bands and standards.
A noticeable trend in VCO and DCO
design is to let them oscillate at a center frequency of approximately 8 GHz
with a sufficiently large tuning range
and to recover cellular frequencies via
frequency division by four or eight.
This is shown in Figure 19, which displays the phase noise at 1 MHz versus
the oscillation frequency of some of the
most significant VCOs and DCOs published in the past five years. It is apparent that the rate at which phase noise
increases with frequency is reduced
thanks to the “free-running” solution,
which also allows for a substantial
improvement of the phase-noise FoM,
demonstrating the noise-power tradeoff, as shown in Figure 20. A second
trend is to design VCOs and DCOs with
a larger tuning range to cover newer
IEEE SOLID-STATE CIRCUITS MAGAZINE
W I N T E R 2 0 12
15
–105
Phase Noise at 1 MHz (dBc/Hz)
–110
CICC’07
CICC’10
ISSCC’06
–115
ESSCIRC’03
ISSCC’08
ISSCC’08
–120
ESSCIRC’05
–125
JSSC’06
JSSC’10
ASSCC’08
ISSCC’10
JSSC’08
JSSC’11
ISSCC’02
–130
–135
ISSCC’12
ISSCC’12
ISSCC’12
JSSC’10
RF Symposium’08
JSSC’09
ISSCC’05
RF Symposium’07
JSSC’06
–140
–145
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
Frequency (GHz)
FIGURE 19: Phase noise at 1-MHz offset frequency versus oscillation frequency.
bands and standards, at the cost of
reduced FoM improvement.
junction transistor CMOS (BiCMOS)
technology. Moving ahead, silicon
millimeter-wave ICs are expected to
mature into fully qualified commercial solutions with ever improving
performance and efficiency.
An emerging research area is
silicon-based submillimeter-wave
or terahertz sources, detectors, and
systems for imaging, radar, and,
potentially, communications. Silicon technology once again allows
reduced cost and high levels of integration, including on-chip antennas.
Trends in Millimeter-Wave
and Terahertz Technology
Silicon millimeter-wave ICs operating at 60–100 GHz continue to be
the subject of very active research.
Specifically, the past seven years
have witnessed a rapid increase
in integration levels, moving from
building blocks to subsystems to
full transceivers to phased arrays on
a chip, all in either CMOS or bipolar
CMOS VCOs have already been demonstrated at 100–500 GHz; wider
tuning ranges and higher output
powers are still needed to realize
useful systems, however. Detectors or
receivers above 100 GHz have been
demonstrated in conventional CMOS
technology, although improved sensitivities are needed to enable highthroughput passive cameras. Finally,
interest in imaging is expected to
drive the development of single-chip
CMOS terahertz cameras with significantly more than 1,000 pixels.
FoM at 20 MHz (dBc/Hz)
200
JSSC’10
ISSCC’08
195
ESSCIRC’05
JSSC’06
JSSC’11
ISSCC’05
ASSCC’08 JSSC’10
185
ISSCC’11
ISSCC’10
RF Symposium’08 ISSCC’08
180
JSSC’09
ISSCC’02
175
ISSCC’12
ISSCC’12
190
ISSCC’12
JSSC’06
JSSC’06
CICCC’07
ISSCC’06
170
CICCC’10
165
0.5
1.5
2.5
3.5
4.5
5.5
6.5
Frequency (GHz)
7.5
FIGURE 20: Phase-noise FoM at 20-MHz offset frequency versus oscillation frequency.
16
W I N T E R 2 0 12
IEEE SOLID-STATE CIRCUITS MAGAZINE
8.5
9.5
10.5
Power Amplifiers (PAs)
Technology Directions (TD)
The role of the Technology Directions Subcommittee is to identify and
encourage developments of potential
importance in the ongoing evolution
of ISSCC. Characteristically, a wide
variety of topics are covered, some
new and some continuing, with success achieved by the transference of
the emerging technique to one of the
evolving mainstream subcommittees.
35
Output Power (dbm)
30
ISSCC’12
ISSCC’12
ISSCC’12
25
20
15
10
5
1.4
1.6
1.8
2
2.2
2.4
Frequency (GHz)
2.6
2.8
3
FIGURE 21: Frequency (GHz) versus output power (dBm) for RF PAs.
70
60
Peak PAE (%)
Since the introduction of CMOS cellular PAs in 2002, continuing efforts
and new design techniques have
improved their performance. While in
the beginning an attempt was made
to deliver enough output power using
2G and 2.5G standards, recently the
focus has shifted to supporting
non-constant-envelope modulations, improving power efficiency,
and supporting more bands with one
PA. All the PAs introduced at ISSCC
2012 target wide-band code division
multiple access (WCDMA), with a
need to support 64QAM; one of them
covers three bands, as shown in
Figures 21 and 22.
With respect to power amplifiers at
millimeter-wave frequencies, the new
trend is toward higher power-added
efficiency (PAE) while maintaining
compliance with process-reliability
concerns. The 77-GHz PA reported
at ISSCC 2012 demonstrates a record
in PAE and a near record in saturated
output power, as shown in Figure 23.
50
ISSCC’12
40
30
ISSCC’12
ISSCC’12
20
10
0
1.4
1.6
1.8
2
2.2
Frequency (GHz)
2.4
2.6
FIGURE 22: Frequency (GHz) versus peak PAE for RF PAs.
Large-Area, Low-Temperature
Electronics
22
A clear breakthrough in research
for large-area electronics in the past
decade has been the development of
thin-film transistor (TFT) processes
with an extremely low temperature
budget. Thanks to the low temperatures required in manufacturing
(<150 8C), these TFTs can be placed
on flexible and inexpensive substrates like plastic films and paper.
The semiconductor materials used
for these developments have for a
long time been carbon-based organic
molecules such as pentacene (a p-type
18
20
ISSCC’12
Peal PAE (%)
16
14
12
10
8
6
4
2
0
8
10
12
14
16
18
Output Power (dBm)
20
22
FIGURE 23: Saturated output power (dBm) versus peak PAE for millimeter-wave PAs.
IEEE SOLID-STATE CIRCUITS MAGAZINE
W I N T E R 2 0 12
17
22
temperature TFTs. Examples include
signage, pressure- and light-sensitive foils, sheets capable of distributing RF power to appliances, and
energy-scavenging devices.
Following this trend, ISSCC 2012
features a flexible pedometer powered by foot motion, a flexible touch
pad based on organic TFTs, an RFID
capable of bidirectional communication using organic and metaloxide TFTs, and an IGZO DAC that
can be used as an integrated column
driver in OLED display backplanes,
as shown in Figures 24 and 25.
cm
2-V Organic
PMOS Circuits
Wireless
Piezoelectric Energy Harvester
(PVDF Sheet)
FIGURE 24: A flexible insole pedometer: a device that counts steps while being powered by
the movement of the foot itself, made with an organic piezoelectric foil (PVDF) coupled to an
organic p-type circuit. (Used with permission from ISSCC.)
semiconductor). More recently, organic
n-type semiconductors and amorphous metal oxides, which are also
n-type semiconductors, have emerged.
Popular metal-oxide semiconductors
are zinc oxide (ZnO) and amorphous
indium–gallium–zinc oxide (IGZO or
GIZO). The mobility of n- and p-type
organic materials has reached values around 1 cm2/Vs, while metal
oxides have surpassed the 10-cm2/Vs
mark. The operational stability of all
semiconductor materials has greatly
improved and should be sufficient to
enable commercial applications, especially in combination with the largearea compatible barrier layers used to
seal the transistor stack.
At the current state of the art,
p-type-only, n-type-only, and complementary technologies are available.
Most TFTs are still manufactured with
subtractive methods based on lithography, but there is a clear emphasis
on the development of additive technologies that could provide higher
production throughput. These are
based on various technologies borrowed from the graphic printing
world, such as gravure, screen printing, and offset.
18
W I N T E R 2 0 12
The technology road map in the
field of large-area and low-temperature electronics thus focuses
on lowering the cost per unit area
instead of increasing the number of
functions per unit area, which is the
focus of monocrystalline Si technology according to Moore’s law.
Traditional applications such as
flexible displays and electronic RFID
tags integrated in the wrapping of retail
goods, together with the improvement of TFT performance, reliability,
and aging stability, have enabled first
prototypes of applications integrating sensors and actuators with low-
FIGURE 25: A touch pad using a capacitive
sensor employing organic p-type transistors.
(Used with permission from ISSCC.)
IEEE SOLID-STATE CIRCUITS MAGAZINE
Data rates for modern wireless
standards are increasing rapidly.
This is evident from cellular standard trends, as shown in Figure 26.
In fact, the data rate has increased
by a factor of 100 over the past
decade, and another increase by a
factor of ten is projected over the
next five years. This trend has been
maintained by using more complex modulation techniques such
as orthogonal-frequency-division
multiplexing (OFDM) for better spectral efficiency but has come at the
cost of increased requirements for
digital signal processing (DSP). In
addition, the expansion of channel
bandwidth is also an effective way
to achieve a data-rate increase. This
can be seen in the wireless-connectivity trend chart (for 802.113) in
Figure 27. It is clear from the figure that channel bandwidth for the
WLAN standards has increased from
the traditional 20 MHz (802.11g) to
40 MHz (802.11n), then to 160 MHz
(802.11ac), and finally to .1 GHz
(802.11ad). Because the available
spectrum is limited in the low-GHz
range, to achieve .1-GHz channel
bandwidth, the carrier frequency
has been moved from 2.4/5 GHz
(802.11a/b/g/n) to 60 GHz (802.11ad)
in the millimeter-wave range.
With the spectrum available in the
60-GHz range, data rates greater than
1 Gb/s can be achieved with modest
modulation. The initial feasibility of
60-GHz CMOS was demonstrated in
Wireline
Wireline continues to be an important application of semiconductor
technology as the need for wired
Wireless Data Rate: Cellular
1G-AMPS-DL
2G-CDMA-DL
3G-EVDO-DL
1G-AMPS-UL
2G-CDMA-UL
3G-EVDO-UL
2G-GSM-DL
2G-GSM-UL
3G-WCDMA-DL 3G-WCDMA-UL
4G-LTE-DL
4G-LTE-UL
1E + 9
1E + 8
b/s
1E + 7
1E + 6
1E + 5
1E + 4
1E + 3
1980
1985
1990
1995
2000
2005
2010
2015
FIGURE 26: Trends in cellular-standards data rates.
Wirelss Data Rate: Connectivity
802.11
802.11g
802.11ac MIMO
802.11b
+ 802.11n SISO
802.11ad - 60 GHz
802.11a
802.11n MIMO
1E + 10
1E + 9
b/s
2009. Then a Silicon Valley start-up,
SiBeam, demonstrated a complete
end-to-end system that supports
a robust wireless link in 60 GHz
and achieves 3.8 Gb/s in 1.76 GHz.
This demonstration ignited more
research and development from both
academia and industry in millimeterwave communication.
An old problem sees a new solution. As wireless applications proliferate, the spectrum is becoming
very crowded because of the many
licensed and unlicensed uses occupying most of the assigned frequency bands. But cognitive radio
is an answer: it promises to identify
and utilize spectral “white space” in
the presence of many other wireless
applications. And so the current
trend for cognitive radio is to design
highly linear transceivers that can
cover a very wide frequency range,
with various channel bandwidths.
As a consequence of these highlinearity wide-band design requirements, distortion-cancellation and
tunable-RF channel-selection techniques are critical. Most transceivers in this category are adopting
digital calibration and analog feedback techniques to increase the
linearity performance for a very
tunable front end so as to cover a
wide range of frequencies.
On another front, wireless sensor
networks (WSNs) require ultralowpower radio to increase the lifetime of the battery—or better still,
to eliminate the battery completely
using energy harvesting. To reduce
the power consumption of the radio,
the first approach is to use the radio
only when it is requested. Wake-up
radio thus becomes one of the main
building blocks of each WSN node.
Once the radio awakens, power efficiency becomes the main target for
both high- and low-data-rate communication. Such WSNs will enable
electronics for sustainability.
1E + 8
1E + 7
1E + 6
1995
2000
2005
2010
2015
FIGURE 27: Trends in the data rates of wireless-connectivity standards (802.11x).
communication flows out from its
long distance origins into smaller
and smaller environments, through
backplanes to inter- and intrachip
connection. A continuing challenge
in this evolution is the adaptation of
techniques that originated on a large
scale to shrinking environments.
High-speed I/O bandwidth needs
are increasing by about a factor of
two each year as the requirements
for data transmission gather momentum, driven by the use of the cloud
and data streaming. Along with the
increase in data rates, such systems
are also rapidly approaching power
limits that constrain the I/O band-
widths. There is also a need for
backward compatibility across the
legacy-interconnect chassis that adds
to the development challenge.
Wireline interconnects using serial
links—once a niche application in
high-speed network routers—are now
used in a wide range of applications,
from high-speed microprocessors to
data converters. To meet integration
requirements, these serial links must
have lower power, even as performance
increases. Hence, a typical FoM considers the energy required per transmit/
receive bit or pJ/bit, which is the ratio of
the power in milliwatts to the data rate
in gigabits per second, or mW/Gb/s.
IEEE SOLID-STATE CIRCUITS MAGAZINE
W I N T E R 2 0 12
19
Power Efficiency (pJ/b)
The past five years have
Summary
2.5
Developments reported at
seen serial-link speeds
90 nm CMOS
ISSCC 2012 continue to presincreasing from 1 Gb/s,
65 nm CMOS
2
45 nm CMOS
ent breakthroughs in the
but a barrier appears to be
32 nm CMOS
broad domain of solid-state
approaching fast. Although
1.5
circuits and systems. In this
limited, specialized 40 Gb/s
rich environment, presentalinks have been developed for
1
tions at ISSCC characteristitelecom applications, and inically predict ways in which
tial 40 Gb/s links have been
0.5
electronics techniques will
demonstrated in the lab; links
64 Mb
fulfill the present and future
able to support a broad set of
0
20
25
5
10
15
needs of society. In this role,
applications at rates above
Data Rate
ISSCC continues to present a
40 Gb/s or able to support 50
road map of things to come,
Gb/s rates at all are conspicu- FIGURE 28: Power efficiency of equalizing receivers. The star
both in the immediate future
ously absent commercially.
represents the low-power equalizer operating at 16 GB/s and
and in the longer term.
Therefore, although the consuming <0.5 pJ/b, as reported at ISSCC 2012.
system challenges require
Acknowledgments
data bandwidth to increase by a faclinks where the equalization is not
The authors wish to acknowledge the
tor of about two each year, existing
as complex, achievable power numcreators of the original material from
technology only allows data rates to
bers are of the order of 1–5 mW/
which this article has been strucincrease by a factor of two every five
Gb/s; state-of-the-art 10-Gb/s links
tured. While this has been largely a
years. At the same time, the need to
typically consume between 10 and
team effort by several members of
support a variety of data channels,
50 mW. For higher data rates (in the
each subcommittee, each has operincluding legacy compatibility, with
range of 25–30 Gb/s), the efficiency
ated under the direction of his or her
a very large number of parallel links
is typically lower because of the
subcommittee chair, as listed below:
means that equalization techniques
additional clock and analog perfor■ Analog: Bill Redman-White, NXP
are essential for robust data transmance requirements imposed by
Semiconductors
mission. Receiver equalization meththe high data rate. The state of the
■ Data Converters: Venu Gopinaods include the “linear” type, for
art at these data rates is therefore in
than, Texas Instruments
boosting the signals for shorter and
the range of 8–10 mW/Gb/s.
■ Energy-Efficient Digital: Tzi-Dar
less complex channels, and “decision
Long-reach links and more
Chiueh, National Chip Implemenfeedback,” for more complex chancomplex channels such as coptation Center
nels with interchannel crosstalk.
per backplanes that include mul■ High-Performance Digital: Stefan
These equalization techniques add
tiple connectors have much higher
Rusu, Intel
to the power consumed by the links,
power consumption and lower effi■ Imagers, MEMS, Medical, and Dishowever.
ciency in terms of mW/Gb/s. This
plays: Roland Thewes, TU Berlin
Figure 28 shows the energy effiyear, ISSCC 2012 is presenting the
■ Memory: Kevin Zhang, Intel
ciency per bit of equalizing receivfirst 28-Gb/s transceiver to address
■ Radio Frequency: Andreia Catheers reported since 2007. The state
medium-reach applications using
lin, STMicroelectronics
of the art is around 0.5 pJ/b for
32-nm SOI and consuming 693 mW
■ Technology Directions: Siva Narequalizers operating at less than
for 35 db of channel loss with an
endra, Tyfone
20 Gb/s. At higher data rates, howFoM of 24.75 mW/Gb/s.
■ Wireless: David Su, Atheros Comever, the energy efficiency is still
These trends in integration,
munications
greater than 1 pJ/b. This year, ISSCC
power consumption, and appli■ Wireline: Daniel Friedman, IBM Thom2012 is presenting best-in-class
cations bring new challenges to
as J. Watson Research Center.
performance in terms of data rate
wireline communications. New techat 16 Gb/s with energy efficiency
niques are required to ensure conAbout the Authors
of less than 0.5 pJ/b, showing the
tinued downscaling of the links, and
Kenneth C. Smith is with the Uniextension of low-power equalizers
improvements in equalization techversity of Toronto in Canada.
to higher data rates.
niques, transmitter design, receiver
Alice Wang is with Texas InstruFor a combined transmitter and
design, and clock distribution are
ments in Dallas, Texas.
receiver channel, the mW/Gb/s
essential. ISSCC 2012 will highlight
Laura C. Fujino is with the UniFoM depends on the target applicamany of the new techniques that
versity of Toronto in Canada.
tion. Today, for short-reach serial
continue to enhance the field.
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IEEE SOLID-STATE CIRCUITS MAGAZINE