The Mont-Blanc approach towards Exascale - Mont

About BSC Computer Science Department
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Origins in UPC Computer Architecture Department
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1985-
Inherited know-how and key personnel
Our mission: To influence the way high-performance
computing systems are built, programmed and used
1991-2000
2000-04
People and teams
Programming
Models
Programming
Models
(26)
Performance
Tools
Performance
Tools
(11)
Accelerators
for HPC
(5)
Grid and
Cluster
Grid and
Cluster
(21)
Autonomic eBusiness
Autonomic eBusiness
(14)
Storage
Systems
Storage
Systems
(11)
Extreme
Computing
Computer
Architecture
Application
Optimization
Directors
Team leaders
Researchers
Associate (UPC)
Heterogenous
Architectures
Heterogenous
Architectures
(17)
OS/CA
Interface
OS/CA
Interface
(21)
OS/PM
Interface
OS/PM
Interface
(26)
Network
Architectures
Network
Architectures
100
75
50
25
Students
0
Support
2005 (28)
2006 (69)
2007 (82)
(3)
2008 (130)
2009 (138)
2010 (162)
2011 (159)
(2)
Department funding sources
6.000.000
5.000.000
4.000.000
Contracts
EU funding
3.000.000
National
Personnel
2.000.000
1.000.000
0
2006
2007
2008
2009
2010
2011
EU projects
HOPSA-EU
OPTIMIS
Red Iberoamericana
de Supercomputación
6.000.000
5.000.000
4.000.000
3.000.000
2.000.000
1.000.000
0
Total: 10.76 M€
Average: 1.8 M€
Current (2012): 2.9 M€
2006
2007
2008
2009
2010
2011
http://www.montblanc-project.eu
The next generation
supercomputer
Alex Ramirez
Barcelona Supercomputing Center
Disclaimer: Not only I speak for myself ... All references to unavailable products are speculative, taken from web sources.
There is no commitment from ARM, Samsung, TI, Nvidia, Bull, or others, implied.
This project and the research leading to these results has received funding from the European Community's Seventh Framework Programme [FP7/2007-2013] under grant agreement n° 288777.
Project goals
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To develop an European Exascale approach
Based on embedded power-efficient technology
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Objetives
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Develop a first prototype system, limited by available technology
Design a Next Generation system, to overcome the limitations
Develop a set of Exascale applications targeting the new system
Outline
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A bit of history
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Supercomputers from mobile components
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Vector supercomputers
Commodity supercomputers
The next step in the commodity chain
Killer mobile examples
Mont-Blanc architecture strawman
Rely on OmpSs to handle the challenges
BSC prototype roadmap
Mont-Blanc project goals and milestones
In the beginning ... there were only supercomputers
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Built to order
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Very few of them
Special purpose hardware
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Very expensive
Control Data, Convex, ...
Cray-1
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1975, 160 MFLOPS
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80 units, 5-8 M$
Cray X-MP
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1982, 800 MFLOPS
Cray-2
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1985, 1.9 GFLOPS
Cray Y-MP
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1988, 2.6 GFLOPS
Fortran+vectorizing compilers
10
The Killer Microprocessors
10.000
MFLOPS
Cray-1, Cray-C90
NEC SX4, SX5
1000
Alpha AV4, EV5
Intel Pentium
100
IBM P2SC
HP PA8200
10
1974
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1984
1989
1994
1999
Microprocessors killed the Vector supercomputers
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1979
They were not faster ...
... but they were significantly cheaper and greener
Need 10 microprocessors to achieve the performance of 1 Vector
CPU
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SIMD vs. MIMD programming paradigms
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Then, commodity took over special purpose
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ASCI Red, Sandia
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1997, 1 TFLOPS (Linpack),
9298 cores @ 200 Mhz
1.2 Tbytes
Intel Pentium Pro
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Upgraded to Pentium II Xeon,
1999, 3.1 Tflops
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MareNostrum, BSC
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2004, 20 TFLOPS
IBM PowerPC 970 FX
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Blade enclosure
Myrinet + 1 GbE network
SuSe Linux
Message-Passing Programming Models
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The next step in the commodity chain
HPC
Servers
Desktop
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Mobile
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Total cores in Jun'12 Top500
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13.5 Mcores
Tablets sold in Q4 2011
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27 Mtablets
Smartphones sold Q4 2011
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> 100 Mphones
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ARM Processor improvements in DP FLOPS
IBM Intel
BG/Q AVX
16
ARMv8
DP ops/cycle
8
Intel
SSE2
4
IBM
BG/P
2
ARM
CortexTM-A9
1
1999
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2001
2003
2005
2007
2009
2011
2013
2015
IBM BG/Q and Intel AVX implement DP in 256-bit SIMD
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ARM
CortexTM-A15
8 DP ops / cycle
ARM quickly moved from optional floating-point to state-of-the-art
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ARMv8 ISA introduces DP in the NEON instruction set (128-bit SIMD)
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Integrated ARM GPU performance
Performance
Skrymir
Mali-T658
High-end solution + compute capability
Scalable to 8 cores, ARMv8 compatible
272 GFLOPS*
Mali-T604
First Midgard architecture product
Scalable to 4 cores
68 GFLOPS*
2012
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2013
2014
GPU compute performance increases faster than
Moore’s Law
* Data from web sources, not an ARM commitment
Are the “Killer Mobiles™" coming?
Cost (log10)
Server ($1500)
Desktop ($150)
HPC-Mobile ($40) ?
Mobile ($20)
Nowadays
Near future
Performance (log2)
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Where is the sweet spot? Maybe in the low-end ...
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Today ~ 1:8 ratio in performance, 1:100 ratio in cost
Tomorrow ~ 1:2 ratio in performance, still 1:100 in cost ?
The same reason why microprocessors killed supercomputers
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Not so much performance ... but much lower cost, and power
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Samsung Exynos 5 Dual Superphone SoC
• 32nm HKMG
• Dual-core ARM Cortex-A15 @ 1.7 GHz
• Quad-core ARM Mali T604
• OpenCL 1.1
• Dual-channel DDR3
• USB 3.0 to 1 GbE bridge
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All in a low-power mobile socket
High density packaging architecture
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Standard BullX blade
enclosure
Multiple compute nodes per
blade
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Additional level of
interconnect, on-blade
network
There is no free lunch
2X more nodes for
the same
performance
½ on-chip memory /
core
8X more address
spaces
1 GbE inter-chip
communication
OmpSs runtime layer manages architecture complexity
P0
P1
P2
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Programmer exposed a simple
architecture
Task graph provides
lookahead
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Automatically handle all of the
architecture challenges
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No overlap
Overlap
Exploit knowledge about the
future
Strong scalability
Multiple address spaces
Low cache size
Low interconnect bandwidth
Enjoy the positive aspects
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Energy efficiency
Low cost
BSC ARM-based prototype roadmap
GFLOPS / W
Pedraforca:
ARM + GPU
Tibidabo:
ARM multicore
2011
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Integrated
ARM + GPU
2012
2013
2014
Prototypes are critical to accelerate software development
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System software stack + applications
Very high expectations ...
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High media impact of ARM-based HPC
Scientific, HPC, general press quote MontBlanc objectives
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Highlighted by Eric Schmidt, Google Executive
Chairman, at the EC's Innovation Convention
The hype curve
Peak of Inflated Expectations
Y1
Visibility
Plateau of Productivity
Y3
Slope of Enlightenment
Trough of Disillusionment
Technology Trigger
Time
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We'll see how deep it gets on the way down ...
Conclusions
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Mont-Blanc architecture is shaping up
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ARM multicore + integrated OpenCL accelerator
Ethernet NIC
High density packaging
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OmpSs programming model port to OpenCL
Applications being ported to tasking model
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Stay tuned!
www.montblanc-project.eu
MontBlancEU
@MontBlanc_EU