ÿþþ ÿ PC 5 - FC 4 - 1 H ardware M anual

PCIx-FC4-1
Hardware Manual
Fibre Channel Simulator/Analyzer Interface Test Module
for PCI-X
October 2012
V01.00 Rev. B
3703 N. 200th Street,
Omaha, NE 68022
Tel: 866.246.1553
402.763.9644
Fax: 402.763.9645
aviftech.com
[email protected]
PCIx-FC4-1
Hardware Manual
Fibre Channel Simulator/Analyzer Interface Test Module for PCI-X
V01.00 Rev. B
October 2012
I
PC5-FC4-1 Hardware Manual
Table of Contents
....................................................................................................1
Section 1 INTRODUCTION
1.1 General .................................................................................................................... 1
1.2 How This Manual
....................................................................................................................
1
is Organized
1.3 Applicable....................................................................................................................
2
Documents
1.3.1 Industry Documents
...................................................................................................... 2
1.3.2 AIT Documents...................................................................................................... 2
1.3.3 Fibre Channel Related
......................................................................................................
Books
2
....................................................................................................3
Section 2 INSTALLATION
INSTRUCTIONS
Section 3 STRUCTURE ....................................................................................................4
3.1 PCI Express
....................................................................................................................
5
Connector
3.2 Power Supply
....................................................................................................................
5
Circuitry
3.3 Triggers .................................................................................................................... 5
3.4 IRIG
.................................................................................................................... 6
3.5 Port Bypass
.................................................................................................................... 6
3.6 RAM
.................................................................................................................... 6
3.7 FPGA
.................................................................................................................... 6
....................................................................................................7
Section 4 EXTERNAL INTERFACES
4.1 Front Panel
....................................................................................................................
7
LEDs
4.2 SFP Fibre....................................................................................................................
8
Channel Interface
4.3 I/O Interfaces
....................................................................................................................
8
for Timing and Triggers
....................................................................................................9
Section 5 BOARD LOGIC
DESCRIPTION
5.1 IRIG Decoding/Generating
.................................................................................................................... 9
5.2 PCI Interface
.................................................................................................................... 11
5.3 Port Logic.................................................................................................................... 11
PC5-FC4-1 Hardware Manual
II
5.3.1 SERDES Interface
...................................................................................................... 11
5.3.2 Analyzer
...................................................................................................... 11
5.3.3 Generator
...................................................................................................... 12
5.3.4 Media Access......................................................................................................
Controller (MAC)
12
Section 6 TECHNICAL ....................................................................................................14
DATA
Section 7 NOTES
....................................................................................................16
7.1 Abbreviations
....................................................................................................................
16
and Acronyms
III
PC5-FC4-1 Hardware Manual
1
INTRODUCTION
1.1
General
DOCUMENT HISTORY
Version
Cover Date
V01.00 Rev. A
April 2012
V01.00 Rev. B
Created by
Description
Drake Dingeman Creation of document
October 2012 Drake Dingeman Technical Updates
This document comprises the user's manual for the AIT PCI Fibre Channel Test & Simulation
module, the PCIx-FC4. A general description of the hardware architecture is provided along
with technical data, including pin-outs and installation instructions, for the hardware module.
Instructions for the installation of the associated software drivers and applications can be
found in the Fibre Channel Software Development Kit (SDK) Getting Started Manual.
The PCIx-FC4-1 module is a member of AIT’s family of high performance, intelligent Fibre
Channel interface modules that offer full function testing, data generation/simulation, and
monitor/analyzer functions. The PCIx-FC4-1 modules have been developed to operate inline or as a Node in Point-to-Point, Switched Fabric, and Arbitrated Loop topologies. The
PCIx-FC4-1 offers on-board data processing, scalable memory resources, IRIG decoder/
generator, and high speed protocol decoding.
1.2
How This Manual is Organized
This hardware manual is comprised of the following sections:
Section 1, INTRODUCTION, contains an overview of this manual.
Section 2, STRUCTURE OF THE PCIx-FC4, describes the main components
and logic functionality.
Section 3, EXTERNAL INTERFACES, describes the faceplate I/O status and
connectors, including pin out description.
Section 4, BOARD LOGIC DESCRIPTION, provides a high level overview of
the board functionality and logic interfaces.
Section 5, TECHNICAL DATA, provides technical specifications of the PCIx-FC4
.
Section 6, NOTES, contains a list of product-specific abbreviations and acronyms.
PC5-FC4-1 Hardware Manual
1
1.3
Applicable Documents
The following documents shall be considered to be a part of this document to the extent that
they referenced herein. In the event of conflict between the documents referenced and the
contents of this document, the contents of this document shall have precedence.
1.3.1
Industry Documents
The following American National Standards Institute (ANSI) Fibre Channel specifications
were used to develop the APG-FC4 module design.
FC Arbitrated Loop, ANSI X3.272:1996
Fibre Channel Framing and Signaling Interface, ANSI/INCITS 373:2003
Fibre Channel Framing and Signaling-2, T11/05-190v3 draft
FC Generic Services, ANSI X3.288:1996
Fibre Channel 2nd Generation Generic Services, ANSI NCITS 288
Fibre Channel - Switch Fabric – 2, ANSI/NCITS 355-2001
PCI 3.0
XMC PCI Express Protocol Layer Standard ANSI/VITA 42.3-2006
1.3.2
AIT Documents
AIT has developed documents that may aid the user with other aspects of the PCIx-FC4
Fibre Channel module. These documents and a summary of their contents are listed below:
FC SDK Getting Started Manual, assists the first-time users of the AIT PCIxFC4 boards and fcXplorer Graphical User Interface (GUI) with software installation,
hardware installation, and starting a sample host application project.
fcXplorer Users Manual, provides definition and step-by-step instructions on how
to use fcXplorer, the Fibre Channel Simulator and Analyzer test software for
Windows. fcXplorer provides a GUI to setup and control the PCIx-FC4.
1.3.3
Fibre Channel Related Books
Fibre Channel; A Comprehensive Introduction, Robert W. Kembel, Northwest
Learning Associates, 3061 N. Willow Creek Drive, Tucson, AZ 85712. See www.
nlabooks.com.
The Fibre Channel Consultant: Arbitrated Loop, Robert W. Kembel, Northwest
Learning Associates, 3061 N. Willow Creek Drive, Tucson, AZ 85712. See www.
nlabooks.com.
The Fibre Channel Consultant: Fibre Channel Switched Fabric, Robert W. Kembel,
Northwest Learning Associates, 3061 N. Willow Creek Drive, Tucson, AZ 85712.
See www.nlabooks.com.
2
PC5-FC4-1 Hardware Manual
2
INSTALLATION INSTRUCTIONS
The PCIx-FC4-1 features full PCI Plug-and Play capability. There are no jumpers or
switches on the board which have to be modified by the user.
Note: We recommend that you use a wrist strap for any installations. If there is no
wrist wrap available, then touch a metal plate on your system to ground yourself and
discharge any static electricity during the installation work.
The following instructions describe how to install the PCIx-FC4-1. Follow the instructions
carefully to avoid any damage on the device.
1.
Shut down your system and all peripheral devices. Unplug the power cord
from the wall outlet. (Inserting or removing modules with power applied may
result in damage to the module devices.)
2.
Remove any chassis panel covers necessary to gain access to a PCI slot.
3.
Place the PCIx-FC4-1 module into an open slot in your chassis.
4.
Screw the PCIx-FC4-1 module into the top rail with the a screw at the top of
the faceplate bracket.
5.
Replace chassis panel covers removed in Step 2.
6.
Connect system with power source and turn on the power to your system.
PC5-FC4-1 Hardware Manual
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3
STRUCTURE
The PCIx-FC4-1 module architecture consists of the following main components as
described in the following sections:
FPGA
RAM
Port Bypass
IRIG
Triggers
Power Supply Circuitry
PCI Edge Connector
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PC5-FC4-1 Hardware Manual
Figure 3 - PCIx-FC4-1 Board Architecture
3.1
PCI Express Connector
Connection back to a host processor is via the PCI edge connector. The PCIx-FC4-1 utilizes
64 bit / 133MHz PCI interface.
3.2
Power Supply Circuitry
Power is supplied from the 3.3V and 5.0V pins of the PCI connector.
3.3
Triggers
The external trigger interface allows for inter-board synchronization of analyzer triggers, and is
capable of generating a LVTTL output signal to trigger other equipment when specified data
is received.
PC5-FC4-1 Hardware Manual
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3.4
IRIG
Both an IRIG-B encoder and decoder are included on the PCIx-FC4-1 card.
3.5
Port Bypass
The PCIx-FC4-1 provides a bypass for incoming data, so that data coming in one port may
be repeated out the second port. This adds a small latency but restores the transmitted signal
quality.
3.6
RAM
Each port on the PCIx-FC4-1 has a RAM dedicated for its own transmit and receive data.
3.7
FPGA
The FPGA on the PCIx-FC4-1 contains the port logic for both Fibre Channel ports and glue
logic for connecting together the board components.
6
PC5-FC4-1 Hardware Manual
4
EXTERNAL INTERFACES
The PCIx-FC4-1 faceplate provides external interfaces for the following:
Status LEDs
Dual SFP Fibre Channel interface
I/O Interface for triggers and IRIG-B
Figure 4 - XMC-FC Front Panel Diagram
4.1
Front Panel LEDs
Each port has two status LEDs located on the faceplate adjacent to its corresponding SFP
socket, Port 0 and Port 1.
LOSS OF SIGNAL – Red LED at low intensity
Indicates the port is NOT receiving a usable signal level
LINK ERROR – Red LED at high intensity
Indicates Link error (invalid transmission word, etc.)
LINK ACTIVE – Blue LED at low intensity
Indicates success of the initialization of the port sequence for either
Point-to-point (N_Port) or Arbitrated Loop Topology (L_Port).
Tx/Rx FRAME – Blue LED at high intensity
Indicates the port is transmitting or receiving frames.
PC5-FC4-1 Hardware Manual
7
4.2
SFP Fibre Channel Interface
The PCIx-FC4-1 module utilizes two Small Form-factor Pluggable (SFP) sockets (Port 0
and Port 1) located on the front panel. These sockets accept either wire (copper) or fiber
transceivers. The optical transceivers provided with the board employ modular LC™
connectors and are powered by a single 3.3 V power source supplied by the board. The
copper transceivers are available in a variety of connectors.
4.3
I/O Interfaces for Timing and Triggers
Each PCIx-FC4-1 board contains an I/O connector on the faceplate for timing and trigger
interfaces. The PCIx-FC4-1 I/O interface connector is a Micro D 15 pin male connector. All
IRIG and trigger inputs/outputs are routed through this connector.
Table 4.3 - PCIx-FC4-1 I/O Pin Out
Pin No.
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PC5-FC4-1 Hardware Manual
Signal
1
GND
2
Reserved
3
trig_out_port1
4
IRIG GND
5
IRIG out
6
trig_in_port1
7
Reserved
8
GND
9
Reserved
10
Reserved
11
IRIG_50
12
IRIG in
13
fp_trig_io0
14
trig_out_port0
15
Reserved
5
BOARD LOGIC DESCRIPTION
The FPGA provides the foundation that allows Port 0 and Port 1 to work simultaneously or
independently in Point-to-point, Switched Fabric and Arbitrated Loop topologies. The
structure of each port supports the operating scenarios for simulating, generating, analyzing
and corrupting the Fibre Channel data streams. As shown in Figures 5.1 and 5.2 and
discussed in the following sections, the main components providing the board functionality are
as follows:
IRIG Decoding/Generating
PCI Interface
Port Logic
SERDES Interface
Analyzer
Generator
Media Access Controller (MAC)
5.1
IRIG Decoding/Generating
The FPGA internal clock decodes and generates the IRIG for applications requiring time
stamping and re-clocking the data. The IRIG decoder provides time synchronization with an
external IRIG source. The IRIG generator provides a synchronization source for multiple
boards in a system. When used without an external IRIG source, the user can initialize the
internal clock using a host clock or manually entering a start time. Once initialized, the internal
clock is independent of the host clock. The internal or external IRIG provides precision time
stamping for all captured data in the monitor log.
NOTE: IRIG is implemented with time code B modulated carrier only. (IRIGB122)
The method of connection of the IRIG signal to the receiver is important. Since IRIG timing is
determined by zero crossings of the IRIG signal, noise can affect accuracy.
PC5-FC4-1 Hardware Manual
9
Figure 5.1 - IRIG Signals
The IRIG input signal should be connected with coaxial cable. The shield of the cable should
be connected to the IRIG_GND pin on the MicroD connector, and nothing else. This will
minimize noise from the internal digital circuits as well as common mode noise on the cable. If
5000 ohm input impedance is desired, then use the IRIG_IN pin for the center conductor on
the coax. If 50 ohm input impedance is desired, then use the IRIG_50 pin for the center
conductor on the coax. In either case, the coax should be terminated with its characteristic
impedance at the receiver end of the cable.
The signal range for the IRIG input is 250mv p-p to 10 volts p-p. The higher the signal, the
less affect noise has on it. Below 250mv p-p, the circuit will automatically squelch the input.
Above 10 volts, the signal distortion (clipping) will occur and may cause timing errors. Also,
when using the 50 ohm terminated input, the power is limited to 0.2 watts which limits the
highest voltage to 3 volts RMS (9 volts p-p with sine wave).
IRIG output is a 5 volt p-p sine wave signal with a modulation of 1:3 (5 volts p-p and 1.67
volts p-p) when no load is presented. With a 50 ohm load this voltage is half these values.
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PC5-FC4-1 Hardware Manual
5.2
PCI Interface
The PCI Interface embedded in the bridge and FPGA chip provides Direct Memory
Addressing (DMA) capability to the module. The DMA controls the transmit data to the
module and stores the received data from the module. This is a 32bit / 66MHz interface.
5.3
Port Logic
The FPGA defined Fibre Channel ports are identical. Each port has a user configurable data
storage RAMs. The ports are structured with an analyzer, generator and Fibre Channel
Media Access Controller (MAC) embedded in the firmware. Additional port logic exists to
multiplex data between the ports, allowing them to work together or independently.
5.3.1
SERDES Interface
The SERDES interface handles the 8B/10B encoding and decoding, as well as controlling the
input multiplexing. Each port can be configured to feed the ports transmit or receive data, or
the opposing port’s transmit or receive data into the analyzer, MAC, and generator. The API
exposes these multiplexer configurations as a variety of inline and point-to-point topologies for
the user to select.
5.3.2
Analyzer
Each port’s analyzer has the capability to capture and synchronize raw data, including errors,
across multiple streams. All data, including headers and payload, may be accessed and
become criteria for triggering and filtering. The functional components of the analyzer include:
Trigger Modules - Trigger modules perform initial data qualification, finding
various user-programmed and predefined events in the data stream. The
trigger modules are programmable using API function calls to output trigger
events on:
Data patterns within frames
Specific ordered sets or data words
Elapsing time periods
Error conditions
Counted occurrences of any of the other trigger modules
Trigger Sequencers - Trigger sequencers feed off of the trigger modules,
allowing complex multi-level triggering for analyzing data. The trigger
sequencers allow multi-level conditional triggering logic for the system. Trigger
sequencers can be programmed to control the start and stop of the timer and
counter trigger modules. Using the output of the trigger modules, the
sequencers generate the following four trigger events:
Internal trigger to mark a specific event in the capture buffer.
FIFO sequencer tags a variety of frames and events for
PC5-FC4-1 Hardware Manual
11
simulation control.
External trigger drives the external trigger output for a port.
A generator trigger gates generator events.
Filter Module - The filter module also feeds off of the trigger modules, so
users can filter out or only store programmed frames and ordered sets. The
filter module sets a default policy that either stores or drops everything.
Individual ordered sets and frame trigger modules can be set to match or
invert this policy for a given event. This allows the user to store or filter the
defined data.
Storage Module - The storage module captures data to the port’s RAM.
The data capture parameters define how much data to store before the trigger
position and the allocation of the port RAM for the capture. The internal
trigger sequencer controls the trigger position occurrence for this module.
5.3.3
Generator
Each port generator has the capability to generate or corrupt data on the output. The user is
provided with the controls to generate random, incrementing, decrementing or custom defined
data on the output, program frame sequence gaps, and perform timing and data disparity
calculations. CRC generation, disparity calculation and fill word injection between frames are
handled by the generator, but can be turned off on a frame-by-frame basis. User defined data
can trigger error injection in the headers or payload.
The Generator uses the Media Access Controller (MAC) for flow control or can be
programmed to transmit user defined data, including error injection and data corruption. The
functional components/capabilities of the Generator include:
DMA Chaining Controller - The DMA controls the input of data into the
generator. These controllers have four priority transmit channels. Each
transmit channel data stream can be programmed for delays or pauses to wait
for generator sequencer events allowing lower priority channels to transmit.
Payload Replacement - The generator allows frame content to be modified
during transmission. This enables single transmit frames to be sent
continuously with new or defined data values (such as OX_ID or S_ID).
These transmitted frames can be cached for subsequent frames. Incrementing
and random data generators are available for replacing general purpose
registers and payload information.
5.3.4
Media Access Controller (MAC)
The Media Access Controller (MAC) manages the flow control of the data buffers for the
generator. The MAC tells the generator when data may be sent and what primitive to send in
FC applications. When interfacing with off-the-shelf FC devices, the MAC manages the
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PC5-FC4-1 Hardware Manual
BB_credit for the user’s simulation. The functional capabilities of the MAC include:
Flow Control - The generator works with the MAC to send frames based on
the number of BB_Credits currently granted to the port.
N_Port/L_Port Initialization - In coordination with the MAC, the generator
can insert the proper N_Port/L_Port primitives into the transmit data stream
to initialize the link in either N_Port or L_Port mode.
PC5-FC4-1 Hardware Manual
13
6
TECHNICAL DATA
PCI bus:
Data path
Standard:
Memory:
Time Tagging:
IRIG Input:
Resolution:
Width:
Signal Type:
Signal Waveform:
Modulation Ration:
Input Amplitude:
Input Impedance:
Coupling:
Time Jitter:
IRIG Output
Signal Type:
Input Amplitude:
Receiver Type:
Receiver Supply:
Trigger Outputs:
:
Front Panel
Connectors:
Dimensions:
14
PC5-FC4-1 Hardware Manual
250mv p-p to 10 volts p-p
5K Ohms
AC Coupled
+/-5nS (typical, module to module)
depending on input signal quality
Lock Time:
1 to 5 seconds depending on input signal
quality
Signal Type:
Single ended analog
Signal Waveform:
Amplitude modulated sine wave
Modulation Waveform: 3:1
5 volts p-p +/- 10% no load
Output Amplitude:
Output Impedance:
Trigger Inputs:
64 bits
3.3V I/O ONLY (NOT 5volt tolerant)
PCI 3.0
2 GB
46 bit time tag;
IRIG-B format with nanoseconds between
seconds
1uS
14 BCD digits (400 days)
Single ended analog
Amplitude modulated sine wave or square
wave
3:1 to 6:1
Signal Type:
Output Amplitude:
Output Impedance:
Driver Type:
Receiver Supply:
2.5 volts p-p +/- 10% 50 ohm load
50 ohms
Signal Type CMOS/TTL
2.5 to 3 Volts;
1.5 Volt threshold
Fairchild 74LVC1T45
3.3 Volts
CMOS/TTL
0 to 3.3 Volts (no load)
25 ohms
Fairchild 74LVC1T45
3.3 Volts
Two SFP sockets
Micro D 15-pin male for I/O IRIG and
Trigger
PCI short card
106.7 x 170 mm
Weight:
Supply Voltage:
0.51 lbs.
Uses PCI 3.3V and 5.0V
Power
Idle 5V:
Operating max 5V:
3.3V:
7.35W
10.2W
2.7W
Temperature:
Standard Operating:
Storage:
0 to +60° C
-40 to +85° C
5 to 95% (non-condensing)
Humidity:
PC5-FC4-1 Hardware Manual
15
7
NOTES
7.1
Abbreviations and Acronyms
AIT
ANSI
API
ASM
BB
BCD
BIP
BIU
BSP
CMOS
CRC
CVT
DDR
DIMM
DMA
DRAM
EDO
FC1
FC2
FC4
FLASH
FPGA
Gb
GB
Gbps
GUI
I/O
INPUT_N
INPUT_P
IRIG
LED
LVTTL
MAC
MIL-STD
MUX
NCITS
OUT_N
OUT_P
PCI
PCIe
cPCIe
16
Avionics Interface Technologies
American National Standards Institute
Application programming interface
Anonymous Subscriber Messaging
Buffer-to-Buffer
Binary Coded Decimal
Bus Interface Processor
Bus Interface Unit
Board Support Package (Software)
Complimentary Metal Oxide Semiconductor
Cyclical Redundancy Check
Current Value Table
Double Data Rate
Dual Inline Memory Module
Direct Memory Addressing
Dynamic Random Access Memory
Enhanced Data Output
Fibre Channel FC-1 Level
Fibre Channel FC-2 Level
Fibre Channel FC-4 Level
Page-oriented electrical erasable and programmable Gate Array
Field Programmable Gate Array
Gigabit
Gigabyte
Gigabits per second
Graphical User Interface
Input/Output
Input Negative
Input Positive
Inter Range Instrumentation Group
Light-Emitting Diode
Low Voltage Transistor-Transistor Logic
Media Access Controller
Military Standard
Multiplex
InterNational Committee for Information Technology Standard
Output Negative
Output Positive
Peripheral Component Interconnect
Peripheral Component Interconnect Express
Compact Peripheral Component Interconnect Express
PC5-FC4-1 Hardware Manual
PCIMG
p-p
PPC
ppm
RAM
RISC
SDK
SDRAM
SFP
SRAM
Vdd
PCI Industrial Computer Manufacturers Group
Peak to Peak
PowerPC
parts per million
Random Access Memory
Reduced Instruction Set Computer
AIT Software Development Kit
Synchronous Dynamic Random Access Memory
Small Form Factor Pluggable
Static Random Access Memory
Voltage to drain
PC5-FC4-1 Hardware Manual
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