IEEE 1687 comparison with 1149.1-2013

About the presenter:
CJ Clark is the CEO of Intellitech Corp.
Prior: ITT Defense, Plantronics/Wilcom, Airex
IEEE Standards Medallion 2013 Award - Dec 2013
For vision, leadership and exceptional dedication in enabling
IEEE standards to lower costs for the electronics industry
IEEE 1149.1/JTAG Chairperson 1996-2001 & 2010-2013
IEEE P1149.10 High Speed JTAG chair
Very active member of P1838, P1687, P1149.6, etc
VTS 2012 Best Special Session Award - "IEEE P1149.1-2013…"
Co-inventor on 40+ US/foreign patents related to FPGA/JTAG
UNH CEPS Advisory Board Member (2000 - 2013 Emeritus )
Copyright © 2014 Intellitech Corp. All rights reserved.
1
Is every solution (or IEEE standard) going to be popular?
-Customer safety?
-Efficient?
ATW 2014
CJ Clark, Intellitech
2
Disclaimer:
Panel sessions are designed to create
Debate. The moderator instructs panelists
to take positions to help stimulate debate.
Any of the views here are not
necessarily that of CJ Clark or Intellitech
Corporation. Nothing should be implied.
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1149.1 is IJTAG - always has been
- Access to on-chip IP via TAP (and via Tcl) has been around since 1990s
Not just about "Boundary Scan"
BOUNDARY REGISTER
INIT-DATA REGISTER
IEEE 1149.1-2013 now brings
Hierarchical descriptions of on-chip IP
Register Segmentation and
Power domain control
USB
DC
Input
0
1
ADC
AC/DC
1
0
Hierarchical operational language for
On-chip IP ("instruments")
DAC
User
Defined
Chain(s)
PLL
Swing
Access via TAP, system clocks, CE,VDD
Volt.
Mon
0
1
PRBS
Synergy with IEEE 1500 and IEEE 1801
- re-use popular IEEE 1500 structures
- TDRs can cross power domains
with SEGSEL and MUX control
CMMV
Logic
BIST
Protocol
On-chip
Reset via
TAP
SysReset
Local Instrument resets, assertions,
Custom mappings ( TSV-2-Register)
Unique
ECID
IR & Decode &
Muxing
IC1
TAP
Memory
BIST
Loopback
Pattern
Run
ForceError
PRBS
Generator
 Describe Interface to IP w/o TAP
 Description is "packaged" in compliant
IEEE 1149.1-2013 package file
 Describe just interface + mnemonics
 Machine readable
Attribute REGISTER_MNEMONICS of SERPRBS : package is
"OnGroup
(ON (1), OFF (0))," &
"PatGroup
( PRBS31(1), PRBS23 (2), PRBS7(3) );"
Attribute REGISTER_FIELDS of SERPRBS : package is
"PRBS [5] ( "&
"(Loopback
"(Pattern
"(Run
"(ForceError
[1]
[2]
[1]
[1]
IS
IS
IS
IS
(4) DEFAULT(OnGroup(ON))), " &
(3,2) DEFAULT(PatGroup(PRBS7)) ), " &
(1)
SAFE(OnGroup(OFF)) ), " &
(0)) DEFAULT(OnGroup(OFF)));"
PRBS - Pseudo-Random Bitstream Sequence
5
Loopback
Pattern
Run
ForceError
PRBS
Generator
Set data
Shift data
Procedural Description Language
- new vectorless re-targetable
language for describing IP operation
iWrite
iWrite
iWrite
iWrite
iApply
Loopback
Pattern
Run
ForceError
ON
PRBS23
ON
OFF
Format: <iWrite > <Register> <value or mnemonic>
6
PRBS
Generator
Package SERPRBS
iWrite Loopback ON
IO(48)
HSSI
Tool converts to:
PRBS
Generator
IO(47)
PRBS
Generator
Package SERPRBS
Package HSSI
iWrite HSSI.IO(48).Loopback 1
Package SERPRBS
Package HSSI
IC BSDL
Tool converts to:
iWrite U1.HSSI.IO(48).Loopback 1
7
Loopback
Pattern
Run
ForceError
PRBS
Generator
Tools read IP package file hierarchy
And integrate with top level IC
1149.1-2013 <info tag> specifically provided
for interactive operation of internal JTAG
registers
Any instance of any IP can be accessed
within the IC hierarchy
8
IEEE Std. 1149.1-2013 lowers industry costs by enabling
test re-use through all phases of the IC life-cycle
-
Specifies best practices for Infrastructure IP test interfaces
Specifies rules for describing IP operation
Enables one description to be used in all test stages
Enables defect correlation between system failures and IC ATE
Note: doesn’t require production IC test through TAP
Track Die via 1149.1-2013 Electronic Chip Identification
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One 1149.1-2013 compliant IP gets leveraged across hundreds of engineers
One 1149.1-2013 compliant IC may have hundreds or thousands of IP
IP
Designer
IC
Designers
Closest
to source
OSAT = Out Sourced Assembly & Test
OSAT
Engineers
PCB
Designers
Test
Engineers
Furthest
Total Industry
Cost Savings
5 wire test
interface
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IEEE 1149.1-2013 and IEEE 1500
IEEE 1149.1-2013 expands IEEE 1500 Wrapper Serial Ports - Segment 1500 wrapper serial ports across domains
- Attribute REGISTER_ASSOCIATION enables TSV -to-register mapping
- Supports BROADCAST to IEEE 1500 WSPs
DIE2
Reg_1500
DIE3
Reg_1500
core
SI
B
C U
C U
DIE4
Reg_1500
core
SO
SI
core
SO
SI
SO
WSC
WSC
WSC
Gating
Gating
Gating
C U
C U
C U Gate_WSP
TSV/uBump
“ready_to_scan”
WSC:
Shift_1500
A
Capture_1500
C
Update_1500
Reset*
TCK
Sel_WSP
C U
Gating
open
3
2
1
0
C U
WSC
core
SI
SO
Reg_1500S
1
SO
0
C U
SI
Start_1500
End_1500
DIE1
IEEE 1149.1-2013 and IEEE 1801
Standardizes Test Data Register segmentation implemented by IEEE 1801
power intent. Both standards now use Tcl as the standard language.
Standardizes the input and description of on-chip or off-chip power control
IEEE 1149.1-2013 discussed in P1838 Stacked Die
VDD_DIE2
N2 M3
M1
M2
U
TMS State
Bit
D
SET
Q
TCK
CLR
C/S C/S C/S
1
Ring
Enable Bit
En/Dis*
Q
1
0
0
EXTEST/PRELOAD
TCK
0
1
Q
CLR
D
SET
Q
STDO
TAPRESET
TMS
N1 N3
STDI
L2
TCK
L1
C/S C/S
SEGSEL
DOMCTRL
C/S
C/S
U
U
0
S2CTRL
S2
PWR
Controller
CHRESET
D2
VDD_DIE2
1
1
IR
0
IR/DR
Decode
FPP
Bypass
ECID
CORE
TAP
SO
REG_1500
SI
S1CTRL
S1
SEGSEL
TDI
0
TMS
CHRESET
TCK
U
1
D
C/S
SET
CLR
TDI
C/S C/S
Q
Q
U
DOMAIN_EXTERNAL
C/S C/S
DOMAIN
VCC_IO
U
CHRESET
SHIFT
VCC_IO
A4 A2 C1 C3
B2
C2
B1 B3
14
P1838 uses reset blocking concepts from 1149.1-2013 for TAPCONFIG register
- not describable in P1687 ICL
15
New Memories HBM and HMC both 1149.1-2013 compliant
16
Hyper Memory Cube - Memory Mapped Registers
- TAP access
- Described in 1149.1-2013 BSDL
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IEEE P1149.6-201x
DC coupling, Vhyst, Vcm parameters in BSDL and PDL
attribute REGISTER_FIELDS of SerdesA : package is
"init_data[5] ( "&
-- TDI
"(SEL [1] IS (4) DEFAULT(ONOFF(OFF) RESETVAL(ONOFF(OFF)) ), "&
"(VCM [1] IS (3) DEFAULT(CMV(0V)) NOPI NOUPD ), "&
"(WEN [1] IS (2) DEFAULT(ONOFF(OFF) RESETVAL(ONOFF(OFF)) ), "&
"(SWING [2] IS (1 DOWNTO 0) DEFAULT(SWING(800mV)) NOPI NOUPD) "&
" )";
# get_VCM returns a voltage.
iProc get_VCM {} {
# Note: the true value of the current VCM is only present
# if SEL is set
set common [iGet -si -mnem VCM]
iApply
# match the strings here with the case of the mnemonics
if {$common == "0V"} {
return "0"
}
else if {$common == "500mV" } {
return "500"
}
else {
puts "The common-mode voltage has never been set\n"
return "ERROR"}}
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CS*
RD/WR*
DATAOUT(16)
DATAIN(16)
ADDR(12)
Pre-wrapping Silicon Instrument™
- Enables more efficient PDL and scan operations
SRAM_BIST_CONTROLLER
C/S C/S C/S C/S
RESET*
RD/WR*
CS*
SysClock
DATAOUT(16)
DATAIN(16)
CPU Test
Mode[3]
CPU Test
Enable
ADDR(12)
SO2
TCK_2
UpdateDRState_2
CaptureDR_2
ShiftDR_2
Busy
Fail
SI2
Pass
Result
Data[16]
SO1
TCK_1
UpdateDRState_1
CaptureDR_1
ShiftDR_1
SI1
Result
Addr[12]
U
C/S C/S C/S C/S C/S
C/S C/S C/S
ClearResults
RESET*
Enable
C/S C/S C/S C/S C/S C/S
D
U
Mode[0]
C/S C/S C/S C/S C/S C/S
C/S
RESET*
Mode[1]
C/S C/S C/S C/S C/S C/S
Mode[2]
C/S C/S C/S C/S C/S C/S
MuxSel
U
https://verificationacademy.com/verification-horizons/march-2014-volume-10-issue-1
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Instruments can be validated pre-silicon
- Fault coverage can be determined
- PDL correctness validated
20
1149.1-2013
iProc
Definition
P1687
iProc
Definition
Copyright © 2014 Intellitech Corp. All rights reserved.
21
Minimum Hardware Requirement:
a) A P1687 interface shall have at least one port function
Can customers specify an IEEE standard in a contract
that has few rules that are needed to achieve compliance?
22
Everything is compliant, even IP designed 20 years ago!
"Having a vendor deliver a P1687 compliant ICs or IP
is like a box of chocolates,
you never know what you're going to get."
- Forrest Gump
23
Some Comparisons of 1149.1-2013 and P1687
1149.1-20013
Yes
Yes
Yes
SEGSEL
Yes
Yes
Yes
Yes
6+user
Yes
Yes
P1687
Yes
Yes
Yes
SIB
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
No
No
Supports on-chip instruments via TAP
Supports Hierarchical descriptions
Variable scan chain lengths
Hierarchical scan chain segmentation
race free by design
Supports IEEE 1500, WIR and other Muxing
Supports broadcast
Addressable Instruments
Local Resets
PDL0/PDL1/Tcl
PDL0 - loop/if/then branching
for ATE vector generation
Support legacy devices (indirect addressing through
random user defined logic)
Plug and play IP
Supports I/O (Voltage etc) configuration
Supports power domains/ external power source
Supports Instrument assertions
checking/'constraints'
Supports TSV mapping
Instrument clock, power, reset requirements
for diagnostics
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P1687 value proposition
Describe die TAP and I/O with 1149.1-2013 and P1149.6-201x BSDL and PDL
Describe ECID via BSDL and PDL
Describe stuff on right in a new language called ICL rather than BSDL
Is pin access to instruments a good thing?
- creates impediment for system level access
to on-chip IP via TAP, clocks, power and reset
26
• New HSTAP for SPI and Gigabit
SERDES
• HSTAP described in BSDL
attributes
• 1149.1-2013 PDL for init_setup
• PEDDA decodes/encodes
Packets from ATE
• Multiple instruments accessed
at the same time
• Multiple scan channels
• I/O wrap segmented
• (like 1149.1)
Reset*
BS_Mode[7:1]
- Pin activation to an instrument is
Going to be too slow and unsynch'd
P1 149.10_Enable
SO
SI
TCK
Ins truct[n:0]
P1149.10 High Speed JTAG
Reset’*
BS_Mode[7:1]’
SI /SO/CSUK _Boundary
System Clock
+
-
S
I
P
O
+
-
PISO
SIPO
40 bit
Sipo Clk
P
I
S
O
SI /SO /CSUK _ DEVICE_ ID
40 bit
SI/ SO/ CSUK _Bypass
Mux
And
Gating
Logic
SI/SO /CSUK _ECID
SI/SO/CSUK_ INIT_ DATA
Packet
Decode
/Encode
SI/SO/CSUK_ CLK_ Ctrl
Clock
Control
SI /SO /CSUK _ CH 1
Piso Clk
SI /SO /CSUK _ CH 2
PISO
SIPO
Mux
And
Gating
Logic
CSUK _Parallel
SI_PP [9:3]
SO_PP[9:3 ]
Packet Decoder /Encoder
with Distribution Matrix
27
Conclusion
IEEE 1149.1-2013 BSDL and PDL
- Needed for Configuration of I/O
- Needed for ECID
- Supports TDR segmentation across
power domains through domain control bit
- supports IEEE 1500 architectures and segments
1500 WSPs for power domains
IEEE 1149.1-2013 used by IEEE 1149.6-201x
IEEE 1149.1-2013 used by IEEE P1149.10-201x
Potentially used by P1838-201x
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