BJT_dc biasing

Tutorial Problems: Bipolar Junction Transistor (DC Biasing)
1.
Consider the circuit shown in Figure 1. Determine IBQ, ICQ and VCEQ for: (a) β = 75, and (b) β = 150.
Assume VBE(on) = 0.7 V.
Figure 1
Solution:
For dc analysis, the capacitor CC is treated as open circuit.
(a) β = 75
The Thevenin voltage source VTH and resistance RTH of the base circuit is found by:
The base current IBQ:
The collector current ICQ:
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The collector-emitter voltage VCEQ:
(b) β = 150
Following the same steps as part (a),
2.
Design the circuit shown in Figure 2 such that the voltage drop across RC is
drop across RE is
VCC and the voltage
VCC. Assume β = 100 and VBE(on) = 0.7 V. The quiescent collector current is to
be ICQ = 0.4 mA, and the current through R1 and R2 should be approximately 0.2ICQ.
Figure 2
Solution:
The design requires that:
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The collector resistor RC:
The emitter resistor RE:
(Note: Since ICQ ≈ IEQ for reasonably large β, it is safe to conclude that RC = RE = 7.5 kΩ without causing
significant error in calculation. In fact, RC and RE are indistinguishable in practical design due to
tolerances in the device values.)
The base resistors R1 and R2:
(Note: The calculation above has assumed that R1 and R2 are in series and have the same current flowing
through them, i.e. 0.2ICQ. For accuracy, the complete equation should be written as: I(R1) = I(R2) + IBQ,
but since IBQ = ICQ / β = 0.004 mA is very small compared to I(R1) and I(R2) our assumption is considered
valid.)
3.
For the circuit shown in Figure 3, let β = 100. (a) Find VTH and RTH for the base circuit. (b)
Determine ICQ and VCEQ. (c) If the resistors RC and RE vary by ± 5 %, determine the range in ICQ and
VCEQ. (d) Draw the load lines corresponding to the maximum and minimum resistor values and mark
the Q-points. Assume VBE(on) = 0.7 V.
Figure 3
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Solution:
For dc analysis, the capacitor CC is treated as open circuit.
(a)
The Thevenin voltage source VTH and resistance RTH of the base circuit is found by:
(b)
The collector current ICQ and the collector-emitter voltage VCEQ:
(c)
If both RC and RE have a tolerance of ± 5 %, their values can vary between 4.75 kΩ ≤ RC ≤ 5.25 kΩ and
0.475 kΩ ≤ RE ≤ 0.525 kΩ. The extreme Q-point values are calculated as follows:
RC = 4.75 kΩ
RE = 0.475 kΩ
RE = 0.525 kΩ
RC = 5.25 kΩ
ICQ = 1.466 mA
ICQ = 1.466 mA
VCEQ = 2.33 V
VCEQ = 1.60 V
ICQ = 1.331 mA
ICQ = 1.331 mA
VCEQ = 2.97 V
VCEQ = 2.30 V
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(d)
The load line of the transistor circuit is given by:
With ± 5 % tolerance of the resistance values of RC and RE, the resulting Q-point value (VCEQ, ICQ) will lie
within the shaded region.
4.
In the circuit shown in Figure 4, find ICQ such that the Q-point is in the center of the load line. Let β
= 75 and VEB(on) = 0.7 V. What are the values of ICQ and VECQ? Why is it desirable to design the Qpoint to be in the center of the load line?
Figure 4
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Solution:
For the pnp transistor circuit shown, designing the Q-point to be in the center of the load line requires:
The Thevenin voltage source VTH and resistance RTH of the base circuit is found by:
The base current IBQ is found by writing KVL equation around the base circuit with the emitter current IEQ
flowing into the emitter and the base current IEQ flowing out of the base:
Since VECQ = 6 V,
A maximum swing of input and output voltage is achieved when the Q-point is in the center of the load
line.
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5.
(a) For the circuit shown in Figure 5, design a bias-stable circuit such that ICQ = 0.8 mA and VCEQ =
5 V. Let β = 100 and VBE(on) = 0.7 V. (b) Using the results of part (a), determine the percentage
change in ICQ if β is in the range 75 ≤ β ≤ 150. (c) Repeat part (a) and (b) with RE = 1 kΩ. What can
you conclude from these results?
Hint: As a general rule, a bias-stable circuit requires RTH ≈ 0.1(1 + β)RE.
Figure 5
Solution:
For dc analysis, the capacitors CC1, CC2 and CE are treated as open circuit. The required Q-point has ICQ =
0.8 mA and VCEQ = 5 V when β = 100.
(a)
The Thevenin voltage source VTH and resistance RTH of the base circuit is expressed by:
To design a bias-stable circuit, the following condition must be satisfied:
Writing the KVL equation around the base circuit gives:
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Hence
Since ICQ = 0.8 mA and VCEQ = 5 V,
(b)
If β changes over the range 75 ≤ β ≤ 150, the quiescent collector current ICQ changes according to the
equation below.
When β = 75,
When β = 150,
The percentage change in ICQ is:
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(d)
If the emitter resistor RE is changed to RE = 1 kΩ, the calculation is repeated as follows:
When β = 75,
When β = 150,
The percentage change in ICQ is:
6.
Design a bias-stable pnp transistor circuit to meet a set of specifications. The transistor Q-point
values are to be: VECQ = 7 V, ICQ ≈ 0.5 mA, and VRE ≈ 1 V. Assume transistor parameters β = 80 and
VEB(on) = 0.7 V.
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Figure 6
Solution:
For dc analysis, the capacitor CC is treated as open circuit. The required Q-point has ICQ = 0.5 mA, VECQ =
7 V when β = 80 and VRE = 1 V.
From these data, the collector resistance RC and emitter resistance RE can be found as:
The Thevenin voltage source VTH and resistance RTH of the base circuit is expressed by:
Writing the KVL equation around the base circuit gives:
Hence
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7.
The range of β for the transistor in the circuit in Figure 7 is 50 ≤ β ≤ 90. Design a bias-stable circuit
such that the nominal Q-point is ICQ = 2 mA and VCEQ = 10 V. The value of IC must fall in the range
1.75 ≤ IC ≤ 2.25 mA.
Figure 7
Solution:
Assume the nominal value of β is given by the mid-range value, i.e. β = (50 + 90) / 2 = 70.
From the data given, the emitter resistance RE is found by:
For bias-stable circuit, the Thevenin resistance RTH of the base circuit is:
Writing the KVL equation around the base circuit gives:
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When β = 50,
When β = 90,
Hence when the value of β changes between 50 ≤ β ≤ 90, the value of ICQ falls within the range 1.75 ≤ IC
≤ 2.25 mA and therefore the design specification is met.
8.
The nominal Q-point of the circuit in Figure 8 is ICQ = 1 mA and VCEQ = 5 V, for β = 60. The current
gain of the transistor is in the range 45 ≤ β ≤ 75. Design a bias-stable circuit such that ICQ does not
vary by more than 5 % from its nominal value.
Figure 8
Solution:
Given the nominal value of β is 60.
From the data given, the emitter resistance RE is found by:
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For bias-stable circuit, the Thevenin resistance RTH of the base circuit is:
Writing the KVL equation around the base circuit gives:
When β = 45,
When β = 75,
Hence when the value of β changes between 45 ≤ β ≤ 75, the value of ICQ does not vary by more than 5 %
from its nominal value and therefore the design specification is met.
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9.
In the circuit shown in Figure 9, the transistor Q0 is biased with a constant current source instead of
resistor network. Design the circuit such that VCE0 = 5 V and VCE2 = 3 V, where the subscript 0 and 2
denotes Q0 and Q2 respectively. Assume β = 50 and VBE(on) = 0.7 V for all transistors.
Figure 9
Solution:
The constant current source formed by Q1 and Q2 is called the current mirror. Summing all currents at the
collector of Q1 by assuming that Q1 and Q2 are identical, we have:
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For the circuit shown in Figure 9,
It is required that VCE0 = 5 V and VCE2 = 3 V, hence:
10. For each transistor in the circuit in Figure 10, β = 120 and VBE(on) = 0.7 V. Determine the quiescent
base, collector, and emitter currents in Q1 and Q2. Also determine VCEQ1 and VCEQ2.
Figure 10
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Solution:
The base circuit of Q1 is replaced with the equivalent Thevenin voltage source VTH and resistance RTH with
the following values:
The base current IBQ1:
The collector current ICQ1 and emitter current IEQ1:
At the collector of Q1, the following equation can be written:
Therefore,
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