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80C52/80C32
CHMOS SINGLE-CHIP 8-BIT MICROCOMPUTER
80C52-8K Bytes of Factory Mask Programmable ROM
80C32~PU with RAM and I/O
80C52/80C32-3.5 MHz to 12 MHz, Vcc =SV ±200/o
80C52-1/80C32-1-3.5 MHz to 16 MHz, Vcc = SV ±200/o
r \,
•
Three 16-Bit Timer /Counters
- Timer 2 is an Up/Down
Timer/Counter and Capture
•
TTL and CMOS Compatible Logic
Levels
•
64K External Program Memory Space
•
•
Power Off Flag
256 Bytes of On-Chip Data RAM
•
64K Extemal Data Memory Space
•
•
Boolean Processor
32 Programmable 110 Lines
•
6 lnterrupt Sources
•
Programmable Serial Channel with:
- Framing Error Detection
- Automatic Address Recognition
•
MCS®-51 Fully Compatible lnstruction
Set
•
Power Saving ldle and Power Down
Modes
•
ONCETM (On-Circuit Emulation) Mode
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to BK bytes of the program memory can reside in the on-chip ROM (BOC52 only). In
addition the device can address up to 64K of program memory external to the chip.
DATA ME MORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
The Intel BOC52 is a single-chip control oriented microcontroller which is fabricated on lntel's reliable
CHMOS Ili technology. Being a member of the 8051 family, the 80C52 uses the same powerful instruction set,
has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The 80C52 is an
enhanced version of the BOC51 BH. lt's added features make it an even more powerful microcontroller for
applications that require up/down counting capabilities such as motor control or amore versatile serial Channel to facilitate multi-processor communications.
For the remainder of this document, the BOC52 and BOC32 will be referred to as the BOC52.
Intel Corporation assumes no responsobility tor the use of any circuitry other than circuitry embodied on an Intel product. No othE:r circ uit patent
licen ses are omphed. lnl ormalion contained he reon supersedes previously published specifications on these devices lrom Intel.
April 1989
'S Intel Corporalion. 1989
/
Order Number: 270757-001
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intef
80C52/80C32
n
P2 .O-P2 .7
,
~
ALE/ F'RN;
TIMING
AND
rl/VPP
CONTROL
RST
_ __ _ _ _ „
~
XTAL1
P3.D- P3 .7
P l.O- Pl .7
270757 - 1
Figure 1. 80C52 Block Diagram
2
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80C52/80C32
PIN DESCRIPTIONS
PACKAGES
Part
Preflx
Package Type
Vcc: Supply voltage.
80C52
80C32
p
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
Vss: Circuit ground.
D
N
(T2) PLO
Vcc
PO.O (ADO)
(T2EX) P1.1
P1.2
Port O is also the mułtiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong interna! pullups when emitting1 's, and can source and
sink severa! LS TIL inputs.
P0.1 (A01)
4
P0.2 (A02)
P0.3 (A03)
P1.4
P1.5
P0.4 (AD4)
P1.6
P0.5 (AD5)
P1.7
P0.6 (AD6)
P0.7 (AD7)
RESET
(RXO) P3 .0
Port O: Port O is an 8-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink severał LS
TIL inputs. Port O pins that have 1 's written to them
float, and in that state can be used as high-impedance inputs.
10
Port O outputs the code bytes during program verifi·
cation on the 80C52. External pullup resistors are
required during program verification.
E\
80C52
80C32
(TXD) P3. 1
11
(INTO) P3.2
12
PSCH
(1NT1) P3 .3
13
P2.7 (A15)
(TO) P3.4
14
P2.6 (A14)
(Tl} P3.5
15
P2.5 (A13)
(Wii) P3.6
16
P2.4 (A12)
(Rii) P3.7
17
P2.3 (A11}
ALE
XTAL2
P2.2 (A10)
XTAL1
P 2. 1 (A9)
21
Vss
P2.0 (A8)
270757-2
Port 1: Port 1 is an 8-bit bidirectional I/ O port with
interna! pullups. The Port 1 output buffers can drive
LS TIL inputs. Port 1 pins that have 1 's written to
them are pulled high by the interna! pullups, and in
that state can be used as inputs. As inputs, Port 1
(: pins that are externally being pulled low will source
current (l1L. on the data sheet) because of the interna! pullups.
DIP
INDEX
CORNER
~
a..
(,)
In addition, Port 1 serves the functions of the following special features of the 80C52:
u
ą
u o
z: >
Q..
""':
~
"ł
o o o
a.. a.. a..
P1.5
P0.4
P1.6
P0.5
P1.7
P0.6
RST
P0.7
Port Pin
Alternate Functlon
P1 .0
T2 (External Count lnput to
Timer/Counter 2)
P1.1
T2EX (Timer/Counter 2
Capture/Reload Trigger
and Direction Control)
u
P3.0
NC
NC
P3.1
AU
P3.2
32
i'ffii
P3.3
31
P2.7
Port 1 receives the low-order address bytes during
ROM verification.
P3.4
P3.5
Port 2: Port 2 is an 8-bit bidirectional I/O port with
interna! pullups. The Port 2 output buffers can drive
LS TIL inputs. Port 2 pins that have 1's written to
them are pulled high by the interna! pullups, and in
that state can be used as inputs. As inputs, Port 2
pins thai are externally being pulled low will source
current (1 1L. on the data sheet) because of the internat pullups.
270757- 3
PLCC
Flgure 2. Pin Connections
3
- - - - - - -- -- --
-- --
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-- - - -- - - - - -- - - - - n r -
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intef
80C52/80C32
When the 80C52 is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). Jn this application it
uses strong interna! pullups when emitting 1's. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from external Program Memory locations
OOOOH to OFFFFH.
Some Port 2 pins receive the high-order address bits
during program verification.
~
-·· ;
EA should be strapped to Vcc for interna! program
executions.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
interna! pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1's written to
them are pulled high by the interna! pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (11L. on the data sheet) because of the pullups.
XTAL 1: lnput to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port Pin
Altemate Functlon
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt O)
INT1 (external interrupt 1)
TO (Timer O external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RO (external data memory read strobe)
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external cłock signal, since the input to the interna! clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
RST: Reset input. A high on this pin for two machina
cycles while the oscillator is running resets the device. An interna! pulldown resistor permits a poweron reset with only a capacitor connected to Vcc.
C2
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory.
-------4XTAL2
D
C1
-------4XTAL1
In normal operation ALE is emitted at a constant
rate of 1,16 the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
--------t Vss
C1, C2 - 30 pF ± 10 pF for Crystals
= 10 pF for Ceramic Resonators
PSEN: Program Stare Enable is the read strobe to
external Program Memory.
270757-4
Flgure 3. Oscillator Connectlons
4
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80C52/80C32
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
N/C
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL 1
With an external interrupt, INTO and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
Vss
270757-9
DESIGN CONSIDERATION
Figure 4. External Clock Drive Configuratlon
• When the idle moda is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machina
cycles before the interna! reset algorithm takes
control. On-chip hardware inhibits access to interna! RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when ldle is terminated by reset, the instruction following the one that invokes
ldle should not be one that writes to a port pin or
to external memory.
• Writing to unspecified SFR's (see Table 3) may
cause unpredictable operation.
IDLE MODE
The user's software can invoke the ldle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during ldle, but
the processor stops executing instructions. ldle
Mode will be exited ił the chip is reset or ił an enabled interrupt occurs.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down moda is terminated.
.~I
ONCE™ MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the BOC52
without the BOC52 having to be removed from the
circuit. The ONCE Mode is invoked by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as AST is deactivated.
On the BOC52 either a hardware reset or an external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the
SFRs and on-chip RAM to retain their values.
While the device is in ONCE Mode, the Port O pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the BOC52 is in this mode,
an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal
reset is applied.
To properly terminate Power Down the reset or external interrupt should not be executed before Vcc is
restored to its normal operating level and must be
Table 1. Status of the External Plns durlng ldle and Power Down
Program
Memory
ALE
PSEN
PORTO
PORT1
PORT2
PORT3
ldle
Interna!
1
1
Data
Data
Data
Data
Mode
ldle
External
1
1
Float
Data
Address
Data
Power Down
Interna I
o
Data
Data
Data
Data
Power Down
External
o
o
o
Float
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook. and Application Note AP-252, "Designing with the 80C51 BH.„
5
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80C52/80C32
• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Ex posure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias . ... 0°C to + 70°C
Storage Temperature . . .... . .. . -65°C to+ 150°C
Voltage on EA/V pp Pin to Vss . . . . .. . . OV to + 6.SV
Voltage on Any Other Pin to Vss .. -O.SV to + 6.SV
Maximum lol per 110 Pin .. .. . . . .... . .. .. .. 1 S mA
Power Dissipation . . .. .. .. . .. . ... ... . ..... . . 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
D.C. CHARACTERISTICS:
Symbol
V1l
NOT/CE Specifications contained within the
fo/lowing tab/es are subject to change.
TA = o•c to + 70°C; Vcc =
Parameter
lnput Low Voltage (Except EA)
Mln
sv
± 10%; Vss = ov
TypicaI
Max
Unit
-0.5
0.2 Vcc-0.1
V
(4)
Test Conditions
V1l1
lnput Low Voltage EA
o
o.2Vcc - 0.3
V
V1H
lnput High Vołtage
(Except XTAL 1, RST)
0.2 Vcc+0.9
Vcc + 0.5
V
V1H1
lnput High Vołtage
(XTAL 1, AST)
0.7 Vcc
Vcc + 0.5
V
Vol
Output Low Vołtage (5)
(Ports 1, 2 and 3, ALE/PROG, PSEN)
0.3
0.45
1.0
V
V
V
łm = 100 µA
lol = 1.6 mA (1)
lol= 3.5 mA
Vol1
Output Low Voltage (5)
(Port 0)
0.3
0.45
1.0
V
V
V
lol= 200 µ.A
lol = 3.2 mA (1)
lol = 7.0 mA
VoH
Output High Voltage
(Ports 1, 2 and 3
ALE/PROG and PSEN)
Vcc - 0.3
Vcc - 0.7
Vcc- 1.5
V
V
V
loH = - 10 µA
loH = - 30 µA
loH = -60µA
VoH1
Output High Voltage
(Port O in External Bus Mode)
Vcc - 0.3
Vcc - 0.7
Vcc - 1.5
V
V
V
loH = - 200 µA
łoH = - 3.2 mA (2)
loH = - 7.0 mA
ltl
Logical O lnput Current
(Ports 1, 2, and 3)
- 10
- 50
µA V1N = 0.45V
lu
lnput leakage Current
(Port O)
0.02
± 10
µA
ITl
Logical 1 to O Transition Current
(Ports 1, 2, and 3)
- 265
- 650
RRST
AST Pulldown Resistor
100
225
CIO
Pin Capacitance
10
lee
Power Supply Current:
Running at 12 MHz (Figure 5)
ldle Mode at 12 MHz (Figure 5)
Power Down Mode
15
5
5
40
o < V1N < Vcc
µA V1N = 2V
K!l
pF (Note6)
ć3V
7.5
75
6
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mA
(Note 3)
mA
µA
(2)
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80C52/80C32
NOTES:
1. Capacitive loading on Ports O and 2 may cause spurious noise pulses to be superimposed on the Vols of ALE and Ports
1, 2, and 3. The noise is due to external bus capacitance discharging into the Port O and Port 2 pins when these pins make
1 to O transitions during bus operations. In applications where capacitance loading exceeds 1OO pFs, the noise pulse on the
ALE signal may exceed O.SV. In these cases, it may be desirable to quality ALE with a Schmitt Trigger, or use an Address
Latch with a Schmitt Trigger Strobe input.
2. Capacitive toading on Ports O and 2 cause the Voo on ALE and PStN to drop below the 0 .9 Vcc specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions. Minimum Vcc for power down is 2V.
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and
SV.
5. Under steady state (non-transient) conditions, lol musi be extemally limited as follows:
Maximum loL per port pin:
10 mA
Maximum lol per 8-bit port Port O: 26 mA
Ports 1, 2. and 3: 15 mA
Maximum total lol for all output pins: 71 mA
li lol exceeds the test condition, Vol may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
6. CtO is the adjacent pin capacitance inherent to the package.
•OmA
30mA
PO
RST
20mA
Ei
80C52
10rn.A. -
r\
XTAL2
XTAL1
Vss
OmA
OM+łJ:
8MHz
.CMHz
12Mtłz.
16Mtłz.
270757-11
270757-10
All olhef pins disconnected
TClCH = TCHCl = 5 ns
lee Max at othef frequencies is given by:
~Ueae
..
MAX = 2 .2 X FRE~
ldle Mode
lee MAX = 0.49 X FREO + 1.6
Where FREO is in MHz, leeMAX is given in mA.
L
Flgure 6. lee Test Condltion, Active Mode
Figure 5. lee vs Frequency
XTAL2
XTALI
RST
Yss
80C52
270757 - 13
All other pins disconnected
XTAL 2
XTAL I
Vss
Flgure 8. lee Test Condltion, Power Down Mode.
Vcc = 2.ov to 6.0V.
270757-12
~
'
All other pins disconnected
TClCH = TCHCL = 5 ns
Flgure 7. lee Test Condltion ldle Mode
270757-14
Flgure 9. Clock Slgnal Waveform for lee Tests In Actlve and ldle Modes. TCLCH
7
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=
TCHCL
=
5 ns.
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80C52/80C32
EXPLANATION OF THE AC SYMBOLS
L: ~level LOW, or ALE
P: PSEN
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
O: Output Data
A: RO signal
T: Time
V: Valid
W : WA signal
X: No longer a valid logic level
Z: Float
A: Address
C: Glock
D: lnput Data
H: Logic level HIGH
I: lnstruction (program memory contents)
For example,
TAVLL = Time from Address Valid to ALE Low
TLLPL = Time from ALE Low to ~ Low
A-C. CHARACTERISTICS TA= o·c to + 1o·c. Vcc = 5V ± 20%, Vss = ov, Load Capacitance for
Port O, ALE and PSE'N" = 1OO pF, Load Capacitance for All Other Outputs = 80 pF
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Oaclllator
Varlable Oscillator
Mln
Mln
Max
3.5
3.5
/'~
Max
1/TCLCL Oscillator Frequency
80C52
80C52-1
~
Unita
MHz
ns
ITLHLL
ALE Pulse Width
127
2TCLCL-40
TAVLL
Address Valid to ALE Low
43
TCLCL - 40
ns
TLLAX
Address Hold After ALE Low
53
TCLCL - 30
ns
TLLIV
ALE Low to Valid lnstruction In
TLLPL
ALE Low to PSEN Low
TPLPH
PSEN Pulse Width
TPLIV
PSEN Low to Valid lnstruction In
TPXIX
lnput lnstruction Hold After PSEN
TPXI Z
lnput lnstruction Float After PSEN
TCLCL - 30
ns
205
3TCLCL - 45
ns
Address to Valid lnstruction In
PSEN Low to Address Float
TALAH
AD Pulse Width
400
TWLWH WA Pulse Width
400
ITRHDX
Data Hold After AD
3TCLCL - 105
145
o
TPLAZ
AD Low to Valid Data In
ns
53
TAVIV
TALDV
4TCLCL - 100
234
o
ns
ns
59
TCLCL - 25
ns
312
5TCLCL - 105
ns
10
10
ns
6TCLCL - 100
ns
6TCLCL - 100
ns
5TCLCL - 165 ns
2 52
o
o
ns
ITAHDZ
Data Float After AD
107
2TCLCL - 60
ns
ITLLDV
ALE Low to Valid Data In
517
8TCLCL - 150
ns
ITAVDV
Address to Valid Data In
585
9TCLCL - 165 ns
TLLWL
ALE Low to RO or WR Low
200
ITAVWL
Address Valid to AD or WA Low
203
4TCLCL - 130
ns
33
TCLCL - 50
ns
33
TCLCL - 50
ns
ITOVWX Data Valid to WR Transition
TWHQX Data Hold after WA
TQVWH Data Valid to WA High
ITRLAZ
AD Low to Address Float
ITWHLH
AD or WA High to ALE High
300
3TCLCL -50 3TCLCL + 50
7TCLCL - 150
433
o
43
123
(11
TCLCL - 40
8
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ns
ns
o
ns
TCLCL + 40
ns
'il
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80C52/80C32
EXTERNAL PROGRAM MEMORY READ CYCLE
ALE
TPXIZ
PORT O
PORT 2
AO-A7
INSTR IN
-----
A8-A15
270757-15
EXTERNAL DATA MEMORY READ CYCLE
ALE
-TLHLL--
TWHLH
PSEN
TRLRH
RO
TRHDX
PORTO
AO-A7 F"ROM PCL
- - -- - T A V W L - --
PORT2
INSTR. IN
--
- - -- - -
P2.0-P2 .7 OR A8-A15 F"ROM DPH
AS-A 15 F"ROM PCH
2 70757-16
9
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80C52/80C32
EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
TLLWL----o----TWLWH---~
TOVWX
!'-.._.._.._.._.._.._..__,
TWHOX
TLLAX-
PORTO
INSTR. IN
PORT2
AB-A 15 FROM PCH
P2.0-P2.7 OR A8-A15 FROM DPH
270757 -1 7
A.C. TESTING INPUT
lnput, Output Waveforms
Float Waveforms
VLOA0~0.1
V
Y0t1-0.1 V
0.2 vcc+o.t
0.45 V
VLOAO
o.2vcc - o.1
TllllWO REFEAENCE
VLOAo-0.1 V
POlllTS
VOL +0.1 V
270757 -1 9
For timing purposes a port pin is no longer flo ating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change trom the loaded VQHI Vo L level occurs.
lo L/IOH ;;, ± 20 mA.
270757-18
AC lnputs during testing are drivan at Vcc- 0 .5V for a Logic " 1"
and 0.4 5V for a Logic " O" . Timing maasuraments ara made at V 1H
min for a Logic " 1" and Vo l max for a Logic "O" .
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Condltions:
Symbol
TA
= o•c to + 70°G; Vcc = sv ± 20%; Vss = OV; Load Capacitance = ao pF
Parameter
12 MHz Oscillator
Mln
Max
Varlable Osclllator
Min
Unita
Max
TXLXL
Serial Port Glock Gycle Time
1
12TGLGL
µ..s
TQVXH
Output Data Setup to Glock
Rising Edge
700
1OTGLGL - 133
ns
TXHQX
Output Data Hołd after
Glock Rising Edge
50
2TGLGL - 117
ns
TXHDX
lnput Data Hold After Glock
Rising Edge
o
o
ns
TXHDV
Glock Rising Edge to lnput
Data Valid
700
10
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1OTGLGL - 133
ns
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inłef
80C52/80C32
SHIFT REGISTER MODE TIMING WAVEFORMS
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
1/TCLCL
Oscillator Frequency
80C52/80C32
80C52-1 /80C32-1
3.5
3.5
12
16
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
RiseTime
20
ns
TCHCL
Fall Time
20
ns
Units
MHz
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
Vcc-0.5 • - - - - - - - - - - - - 0 .7 Vcc
o .45V - - - " ' 0 . 2 Ycc-0. 1
TCHCL
TCLCX
TCHCX
TCLCH
--~~~~~TCLCL~~~~~--~
270757-6
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inłef
80CS2/80C32
ROM CHARACTERISTICS
Table 2 shows the logic
levełs
for verifying the code data and reading the signature bytes on the 80C52.
Table 2. ROM Modes
Mode
RST
PSEN
ALE
EA
P2.7
P2.6
P3.6
P3.7
Verify Code Data
1
1
1
1
1
o
o
1
1
o
o
1
Read Signature
o
o
o
o
NOTES:
" 1" = Valid high for thai pin
"O" = Valid low for thai pin
Program Verification
cations will come out on Port O. External pullups are
required on Port O for this operation.
The address of the Program Memory location to be
read is applied to Port 1 and pins P2.0-P2.4. The
other pins should be held at the "Verify" levels indicated in Table 2. The contents of the addressed Io-
Figure 1O shows the setup for verifying the program
memory.
+SV
Vcc
A0-A7
Pl
PO---v
~~~A
--MRST
P3.6
o
80C52
PJ.7
P2.7
o
XTAL2
P2.6
o
XTAL 1
P2.0
-P2 .-4
(ENABLE)
•-sMHz0
A8-A12
Yss
270757- 7
Flgure 10. Verifylng the ROM
ROM VERIFICATION CHARACTERISTICS
TA = 21·c to 27°C; Vcc = 5V ± 0.25V;
v55
=
ov
ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol
Parameter
Min
Max
Unlts
4
6
MHz
1/TCLCL
Oscillator Frequency
TAVQV
Address to Data Valid
48TCLCL
TELO V
ENABLE Low to Data Valid
48TCLCL
TEHOZ
Data Float after ENABLE
o
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48TCLCL
n·
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80C52/80C32
ROM VERIFICATION WAVEFORMS
Pt.O-Pt.?
P2.0-P2.4
PORT
o
VERIFICATION
----j.......
AOORESS
)
,.._E--T-AV_O_V_ __
------41
P2 .7
DATA OUT
mov1
}
ti.-----0
""oz
270757-8
Reading the Signature Bytes
The signature bytes are read by the same procedura as a norma! verification of locations 030H and 031 H,
except that P3.6 and P3. 7 need to be pulled to a logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
(031 H) = 53H indicates 80C52
Table 3. 80C52 Speclal Function Registers
Address
80H
81H
82H
83H
87H
88H
89H
8AH
88H
BCH
8DH
90H
98H
99H
OAOH
OABH
OA9H
080H
088H
089H
OC8H
OC9H
OCAH
OC8H
OCCH
OCDH
ODOH
OEOH
OFOH
• =
Name
Reset Value
PO*
SP
OPL
DPH
PCON
TCON"
TMOD
TLO
TL1
THO
TH1
111 111118
000001118
000000008
000000008
OOXX00008
000000008
000000008
000000008
000000008
000000008
000000008
111111118
000000008
XXXXXXXX8
111111118
000000008
000000008
111111118
X00000008
000000008
000000008
XX XX XXXOB
000000008
000000008
000000008
000000008
000000008
000000008
000000008
pp
SCON *
S8UF
P2*
IE*
SAD DR
p3•
IP*
SADE N
T2CON*
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW *
ACC*
s·
Bit Addressable
13
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