Physical Modeling of the Capacitance and Capacitive Coupling

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013
123
Physical Modeling of the Capacitance and Capacitive
Coupling Noise of Through-Oxide Vias in
FDSOI-Based Ultra-High Density 3-D ICs
Chuan Xu, Member, IEEE, and Kaustav Banerjee, Fellow, IEEE
Abstract—Fully depleted silicon-on-insulator (FDSOI) technology boosts the opportunity to make 3-D ICs with ultrahigh integration density, due to the short and tiny through-oxide vias
(TOVs), which are made after removing the entire silicon under
the buried-oxide layer. This work, for the first time, develops
compact physical models for the capacitance of the TOV and
the coupling capacitance between the TOV and active regions in
the presence of periodical power/ground lines, from fundamental
electrostatic considerations. Calculation results from the models
show good agreement with the simulation results from a full-3-D
capacitance solver. The models are further used to analyze the
threshold voltage (Vth ) variation in the FDSOI MOSFETs. The
TOV in FDSOI and the through-silicon via (TSV) in bulk-CMOSbased 3-D ICs are finally compared in terms of the self-impedance
as well as their impact on MOSFET Vth variation through capacitive noise coupling. These results provide important insights to
TOV/TSV design and optimization in emerging 3-D ICs.
Index Terms—Active region, capacitance, compact model, coupling noise, interconnect, power/ground lines, through-oxide via
(TOV), through-silicon via (TSV), 3-D integrated circuits.
I. I NTRODUCTION
T
HREE-DIMENSIONAL integrated chips (3-D ICs),
which employ stacking of different wafers or chips (active
layers or tiers), can provide reduced interconnect delay and a
platform to integrate dissimilar technologies [1], [2]. Threedimensional ICs can be implemented in both bulk CMOS [3]–
[5] and silicon-on-insulator (SOI) technologies [6], [7]. In bulk
CMOS technology, most of the prior works employ throughsilicon vias (TSVs) to electrically connect different tiers [3]–
[5]. In SOI technology, since the buried oxide (BOX) can be
treated as an etch stop when thinning the silicon substrate
[from Fig. 1(a) to (b)], there is an opportunity to eliminate the
entire silicon substrate below the BOX for the second tier and
Manuscript received June 6, 2012; revised September 30, 2012; accepted
November 9, 2012. Date of current version December 19, 2012. This work
was supported in part by the National Science Foundation under Grant CCF0917385 and in part by the National Institute of Standards and Technology
under Grant 60NANB12D148. The review of this paper was arranged by Editor
D. Esseni.
C. Xu was with the Department of Electrical and Computer Engineering,
University of California, Santa Barbara, CA 93106 USA. He is now with the
Technology Development and Innovation Group, Maxim Integrated, Beaverton,
OR 97005 USA (e-mail: [email protected]).
K. Banerjee is with the Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106 USA (e-mail:
[email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2012.2227966
Fig. 1. Schematic plots showing the fabrication steps of SOI-based 3-D ICs
using TOVs. (a) Two tiers with fabricated front-end-of-line (containing active
devices) and back-end-of-line are bonded face to face. (b) The Si substrate
in the second tier is completely removed by using the BOX as the etch stop.
(c) TOV holes are drilled, and metal is filled in. (d) The third tier is bonded and
electrically connected with the second tier using similar fabrication steps.
beyond [6], [7], and thereby, short and tiny through-oxide
vias (TOVs) [see Fig. 1(c)] instead of TSVs can be used. For
example, the TOV (with a diameter of < 3 μm and a height
of ∼ 8 μm) fabricated in 0.18-μm technology [7] is already
smaller than the TSV (with a diameter of ∼ 5 μm and a height
of ∼ 20 μm) fabricated in 0.13-μm technology [5]. The smaller
size increases the integration density significantly. Stacking the
third tier is similar to stacking the second tier [see Fig. 1(d)].
Although the TOVs in SOI technology are much smaller than
TSVs in the same technology node, they are still much bigger
than the short vias (that connect the horizontal interconnects of
different levels within one tier)1 and can significantly impact
the performance of 3-D ICs as well as noise coupling to the
active devices.
Many works have discussed electrical modeling and/or simulation of TSVs/TOVs [9]–[15] and their coupling to the active
1 There is another configuration that can utilize the SOI technology, called
3-D CMOS sequential integration [8], which involves fabricating the active devices after stacking the SOI wafer and substrate removal. In such configuration,
the TOVs are even smaller as they are essentially the source/drain/gate contacts
and, thereby, can be treated as standard vias in 2-D ICs.
0018-9383/$31.00 © 2012 IEEE
124
regions [13]–[16]. The silicon depletion region effect (MOS
effect) has been investigated for TSVs [9]–[11]. A 3-D analytical series impedance model has been developed for TSVs with
consideration of the substrate eddy current effect [12]. Threedimensional analytical self parallel-admittance/capacitance
models have been developed for TSVs [13] and TOVs [15], and
a 3-D fast extraction method of parallel admittance among multiple TSVs has been developed for TSVs [14]. The 3-D analytical model or fast extraction of the capacitance among multiple
TOVs needs to be investigated. On the other hand, analytical
models for the TSV coupling to the active region in bulk CMOS
have been developed in [13], which shows that this coupling
noise can be more important than other noise sources such as
the substrate white noise and the flicker noise from the TSV.
However, the analysis presented in [13] for the TOV coupling to
the active region assumed a partially depleted SOI (PDSOI) and
employed time-consuming electromagnetic simulations, but no
analytical solutions were obtained. While recent works have
addressed the coupling from the TOV to fully depleted SOI
(FDSOI) MOSFETs through analytical modeling [15] as well
as TCAD simulations [16], the verification of the analytical
model through TCAD simulations has not been shown.
The series impedance (resistance and inductance) and inductive coupling of TOVs can be obtained by the reduced model of
the TSV case [12] (substrate eddy current can be neglected) and
is negligible as compared with the capacitance and capacitive
couplings due to the same reasons as already demonstrated for
the TSVs [11], [13] (the TSV/TOV size is much smaller than
the electromagnetic quarter-wave length for any frequencies
below signal significant frequency). Therefore, it is important to
focus on the capacitance and capacitive coupling noise of TOVs
in FDSOI-based 3-D ICs. In particular, their analytical solutions
with better physical insights are of high priority. However, the
impact of coupling noise of the TOV to FDSOI devices is more
difficult to model than that of the TSV to bulk CMOS, due to
two reasons: 1) in bulk CMOS or PDSOI, the body under the
channel serves as the shield, which does not exist in FDSOI;
2) in bulk CMOS, the current density from the TSV to the
wells has approximate azimuthal symmetry since the wells have
much higher conductivity [13].
In this paper, analytical models for TOV capacitance and
capacitive coupling noise are derived from fundamental electrostatic considerations. Capacitance among multiple TOVs is
investigated for the first time. The capacitance and capacitive
coupling models are verified against a full-3-D capacitance
solver, i.e., FastCap [17], whereas the analytical model for the
threshold voltage (Vth ) variation arising from TOV coupling
to FDSOI MOSFETs is verified against TCAD simulations
using Silvaco ATLAS [18]. Using the analytical models in
this paper and those in [13] (for TSVs), the impedance and
the couplings are compared between the cases with TSVs in
bulk CMOS technology and TOVs in FDSOI technology. The
results show that the TOV+pad in FDSOI has much smaller
parallel admittance toward the power/ground lines (implying
better performance) than the TSV in bulk CMOS. On the other
hand, the Vth variation from TOV coupling in FDSOI is smaller
(larger) than that from TSV coupling in bulk CMOS at higher
(lower) frequencies.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013
Fig. 2. Self-capacitance of a TOV+pad structure in a homogeneous dielectric.
(a) The schematic of the TOV+pad structure (hTOV , wTOV , tpad , and wpad
are defined in the plot), whose homogeneous medium self-capacitance (C0 )
can be extracted using (1). The actual and simplified structures have the same
As . While the width of the bottom pad is larger due to the large misalignment in
wafer bonding, the width of pad 2 is similar to that of the TOV and, thereby, can
be neglected. (b) C0 as a function of the top-to-bottom TOV-width-ratio using
(1) as well as field solver ANSYS Mechanical [20]. In (b), hTOV = 7.4 μm;
tpad = 0.5 μm; wpad = 5.5 μm; the average width of TOV top and bottom
is 2.1 μm; the width of pad 2 is the same as that of TOV top; the relative
permittivity of the surrounding medium is set to be 4.0 (ε = 4.0ε0 ); qss is set
to be 1. For simplicity, we use the simplified structure in the subsequent analysis
in this paper.
II. TOV S ELF -C APACITANCE AND C APACITANCE
TO THE P OWER /G ROUND L INE ( S )
The TOV self-capacitance in a homogeneous dielectric (C0 )
can be expressed as
C0 = qss ε 4πAs
(1)
where ε is the permittivity, As is the total surface area of the
structure, and qss is a parameter based on the shape of the
structure [19] ([19] mainly discusses thermal models, while
the similarity of an electrostatic problem and a steady-state
thermal problem is that both of them satisfy the Laplace’s
equation in the dielectrics). Fig. 2(a) shows the actual shape
and the simplified shape of the TOV+pad structure. Fig. 2(b)
provides a comparison between ANSYS Mechanical [20]2 and
(1) with qss ≈ 1 for C0 of the actual shape, as a function of the
top-to-bottom TOV-width-ratio (when the ratio is 1, the actual
shape reduces to the simplified shape). The results indicate that
it is valid to use (1) with qss ≈ 1 for both the actual shape and
the simplified shape. Therefore, for simplicity, this paper will
only consider the simplified shape. In addition, as indicated in
[15, Fig. 2(b)–(d)], we found that assuming qss = 1 only results
in a small error as compared with FastCap [17] for various
geometrical parameters (various hTOV , wTOV , and wpad ) in the
simplified shape. Therefore, we assume qss = 1 in the following
analysis.
The capacitance (Ctotal ) between a TOV+pad and a power/
ground line (Vdd or Gnd) can be derived from the electrostatic
problem of a point charge outside a conducting cylinder [21]
through several steps of approximations. In Fig. 3(a), the power/
2 Both ANSYS Mechanical and FastCap are standard full-3-D field solvers.
The simulation results from FastCap and ANSYS Mechanical are almost
identical. The benefit of using ANSYS Mechanical in Fig. 2(b) is due to its
convenience in building arbitrary shapes, whereas FastCap is not as convenient
for nonright-angle shapes. However, for the structures simulated in this paper,
FastCap is much faster. Therefore, we use FastCap instead of ANSYS Mechanical as a comparison reference to our models in the following analysis.
XU AND BANERJEE: CAPACITANCE AND COUPLING NOISE OF TOVS IN FDSOI-BASED 3-D ICs
Fig. 3. Schematic plots showing (a) a power/ground line can be approximately
treated as an equivalent elliptic cylinder, which can be further treated as an
equivalent cylinder with an equivalent radius apl , and (b) the power/ground
line has a c2c distance of ρ to the TOV+pad.
ground line with a cross section of wpl × hpl can be approximately treated as an equivalent elliptic cylinder (“equivalent”
implies same or similar self-capacitance), which has semi-axes
of wpl /2 and hpl /2. Note that the homogeneous medium selfcapacitance of an elliptic cylinder with semi-axes of a and b
is the same as that of a cylinder with a radius of (a + b)/2,
which is derived from the exact expression of the charge density
distribution of a conducting ellipsoid [22], where an infinitely
long elliptic cylinder is a special case of an ellipsoid (see
the Appendix for details). Therefore, the equivalent elliptic
cylinder can be further treated as an equivalent cylinder. In other
words, the power/ground line with a cross section of wpl × hpl
can be approximately treated as an equivalent cylinder with a
radius of apl , where
apl = (wpl + hpl )/4.
(2)
The TOV+pad is treated as a point charge when calculating the
electrostatic force and/or energy between the TOV+pad and the
power/ground line (equivalent cylinder) [shown in Fig. 3(b)].
According to [21], the electrostatic force [23] between an
external point charge of q (or a conducting object with charge
of q) and a conducting infinite long cylinder is
−
→
F =−
2
q 2 ρ̂
·
4πε · ρ2 π
∞
λK0 (λ)K1 (λ)
dλ
K0 (λapl /ρ )
(3)
0
where ρ is the center-to-center (c2c) distance between the
point charge (or the conducting object) and the cylinder (or
the power/ground line); ρ̂ is the radial direction vector; ε is the
permittivity of the surrounding dielectric; λ is an integration
variable, derived from an integration of integral transform (λ/ρ
is the radial spectrum; see [21, eq. (43)], where “λ” in this
paper is “x” in [21]); and K0 and K1 are the zeroth- and firstorder modified Bessel function of the second kind, respectively.
Therefore, the work needed to take the charge q from infinity to
a c2c distance of ρ is
∞
W =
ρ
− |F (ρ )| dρ ≈ −
q2
.
16ερ ln (8.3ρ /apl )
(4)
The total work, which is related to the total capacitance
(Ctotal ), is W plus the work needed to add charge q on the con-
125
Fig. 4. (a) Cross-sectional view of a TOV+pad and a power/ground line.
(b) 1/C0 − 1/Ctotal of the structure in (a) from both FastCap [17] and our
models [(2), (6), and (7a)] or [(2), (6), and (7b)], where C0 and Ctotal are
defined in the text. The geometrical parameters of the power/ground line are
wpl = 2 μm and hpl = 0.5 μm. The geometrical parameters of the TOV+pad
are hTOV = 7.4 μm, tpad = 0.5 μm, wpad = 5.5 μm, and wTOV = 2.1 μm,
which result in Δz = 2.08 μm (calculated from the centroid of the surfaces).
Surrounding medium permittivity ε = 4.0ε0 .
ducting object before moving the object from infinity, i.e.,
W + q 2 /2C0 = q 2 /2Ctotal
(5)
where the expression for the homogeneous medium selfcapacitance (C0 ) can be found in (1). Therefore
−1
Ctotal = C0−1 − f1 (ρ , apl )/ε
(6)
where
f1 (ρ , apl ) = [8ρ ln (8.3ρ /apl )]
−1
.
(7a)
The capacitance model [(2) (6) (7a)] is verified against
FastCap [17] by comparing 1/C0 − 1/Ctotal in a test case in
Fig. 4. Good agreement is achieved when Δx ≥ 5 μm (in other
words, the edge-to-edge distance between the power/ground
line and TOV+pad, Δd ≥ 1.25 μm). When Δd is too small,
the point charge approximation becomes more and more inaccurate with an increasing proximity effect. One could introduce
some empirical parameter to compensate for approximation
inaccuracies. For example, (7b) provides a fitting parameter χ
(χ = 6 × 10−4 μm2 in the test case in Fig. 4), which fits the
1/C0 − 1/Ctotal results better, i.e.,
f1,empirical (ρ , apl , Δd) = [8ρ ln (8.3ρ /apl )]
−1
+ χ/Δd2 .
(7b)
In the following analysis, we will retrieve using (7a), which is
free of technology-dependent empirical parameters. However,
in realistic applications, empirical extension of our physical
models [such as (7b)] could be introduced to further improve
the accuracy of our models. It should be also noted that the test
case in Fig. 4 has the same z-coordinate for the power/ground
line and the pad, but this is not a restriction in our model.
Our model can be extended to the extraction of the capacitance (also labeled as Ctotal ) between a conducting object (such
as TOV+pad) and two power/ground lines (shown in Fig. 5)
from an empirical expression, i.e.,
ε · (1/C0 − 1/Ctotal ) = [f1 (ρA , apl ) + f1 (ρB , apl )
− f1 ((dAB + ρA + ρB )/2, apl )]
(8)
126
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013
Fig. 5. Capacitance (Ctotal ) between a conducting object (such as
TOV+pad) and two power/ground lines can be obtained from an empirical
expression.
where ρA and ρB are the c2c distance from the conducting
object to power/ground lines A and B, respectively, and dAB is
the c2c distance between the two power/ground lines. Note that
when dAB = ρB − ρA (line B is behind line A from the object), (8) reduces to the case of only one cylinder (cylinder A),
where the effect from the other cylinder (cylinder B) is neglected. The model can be further extended to the case of
Ctotal between an object (such as TOV+pad) and periodical
power/ground lines, by assuming that only the nearest two
power/ground lines contribute.
Our approach shows good agreement with FastCap [17] in
[15, Fig. 6] by comparing 1/C0 − 1/Ctotal . The results from
two power/ground lines have negligible difference from those
obtained from periodical power/ground lines (typical power
grid in IC layout design), which indicates that the power/ground
lines farther than the nearest two power/ground lines have
negligible impact on 1/C0 − 1/Ctotal .
III. TOV TO ACTIVE D EVICE C OUPLING C APACITANCE
The source, drain, and gate of an active device, which are
either silicide/metal or highly doped silicon, are good conductors, whereas the channel is very close to the gate (although
the channel is not a good conductor when the device is off).
Therefore, from the TOV coupling capacitance point of view,
the entire active device can be treated as a good conductor.
Here, due to the planar nature, the active device is treated as
a conducting rectangle.
The coupling capacitance between the TOV and the active
device (C21 ) can be obtained from [Pij ], the inverse of capacitance matrix3
−1
P11 P12
C11 C12
(9)
=
P21 P22
C21 C22
which gives
2
.
C21 = −P21 / P11 P22 − P21
(10)
Here, 1/P11 and 1/P22 are the capacitance values of TOV+pad
and active device w.r.t. the periodical power/ground lines, respectively, i.e.,
P11 = 1/Ctotal,TOV+pad
(11)
P22 = 1/Ctotal,FET .
3 The concept of the P matrix is similar to that in [17]. The difference is that
we treat each conductor (TOV + pad or active device) as a whole, whereas [17]
treats each conductor as a combination of many small conducting panels.
Fig. 6. Analytical model for the coupling capacitance C21 between
TOV+pad and the active region. (a) From the aspect of TOV+pad capacitance,
the periodical power/ground lines are equivalent to a ground plane, which
has an equivalent distance of zTOV,eq1 from the centroid of TOV+pad. The
induced Evirtual at the position of the active region (xFET ) can be subsequently obtained. (b) V (x, |E|), the electric potential distribution at z = 0 and
apl < x < dAB due to periodical wires and external electric field strength |E|,
can be expressed as from the contribution of all the periodical wires.
Ctotal,FET can be obtained from the method similar to that
for Ctotal,TOV+pad , as described in Section II, and from treating the active device as a rectangle (shape parameter qss,FET =
0.932 [19]). P21 represents the induced voltage on the active
device (MOSFET region) when TOV+pad has unit charge.
P21 can be treated as the product of two parts, Evirtual and
V (x, |E|), i.e.,
qP21 = V (xFET , |Evirtual |)
(12)
where q is the total charge on TOV+pad, and xFET is the
x-coordinate of the central position of the active device [see
Fig. 6(a)].
Evirtual is the virtual electric field strength on the equivalent
ground plane [from the aspect of TOV+pad capacitance, the periodical power/ground lines in the top configuration in Fig. 6(a)
are equivalent to a ground plane in the bottom configurations in
Fig. 6(a)]. The “equivalence” is in the sense that the capacitance
between TOV+pad and ground is the same. Therefore
1
1
1
=
−
8πε · zTOV,eq1
C0,TOV+pad
Ctotal,TOV+pad
(13)
where zTOV,eq1 is an equivalent distance from the centroid
of TOV+pad to the equivalent ground plane. The induced
Evirtual at the position of the active device can be subsequently
obtained, i.e.,
3
3
) ≈ qzTOV,eq1 /(2πεr12
)
Evirtual ≈ qzTOV,eq1 /(2πεr12,eq
(14)
XU AND BANERJEE: CAPACITANCE AND COUPLING NOISE OF TOVS IN FDSOI-BASED 3-D ICs
127
where r12 is the c2c distance between the TOV+pad and the
active device.
V (x, |E|) is the electric potential at z = 0 and apl < x <
dAB − apl due to periodical wires and external electric field
strength |E| [see Fig. 6(b)]. V (x, |E|) can be obtained from the
superposition of the contribution of all the periodical wires, i.e.,
V (x, |E|)
∞ x+(n−1)dAB
ndAB −x
−Qline =
ln
+ln
2πε n=1
apl +(n−1)dAB
ndAB −apl
(15a)
where Qline is the induced charge per unit length on one of the
periodical wires. Using Gauss’s Law
Qline = −ε|E|dAB .
(15b)
Therefore
V (x, |E|) = |E| dAB · [f2 (x/dAB ) − f2 (apl /dAB )]
IV. I MPACT OF TOV/TSV C OUPLING TO ACTIVE D EVICES
(16b)
where Γ is the Gamma function.
From (13)–(16)
3
P21 ∼ zTOV,eq1 /2πεr12
· dAB · [f2 (xFET /dAB ) − f2 (apl /dAB )] .
where β is a parameter that can be obtained from the right2
.
hand side of (19) and can be plotted as a function of r12
Subsequently, α can be obtained. A particular test case has
been discussed in [15, Fig. 8], which shows good agreement
with FastCap [17]. It should be noted that when there are other
TOV(s) or active device(s) present, C21 for a particular pair of
TOV and active device will be reduced due to charge sharing.
Modeling of multiple TOVs and active devices is illustrated in
Section VI.
(16a)
where the function
f2 (λ) = − ln (Γ(λ) · Γ(1 − λ)) /2π
Fig. 7. Schematic plot of (a) FDSOI and (b) bulk CMOS showing impact of
the electrical coupling from TOV/TSV.
(17)
The above expression is more accurate when r12 dAB . To
make the expression valid for any r12 and xFET , an empirical
fitting parameter α is introduced, i.e.,
−3/2
zTOV,eq1 2
r12 + αd2AB
P21 ≈
2πε
xFET
apl
· dAB · f2
− f2
dAB
dAB
−3/2
zTOV,eq1 2
r12 + αd2AB
=
· zeq2 .
(18)
2πε
Note that the z-coordinate value of the MOSFET is close to that
of the power/ground lines, whereas the periodical power/ground
lines are approximately treated as equivalent cylindrical wires
[see Fig. 3(a)]. The fitting parameter α is dependent on the
size and distribution of power/ground lines. C21 is most crucially determined by Ctotal,TOV+pad and Ctotal,FET , which are
mostly dependent on the sizes of TOV+pad and of the active
device, respectively, as well as P21 , which is most crucially
determined by the distance between the TOV and the active
device.
From (18)
The impact of TOV/TSV coupling to active devices can
be characterized from the threshold voltage (Vth ) variation
of the active devices (MOSFETs). In FDSOI-based 3-D ICs,
the coupling capacitance of the TOV+pad to active device
(C21,TOV+pad ) can be used to obtain the Vth variation, which is
illustrated in Fig. 7(a). In the ON-state of an FDSOI MOSFET,
the charge density (Qch ) in the channel is determined by both
the gate voltage (VG ) and the TOV voltage (VTOV ), i.e.,
dQch = Cox dVG + (κ|C21,TOV+pad |/AFET )dVTOV
(20)
where Cox is the gate oxide capacitance per unit area, C21 is the
TOV to active region coupling capacitance, AFET is the entire
area of the active region including both the channel region and
the source/drain region, and the factor of κ in (20) represents the
ratio of TOV+pad contributed electric flux density terminated
by the channel to the TOV+pad contributed average charge
density at the entire area (AFET ) of the active region. κ is
close to 0.5, due to the fact that about half of the electric flux is
terminated by the gate, whereas the other half of it is terminated
by the channel [see Fig. 7(a)] in the gate/channel region. Note
that the threshold voltage of an FDSOI MOSFET (Vth ) can
be defined as the particular VG so that the channel has certain
amount of charge. Let dQch = 0, the ratio between the variation
of Vth and VTOV can then be expressed as
(∂Vth /∂VTOV )FDSOI = −κ|C21,TOV+pad |/(AFET Cox ).
(21)
In bulk-CMOS-based 3-D ICs, g21,TSV (derived in [13]), the
voltage coupling coefficient of a TSV to an observation point
in the well (body of MOSFET), can be used to obtain the Vth
2
+αd2AB =β
r12
variation. The Vth of a MOSFET can be expressed as
2/3
f2 (xFET/dAB )−f2 (apl /dAB )
Vth = Vth0 + γ
2φF − VBS − 2φF
= zTOV,eq1·dAB·
2πεP21
≈ Vth0 − VBS · γ/ 2 2φF
(22)
(19)
128
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013
Fig. 9. Extraction of |∂Vth /∂VTOV |FDSOI from Silvaco ATLAS [18], and
|C21 |/(AFET Cox ) where C21 from ANSYS Mechanical [20], for the test
case in Fig. 8. According to (21), κ is extracted as 0.66.
Fig. 8. Schematic plots of a test structure to verify our model of the FDSOI
MOSFET Vth variation from VTOV : (a) top view (XY plane); (b) crosssectional view (XZ plane); (c) zoom-in cross-sectional view (YZ plane). The
Neumann boundary condition is applied for the simulation region boundaries,
except for those exposed to the electrical terminals of source, gate, drain, and
TOV. MOSFET gate length is 0.18 μm, and equivalent oxide thickness is 3 nm.
where γ is the body effect parameter, 2φF is the surface
potential parameter, and VBS is the body bias voltage. When
the series resistance from the body of MOSFET to its contacts
(RB ) and the total body capacitance to the source, drain,
and gate (CB ) satisfy RB 1/jωCB [RB and CB shown in
Fig. 7(b)], the ratio between the variation of threshold voltage of
MOSFET (Vth ) and TSV voltage (VTSV ) can be expressed as
(∂Vth /∂VTSV )bulk = g21,TSV · (∂Vth /∂VBS )
= −g21,TSV γ/ 2 2φF .
(23)
Note that the z-coordinate value of the MOSFET is close
to that of the power/ground lines. In addition, note that if the
planar MOSFETs are replaced by FinFETs, the ∂Vth /∂VTOV
or ∂Vth /∂VTSV would be much less since the channel is mostly
shielded by the gate.
We verify (21), our model of the FDSOI MOSFET Vth
variation from VTOV , through comparison of the results of a
test structure from TCAD simulation (Silvaco ATLAS [18]) and
from capacitance simulation (ANSYS Mechanical [20]) plus
(21). The test structure is shown in Fig. 8, where Fig. 8(a)–(c)
shows the schematic views of the structure from different
angles. Please note that the verification of (21) does not require
the presence of power/ground lines. Therefore, for simplicity
and easier convergence of TCAD simulation, in both Silvaco
ATLAS and ANSYS Mechanical simulations, we have not
included the periodical power/ground lines, and we assume a
Neumann boundary condition for the simulation region boundaries, except for those exposed to the electrical terminals of
source, gate, drain, and TOV. Due to this fact, the results here
(for 0.18-μm technology) cannot be used to compare the results
in Section V (for 22-nm technology) for a scaling analysis.
The geometrical parameters are shown in Fig. 8, where the
c2c horizontal distance between TOV and MOSFET (d) varies
from 3.5 to 11.5 μm. In ANSYS capacitance extraction, the
MOSFET is treated as a square area of 1 μm × 1 μm on top
of the simulation region boundary, whereas the gate overlap
regions [see Fig. 8(a) and (b)] are ignored.
The results are shown in Fig. 9, and the extracted κ is 0.66.
Due to the Neumann boundary condition in this simplified
test case in Fig. 8, the majority of the TOV-induced electric
flux density is terminated by the bottom (or +z face) of the
MOSFET, which implies that the factor of about 0.5 for κ does
not exist in this test case. On the other hand, such electric
flux density terminated by the channel of MOSFET is weaker
than that terminated by the source and drain regions (electric
flux density near the edges and corners of a conducting object
tends to be stronger) and is further weakened due to the electric
flux termination at source/channel and drain/channel sidewall
boundaries [see Fig. 8(c)]. Therefore, κ is actually less than 1,
or in other words, |C21,TOV+pad |/AFET from ANSYS simulation is larger than (∂Vth /∂VTOV )FDSOI from ATLAS simulation. Nevertheless, in a realistic situation, the TOV-induced
electric flux density terminated by the bottom of the MOSFET
is similar to that terminated by the top; hence, κ is less than the
value in the test case in Fig. 8 (or 0.66). In Section V, we assume
κ = 0.5, as is consistent with [15].
As for the scaling analysis of the TOV–MOSFET interaction,
if TOV and MOSFET are shrunk in the same ratio, C21 is
proportional to the technology node Lg (C21 ∝ Lg ). In such
situation, according to (21), AFET ∝ L2g and Cox ∝ L−s
g (0 <
s < 1), we find (∂Vth /∂VTOV )FDSOI ∝ Ls−1
g . In other words,
the TOV–FET interaction is more important when the technology shrinks. In addition, if the TOV shrinks slower than the
FET (which is most likely the case), the TOV–FET interaction
is even more important when the technology scales.
V. C OMPARISON OF TOV IN FDSOI AND
TSV IN B ULK CMOS
Using comparable sets of geometrical parameters, the TOV
in FDSOI and the TSV in bulk CMOS (without p+ buried
layer) are compared in terms of the impedance (Z11 ) and
Vth variation in MOSFETs. Fig. 10 shows the comparison
results. Here, Z11,TOV+pad and (∂Vth /∂VTOV )FDSOI are obtained from the analytical models in this paper (note that
Z11,TOV+pad = 1/jωCtotal,TOV+pad , and κ is assumed to be
XU AND BANERJEE: CAPACITANCE AND COUPLING NOISE OF TOVS IN FDSOI-BASED 3-D ICs
Fig. 10. Comparison between TOV+pad in FDSOI and TSV in bulk CMOS
in terms of (a) their impedance to the periodical power/ground lines (Z11 )
and (b) impact of their coupling on the Vth variation of a MOSFET in 22-nm
technology node. The geometrical parameters (length, width, height, and distance) in the case of TOV+pad in FDSOI are assumed to be 0.3× of those in
[15, Figs. 6 and 8], except that xFET = 1 μm and that the cross section of
power/ground lines is wpl = 0.4 μm and hpl = 0.15 μm, which are consistent
with the values in the case of TSV in bulk CMOS. The geometrical and material
parameters in [13, Fig. 6] are applied in the case of TSV in bulk CMOS in this
figure. In addition, Cox = 3.4 μF/cm2 , γ = 0.414 V1/2 , and 2φF = 1.02 V
are calculated from [24].
0.5). Z11,TSV and (∂Vth /∂VTSV )bulk are obtained from the
analytical results of Z11,TSV and g21,TSV in [13] and (23).4
The smaller size of TOVs results in much larger impedance
from TOV+pad in FDSOI than from TSV in bulk CMOS to
periodical power/ground lines [see Fig. 10(a)] and in (∂Vth /
∂VTOV )FDSOI < (∂Vth /∂VTSV )bulk at higher frequencies [see
Fig. 10(b)]. On the other hand, the Vth variation in MOSFET
from TOV+pad coupling in the case of FDSOI is independent
of frequency, due to the fact that there is no body contact in
FDSOI MOSFET, whereas in bulk CMOS, the body is connected to Vdd or Gnd through well resistance (RB ). Therefore,
(∂Vth /∂VTOV )FDSOI > (∂Vth /∂VTSV )bulk at lower frequencies [see Fig. 10(b)]. Note that the shunt impedance due to
body capacitance (1/jωCB ) becomes more dominant than RB
at very high frequencies. However, this is beyond the scope
of this paper. Therefore, (∂Vth /∂VTSV )bulk under very high
frequencies (> 15 GHz) is not shown in Fig. 10(b).
VI. M ODELING OF M ULTIPLE TOV S
AND ACTIVE D EVICES
Capacitance matrix (C matrix) of multiple TOVs (here,
“TOV” implies the conducting object of TOV and its pad
together) and active devices can be obtained from its inverse
(P matrix), where the P matrix elements describing the interaction between two conducting objects can be calculated without
consideration of other TOVs and active devices.
We label the subscripts of P matrix elements by the serial
numbers of TOVs and active devices: The subscript corresponding to TOV i is labeled as iTOV ; the subscript corresponding to active device k is labeled as kFET . Assuming
the periodical power/ground rails as the ground conductor, the
elements PiTOV ,iTOV (TOV self terms) and PkFET ,kFET (FET
self terms) can be obtained using the model in Section II
[i.e., (1), (2), (7), and (8)]. When TOV i and FET k are
4g
21,TSV and (∂Vth /∂VTSV )bulk are dependent on the parameters
in the bulk CMOS technology profile. For example, both g21,TSV and
(∂Vth /∂VTSV )bulk are approximately proportional to the well resistance (see
[13, eq. (10)]).
129
Fig. 11. To extract PiTOV ,i
between TOVs i and i with surrounding
TOV
periodical power/ground lines [shown in (a)], we treat the problem as the
interaction between an equivalent point charge and an equivalent observation
point with an equivalent ground plane [shown in (b)].
separated by power/ground line(s), the element PkFET ,iTOV for
the interaction between TOV i and FET k can be obtained using
the model in Section III [i.e., (2), (7), (8), (13), and (18)]. When
FET k and FET k are separated by power/ground line(s), the
model in Section III can be directly extended to the case of
. However, for the case of the interacthe element PkFET ,kFET
tion between TOV i and TOV i [separated by power/ground
line(s)], an empirical modification needs to be made in
(18) to obtain PiTOV ,iTOV , because the center of TOV+pad
can have a significantly different z-coordinate from that of the
power/ground lines. The slight modification is to let the term
zTOV,eq2
2
= d2AB · [f2 (xTOV /dAB ) − f2 (apl /dAB )]2 + ΔzTOV
(24)
substitute zeq2 in (18), where ΔzTOV is the z-coordinate difference of the centers of TOV+pad and the power/ground lines
(see [15, Fig. 6(a)] or Fig. 6 in this paper), and zTOV,eq2 is the
distance from the equivalent observation point to the equivalent
ground plane [see Fig. 11(b)]. The electric potential V (x, z, E)
due to periodical wires and external electric field strength |E|
[see Fig. 6(b)] should satisfy
V (xTOV , zTOV , |E|) ≈ zTOV,eq2 |E| .
(25)
Such empirical modification guarantees that zTOV,eq2 reduces to dAB [f2 (xTOV /dAB ) − f2 (apl /dAB )] when ΔzTOV
is small (when the TOV can be treated as in the same plane
as that of the power/ground lines), whereas zTOV,eq2 reduces
to ΔzTOV when ΔzTOV is large (when the TOV centroid is
far from the power/ground lines, the power/ground lines can be
simply treated as ground plane for calculating PiTOV ,iTOV ).
For the case of the interaction between TOVs i and i [located
between the same pair of power/ground lines, as in Fig. 11(a)],
we treat the periodical power/ground lines as equivalent ground
130
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 1, JANUARY 2013
coupling between TOV(+pad) and FET can be stronger than
that between two FETs, although the TOV(+pad)s and FETs
are separated by power/ground line(s). This is due to the fact
that the TOV(+pad)s are much bigger than the FETs.
VII. S UMMARY
Compact models for TOV capacitance and coupling capacitance between the TOV and active devices are developed
from basic electrostatic considerations and verified against a
3-D capacitance solver. The models in this paper and in [13]
are used to analyze TOV/TSV impedance to the periodical
power/ground lines (Z11 ) and their impact on MOSFET Vth
variation. The results show that TOVs in FDSOI have larger Z11
(indicating higher performance) and that the impact of TOVs in
FDSOI on Vth variation is less (more) at high (low) frequencies,
as compared with TSVs in bulk-CMOS-based 3-D ICs.
Fig. 12. Comparison of the results from our model with FastCap [17] for
(a) a test case of two TOV(+pad)s and two FETs with periodical power/ground
lines: (b) results of C1,1 (total capacitance from one TOV/pad to all other
conducting objects and periodical power/ground lines) and −C2,1 (mutual
capacitance between TOVs 1 and 2); (c) results of −C3,1 (mutual capacitance
between TOV 1 and FET 3), −C4,1 (mutual capacitance between TOV 1
and FET 4), and −C4,3 (mutual capacitance between FETs 3 and 4). The
surrounding dielectric has a dielectric constant of 4.0. The size of the active
device is 2 μm × 2 μm (assuming a multifinger MOSFET with a width of
2 μm for each finger). The centers of the TOV(+pad)s and FETs form a
rectangle. The c2c horizontal distance Δy is varied. The horizontal locations
of TOV(+pad)s and FETs are labeled in (a), and all the other geometrical
parameters of TOV(+pad)s and periodical power/ground lines in this test case
are the same as those in [15, Figs. 6 and 8]. The empirical parameter α = 0.5.
plane, as shown in Fig. 11(b). The TOVs are treated as equivalent source point charge and equivalent observation point,
which have the same x- and y-coordinates with the centroid of
TOVs. zTOV,eq1 is the distance from the equivalent source point
charge to the equivalent ground plane. zTOV,eq1 is given by
(13). zTOV,eq2 is the distance from the equivalent observation
point to the equivalent ground plane. zTOV,eq2 is given by (24).
Under such equivalence, PiTOV ,iTOV between TOVs i and i
(located between the same pair of power/ground lines) can be
obtained, i.e.,
1
· 1
PiTOV ,iTOV =
(zTOV,eq1 − zTOV,eq2 )2 + Δy 2
4πε
−1
(zTOV,eq1 + zTOV,eq2 )2 + Δy 2 . (26)
To briefly summarize, we use (2), (7), (8), (13), (16b), (24),
and (26) to obtain PiTOV ,iTOV for the case of the interaction
between TOVs i and i (located between the same pair of
power/ground lines). We use similar formulas for the counterpart of FETs k and k. The capacitance matrix C is obtained by
inverting P afterward.
Our model is verified against an electrostatic field solver, i.e.,
FastCap [17], for a test case of two TOV(+pad)s and two FETs
with periodical power/ground lines, as shown in Fig. 12. Our
model is shown to be accurate for the TOV total and mutual
capacitance and gives a reasonable estimation for the TOV to
FET coupling capacitance. Our results also demonstrate that the
A PPENDIX
E QUIVALENT C YLINDER OF AN E LLIPTIC C YLINDER
The surface equation of an ellipsoid centered at the origin
with semi-axes of a, b, and c can be expressed as
x2 /a2 + y 2 /b2 + z 2 /c2 = 1
(27)
where (x, y, z) is the coordinate on the ellipsoid surface. According to [22], if the surface charge density of an ellipsoid
(ξellipsoid ) is projected onto any of its symmetry planes, the
result is independent of the extent of the ellipse perpendicular
to the plane of projection (e.g., the projection of ξellipsoid on the
xy plane, i.e., ξxy , is independent of parameter c).
An infinitely long elliptic cylinder centered at the origin with
semi-axes of a and c is a special case of an ellipsoid, where the
surface equation can be expressed as
x2 /a2 + z 2 /c2 = 1.
(28)
Therefore, ξxy for the infinitely long elliptic cylinder is the
same as that for an infinitely long cylinder with a radius of a,
and ξxy can be estimated from the surface charge density of an
infinitely long cylinder (ξcylinder ). Due to the symmetry of a
cylinder, ξcylinder can be expressed as
ξcylinder = Q/(2πa)
(29)
where Q is the total charge per unit length of the infinitely long
cylinder. Therefore, ξxy for the infinitely long (elliptic) cylinder
can be expressed as
1 ξxy = Q/ a2 − x2 .
(30)
π
Hence, the electric potential of the conducting infinitely long
elliptic cylinder, i.e., Φ, can be expressed as
a
Φ=
−a
Q
1
√
ln
·
x2 + c2 (1 − x2 /a2 ) dx
π a2 − x2 2πε
= Q ln ((a + c)/2) /(2πε)
(31)
XU AND BANERJEE: CAPACITANCE AND COUPLING NOISE OF TOVS IN FDSOI-BASED 3-D ICs
where ε is the permittivity of the homogeneous dielectric
medium surrounding the elliptic cylinder.
On the other hand, the electric potential of a conducting infinitely long cylinder with a radius of r0 can be expressed as
Φ = Q ln(r0 )/(2πε).
(32)
Comparing (31) and (32), a conducting infinitely long elliptic
cylinder with semi-axes of a and c can be treated as an equivalent cylinder with a radius of r0 = (a + c)/2 (“equivalent”
implies same homogeneous medium self-capacitance).
R EFERENCES
[1] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A novel
chip design for improving deep-submicrometer interconnect performance
and systems-on-chip integration,” Proc. IEEE, vol. 89, no. 5, pp. 602–633,
May 2001.
[2] G. L. Loi, B. Agrawal, N. Srivastava, S.-C. Lin, T. Sherwood, and
K. Banerjee, “A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy,” in Proc. ACM/IEEE 43th
DAC, 2006, pp. 991–996.
[3] N. Sillon, A. Astier, H. Boutry, L. Di Cioccio, D. Henry, and P. Leduc,
“Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs,” in Proc. IEEE IEDM, 2008, pp. 595–598.
[4] F. Liu, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi, K. N. Chen,
X. Li, D. A. Dipaola, D. Brown, C. T. Ryan, J. A. Hagan, K. H. Wong,
M. Lu, X. Gu, N. R. Klymko, E. D. Perfecto, A. G. Merryman,
K. A. Kelly, S. Purushothaman, S. J. Koester, R. Wisnieff, and
W. Haensch, “A 300-mm wafer-level three-dimensional integration
scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding,” in Proc. IEEE IEDM, 2008, pp. 599–602.
[5] G. Katti, A. Mercha, J. Van Olmen, C. Huyghebaert, A. Jourdain,
M. Stucchi, M. Rakowski, I. Debusschere, P. Soussan, W. Dehaene,
K. De Meyer, Y. Travaly, E. Beyne, S. Biesemans, and B. Swinnen, “3D
stacked ICs using Cu TSVs and die to wafer hybrid collective bonding,”
in Proc. IEEE IEDM, 2009, pp. 357–360.
[6] A. W. Topol, D. C. La Tulipe, L. Shi, S. M. Alam, D. J. Frank,
S. E. Steen, J. Vichiconti, D. Posillico, M. Cobb, S. Medd, J. Patel,
S. Goma, D. DiMilia, M. T. Robson, E. Duch, M. Farinelli, C. Wang,
R. A. Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T. Kwietniak,
C. D’Emic, J. Ott, A. M. Young, K. W. Guarini, and M. Ieong, “Enabling
SOI-based assembly technology for three-dimensional (3D) integrated
circuits (ICs),” in IEDM Tech. Dig., 2005, pp. 352–355.
[7] J. A. Burn, B. F. Aull, C. K. Chen, C.-L. Chen, C. L. Keast, J. M. Knecht,
V. Suntharalingam, K. Warner, P. W. Wyatt, and D.-R. W. Yost, “A waferscale 3-D circuit integration technology,” IEEE Trans. Electron Devices,
vol. 53, no. 10, pp. 2507–2516, Oct. 2006.
[8] P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Previtali,
C. Tabone, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli,
F. Allain, V. Mazzocchi, D. Lafond, O. Thomas, O. Cueto, N. Bouzaida,
D. Fleury, A. Amara, S. Deleonibus, and O. Faynot, “Advances in 3D
CMOS sequential integration,” in Proc. IEEE IEDM, 2009, pp. 345–348.
[9] T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, and
R. Tummala, “Electrical modeling of through silicon and package vias,”
in Proc. IEEE 3DIC Syst. Integr., 2009, pp. 1–8.
[10] G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “Electrical modeling
and characterization of through silicon via for three-dimensional ICs,”
IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 256–262, Jan. 2010.
[11] C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC modeling and
performance analysis of through-silicon vias in 3-D ICs,” IEEE Trans.
Electron Devices, vol. 57, no. 12, pp. 3405–3417, Dec. 2010.
131
[12] C. Xu, V. Kourkoulos, R. Suaya, and K. Banerjee, “A fully analytical
model for the series impedance of through-silicon vias with consideration
of substrate effects and coupling with horizontal interconnects,” IEEE
Trans. Electron Devices, vol. 58, no. 10, pp. 3529–3540, Oct. 2011.
[13] C. Xu, R. Suaya, and K. Banerjee, “Compact modeling and analysis
of through-Si-via-induced electrical noise coupling in three-dimensional
ICs,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 4024–4034,
Nov. 2011.
[14] C. Xu, R. Suaya, and K. Banerjee, “Fast extraction of high-frequency
parallel admittance of through-silicon-vias and their capacitive couplingnoise to active regions,” in Proc. IEEE/MTT-S Int. Microw. Symp. Dig.,
Montréal, Canada, Jun. 17–22, 2012, pp. 1–3.
[15] C. Xu and K. Banerjee, “Compact capacitance and capacitive couplingnoise modeling of through-oxide vias in FDSOI based ultra-high density
3-D ICs,” in Proc. IEEE IEDM, 2011, pp. 817–820.
[16] A. R. Trivedi and S. Mukhopadhyay, “Through-oxide-via-induced backgate effect in 3-D integrated FDSOI devices,” IEEE Electron Device Lett.,
vol. 32, no. 8, pp. 1020–1022, Aug. 2011.
[17] K. Nabors and J. White, “FastCap: A multipole accelerated 3-D capacitance extraction program,” IEEE Trans. Comput.-Aided Design Integr.
Circuits Syst., vol. 10, no. 11, pp. 1447–1459, Nov. 1991.
[18] Silvaco ATLAS. [Online]. Available: www.silvaco.com/products/
device_simulation/atlas.html
[19] F. P. Incropera, D. P. DeWitt, T. L. Bergman, and A. S. Lavine, Fundamentals of Heat and Mass Transfer, 6th ed. Hoboken, NJ: Wiley, 2007,
pp. 209–210.
[20] ANSYS Inc., Canonsburg, PA, 2011, Release 13.0.
[21] J. A. Hernandes and A. K. T. Assis, “Electric potential due to an infinite
conducting cylinder with internal or external point charge,” J. Electrostat.,
vol. 63, no. 12, pp. 1115–1131, Oct. 2005.
[22] K. T. McDonald, “Conducting ellipsoid and circular disk,” Princeton
Univ., Princeton, NJ. [Online]. Available: http://puhep1.princeton.edu/
~mcdonald/examples/ellipsoid.pdf
[23] J. D. Jackson, Classical Electrodynamics, 3rd ed. New York: Wiley,
1998, ch. 1–4, pp. 1–131.
[24] Predictive Technology Model (PTM). [Online]. Available: http://www.
eas.asu.edu/~ptm/
Chuan Xu (S’08–M’12) received the Ph.D. degree in electrical engineering from the University of
California, Santa Barbara.
He is currently with Maxim Integrated,
Beaverton, OR.
Kaustav Banerjee (S’92–M’99–SM’03–F’12) is
currently a Professor with the University of
California, Santa Barbara. He is one of five engineers
worldwide to receive the Friedrich Wilhelm Bessel
Research Award (2011) from the Alexander von
Humboldt Foundation, Germany.