supervia

Relieving Local Metal Layer Congestion Using Super-Via
Device & Design Interface
Student Photo
Saptadeep Pal, Yasmine Badr, Puneet Gupta, UCLA
Hyein Lee, Kwangsoo Han, Andrew Kahng, UCSD
[email protected]
Workshop
April 15, 2016
Possible Reasons for Min Area Rule
Motivation
Impact of Minimum Area Rule
●  Lithography
○  Patterning small polygons difficult for sub-20nm node.
○  Multiple Patterning improves pitch but not minimum
achievable polygon area
●  Deposition
65nm
45nm
28nm
○  Deposition of uniform barrier/seed layer difficult
○  PVD/CVD/electroplating used for deposition
16 nm
○  Minimum trench area required
●  Minimum area rule ↑ ➡ Via blockage ↑➡Congestion↑
●  CMP
○  Hardness mismatch between Cu and SiOX
○  Difficult to optimize for small metal polygons
●  Via blockage on M2 : 11% (3x) & 18% (5x)
●  MinArea rule shows increasing trend in newer nodes
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Do We Need Supervia in all layers?
minArea
Rule
Utilization with rule imposed
on all Layers
Utilization with rule not
imposed on M2
0.95 ((MIPS) 0.91 (AES)
0x
0.95 (MIPS)
0.91 (AES)
3x
0.89 (MIPS)
0.85 (AES) 0.93 (MIPS)
5x
0.86 (MIPS)
0.78 (AES) 0.91 (MIPS)
0.88 (AES)
0.88 (AES)
Utilization with rule not
imposed on M2 and M3
0.95 (MIPS)
0.91 (AES)
0.95 (MIPS)
0.9 (AES)
0.94 (MIPS)
0.9 (AES)
●  MinArea rule primarily impacts M2 and M3 congestion.
A 3D-mesh graph
Chip Level Solution (Encounter/OA Flow)
Chip-­‐level Solu-on for Super-­‐Via Inser-on (WIP) ○  Horizontal and vertical tracks
● Metal layers
● A routed net = a set of edges
t
Commercial PR tools don’t
allow via spanning multiple
cuts layers
Using OpenAccess, find the nets which contains super-­‐via and also all other metal segments sa-sfy minArea rule Make these nets as fixed and delete all other nets ● Pin shape
● Objective: Find an optimal routing for a given set of nets
under design rule constraints
● Subject to
No Decrease U-liza-on 5
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Objective
c: cost, e: edge, f: flow
New Constraints
● EOL extension
○  Create EOL variable l, which represent EOL options
•  fi,jk variable represents a flow on via,
where xj = xi, yj = yi and zj = zi ± 1
→ Minimize cost
→ Flow conservation (= connection)
→ Edge is taken when there is a flow
Routing constraints
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Clip-based Area Cost Estimation
Results and Discussion
•  OptRouter ➡Routability
Analysis
●  6% utilization benefit for both AES and MIPS minArea = 3x.
•  3x, 5x min area rules
●  For sub-10nm nodes, expected utilization benefit is 10 ~ 15%
•  Feasibility ➡ Area cost: Count the minimum number of additional
routing tracks which makes an infeasible clip feasible
•  lr2,ik + lr1,ik + lr0,ik + ll0,ik + ll1,ik + ll2,ik ≥ fi,jk
● Minimum area rule
○  Given min area M,
→ If a via is placed at i, one of EOL
extension options must be picked
● Super-Via
•  fi,jk, where j = (xi, yi zi – 1) and fi,j’k, where j’ = (xi, yi, zi + 1)
•  lr2,ik + lr1,ik + lr0,ik + ll0,ik + ll1,ik + ll2,ik ≥ fi,jk - fi,j’k
→ If there are two aligned consecutive vias, min area rule
is not applied for intermediate layer
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Future Goals
●  Develop a scalable full chip supervia-aware routing solution
●  Analysis of benefits coming from supervia with area larger than
that of a normal via
●  Supervia layers ↑, cost ↑; M1-M3 and M2-M4 should suffice
•  Tracks are inserted between the most
critical pins
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Use Opt-­‐Route to Re-­‐route clips Final Layout + more constraints for design rules
●  Analyse and understand the supervia fabrication process
10x1
0
Clip A
No For each net routing
[HanKL15] K. Han, A. B. Kahng and H. Lee, "Evaluation of BEOL Design Rule Impacts Using an Optimal ILP-Based
Detailed Router", Proc. ACM/IEEE Design Automation Conf., 2015..
Yes Localize problem to layout clips Optimal ILP-based Detail Router [HanKL’15]
○  Unidirectional routing
○  Via shape
○  Minimum area rule (new constraint)
○  End-of-line extension (new constraint)
○  Super via (new constraint)
•  Total nine clips are tested; #layers = 5
•  5x min area rule, 4 out of 9 clips feasible
with SV, zero clips feasible without SV
•  Average area benefit of SV = 1.25 tracks
Feasible? ll2,ik ll1,ik ll0,ik lr1,ik
lr2,ik
Available
layers
•  Initial results with AES, 7nm library
Solve LP for Inser-on of Super Via & Enforcing Min Area Rule (Layout-­‐Compac-on Approach) Utilization benefit of 6%
is achieved for
minArea=3x routing
Run PR using minArea=N*(minWidth) Yes Final Layout Horizontal
tracks
Do PR using minArea=(minWidth)2 Do PR using minArea=(minWidth)2 Feasible? Vertical tracks
●  Sub-16nm node is expected to have minArea > 6x
3
4
● Routing resources
●  Utilizations drops 12% for minArea > 5x
2
●  Supervia between M1 & M3 and M2 & M4 gives most
benefit
Optimal ILP-based Detail Router [HanKL’15]
●  MinArea Rule ↑ , Utilization ↓ , Area ↑
Clip B
Clip A + 1 track
Clip C
Clip A + 2 tracks
# Feasible
clips
●  Supervias span two layers, aspect ratio ↑
●  Larger area required for supervia to maintain aspect ratio
(%)
3x, SV
9
100%
3x, noSV
9
100%
5x, SV
4
44%
5x, noSV
0
0%
5x, noSV + 1 track
3
33%
5x, noSV + 2 tracks
4
44%
●  ALD for barrier/ seed layer deposition can help achieve
high aspect ratio
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●  Exploring supervia for standard cell routing for potential
routability and pin-access benefits
Acknowledgement
Sponsored by Applied Materials, ARM, ASML, Global
Foundries, IBM, Intel, KLA-Tencor, Marvell Technology,
Mentor Graphics, Panoramic Tech, Photronics,
Qualcomm, SanDisk and Tokyo Electron.
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