Digital Techniques in Frequency Synthesis A Thesis

Transcription

Ain Shams University
Faculty of Engineering
Electronics and Communications Department
Digital Techniques in Frequency Synthesis
A Thesis
Submitted in partial fulfillment for the requirements of Master of Science
degree in Electrical Engineering
Submitted by:
Mohammed Ibrahim Ibrahim El-Shennawy
B.Sc. of Electrical Engineering
(Electronics and Communications Department)
Ain Shams University, 2004.
Supervised by:
Dr. Safwat Mahrous Mahmoud
Dr. Emad El-Din Mahmoud Hegazi
Dr. Hani Fikry Ragai
Cairo 2011
Curriculum Vitae
Name: Mohammed Ibrahim Ibrahim El-Shennawy
Date of Birth: 16/11/1981
Place of Birth: Giza, Egypt
First University Degree: B.Sc. in Electrical Engineering
Name of University: Ain Shams University
Date of Defense: 31st of July 2011
ii
Statement
This dissertation is submitted to Ain Shams University for the degree of Master of Science
in Electrical Engineering (Electronics and Communications Engineering).
The work included in this thesis was carried out by the author at the Electronics and
Communications Engineering Department, Faculty of Engineering, Ain Shams University,
Cairo, Egypt.
No part of this thesis was submitted for a degree or a qualification at any other university or
institution.
Name: Mohammed Ibrahim Ibrahim El-Shennawy
Date: 31/7/2011
iii
Acknowledgements
Thanks to Allah for the completion of this work. I would like to dedicate it to all who have
encouraged me throughout my study & industrial work; especially I would like to thank my
supervisors: Dr. Safwat Mahrous, Dr. Emad Hegazi & Dr. Hani Fikry; my examining
committee: Dr. Khaled Sharaf & Dr. Abdel-Halim Shousha; my managers: Tarek El-Esseily &
Ahmed Saad; my colleagues: Hossam Ali & Ahmed Hassan Fahmy; my family & my wife who
I could never give her what she deserves. She always supported me and pushed my spirits up.
I am really grateful to her.
Mohammed Ibrahim Ibrahim El-Shennawy
Electrical and Communications Department
Faculty of Engineering
Ain Shams University
Cairo, Egypt
2011
iv
Abstract
Mohammed Ibrahim Ibrahim El-Shennawy, Digital Techniques in Frequency Synthesis
Faculty of Engineering, Ain Shams University, 2011
The thesis contains a study for some Digital Techniques in Frequency Synthesis
that makes the use of an All Digital PLL possible. At the heart of the All Digital PLL lies a
Digitally Controlled Oscillator which deliberately avoids any analog tuning voltage
controls. We address two of the main issues of the Digitally Controlled Oscillator; that is
its center frequency (fDCO) variations & tuning gain (KDCO) variations.
To mitigate the center frequency variations, we propose a new fast automatic
tuning algorithm for LC based oscillators. The proposed algorithm is verified over a wide
range of initial Digitally Controlled Oscillator frequencies & phases to guarantee robust
operation over all process corner variations with the worst case tuning time being only
7.2µsec.
To mitigate tuning gain variations, we study a fast tuning gain estimation &
calibration algorithm. This tuning gain calibration makes it possible to use a two point
modulation scheme to transmit Frequency Shift Keying data at symbol rates much
higher than the loop bandwidth upto the Nyquist frequency of half the reference
frequency.
We use a Verilog model to verify the successful All Digital PLL functionality &
performance transitioning from reset to center frequency automatic tuning to tuning
v
gain estimation & calibration to Frequency Shift Keying data transmission. Also when
used as a local oscillator, the implemented All Digital PLL has spurious tones at only 98dBc.
Key words: All Digital PLL, Digitally Controlled Oscillator, Automatic Tuning,
Tuning Gain Estimation, Tuning Gain Calibration, Two Point Modulation, Frequency Shift
Keying.
vi
Summary
The thesis contains a study for some Digital Techniques in Frequency Synthesis
that makes the use of an All Digital PLL possible. All Digital PLLs have its loop control
circuitry implemented in a fully digital manner. When implemented in a digital deep sub
micrometer CMOS process, the All Digital PLL appears more advantageous over
conventional charge-pump-based PLLs, since it exploits the signal processing
capabilities of digital circuits and avoids relying on the fine voltage resolution of analog
circuits.
In an All Digital PLL, the conventional phase/frequency detector, charge pump
and RC loop filter are replaced by a time-to-digital converter and a simple digital loop
filter. While at the heart of the All Digital PLL lies a Digitally Controlled Oscillator which
deliberately avoids any analog tuning voltage controls.
The Digitally Controlled Oscillator however remains the only building block of
the All Digital PLL whose parameters are subject to variations due to fabrication process
variations since it is in essence a Radio Frequency LC based Oscillator that doesn’t use
varactors. The digital automatic tuning & calibration techniques required to mitigate
these variations are the scope of this thesis.
Namely, we address two of the main issues of the Digitally Controlled Oscillator;
that is its center frequency (fDCO) variations & tuning gain (KDCO) variations.
To mitigate the center frequency variations, we propose a new fast automatic
tuning algorithm for LC based oscillators. The new idea is presented, it depends on a
binary search sequence where in each search iteration the reference & oscillator clocks
vii
are put into a race that is terminated once we know the faster clock thus minimizing the
tuning time needed compared to other tuning algorithms with fixed search times. The
proposed algorithm is verified over a wide range of initial Digitally Controlled Oscillator
frequencies & phases to guarantee robust operation over all process corner variations
with the worst case tuning time being only 7.2µsec.
To mitigate tuning gain variations, we study a fast tuning gain estimation &
calibration algorithm. It makes use of the fact that since the loop control is now digital, it
is easier to estimate the tuning gain just in time by introducing a known frequency step
to the All Digital PLL input & monitoring the change on the Digital Controlled Oscillator
tuning input. This tuning gain calibration makes it possible to use a two point
modulation scheme to transmit Frequency Shift Keying data at symbol rates much
higher than the loop bandwidth upto the Nyquist frequency of half the reference
frequency.
The All Digital PLL together with the center frequency automatic tuning
algorithm & the tuning gain estimation & calibration algorithm are all modeled &
integrated in Verilog. We use this model to verify the successful All Digital PLL
functionality & performance transitioning from reset to center frequency automatic
tuning to tuning gain estimation & calibration to Frequency Shift Keying data
transmission. Also when used as a local oscillator for receivers, the implemented All
Digital PLL has spurious tones less than -98dBc.
The thesis contains six chapters:
In Chapter 1 we present the motivation behind this work and a brief
introduction to the different frequency synthesis techniques.
In Chapter 2, we present the basics of the All Digital PLL, we show its main
building blocks and principle of operation.
viii
In Chapter 3, we show how we model the various All Digital PLL building blocks
using Verilog, we build a simple All Digital PLL model and use a simple frequency plan to
understand in more depth the All Digital PLL operation.
In Chapter 4, we study the first of the main problems of LC Digitally Controlled
Oscillators which is the center frequency variations over process variations. We
introduce a fast automatic tuning algorithm for these oscillators with multiple tuning
curves which we published recently. Many practical implementation issues are shown
along with their solutions.
In Chapter 5, we study the other main problem of LC Digitally Controlled
Oscillators which is its tuning gain variations also across process variations. We explain
a method of estimating the gain of the Digitally Controlled Oscillator. By executing the
calculation algorithm just-in-time at the beginning of every packet, the Digitally
Controlled Oscillators gain can be conveniently tracked and compensated.
In Chapter 6, we integrate the introduced Digitally Controlled Oscillator autotuning algorithm and tuning gain estimation and normalization algorithm with the All
Digital PLL model introduced in Chapter 3 and we show how these algorithms are
incorporated in sequence to prepare the All Digital PLL to be used as a Frequency Shift
Keying transmitter.
ix
Contents
Chapter 1 .............................................................................................................................. 1
Introduction .......................................................................................................................... 1
1.1. Motivation .................................................................................................................. 1
1.2. Frequency Synthesis ................................................................................................... 2
1.3. Frequency Synthesis Techniques ................................................................................ 3
1.3.1.
Direct Analog Synthesis ................................................................................. 3
1.3.2.
Direct Digital Synthesis ................................................................................. 4
1.3.3.
Indirect Synthesis Using Phase Locking ......................................................... 6
1.3.4.
Hybrid Structure Frequency Synthesis............................................................ 7
1.4. Frequency Synthesizers for Mobile Communications ................................................. 8
1.4.1.
Integer-N PLL Architecture ......................................................................... 10
1.4.2.
Fractional-N PLL Architecture ..................................................................... 10
1.4.3.
Toward an All-Digital PLL Approach .......................................................... 17
1.5. Thesis Outline .......................................................................................................... 18
Chapter 2 ............................................................................................................................ 19
ADPLL Basics .................................................................................................................... 19
2.1. Introduction .............................................................................................................. 19
2.2. ADPLL System ........................................................................................................ 21
2.3. Phase Domain Operation .......................................................................................... 22
2.4. Reference Clock Retiming ........................................................................................ 24
2.5. Phase Detection ........................................................................................................ 26
2.6. Modulo Arithmetic of Phase Domain Signals ........................................................... 27
x
2.7. Discrete Time Z-Domain Model ............................................................................... 29
2.8. Linear S-Domain Approximation .............................................................................. 31
2.9. Summary .................................................................................................................. 32
Chapter 3 ............................................................................................................................ 33
ADPLL Modeling ............................................................................................................... 33
3.1. Introduction .............................................................................................................. 33
3.2. ADPLL Building Blocks .......................................................................................... 34
3.3. Synchronous Counter with Reset Model ................................................................... 35
3.4. Sampler Model ......................................................................................................... 36
3.5. Synchronizer Model ................................................................................................. 37
3.6. Phase Detector Model ............................................................................................... 38
3.7. DCO Model .............................................................................................................. 39
3.8. ADPLL Top Level Model......................................................................................... 40
3.9. ADPLL Top Level Test Bench ................................................................................. 41
3.10. TDC Model ............................................................................................................ 43
3.11. Summary ................................................................................................................ 45
Chapter 4 ............................................................................................................................ 46
DCO Automatic Tuning ...................................................................................................... 46
4.1. Introduction .............................................................................................................. 46
4.2. Existing Automatic Tuning Algorithms .................................................................... 47
4.3. Proposed Automatic Tuning Algorithm .................................................................... 49
4.4. Fully Custom Block: ................................................................................................. 50
4.4.1.
External High Speed Divider by 4: ............................................................... 50
4.5. Fully Digital Block: .................................................................................................. 50
4.5.1.
Multiplexer: ................................................................................................. 50
4.5.2.
Clock Gating: ............................................................................................... 50
4.5.3.
Synchronizer: ............................................................................................... 51
4.5.4.
Divider by 4: ................................................................................................ 51
4.5.5.
Synchronous Counter with Reset:................................................................. 52
4.5.6.
Bus Synchronizer: ........................................................................................ 52
4.5.7.
Comparator: ................................................................................................. 52
4.6. Algorithm Execution Sequence ................................................................................. 54
xi
4.7. Algorithm Verilog Code ........................................................................................... 55
4.8. Simulation Results .................................................................................................... 69
4.9. Summary .................................................................................................................. 71
Chapter 5 ............................................................................................................................ 72
KDCO Calibration within the ADPLL ................................................................................... 72
5.1. Introduction .............................................................................................................. 72
5.2. DCO Transfer Function & Gain ................................................................................ 75
5.3. DCO Gain Normalization ......................................................................................... 75
5.4. Predictive/Closed PLL Operation ............................................................................. 76
5.5. DCO Gain Estimation using the ADPLL .................................................................. 78
5.6. Effect of Incorrect KDCO Estimation .......................................................................... 81
5.7. Algorithm Verilog Code ........................................................................................... 85
Chapter 6 ............................................................................................................................ 92
The ADPLL as an FSK Transmitter .................................................................................... 92
6.1. Introduction .............................................................................................................. 92
6.2. Test Bench Verilog Code .......................................................................................... 93
6.4. Spurious Tones ....................................................................................................... 106
Conclusion ........................................................................................................................ 110
Future Work...................................................................................................................... 112
References ........................................................................................................................ 113
xii
List of Figures
Figure ‎1-1 Frequency Synthesis ............................................................................................ 2
Figure ‎1-2 Possible outputs of a synthesizer: sinusoidal and digital waveforms ..................... 3
Figure ‎1-3 Direct digital frequency synthesis. ........................................................................ 4
Figure ‎1-4 Phase accumulator front end of a DDFS system with frequency modulation ......... 5
Figure ‎1-5 Phase Locked Loop .............................................................................................. 6
Figure ‎1-6 DDFS-PLL hybrid ............................................................................................... 7
Figure ‎1-7 Typical charge-pump-based PLL for RF wireless applications. ............................ 9
Figure ‎1-8 Alternating divide ratio of fractional-N PLL....................................................... 11
Figure ‎1-9 Periodic and deterministic phase error in a fractional-N PLL .............................. 12
Figure ‎1-10 Fractional-N PLL incorporating phase interpolation ......................................... 12
Figure ‎1-11 Fractional-N synthesizer using a ΣΔ-modulated clock divider .......................... 13
Figure ‎1-12 MASH-3 ΣΔ digital modulator divider ............................................................. 14
Figure ‎1-13 ΣΔ-divided clock: clock output spectrum (left), phase spectrum (right) ............ 15
Figure ‎1-14 Modulating a wideband fractional-N synthesizer .............................................. 16
Figure ‎1-15 ADPLL-based RF frequency synthesizer .......................................................... 17
Figure ‎2-1 ADPLL-based RF frequency synthesizer. ........................................................... 21
Figure ‎2-2 Concept of synchronizing the clock domains by retiming the FREF. .................. 23
Figure ‎2-3 Hardware implementation of the variable phase & the reference phase .............. 25
Figure ‎2-4 Fractional-N division ratio timing example with N = 2+(1/4) ............................ 25
Figure ‎2-5 Modulo arithmetic of the reference and variable phase registers ......................... 28
Figure ‎2-6 Rotating vector interpretation of the reference and variable phases. .................... 28
Figure ‎2-7 z-domain model of the type-II ADPLL. .............................................................. 29
xiii
Figure ‎2-8 Linear s-domain model of the type-II ADPLL. ................................................... 31
Figure ‎3-1 ADPLL main building blocks............................................................................. 34
Figure ‎3-2 Synchronous counter with reset model ............................................................... 35
Figure ‎3-3 Sampler model ................................................................................................... 36
Figure ‎3-4 Synchronizer model ........................................................................................... 37
Figure ‎3-5 Phase detector model.......................................................................................... 38
Figure ‎3-6 DCO model........................................................................................................ 39
Figure ‎3-7 ADPLL top level model. .................................................................................... 40
Figure ‎3-8 ADPLL top level test bench. .............................................................................. 41
Figure ‎3-9 ADPLL top level simulation results ................................................................... 42
Figure ‎3-10 TDC functionality example with FCW = 2+(1/4) ............................................ 44
Figure ‎3-11 TDC Model ...................................................................................................... 44
Figure ‎3-12 TDC model waveforms. ................................................................................... 45
Figure ‎4-1 DCO Auto Tuning simplified block diagram ...................................................... 47
Figure ‎4-2 Proposed DCO Auto Tuning block diagram ....................................................... 51
Figure ‎4-3 Proposed DCO Auto Tuning control signals timing diagram .............................. 55
Figure ‎4-4 Simulated Final DCO Frequency vs. Regression Iteration .................................. 70
Figure ‎4-5 Simulated Tuning Curve Number vs. Regression Iteration ................................. 71
Figure ‎4-6 Simulated Tuning Time vs. Regression Iteration ................................................ 71
Figure ‎5-1 Normalized DCO block diagram ........................................................................ 76
Figure ‎5-2 Two point modulated ADPLL model ................................................................. 77
Figure ‎5-3 DCO gain estimate by measuring tuning word change in response to a fixed
frequency jump. .................................................................................................................. 79
Figure ‎5-4 DCO gain estimation flowchart. ......................................................................... 80
Figure ‎5-5 Complex plane location of the H(z) zero and pole movement with different values
of the DCO gain estimate accuracy r. .................................................................................. 82
Figure ‎5-6 Direct modulation transfer function H(f) where f ≈ (fR/2π)(z-1) for f << fR, with
different values of the DCO gain estimate accuracy r according to [Staszewski 06]. ............ 84
Figure ‎5-7 Actual direct modulation transfer function H(f) where f ≈ (fR/2π)(z-1) for f << fR,
with different values of the DCO gain estimate accuracy r according to this work. .............. 85
Figure ‎5-8 KDCO Calibration Simulation Result ................................................................... 91
Figure ‎6-1 ADPLL-based RF frequency synthesizer when used as an FSK transmitter ........ 93
xiv
Figure ‎6-2 ADPLL output in the various modes of operation ............................................... 97
Figure ‎6-3 Zoom in on the DCO Autotuing period .............................................................. 98
Figure ‎6-4 Zoom in on the KDCO estimation period .............................................................. 99
Figure ‎6-5 2.4GHz Center frequency at the start of KDCO estimation ................................. 100
Figure ‎6-6 1MHz positive frequency shift ......................................................................... 101
Figure ‎6-7 1MHz negative frequency shift ........................................................................ 102
Figure ‎6-8 2Mbps data transmission. ................................................................................. 103
Figure ‎6-9 Zoom in on the FSK data transmission ............................................................. 104
Figure ‎6-10 FSK transmission at fR/2 ................................................................................ 105
Figure ‎6-11 Zoom in on the modulating part of the NTW .................................................. 107
Figure ‎6-12 FFT of the modulating part of the NTW ......................................................... 108
Figure ‎6-13 ADPLL measured output spectrum from [Staszewski 03a] ............................ 109
xv
List of Tables
Table ‎3-1 ADPLL simple frequency plan ............................................................................ 42
Table ‎4-1 Regression Test Bench Results Summary ............................................................ 70
Table ‎6-1 Measured key synthesizer performance from [Staszewski 03a] .......................... 109
xvi
List of Symbols
.f
Fractional Part of the Frequency Division Ratio.

Proportional Loop Gain of the Loop Filter.
ACF z 
Forward Transfer Function of the Compensating Feed.
ADF z 
Forward Transfer Function of the Direct Feed.
bt 
The Sigma Delta modulator output in the time domain.
 CF z 
Feed Back Transfer Function of the Compensating Feed.
 DF z 
Feed Back Transfer Function of the Direct Feed.
cnt _ div
Output word of the divided DCO counter.
cnt _ ref _ s
Output word of the reference counter.
d k 
Oscillator Tuning Word.
f
DCO frequency step corresponding to an Oscillator Tuning Word step.
dco _ autotune _ N
DCO Coarse Tuning Word output of the Auto Tuning Algorithm.
dco _ cal _ done
DCO Automatic Tuning done signal.
E  fV 
Average DCO frequency output.
E q3 z 
Quantization noise of the 3rd stage of the ΣΔ modulator in the z-domain.
 k 
TDC Output after DCO Period Normalization.
f DCO
Frequency difference between the actual & required DCO frequencies.
xvii
fR
Reference Frequency.
f out
Synthesized Frequency.
f vco
VCO Output Frequency.
f DDFS
Direct Digital Frequency Synthesizer Output Frequency.
f RF
Hybrid Frequency Synthesizer RF Output Frequency.
f (OTW )
DCO frequency as a function of the Oscillator Tuning Word.
fo
DCO Center Frequency.
f DIV
Divided DCO Frequency.
f DCO
DCO Frequency.
f div4
DCO Frequency Divided by 4.
f div4 _ g
DCO Frequency Divided by 4 after Clock Gating.
f div
f div4 _ g Divided by 4.
f ref
Reference Frequency Signal.
f ref _ g
Reference Frequency Signal after Clock Gating.
f ref _ s
Reference Frequency Signal after Clock Gating & Retiming.
H ol z 
Open Loop Transfer Function in the z-domain.
H cl z 
Closed Loop Transfer Function in the z-domain.
H ol s 
Open Loop Transfer Function in the s-domain.
H cl s 
Closed Loop Transfer Function in the s-domain.
H CF z 
Closed Loop Transfer Function of the Compensating Feed.
xviii
H DF z 
Closed Loop Transfer Function of the Direct Feed.
i
DCO clock transition index.
k
Reference clock transition index.
K vco
VCO Tuning Gain.
K DCO
DCO Tuning Gain.
K̂ DCO
Estimated DCO Tuning Gain.
K nDCO
Normalized DCO Tuning Gain.
L f 
Phase Noise vs. Frequency.
m
The number of the ΣΔ modulator stages.
mid _ OTW
Centre Oscillator Tuning Word.
N avg
Average Division Ratio.
N div
Integer Instantaneous Division Ratio.
N div z 
Integer Instantaneous Division Ratio in the z-domain.
Ni
Integer part of the FCW.
Nf
Fractional part of the FCW.
N
ADPLL Multiplication Factor, also defined as FCW.
N dco
DCO Tuning Word.
N RO
Number of cycles until roll over occurs.
OV1
Overflow (carry output) of the 1st accumulator of the ΣΔ modulator.
 E k 
Phase Error.
V
Conventional Variable Phase.
xix
R
Conventional Reference Phase.

Integrator Gain of the Loop Filter.
r
DCO Gain Estimation Accuracy.
RR k 
Reference Phase Accumulator Output.
RV k 
Sampled DCO Phase Accumulator Output.
RV i 
DCO Phase Accumulator Output.
reset _ out _ div
Reset signal for the blocks driven by the f div clock.
reset _ out _ ref _ s
Reset signal for the blocks driven by the f ref _ s clock.
V
Dimensionless Variable Phase.
R
Dimensionless Reference Phase.
tV
DCO clock transition timestamps.
TV
DCO clock period.
tR
Reference clock transition timestamps.
TR
Reference clock period.
to
Initial time offset between the DCO & reference clocks.
TDIV
Divided DCO clock period.
n
Natural Oscillating Frequency.
W
Word Length of an Accumulator.
WI
Word Length of the Integer part of the accumulator
WF
Word Length of the Fractional part of the accumulator

Damping Factor.
xx
List of Abbreviations
ADPLL
All Digital Phase Locked Loop.
CKV
DCO Output Clock.
CKR
Retimed Reference Clock.
DCO
Digitally Controlled Oscillator.
FCW
Frequency Command Word.
NTW
Normalized Oscillator Tuning Word.
nDCO
Normalized DCO.
OTW
Oscillator Tuning Word.
PHE
Phase Error.
TDC
Time to Digital Converter.
UI
Unit Interval.
xxi
Chapter 1
Introduction
In this chapter we present the motivation behind this work, briefly introduce the different
frequency synthesis techniques & finally we present the thesis outline.
1.1. Motivation
With the explosive growth of the wireless communication industry, research related to
communication circuits and architectures has received a great deal of attention. The major
issues being addressed are low-cost, low-voltage, and low-power designs, which combine
necessary performance with the ability to be manufactured economically in high volumes.
The use of deep-submicrometer CMOS processes allows for an unprecedented degree of
scaling and integration in digital circuitry, but complicates the implementation of traditional RF
and analog circuits. Consequently, a new research focuses on finding digital architectural
solutions to these integration problems. Modern transceivers are expected to operate over a
Chapter 1 Introduction
2
wide range of frequencies. Although crystal oscillators offer high spectral purity, they cannot
be tuned over a wide range of frequencies. Hence, some form of frequency synthesis is
employed by these transceivers.
1.2. Frequency Synthesis
The term frequency synthesizer generally refers to an active electronic device Figure 1-1 that
accepts some frequency reference (FREF) input signal of a very stable frequency fR and then
generates frequency output as commanded by the frequency command word (FCW), whereby
the stability, accuracy, and spectral purity of the output correlate with the performance of the
input reference. The desired value of the output frequency is an FCW multiple (generally, a
real number) of the reference frequency according to the equation
f out  FCW  f ref
Frequency
Reference
Frequency
Synthesizer
(fref)
(1.1)
Synthesized
Frequency
(fout)
FCW
Frequency Command Word
Figure 1-1 Frequency Synthesis
Interestingly, the definition above does not specify the shape of the synthesized output. It
could be a sinusoid or a rectangular signal (Figure 1-2). The frequency and phase information
is preserved in either a continuous-time waveform fit to the ideal sinusoid or in edge transition
times, respectively. A clear advantage of the rectangular digital signal is that it is more useful
for digital CMOS process technology.
3
time
HI=1
HI=1
LO=0
ti
LO=0
ti+1
ti+2
time
Figure 1-2 Possible outputs of a synthesizer: sinusoidal and digital waveforms
1.3. Frequency Synthesis Techniques
There are three major conventional frequency synthesis techniques:

Direct analog mix/filter/divide

Direct digital

Indirect or phase-locked loop

Hybrids: any combination of the three methods above
Each of these methods has its own advantages and disadvantages; hence, each application
requires selection based on the most acceptable combination of compromises.
1.3.1. Direct Analog Synthesis
Direct analog synthesis, also called mix/filter/divide, uses frequency multipliers, dividers,
and other mathematical manipulations to produce the desired new frequency [Reinhardt 86].
The process is called direct because the error correction process is avoided; hence, the quality
of the output correlates directly with the quality of the input. Phase noise is typically excellent
because the direct process and switching speed can be very fast. Unfortunately, a broadband
mix/filter/divide synthesizer requires many references, which makes it extremely expensive.
Because of its high cost and high power disadvantages, the direct analog synthesis method is
used primarily in instrumentation and is not practical for low-power portable applications such
as mobile communication terminals.
4
1.3.2. Direct Digital Synthesis
Direct digital frequency synthesis (DDFS) is the most recently developed frequency
synthesis technique, dating from the early 1970s [Tierney 71]. A DDFS system uses logic and
memory to construct the desired output signal digitally, and a data conversion device [a
digital-to-analog converter (DAC)] to convert it from the digital to the analog domain, as
shown in Figure 1-3. Therefore, the DDFS method of constructing a signal is almost entirely
digital, and the precise amplitude, frequency, and phase are known and controlled at all times.
For these reasons, the switching speed is extremely high, but the power consumption could be
excessive at high clock frequencies. The DDFS method is not entirely digital in the true sense
of the word since it requires a DAC and a low-pass filter (LPF) to attenuate spurious
frequencies produced by the digital switching. In addition, a very stable frequency reference
clock of at least three times the output frequency is required. Considering this and the fact that
the DAC and LPF might be difficult to build and would consume excessive amount of power
at gigahertz operational frequency, the DDFS solution is not acceptable for radio-frequency
(RF) applications such as mobile communication terminals.
Time-sampled
phase
Frequency
Control
Word
(FCW)
Phase
Accumulator
Frequency
Reference
Clock
(FREF)
Time-sampled
amplitude
Time-continuous
amplitude
ROM
DAC
LPF
t
t
t
Output
(fout)
t
Figure 1-3 Direct digital frequency synthesis [Tierney 71].
Due to its digital waveform reconstruction nature, the DDFS technique is best suited for
implementing wideband transmit modulation as well as fast channel hopping schemes [Tan
95]. As an example, Figure 1-4 shows the phase accumulator front end of a DDFS system
5
with an arithmetic adder that combines the FCW components of the channel selected and the
frequency-modulating data.
Phase
Accumulator
FCW
FCW(data)
phase
FCW(channel)
FREF
Figure 1-4 Phase accumulator front end of a DDFS system with frequency modulation [Tan 95].
Let the word length of the accumulator be W. For a given frequency command word FCW
and clocking (FREF) frequency fR, the output frequency fout of the synthesizer is given by
f out 
FCW
f ref
2W
(1.2)
1
f ref
2W
(1.3)
and the frequency resolution is
f out 
Because it is very costly to implement a DDFS system at frequencies of interest for wireless
communications (multi-GHz range), to date this technique has been used directly only in
military applications or to build the low IF DSP in digital communication modems. From yet
another perspective, the DDFS method is fundamentally not the best choice for generating RF
signals. As explained previously, in a deep-submicron process technology, the digital clock of
Figure 1-2 is preferred over the sinusoidal signal, which the DDFS technique attempts to
produce. The complete digital reconstruction of the entire waveform is simply too wasteful if
ultimately, only the zero crossings are what is needed.
6
1.3.3. Indirect Synthesis Using Phase Locking
Indirect synthesis using a PLL compares the output phase of an oscillator, such as a voltagecontrolled oscillator (VCO), with a phase of a reference signal FREF ( fR ) [Egan 00], [Egan
98], as shown in Figure 1-5. As the output drifts, detected errors produce correction
commands to the oscillator, which responds in a negative-feedback manner. Phase and
frequency deviation monitoring occurs in the phase/frequency detector (PFD), which adds
phase noise close to the carrier.
Loop
Filter
Phase/Frequency
Detector
FREF
(fref)
Voltage-Controlled
Oscillator
FVCO
PFD
Phase
error
(fvco)
Tuning
voltage
Kvco
Frequency Divider
FDIV
1/Ndiv
(fdiv)
Figure 1-5 Phase Locked Loop.
However, a PLL can outperform direct synthesis at larger frequency offsets. Fine frequency
steps degrade phase noise, and fast switching is difficult to achieve with a PLL design even
when using aggressive VCO pre-tuning techniques [Lee 04].
In general, the indirect synthesizer uses a PLL and a programmable fractional-N divider,
which multiplies the stable reference frequency fR. In the loop, a loop filter (LF) is present so
as to suppress spurs produced in the phase detector so that they do not cause unacceptable
frequency modulation in the VCO (see Section 1.4). However, the filter causes degradation in
the transient response, which limits the switching time. Therefore, the requirements for
frequency switching time and suppression of spurs are in conflict. The classical PLL-based
7
frequency synthesizers are suitable only for narrowband frequency modulation schemes, in
which the modulating data rate is well within the PLL bandwidth.
1.3.4. Hybrid Structure Frequency Synthesis
In certain applications it is necessary to combine two (rarely, three) major synthesis
techniques such that the best features of each basic method are emphasized. Generally, it is a
hybrid of DDFS and PLL structures that is used in certain wireless devices. As shown in
Figure 1-6, the wideband modulation and fast channel-hopping capability of the DDFS
method, which now operates at lower frequency, could be combined with the frequency
multiplication property of a PLL that up-converts it to the RF band.
FCW
DDFS
(fDDFS)
PLL
(fRF)
Out
(fclk)
CLK
Figure 1-6 DDFS-PLL hybrid
As another example of a hybrid approach, [Hafez 99] describe a 900-MHz band hybrid
synthesizer structure that uses a 1.10 to 1.85-MHz low-frequency DDFS to generate a stable
frequency reference to the main PLL. Instead of using a conventional digital frequency divider
or prescaler, a PLL uses sub-sampler mixing to translate the RF frequency down to fR. The
frequency resolution of the synthesizer is established by the DDFS system, and the PLL is used
primarily as a frequency integer multiplier. Since the DDFS system operates at low frequency,
its major limitation of high-power dissipation is not a concern, but unfortunately, the subsampling process introduces excessive noise.
8
1.4. Frequency
Synthesizers
for
Mobile
Communications
A great majority of RF wireless synthesizers for mobile applications are based on a chargepump PLL structure [Gardner 80]. Under locked conditions the average output frequency of a
PLL bears an exact relationship to the reference input frequency, so the frequency accuracy is
extremely high. Unfortunately, its acquisition time is rather long since the phase/frequency
detector evaluates the frequency difference between the reference and generated clocks by
means of the phase difference. In modern wireless applications, the fast acquisition
characteristic of the frequency synthesizer is crucial (e.g., in channel hopping). The acquisition
time is directly proportional to the initial frequency difference Δfo and inversely proportional to
the loop bandwidth fBW [Wolaver 93]. Consequently, to reduce the acquisition time, a small
initial frequency difference and wide loop bandwidth are desirable.
However, it is not always possible to achieve a small Δfo value at the design stage, due to
the presence of process, voltage, and temperature (PVT) variations; thus, a self-calibrating
mechanism would be preferred [Wilson 00]. We will show this mechanism in more detail in
Chapter 4. In addition, an attempt to enhance the acquisition time through a wide loop
bandwidth increases the contribution of the reference phase noise and is therefore rarely
possible.
The frequency difference could be measured directly, as in [Hwang 01], to reduce the
acquisition time significantly, to just a few clock cycles independent of the initial frequency
difference.
9
Charge Pump
Phase/Frequency
Detector
FREF
(fref)
Loop Filter
Voltage-Controlled
Oscillator
UP
PFD
FVCO
IP
DOWN
R1
IN
C2
(fvco)
Tuning
voltage
Kvco
C1
Frequency Divider
FDIV
(fdiv)
1/Ndiv
Figure 1-7 Typical charge-pump-based PLL for RF wireless applications.
As shown in Figure 1-7, the PFD estimates the phase difference between the frequency
reference FREF input and the divided-by-N VCO clock FDIV by measuring time between
their respective closest edges and generates either an UP or a DOWN pulse whose width is
proportional to the time difference measured. This signal, in turn, produces a current pulse IP IN with the proportional duty cycle in a charge-pump block. At the loop filter, this current is
converted into a VCO tuning voltage. C2 is an integrating capacitor and introduces a pole at
dc, thus giving rise to a type II loop. Its main task is to suppress the glitch generated by the
charge pump on every phase comparison instant. The glitch arises from mismatches between
the width of UP and DOWN pulses produced by the PFD as well as charge injection and clock
feed-through mismatches between PMOS and NMOS devices in the charge pump. This
periodic glitch will modulate the VCO output frequency, thus giving rise to frequency spurs.
The primary sidebands will be located on both sides of the carrier at the comparison frequency
offset. The double integrator configuration is only marginally stable, and it is necessary to
stabilize the loop with a pole–zero combination introduced by R1 and C1.
10
1.4.1. Integer-N PLL Architecture
Conventional PLL has an integer divider ratio of Ndiv such that fvco = Ndiv.fR. The letter N is
used historically in the PLL field to designate its frequency multiplication property and is
equivalent to FCW as defined by Eq. 1.1. Resolution is equal to the reference frequency,
which is usually selected to be the same as the channel spacing. Narrow loop bandwidths are
undesirable because of long switching times, inadequate suppression of he VCO phase noise,
and susceptibility to supply and substrate noise.
The PLL building blocks for the RF applications require extreme care due to the high
frequency of operation, matching, and linearity. Because of the spur reduction requirements,
the loop filter requires large resistors and capacitors, most likely external to the IC chip, to
achieve a low PLL bandwidth of several kilohertz. Realizing a monolithic capacitance on the
order of a few hundred pico farads would require a prohibitively large area if implemented as a
high quality metal–insulator–metal (MIM) capacitor. Implementing it as a MOS capacitor
would take less area, but it would probably be unacceptable because of its high leakage
current and nonlinearity. Another major disadvantage of this analog intensive synthesizer is
lack of portability from one process technology to another.
1.4.2. Fractional-N PLL Architecture
In fractional-N synthesizers, the output frequency can increment by fractions of the
reference frequency, allowing the latter to be much greater than the channel spacing required.
This allows wide loop filter design at the expense of fractional spurs, resulting in improved
loop dynamics and attenuation of the oscillator-induced noise [Razavi 98]. The PLL
bandwidth is usually set at roughly 10% of the reference frequency to avoid any significant
feedthrough of the reference tone and may now span several channels. In response to a change
11
in a frequency control word, the PLL output frequency settles to the programmed value with a
time-constant inversely related to the loop bandwidth.
divide ratio
TN+1
Ndiv+1
average
Ndiv
time
TN
Figure 1-8 Alternating divide ratio of fractional-N PLL
Fractional-N PLL can achieve an arbitrary fine time-averaged frequency-division ratio of
(Ndiv.f) by modulation of the instantaneous integer division ratio of N div and Ndiv + 1. (In
practice, a multi-bit modulus could be used, as demonstrated in [Kenny 99].)
Figure 1-8 reveals the principle in which the integer division is periodically altered from Ndiv
to Ndiv + 1. The resulting average divide ratio will be increased from Ndiv by the duty cycle of
the Ndiv + 1 division:
N avg 
N divTN  N div  1TN 1
TN 1
 N div 
 N div  . f   N div. f 
TN  TN 1
TN  TN 1
(1.4)
where f corresponds to the fractional part of the frequency-division ratio. Figure 1-9 shows
details of various signals (active edges only) for Navg = 2.25. The timestamps shown on FREF
edges are given in terms of VCO edges (each FREF cycle comprises 2.25 VCO cycles). The
phase error is given with respect to the nearest FREF edge.
The phase detector will operate at a frequency of fR + (.f/Ndiv)fR, and the phase error of the
phase detector causes VCO fractional spurs at a multiple of the offset frequency (.f)fR.
12
example Navg = 2 + 1/4
VCO clock edges
FDIV clock edges
FREF clock edges
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
0
2
4
0
2¼
4½
7
9
11
13
6¾
9
11¼
13½
16
18
15¾
18
time
phase error
[VCO cycle units]
φ[1]
φ[2]
φ[3]
φ[4]
φ[5]
φ[6]
φ[7]
φ[8]
-¼
-½
+¼
0
-¼
-½
+¼
0
Figure 1-9 Periodic and deterministic phase error in a fractional-N PLL
Phase/Frequency
Phase
Detector
Interpolation
FREF
X
(fref)
+
Loop
Filter
F(s)
Voltage-Controlled
Oscillator
FVCO
Tuning
voltage
(fvco)
Kvco
FDIV
(fdiv)
clk
Ndiv/
(Ndiv+1)
Modulus
Control
ovfl
X
D/A
Figure 1-10 Fractional-N PLL incorporating phase interpolation
There are several methods available to suppress the fractional spurs. A more conventional
method is the analog fractional-N compensation scheme that uses an accumulator and a DAC
and is based on the observation that the phase-error perturbation is periodic and deterministic
(Figure 1-9) and could be canceled out by a tracking circuit. This form of correction, called
phase interpolation, is presented in Figure 1-10. The fractional spurs are reduced to the extent
that the phase interpolation signal exactly matches the phase error. In practice, it is difficult to
achieve fractional spurs lower than -70dBc. This requires a precision DAC and carefully
13
designed phase detector and sampler circuitry. Due to its analog complexity, the interpolation
scheme is not suitable in most applications. The second method uses a SD-modulated clock
divider as described by [Miller 91] and [Riley 93] and is shown in Figure 1-11. This solution is
more digital in nature since it does not rely on precise analog component matching of the
previous technique. It trades the reduction in fractional spurs for the increase in the noise floor
as shown in Figure 1-13 (left).
Figure 1-12 shows the third-order ΣΔ digital modulator divider described in [Miller 91]. It
uses three accumulator stages, in which the storage is performed in the accumulator feedback
path. The modulator input is a fractional fixed-point number and its output is a small integer
stream. It is shown in [Miller 91] that its transfer function is


N div z   . f z   1  z 1 Eq 3 z 
(1.5)
3
where Eq3, the quantization noise of the third stage, equals the output of the third stage
accumulator. The first term is the desired fractional frequency, and the second term represents
noise due to fractional division.
FREF
(fref)
Phase/Frequency
Detector
Loop
Filter
X
F(s)
Voltage-Controlled
Oscillator
FVCO
Tuning
voltage
(fvco)
Kvco
FDIV
(fdiv)
1/(Ndiv+b)
RF/analog
digital
b(t)
Sigma-Delta
Modulator
Figure 1-11 Fractional-N synthesizer using a ΣΔ-modulated clock divider [Miller 91] & [Riley 93].
14
Figure 1-13 plots the spectrum of the output signal FVCO. It shows quantization noiseshaping properties of the first-, second-, and third-order ΣΔ modulation of the clock division
ratio. The first order of SD operation turns out to be equivalent to the conventional but
uncompensated fractional-N architecture and exhibits systematic division ratio patterns that
produce unacceptably large frequency tones. In this case, the quantization noise is
concentrated at discrete frequencies rather than being spread continuously and merged into the
noise floor as in second and higher ΣΔ orders. Figure 1-13 (left) shows the power spectral
density of the divided clock and is centered around fdiv. As shown, the third order of ΣΔ
dithering introduces enough randomness to eliminate completely any frequency spurs that are
clearly shown with the second- and first order ΣΔ dithering. The right plot shows the PSD of
the divided clock phase, and it demonstrates that the second-order ΣΔ dithering performs
high-frequency shaping of the division ratio quantization noise of 20 dB/decade, whereas the
third order produces 40 dB/decade. The noise at higher frequencies then gets filtered out in
the loop filter.
Z-1
Z-1
b(t) = Ndiv(k)
OV1
OV2
.f(k)
OV3
Z-1
Z-1
Z-1
Figure 1-12 MASH-3 ΣΔ digital modulator divider [Miller 91].
15
Figure 1-13 ΣΔ-divided clock: clock output spectrum (left), phase spectrum (right)
The ΣΔ modulators are usually built as a multistage structure of single-bit modulators
[Matsua 87]. As derived in [Miller 91], the quantization noise shaping is related to the number
of modulator stages m by the following formula and is given in rad2/Hz:
2 2 
L f  
12 f ref
f
 f / 2
 ref




2  m 1
(1.6)
The fractional-N frequency synthesizer architecture lends itself well to an indirect
narrowband frequency modulation which could be implemented entirely in a digital manner. As
long as the modulation data rate is lower than the PLL bandwidth, the average division ratio N
digital command word, which corresponds to a desired channel, could be augmented by the
instantaneous value of the modulation frequency deviation. There has been some research to
increase the data rate by compensating for the PLL high-frequency attenuation by boosting the
high-frequency components of the modulation signal as shown in [Perrott 97]. After the
equalized modulation signal passes through the PLL, the modulation spectrum could be
restored to its original form.
16
Loop
Filter
DSP
D/A
F(s)
Voltage-Controlled
Oscillator
FVCO
Tuning
voltage
(fvco)
Kvco
FREF
(fref)
Integrator
X
PDF
Multimodulus
Divider
2 – z-1
Sigma-Delta frequency discriminator
b(t)
data
GFSK Filter
+ Equalizer
Sigma-Delta
Modulator
Figure 1-14 Modulating a wideband fractional-N synthesizer [Bax 01].
The digital equalizer could be embedded in the GFSK filter with little extra overhead.
However, the precise loop compensation requirement makes this architecture not very
practical for manufacturing. The problem of mismatch between the digital compensation filter
and the analog PLL got addressed by [Bax 01]. The fractional-N PLL is re-architectured there
to place a ΣΔ frequency discriminator, whose transfer function is set digitally and well
controlled, in the feedback path (Figure 1-14). As a result, the only analog component left that
requires a substantial amount of matching is the VCO.
17
1.4.3. Toward an All-Digital PLL Approach
The need for an All-Digital PLL approach is rising because advanced deep-submicron
CMOS processes make it extremely difficult to implement traditional analog circuits, though
on the good side it presents better integration opportunities. To address the various deepsubmicron RF integration concerns, some new and radical system and architectural changes
have been recently presented by [Staszewski 03a] towards the All-Digital PLL approach.
This new ADPLL which is the main focus of this thesis is based on a digitally controlled
oscillator (DCO), which deliberately avoids any analog tuning voltage controls as shown in
Figure 1-15. This allows for its loop control circuitry to be implemented in a fully digital
manner. When implemented in a digital deep sub micrometer CMOS process, the proposed
architecture appears more advantageous over conventional charge-pump-based PLLs, since it
exploits the signal processing capabilities of digital circuits and avoids relying on the fine
voltage resolution of analog circuits. In the proposed ADPLL, the conventional
phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital
converter and a simple digital loop filter. The basics of this new ADPLL will be presented in
more detail in the following chapter.
Reference Phase
Accumulator
Frequency
Command Word
Σ
FCW
Phase
Detector
Loop
Filter
ΦE[k]
RR[k]
+
+
-
d[k]
Latch
OTW
Sampler
DCO Phase
Accumulator
RV[i]
Σ
DCO Period
Normalization
Synchronizer
FREF
KDCO
NTW
CKV
-
RV[k]
X
Digitally Controlled
Oscillator
fR/KDCO
PHE
-ε[k]
TDC
DCO Gain
Normalization
Retimed FREF
(CKR)
Figure 1-15 ADPLL-based RF frequency synthesizer [Staszewski 04].
1
18
1.5. Thesis Outline
This thesis is organized as follows: In Chapter 1 we presented the motivation behind this
work and a brief introduction to the different frequency synthesis techniques.
In Chapter 2, we present the basics of the All Digital Phase Locked Loop (ADPLL), we
show its main building blocks and principle of operation.
In Chapter 3, we show how we model the various ADPLL building blocks using Verilog, we
build a simple ADPLL model and use a simple frequency plan to understand in more depth the
ADPLL operation.
In Chapter 4, we study one of the main problems of LC digitally-controlled-oscillators
(DCOs) which is the center frequency (fDCO) variations across process variations. We
introduce a fast automatic tuning algorithm for these oscillators with multiple tuning curves
which we published recently. Many practical implementation issues are shown along with their
solutions.
In Chapter 5, we study another problem of LC DCOs which is its tuning gain (KDCO)
variations also across process variations. We explain a method of estimating the gain of the
DCO. By executing the calculation algorithm just-in-time at the beginning of every packet, the
DCO gain can be conveniently tracked and compensated.
In Chapter 6, we integrate the introduced DCO auto-tuning algorithm and KDCO estimation
and normalization algorithm with the ADPLL model introduced in Chapter 3 and we show
how these algorithms are incorporated in sequence to prepare the ADPLL to be used as an
FSK Transmitter.
Chapter 2
ADPLL Basics
In this chapter we walk through the basics of the All Digital PLL presenting its mathematical
description and some of its operational details.
2.1. Introduction
The frequency synthesizer is a key block used for both up-conversion and down-conversion
of radio signals and has been traditionally based on a charge-pump PLL, which is not easily
amenable to integration. As introduced in chapter 1, a digitally controlled oscillator (DCO),
which deliberately avoids any analog tuning voltage controls, was recently presented in
[Staszewski 03b] for RF wireless applications. This allows for its loop control circuitry to be
implemented in a fully digital manner as first proposed in [Staszewski 03a] and then
demonstrated as a novel digital-synchronous phase-domain all-digital PLL (ADPLL) in a
commercial 0.13 µm CMOS single-chip Bluetooth radio [Staszewski 04a].
20
Chapter 2 ADPLL Basics
When implemented in a digital deep sub micrometer CMOS process, the proposed
architecture appears more advantageous over conventional charge-pump-based phase-locked
loops (PLLs), since it exploits signal processing capabilities of digital circuits and avoids
relying on the fine voltage resolution of analog circuits. In the proposed ADPLL, the
conventional phase/frequency detector, charge pump and RC loop filter are replaced by a
time-to-digital converter and a simple digital loop filter.
Per PLL classification in [Best 93], the proposed frequency synthesizer is not a classical
digital PLL (DPLL), which actually is considered a semi-analog circuit, but an ADPLL with all
building blocks defined as digital at the input/output level. Similar to a flip-flop, which is a
cornerstone of digital circuits, the DCO is built as an application-specific integrated circuit
(ASIC) cell, whose internals are analog, but the analog nature does not propagate beyond its
boundaries [Staszewski 03b]. In this chapter, we present a mathematical description and
operational details of the phase-domain ADPLL. The phase-domain operation is motivated by
an observation [Kajiwara 92], that, since the reference phase and oscillator phase are in a
linear form, their difference produced by the phase detector is also linear with no spurs and the
loop filter would not be needed. This is in contrast with conventional charge-pump-based
PLLs that generate significant amount of spurs that require a strong loop filter that degrades
the transients and limits the switching time.
21
2.2. ADPLL System
Reference Phase
Accumulator
Frequency
Command Word
Σ
FCW
Phase
Detector
Loop
Filter
ΦE[k]
RR[k]
+
+
-
d[k]
PHE
Latch
OTW
Sampler
DCO Phase
Accumulator
CKV
RV[i]
Σ
1
DCO Period
Normalization
Synchronizer
FREF
KDCO
NTW
-
RV[k]
X
Oscillator
fR/KDCO
-ε[k]
TDC
DCO Gain
Normalization
Retimed FREF
(CKR)
Figure 2-1 ADPLL-based RF frequency synthesizer [Staszewski 04]
Figure 2-1 shows a block diagram of the ADPLL-based frequency synthesizer. It operates in
a digitally synchronous fixed-point phase domain, which was recently proposed in [Staszewski
04a]. The variable phase signal RV[i] is determined by counting the number of rising clock
transitions of the DCO oscillator clock. The reference phase signal RR[k] is obtained by
accumulating the frequency command word (FCW) with every rising edge of the retimed
frequency reference (FREF) clock. The sampled variable phase RV[k] is subtracted from the
reference phase in a synchronous arithmetic phase detector. The digital phase error is
conditioned by a simple digital loop filter and then normalized by the DCO gain, KDCO. The
KDCO normalization is needed to precisely establish the loop bandwidth and to perform a direct
transmit frequency modulation, as described in [Staszewski 03c]. The FREF input is resampled
by the RF oscillator clock, and the resulting retimed clock (CKR) is used throughout the
system. This ensures that the massive digital logic is clocked after the quiet interval of the
phase error detection by the time-to-digital converter (TDC). A detailed description follows
below.
22
2.3. Phase Domain Operation
Let us define the actual clock period of the variable oscillator (DCO or voltage-controlled
oscillator, in general) output (CKV) as TV and the clock period of the FREF as TR. Let us
assume that the oscillator runs appreciably faster than the available reference clock, TV << TR,
which is the case in RF synthesizers, where the generated multi-gigahertz RF carrier frequency
is of orders of magnitude higher than the crystal reference. Let us further assume, in order to
simplify the initial analysis, that the actual clock periods are constant or time invariant. The
CKV and FREF clock transition timestamps tV and tR, respectively, are governed by the
following equations:
tV  i  TV
(2.1)
t R  k  TR  t o
(2.2)
Where i = 1,2,… , and k = 1,2,… are the CKV and FREF clock transition index numbers,
respectively, and to is some initial time offset between the two clocks, which is absorbed into
the FREF clock..
It is convenient in practice to normalize the transition timestamps in terms of actual TV units,
referred to as unit intervals (UI), since it is easy to observe and operate on the actual CKV
clock events. Let us define dimensionless variable and reference “phase”
V  tV / TV
(2.3)
 R  t R / TV
(2.4)
The term θV is only defined at CKV transitions and indexed by i. Similarly, θR is only
defined at FREF transitions and indexed by k. This results in
V i  i
(2.5)
 R k   k  TR / TV  to / TV  k  N   o
(2.6)
23
The normalized transition timestamps θV[i] of the variable clock, CKV, could be estimated by
accumulating the number of significant (rising or falling) edge clock transitions
(2.7)
i
RV i  TV   RV i   1
l 0
Without the FREF retiming (described in 2.4), the normalized transition timestamps θR[k] of
the FREF clock, could be obtained by accumulating the FCW on every significant edge of the
FREF clock
(2.8)
k
RR k  TR   RR k    FCW
l 0
FCW is formally defined as the frequency division ratio of the expected variable frequency to
the reference frequency
FCW  E  fV  / f R
(2.9)
The reference frequency is usually of excellent long-term accuracy, at least as compared to the
variable oscillator. For this reason, we do not use the expectation operator on fR.
FREF
D
Q
CKR
CKV
FREF
CKV
CKR
time
1
2
3
Figure 2-2 Concept of synchronizing the clock domains by retiming the FREF.
FCW control is generally expressed as being comprised of an integer (Ni) and fractional (Nf)
parts
FCW  N  N i  N f
(2.10)
The PLL achieves, in a steady-state condition, a zero or constant averaged phase difference
between the variable θV[i] and the reference θR[k] normalized timestamps. Attempt to
formulate the phase error as this dimensionless phase difference φE = θR - θV would be
unsuccessful due to the nonalignment of the time samples. This will be addressed in 2.4.
24
The additional benefit of operating the PLL with phase-domain signals is to alleviate the
need for the frequency-detection function within the phase detector. This allows to operate the
PLL as type-I (only one integrating pole due to the DCO frequency-to-phase conversion),
where it is possible to eliminate a low-pass loop filter between the phase detector and the
oscillator input, resulting in a high bandwidth and fast response of the PLL. It should be noted
that conventional PLLs, such as a charge-pump-based PLL, do not truly operate in the phase
domain.
There, the phase modeling is only a small-signal approximation under the locked condition.
Their reference and feedback signals are edge based and their closest distance is measured as a
proxy for the phase error. Gardner describes this as “converting the timed logic levels into
analog quantities” [Gardner 80]. False frequency locking is a deficiency that directly results of
not truly operating in the phase domain, and it requires extra measures, such as use of a
phase/frequency detector.
2.4. Reference Clock Retiming
It must be recognized that the two clock domains as described in 2.3 are not entirely
synchronous, and it is difficult to physically compare the two digital phase values at different
time instances and without having to face metastability problems. (Mathematically, θV[i] and
θR[k] are discrete-time signals with incompatible sampling times and cannot be directly
compared without some sort of interpolation.) Therefore, it is imperative that the digital-word
phase comparison be performed in the same clock domain. This is achieved by over-sampling
the FREF clock by the high-rate DCO clock, CKV, (see Figure 2-1) and using the resulting
CKR clock to accumulate the reference phase θR[k] as well as to synchronously sample the
high-rate DCO phase θV[k], mainly to contain the high-rate transitions. Since the phase
25
comparison is now performed synchronously at the rising edge of CKR, then (2.5) and (2.6)
ought to be re-written as follows:
V k   k
(2.11)
 R k   k  N   o   k 
(2.12)
1
RV[k]
FCW
RR[k]
RV[i]
CKV
CKR
CKR
Figure 2-3 Hardware implementation of (a) the variable phase RV[k] and
(b) the reference phase RR[k] estimators.
Variable phase 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tV = i · TV
Reference phase 0
tR = k · TR + to
Retimed reference phase 0
tR = k · TR + to
2¼
3
4½
6¾
9
5
7
9
11¼
13½
15¾
18
14
16
18
12
time
Fractional error correction
[clock cycle units]
ε[1]
ε[2]
ε[3]
ε[4]
ε[5]
ε[6]
ε[7]
ε[8]
¾
½
¼
0
¾
½
¼
0
Figure 2-4 Fractional-N division ratio timing example with N = 2+(1/4).
The set of phase estimate [(2.7) and (2.8)] should be augmented by the sampled variable phase
(2.13)
i
RV k   1
l 0
iTV  kTR
The index k is now the kth transition of the retimed reference clock CKR, not the kth
transition of the reference clock FREF. By constraint, it contains an integer number of CKV
clock transitions. As shown in Figure 2-3, RV[k] is implemented as an incrementer followed by
a flip-flop register and RR[k] is implemented as an accumulator.
ε[k] of (12) is the CKV clock edge quantization error, in the range of (0,1), that could be
further estimated and corrected by other means, such as the TDC-based fractional error
correction circuit [Staszewski 04a]. This operation is graphically illustrated in Figure 2-4 as an
example of integer-domain quantization error for a simplified case of the frequency division
26
ratio of N=2+1/4. Unlike ε[k], which represents rounding to the next DCO edge, conventional
definition of the phase error represents rounding to the closest DCO edge. An exact definition
of the correction signal is not extremely important, as long as it is consistent and properly
provides a negative feedback. The reference retiming operation (shown in Figure 2-2) can be
recognized as a quantization in the DCO clock transitions integer domain, where each CKV
clock rising edge is the next integer and each rising edge of FREF is a real-valued number.
Since the system must be time-causal, quantization to the next DCO transition (next integer),
rather than the closest transition (rounding-off to the closest integer), could only be
realistically performed.
2.5. Phase Detection
Figure 2-4 suggests that the conventional definition of the phase error, expressed as a
difference between the reference and variable phases, needs to be augmented here to account
for the quantization correction ε.
E k    R k   V k    k 
(2.14)
Additionally, the unit of radian is not very useful here because the loop operates on the
whole and fractional parts of the variable period and true dimensionless variables are more
appropriate. The initial temporary assumption made in 2.3 about the actual clock periods to be
constant or time-invariant could now be relaxed at this point. Instead of producing a constant
ramp of the detected phase error ΦE, the phase detector will now produce an output according
to the real-time clock timestamps. The phase error can be estimated in hardware by the phase
detector operation defined by
ˆE k   RR k   RV k    k 
(2.15)
27
2.6. Modulo Arithmetic of Phase Domain Signals
The variable and reference accumulators RV[i] and RR[k], respectively, are implemented in
modulo arithmetic in order to practically limit word length of the arithmetic components. In
this implementation, the integer part of the accumulators is WI = 12 and the fractional part of
the reference accumulator is WF = 16. These accumulators represent the variable and reference
phases, θV and θR, respectively, which are linear and grow without bound with the
development of time. The registers, on the other hand, cannot hold unbounded numbers, so
they are restricted to a small stretch of line from zero to infinity, which repeats itself
indefinitely such that any such stretch is an alias of the fundamental stretch from 0 to 2WI. A
good example of such an approximation is modulo arithmetic. Any accumulator of length WI,
whose carry out bits are simply disregarded and which does not perform saturation, is a
modulo-2WI accumulator. In fact, the modulo arithmetic is very natural in the digital logic.
Note that modulo accumulators are not absolutely linear in the strictest sense of the word.
They are, however, linear in the local sense (for a constant frequency, of course). The phase
equations (2.7) and (2.8) are now rewritten to acknowledge the implicit modulo operation.

RV i  1  mod RV i   1,2WI


RR k  1  mod RR k   FCW ,2WI
(2.16)

(2.17)
Figure 2-5 shows an example of modulo-16 operation with the frequency division ratio of
N=10 and exhibiting small alignment offset (ΦE = 3) between the two phases. If the system is
in a settled state, then both phases follow a saw tooth trajectory with the same linear speed.
The variable phase RV[i] traverses all integers at a very fast pace. The reference phase RR[k],
on the other hand, moves infrequently (ten times less often) but with large steps (ten times
bigger). As a net effect, their traversal velocity is the same. Also shown every ten CKV clock
28
cycles is the sampling process of RV[k] = RV[i] during activity at RR[k]. The difference
between RR[k] (3, 13, 7, 1, 11, … ) and RV[k] (0, 10, 4, 14, 8, … ) readout sequences should
always be 3, and it is so except for the forth comparison. Here, the error of -13 is inconsistent
and performing modulo-16 arithmetic will get it to 3, which is in line with the rest.
The modulo arithmetic on RV and RR could be visualized as two rotating vectors and the
smaller angle between them constituting the phase error (Figure 2-6). Both RV and RR are
positive numbers and their maximum value possible without rollover depends on the counter
width or integer part of the FCW, and equals 2WI. The phase error has the same range but is
symmetric around zero, i.e., it is a two’s complement number.
RV[i]
14
10
8
4
0
0
10
20
30
40
CKV clocks
0
1
2
3
4
CKR clocks
RR[k]
13
11
7
3
1
Figure 2-5 Modulo arithmetic of the reference and variable phase registers with
the phase offset of ΦE = 3.
0,2π,4π,...
θV
ΦE
ωV
θR
ωR
Figure 2-6 Rotating vector interpretation of the reference and variable phases.
29
Figure 2-1 also helps to understand that the phase detector is not only the arithmetic
subtractor of two numbers, but also performs a cyclic adjustment so that, under no
circumstance, the larger angle between the two vectors would be decided. This could happen
if, for example, the larger vector appears just before the smaller vector which is already on the
other side of the “zero” radius line. Because the PD output is a WI-bit constrained signed
number, the conversion is always implicitly made and the output lies within (-2WI-1, 2WI-1-1).
Consequently, no extra hardware is required.
2.7. Discrete Time Z-Domain Model
The proposed ADPLL is a discrete-time sampled system implemented with all digital
components connected with all digital signals. Consequently, the z-domain representation is
not only the most natural fit but it is also the most accurate with no necessity for those
approximations that would result, for example, with an impulse response transformation due
to the use of analog loop filter components [Hein 88].
Figure 2-7 shows the z-domain model. The ΔθV and ΔθR are the excess θV variable (2.3) and
θR reference (2.4) normalized transition timestamps, respectively. They are related to the
conventional definition of phase, Φ, by ΦV = 2π ΔθV and ΦR = 2π ΔθR/N. The sampling rate is
the reference frequency fR.
ΔfR
fR
1
Phase Detector
Loop Filter
N
α
ΔθR
Normalized DCO
ΔfV
ΦE
fV
1
z-1
KDCO
KDCO
1
z-1
ΦR/2π
ρ
ΦV/2π
ΔθV
1
z-1
Figure 2-7 z-domain model of the type-II ADPLL.
30
Two approximations are used in order to simplify the model. The first is to force a uniform
PLL update rate, despite the presence of a small amount of jitter in FREF. The second is the
linearity assumption between a frequency deviation Δf from a center frequency f=1/T and a
period deviation ΔT: Δf = f2 ΔT, [Staszewski 03a]. These two approximations are very
accurate since the period deviation due to jitter and modulation is several orders of magnitude
smaller than the DCO period. The open-loop phase transfer function can be expressed as:
H ol z  
 z  1  
z  1
(2.18)
2
For simplicity, the DCO gain estimation accuracy r  K DCO / Kˆ DCO is assumed to be unity.
Otherwise, it would only result in scaling of the loop gain parameters: α  rα and ρ  rρ.
This will be discussed in more detail in Chapter 5. Since the TDC-based phase detection
mechanism of the proposed architecture measures the oscillator timing excursion normalized
to the DCO clock cycle [Staszewski 04a], the frequency multiplier N ≡ FCW is not part of the
open-loop transfer function and, hence, does not affect the loop bandwidth. This is in contrast
to conventional PLLs that use frequency division in the feedback path, but is similar, however,
to the PLL architectures with frequency down-conversion (heterodyning) in the feedback path.
Phase deviation of the FREF, on the other hand, needs to be multiplied by N since it is
measured by the same phase detection mechanism normalized to the DCO clock cycle. The
same amount of timing excursion on the FREF input translates into a larger phase by a factor
of N when viewed by the phase detector. The closed-loop phase transfer function is written as:
H cl z  
V z 
H ol z 
N
 R z 
1  H ol z 
(2.19)
where, Φ(z) is a z-transform of Φ. It could be expanded as:
H cl z   N
 z  1  
z  12   z  1  
(2.20)
31
2.8. Linear S-Domain Approximation
The z-operator is defined as z  e s / f R , where s = j2πf and 1/fR is the sampling period. For
small values of f in comparison with the sampling rate fR, we can make the following
approximation:
z  e s / fR  1 
Phase Detector
(2.21)
s
fR
Loop Filter
Normalized DCO
α
N
ΦR
ΦE
fR
1
KDCO
s
ΦV
KDCO · 2π
1
fR
2π
s
ρ
Figure 2-8 Linear s-domain model of the type-II ADPLL.
which results in:
s  f R z  1
(2.22)
Using (2.22) to transform (2.18) and (2.20) gives
1
  f R  f R   f R2

H ol s     


s  s
s

f R s  f R2
H cl s   N 2
s  f R s  f R2
s
  fR
(2.23)

s
(2.24)
The open-loop transfer function shows two poles at origin and one complex zero at
 z  j  f R /  . The closed-loop transfer function Hcl(s) can be compared to the classical
two-pole system transfer function
H cl s   N
2 n s   n2
s 2  2 n s   n2
(2.25)
32
where, ζ is the damping factor and ωn is the natural frequency. Fitting the two equations
yields:
n   f R
 
f R 1 

2 n 2 
(2.26)
(2.27)
The main motivation behind adding the integral term to the proportional loop gain is to be
able to further attenuate (up to 40 dB/dec) the lower-frequency 1/f noise components. Figure
2-8 shows the s-domain linear model of ADPLL in the type-II setting. It is a continuous-time
approximation of a discrete-time z-domain model and is valid as long as the frequencies of
interest are much smaller (see (2.21); [Gardner 80] reports ≤ 1/10) than the sampling rate,
which in this case equals fR. There is a multiplication factor of 1/2π at the output of the phase
detector. It is simply due to the fact that the digital phase error is expressed not in units of
radian of the DCO clock, but in the number of its cycles.
2.9. Summary
We have presented mathematical description and operational details of the phase-domain
ADPLL. The architecture is built from the ground up using digital techniques that exploit high
speed and high density of a deep-submicrometer CMOS process while avoiding its weaker
handling of voltage resolution. The conventional phase/frequency detector and charge-pump
combination is replaced by a digital-to-frequency converter and is followed by a simple digital
loop filter that controls a DCO. Modulo arithmetic is used to represent the phase-domain
fixed-point signals. A novel method of retiming the reference clock allows creating a single
clock domain for the synchronous operation of digital logic. Both z and s-domain models of
the ADPLL are derived, and the fit into the classical two-pole control system is given.
Chapter 3
ADPLL Modeling
In this chapter we show how we model the various ADPLL building blocks using Verilog,
we build a simple ADPLL model and use a simple frequency plan to understand in more depth
the ADPLL operation.
3.1. Introduction
Since the ADPLL is digital intensive by design, it is more suitable to use digital simulation
tools to study its various functionality and performance aspects. Digital systems modeling
using Verilog enables us not only to speed up digital circuits simulation by its event driven
simulation techniques, but also has the potential to handle analog quantities like DCO
frequency and time delay between different signals. This makes Verilog the most suitable
modeling and simulation tool for the ADPLL.
Chapter 3 ADPLL Modeling
34
3.2. ADPLL Building Blocks
The main ADPLL building blocks shown in Figure 3-1 are the Synchronous counter with
reset, Sampler, Synchronizer, Phase Detector & finally the DCO & TDC which are the more
analog in nature building blocks. Now we show how these blocks can be modeled in the
simplest way possible.
Reference Phase
Accumulator
Frequency
Command Word
+
+
10
10
Loop
Filter
10
d[k]
-
Latch
10
Synchronizer
FREF
KDCO
PHE
NTW
OTW
10
10
10
Sampler
DCO Phase
Accumulator
CKV
10
RV[k]
RV[i]
10
10
X
10
Oscillator
fR/KDCO
-ε[k]
TDC
DCO Gain
Normalization
ΦE[k]
RR[k]
Σ
FCW
Phase
Detector
DCO Period
Normalization
Retimed FREF
(CKR)
Figure 3-1 ADPLL main building blocks
Σ
1
35
3.3. Synchronous Counter with Reset Model
The Synchronous counter with reset is used for DCO phase accumulation & Reference
phase accumulation. Figure 3-2 shows the Verilog model of this counter. The counter has a
clk input to be used as the driving clock for synchronizing the accumulation action, a step
input that is used as the accumulator increment for each clk rising edge, a reset input to put
the accumulator in a defined state (all zeros) when required and finally a count output that
represents the state of the accumulator. The width of the accumulator is defined by the
parameter width. In our example, with width = 10, the accumulator count from 0 to 210-1 =
1023 before it rolls over.
Figure 3-2 Synchronous counter with reset model
36
3.4. Sampler Model
The Sampler is used for sampling the DCO phase accumulator output Rv[i] that is updated
at the DCO output frequency rate by the retimed reference clock to produce the sampled DCO
phase signal Rv[k] that is updated at approximately the FREF frequency. This is important to
allow the rest of the ADPLL building blocks to operate at the lower FREF frequency for
optimum power consumption. Figure 3-3 shows the Verilog model of this sampler. The
sampler has a clk input to be used as the driving clock for synchronizing the sampling action,
an in input that is the input bus to be sampled, and finally an out output that is the sampled
version of the input bus. The width of the sampler is also defined by the parameter width.
Figure 3-3 Sampler model
37
3.5. Synchronizer Model
The Synchronizer is used for synchronizing the FREF low frequency reference clock of the
ADPLL by the FDCO high frequency DCO output clock. This is important to allow the rest of
the ADPLL building blocks to operate at the same frequency domain (that of the DCO) to
avoid metastability problems. Figure 3-4 shows the Verilog model of this synchronizer. The
synchronizer has a clk input to be used as the high speed synchronizing clock, an in input
that is the input low speed clock to be synchronized, and finally an out output that is the
synchronized version of the input clock. The synchronizer block is basically the double
flopping configuration (two D-Flip Flops in cascade) that is well known in the digital design
field for synchronizing asynchronous signals.
Figure 3-4 Synchronizer model
38
3.6. Phase Detector Model
The phase detector is used for comparing the FREF & FDCO phases taking into account the
retiming error from the TDC and produce the correcting error signal PHE for the DCO.
Figure 3-5 shows the Verilog model of this comparator. The comparator has an in_ref input
which is the output from the reference accumulator representing the phase of the retimed
reference, an in_dco input which is the sampled output from the DCO accumulator
representing the phase of FDCO & an in_err which represents the output from the TDC
(assumed to be all zeros for the moment). The out output is the representation of the phase
error between FREF & FDCO. The width of the various inputs of the phase detector is also
defined by the parameter width. The out output is a signed word whose width is also defined
by the parameter width.
Figure 3-5 Phase detector model.
39
3.7. DCO Model
The DCO is the heart of the ADPLL, it is responsible for converting the oscillator tuning
word OTW which is the filtered version of the phase error signal PHE into the corresponding
RF frequency FDCO. Figure 3-6 shows the Verilog model of the DCO. The DCO has an N
input which is the oscillator tuning word and an out output which is the DCO output RF
frequency signal FDCO. The input N is a signed word whose width is also defined by the
parameter width.
Figure 3-6 DCO model
40
3.8. ADPLL Top Level Model
Figure 3-7 shows the ADPLL top level model. All the ADPLL basic building blocks are
instantiated. Note that the TDC for the moment is considered a constant value of 0 for the
moment.
Figure 3-7 ADPLL top level model.
41
3.9. ADPLL Top Level Test Bench
Figure 3-8 shows the ADPLL top level test bench. The ADPLL top level is instantiated. The
reference frequency is defined to be 156.25MHz in this example. The test bench proceeds as
follows:

A reset pulse is issued to reset all registers

FCW starts at 16  FDCO should go to 16 x 156.25 = 2.500GHz

After 2000nsec FCW is changed to 24  FDCO = 24 x 156.25 = 3.750GHz


The calculated frequencies above are the expected DCO frequencies according to the simple
frequency plan shown in
Table 3-1 where FDCO = FCW x FREF.
Figure 3-8 ADPLL top level test bench.
42
Note that in this simple ADPLL example, the DCO has an oscillation period defined as:
Tdco = 0.4 - Ndco*0.0005 in nsec. Also note that since the TDC is not yet modeled and all
signal busses don’t have fractional bits, this ADPLL is considered as an Integer-N ADPLL.
That’s why we use only integer values for FCW in this example.
Ndco
Tdco [nsec]
Fdco [GHz]
Fref [MHz]
FCW
-267/-266
0.5333
1.875
156.25
12
0
0.4
2.5
156.25
16
266/267
0.2667
3.75
156.25
24
400
0.2
5
156.25
32
Table 3-1 ADPLL simple frequency plan
Figure 3-9 shows the ADPLL top level simulation results. We plot the DCO OTW as an
analog waveform to show the locking behavior in the closed loop operation of the ADPLL.
The cursor is placed at an instance of time when the FCW is 32, then as expected from the
frequency plan in
Table 3-1, the DCO OTW is equal to 400.
Figure 3-9 ADPLL top level simulation results
43
3.10. TDC Model
In order to operate the ADPLL in Fractional-N mode, all the busses in the system are
augmented with extra bits for the fractional part, i.e. the part to the right of the decimal point.
This is called fixed point representation of real numbers as opposed to the floating point
representation that expresses fractions using an infinite number of fractional bits. Also a TDC
has to be used to correct for the retiming errors that will be there all the time even under
locked conditions as the reference period is now not an integer multiple of the DCO period.
To correct the retiming errors caused by the synchronizer, the TDC converts the time
between the FREF rising edge & the next FDCO rising edge to a digital quantity representing
this time in units of unit intervals (UI) of the DCO output period as shown in Figure 3-10.
Figure 3-11 shows the Verilog model of this TDC. The TDC has a fref_s input to be used as
the synchronizing clock for the time to digital conversion action. The fref input that is the
input reference low speed clock. The rising edge of fref marks the start of the time interval to
be converted to digital. The fdco input that is the DCO high speed clock. The next rising edge
of fdco marks the end of the time interval to be converted to digital. Finally, the out output is
the digital representation of the time interval explained previously in units of DCO UI. The
TDC output bus width is also defined by the parameters width & width_fraction. Note that
for causality reasons discussed in chapter 2, the TDC output is always a positive fraction
ranging from 0 to 1. In our example, when the TDC output is described in fixed point
representation by a word with 3 bits for representing fractions, the TDC resolution is 1/2 3 of
the DCO period.
44
Variable phase 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tV = i · TV
Reference phase 0
tR = k · TR + to
Retimed reference phase 0
tR = k · TR + to
2¼
3
4½
6¾
9
5
7
9
11¼
12
13½
15¾
18
14
16
18
time
Fractional error correction
[clock cycle units]
ε[1]
ε[2]
ε[3]
ε[4]
ε[5]
ε[6]
ε[7]
ε[8]
¾
½
¼
0
¾
½
¼
0
Figure 3-10 TDC functionality example with FCW = 2+(1/4).
Figure 3-11 TDC Model
45
For better understanding, Figure 3-12 shows an example for some waveforms from the
TDC. We see that fref rising edge comes at 22.4nsec while the next fdco rising edge comes at
22.7687nsec. So the difference is 0.3687nsec which when divided by the DCO period of
0.3927nsec yields 0.939UI. Using 3 bits to represent this fraction we get 0.939 x 23 = 7.51393
which truncates to 7.
Figure 3-12 TDC model waveforms.
3.11. Summary
We have presented the Verilog modeling technique used to describe the various building
blocks of the ADPLL. We used an integer-N ADPLL example with a simple frequency plan to
have more insight into the ADPLL modeling & operation. We have created a test bench for
the ADPLL and used it to observe the locking behavior. Finally the TDC modeling was
presented together with some waveforms to better understand its operation. From now on in
this thesis, the Fractional-N operation will be used unless mentioned otherwise.
Chapter 4
DCO Automatic Tuning
In this chapter we present one of the more sophisticated aspects of the ADPLL, that is a fast
automatic tuning algorithm for the DCO. Many practical implementation issues are shown
along with their solutions. To evaluate the speed of the algorithm, our design example
comprising a 2.4GHz DCO is presented where we use a regression test bench to run the
algorithm many times each with a different initial DCO frequency and record the final DCO
frequency and tuning time. The worst case tuning time is only 7.2µsec.
4.1. Introduction
The DCO is a critical building block of the ADPLL. LC DCOs in particular are preferred for
their potentially better phase noise performance. These LC DCOs use a programmable
switched capacitor bank to produce multiple tuning curves for coarse tuning in an auxiliary
loop as shown in Figure 4-1 using the reference frequency for comparison and an enable signal
Chapter 4 DCO Automatic Tuning
47
to start the algorithm. Then after selecting the nearest curve to the desired frequency, we close
the main loop to perform fine tuning [Kral 98].
DCO
OTW
0
fdco
(Fine)
1
mid_OTW
dco_autotune_N
(Coarse)
dco_auto_tune_enable
fdco
dco_autotune_N
fref
DCO Auto Tune
Figure 4-1 DCO Auto Tuning simplified block diagram
4.2. Existing Automatic Tuning Algorithms
Different methods exist in literature for auto tuning of LC VCOs. A method that relies on
analog comparators is presented in [Behbahani 00]. There, the control voltage of the PLL is
compared to two analog references to guarantee that the PLL is limited within a preset
window of tuning range. The output of the two comparators determines whether the
frequency of the VCO has to be increased or decreased. The technique is cumbersome in the
case of conventional PLLs because of the presence of analog components however it might be
less cumbersome in ADPLLs since digital comparators can be used instead of the analog
comparators.
Another method that is more digital intensive suggests opening a constant time slot specified
by a number of reference cycles, and counting the number of DCO cycles in that time slot for
each tuning curve. Then the tuning curve with the number of DCO cycles closest to an
expected number is chosen as the best curve. This is in essence so similar to another method
48
described in [Wilson 00], where it uses a phase detector and an accumulator. This method
relies on putting both the reference clock and the divided DCO clock to race by counting
edges of both clocks in an accumulator and determine which clock is faster. In [Wilson 00] a
sequential search was implemented but a binary search may also be adopted to expedite the
search.
However, [Hegazi 07] proves that the fundamental problem with this tuning method is that
the phase error between the reference and the divided DCO clock at the beginning of each
search iteration is arbitrary. Therefore, if the divider output is faster than the reference but its
first edge comes late because of a phase shift, the algorithm needs to wait long enough such
that the divided DCO clock compensates for the initial phase delay in order to be able to take
a trusted decision. Moreover, the duration of each search iteration is fixed and limited by the
desired accuracy, i.e. even when the frequency difference between the divider output and the
reference is large the search iteration still waits the same time required to compare smaller
frequency differences.
To mitigate the draw backs in [Wilson 00], [Hegazi 07] proposes a new architecture relying
on three main concepts:
1. Implement a phase detection method that can decide an irreversible decision on which
clock is faster than the other.
2. Terminate the search step once the faster clock is determined.
3. Reduce the maximum initial phase error.
In this work that we published recently in [Shennawy 10] we show how to use the concepts
in [Hegazi 07] to do some modifications to mitigate the drawbacks in the same architecture in
[Wilson 00].
49
4.3. Proposed Automatic Tuning Algorithm
If we are putting the divided DCO frequency fDIV (with period TDIV) and the reference
frequency fR (with period TR) into race, then in order to always guarantee zero initial phase
error, we do the following:
1. In the initial search iteration, we wait until phase alignment occurs and then we start
the algorithm from there.
2. If one clock is faster than the other, their edges will misalign then realign (roll-over)
after a number of cycles “NRO” determined by the DCO center frequency fDCO and the
frequency difference between the two clocks εfDCO.
N RO  TR  N RO  1 TDIV
N RO 1 
N RO
1
TR
TDIV
1
T
f
f
 R  DIV  1  DCO 
N RO TDIV
fR
f DCO
N RO 
f DCO
f DCO
(4.1)

3. Once they realign, a comparator could know which clock is faster for sure and the
search iteration is terminated right away allowing the next search iteration to start,
again with an almost zero initial phase error.
The implementation of this algorithm is shown in Figure 4-2 where a 2.4GHz DCO with 5
tuning bits is tuned using a 150MHz reference frequency. The implementation consists of two
parts: a fully custom block & a fully digital block described in the next sections.
50
4.4. Fully Custom Block:
4.4.1. High Speed Divider by 4:
The high speed divider by 4 divides the 2.4GHz DCO clock fdco to produce the divided
DCO clock fdiv4 which is in the 600MHz range. This is to enable the rest of the algorithm
blocks to operate within the frequency capabilities of digital standard cells and be fully
synthesized. This divider has an enable signal dco_autotune_enable1 to minimize the current
consumption when the algorithm is not in use. Note that for best results, this divider is
required to produce a 50% duty cycle output across all PVT variations. This is to prevent
eating up our setup/hold timing budget in the subsequent logic. A good duty cycle adjustment
circuit is presented in [Maneatis 96].
4.5. Fully Digital Block:
The fully digital block refers to the rest of the algorithm blocks that are fully synthesizable
and can be easily ported from technology to technology.
4.5.1. Multiplexer:
The multiplexer selects to apply mid OTW to the DCO during the automatic tuning process
using the signal dco_autotune_enable1. In normal operation it selects the normal OTW of the
digital loop.
4.5.2. Clock Gating:
Clock gating is used to gate the input clocks fdiv4 and fref by the dco_autotune_enable2
signal to produce the gated clocks fdiv4_g and fref_g. This is to minimize the dynamic current
51
consumption of the subsequent building blocks due to the input clocks when the algorithm is
not in use.
fdiv4
(600MHz)
/4
fdco
(2.4GHz)
OTW
0
DCO
(Fine)
1
mid_OTW
dco_autotune_N
(Coarse)
dco_auto_tune_enable1
fdiv4
(600MHz)
fdiv4_g
(600MHz)
fdiv
(150MHz)
/4
cnt_div
(150MHz)
DCO
Counter
fref_s
(150MHz)
fdiv
(150MHz)
Clock Gating
fref
(150MHz)
fref_g
(150MHz)
Synchronizer
fref_s
(150MHz)
REF
Counter
cnt_ref
(150MHz)
Synchronizer
cnt_ref_s
(150MHz)
Comparator
reset_out_div
dco_auto_tune_enable2
reset_out_ref_s
dco_autotune_reset
dco_autotune_reset
dco_cal_done
On-Chip Digital Controller
Figure 4-2 Proposed DCO Auto Tuning block diagram.
4.5.3. Synchronizer:
Two cascaded D-Flip-Flops used to synchronize the 150MHz fref_g clock by the 600MHz
fdiv4_g clock to produce the synchronized 150MHz reference clock fref_s. This is to let the
whole algorithm be clocked by the same frequency domain –that of the DCO– to avoid any
metastability issues in the subsequent logic.
4.5.4. Divider by 4:
A divider by 4 divides the 600MHz fdiv4_g clock again to produce the fdiv clock which is in
the 150MHz range to be ready for comparison with the 150MHz fref_s clock.
52
4.5.5. Synchronous Counter with Reset:
Two identical counters, one to count the number of ticks of the 150MHz fdiv clock and the
other to count the number of ticks of the 150MHz fref_s clock. The width of these counters
should allow the counting of at least double the number of cycles calculated from (4.1) –
replacing εfDCO by half of the frequency spacing between tuning curves– without overflow.
4.5.6. Bus Synchronizer:
A bus of single D-Flip-Flops used to align the output of the 150MHz REF Counter cnt_ref
to the output of the 150MHz DCO Counter cnt_div rather than being 1, 2 or 3 fdiv4_g cycles
skewed. The alignment is done using the 150MHz fdiv clock producing the 150MHz aligned
REF Counter output cnt_ref_s. This alignment is to enable the subsequent Comparator be a
150MHz Comparator rather than a 600MHz Comparator to be more easily synthesized. Note
that in order to compensate for the delay caused by this Bus Synchronizer, cnt_div is
initialized to 0 while cnt_ref is initialized to 1 when reset.
4.5.7. Comparator:
This block is clocked by the 150MHz fdiv clock. It subtracts cnt_ref_s from cnt_div, and
based on the difference, it determines weather the divided DCO frequency is within the
required REF frequency (in case of zero or ±1) or faster (in case of +2) or slower (in case of 2), then accordingly it takes the decision to terminate the search iteration and instantly jump to
the next curve in a binary search sequence. The Comparator ends the algorithm and asserts the
dco_autotune_done output signal in one of four cases:
1. The initial curve compared is the right one, and then the algorithm is stopped by a
watch dog equal to double the number of fdiv cycles obtained from (4.1).
53
2. The right curve is found in any search iteration before the last search iteration –the one
determining the LSB of dco_autotune_N–, and then the algorithm is stopped by a
watch dog equal to the number of fdiv cycles obtained in (4.1).
3. The right curve is not found until the search iteration before the last, and then in the
last search iteration, the next curve in the search sequence is considered the right one
and the algorithm is stopped right away as there is no need to wait as we have no more
search iterations left to refine the result. This of course assumes monotonic tuning
steps which is a minimum requirement for a good DCO design. This optimization
helped decrease the worst case tuning time from 10.6 to 7.2µsec.
4. The only exception is when we reach the curve number 2 and the Comparator indicates
that we have to go to curve number 1. Only then, we compare the curve number 1
since we still have the curve number 0 to refine the result. If the Comparator indicates
we have to go to curve number 0, then it is considered as the right curve and the
algorithm is stopped right away.
The Comparator block also controls the delivery of the different reset signals to the different
blocks of the algorithm. Namely, the DCO Counter, the Bus Synchronizer and the Comparator
itself are reset by signals synchronized to the fdiv clock. While the REF Counter is reset by
signals synchronized to the fref_s clock. This is to ensure that each block is reset by signals
originating from their input clocks to avoid any release/recovery violations in these blocks.
The reset signal is delivered to the Synchronous Counters and the Bus Synchronizer in each
of the following cases:
54
1. At the beginning of the algorithm upon the assertion of the dco_autotune_reset signal
2. At the end of each search iteration.
3. At the end of the algorithm.
The reset signal is delivered to the Comparator only at the beginning of the algorithm upon
the assertion of the dco_autotune_reset signal.
4.6. Algorithm Execution Sequence
To start the algorithm, the control signals shown in Figure 4-3 should be delivered by the
on-chip digital controller as follows:
1. Assert dco_autotune_enable1 to enable the external divider and apply the mid_OTW.
2. Wait for some time for the external divider to be operational in all PVT conditions, say
100nsec.
3. Assert dco_autotune_enable2 to enable the clock gating and the internal divider.
4. Wait for some time for the gated clocks and internal divider to be operational, say
100nsec.
5. Assert dco_autotune_reset to reset the algorithm blocks.
6. Wait for some time for the algorithm blocks to be reset, say 100nsec.
7. Deassert dco_autotune_reset to actually start the algorithm.
8. Wait until the algorithm is concluded and the dco_autotune_done signal is asserted.
9. Wait for some time for the algorithm blocks to be reset, say 100nsec.
10. Deassert dco_autotune_enable2 to disable the clock gating and the internal divider.
11. Wait for some time for the gated clocks and internal divider to be stopped, say
100nsec.
12. Deassert dco_autotune_enable1 to disable the external divider and apply the OTW.
55
Note that the tuning time that we report is that during which the dco_autotune_enable1
signal is asserted. Smaller tuning times could be obtained by optimizing the wait intervals
between the control signals. In our case we have a total overhead of 0.5µsec that could be
optimized.
Tuning Time
dco_autotune_enable1
dco_autotune_enable2
dco_autotune_reset
dco_autotune_N
16
8
12
14
15
dco_autotune_done
Figure 4-3 Proposed DCO Auto Tuning control signals timing diagram
4.7. Algorithm Verilog Code
`timescale 1ns/1fs
module adpll_dco_auto_tune (dco_auto_tune_enable2, fref, fdiv4,
dco_auto_tune_reset, dco_auto_tune_override, dco_auto_tune_N_override,
dco_auto_tune_N, dco_auto_tune_done);
parameter width = adpll_top_tb.width;
parameter width_atcntr = adpll_top_tb.width_atcntr;
parameter inv_alpha = adpll_top_tb.dut.flt.inv_alpha;
input dco_auto_tune_enable2;
input dco_auto_tune_reset;
input fref;
56
input fdiv4;
input dco_auto_tune_override;
input [width-1-inv_alpha:0] dco_auto_tune_N_override;
output wire [width-1-inv_alpha:0] dco_auto_tune_N;
output wire dco_auto_tune_done;
wire fref_g;
wire fdiv4_g;
wire fref_s;
wire fdiv;
wire [width_atcntr-1:0] cnt_div;
wire [width_atcntr-1:0] cnt_ref;
wire [width_atcntr-1:0] cnt_ref_s;
wire reset_out_div;
wire reset_out_fref_s;
wire [width-1-inv_alpha:0] dco_auto_tune_N_int;
assign dco_auto_tune_N[width-1-inv_alpha] = ~dco_auto_tune_N_int[width-1inv_alpha];
// To convert center curve from mid code to code 0 to be compatible
with 2's compliment arithmetic
assign dco_auto_tune_N[width-2-inv_alpha:0] = dco_auto_tune_N_int[width-2inv_alpha:0];
// To convert center curve from mid code to code 0 to be compatible
with 2's compliment arithmetic
adpll_dco_clock_gating vco_clk_gate (dco_auto_tune_enable2, fref, fdiv4, fref_g,
fdiv4_g);
//fdiv4 = 600MHz, fdiv = 150MHz
adpll_dco_reset_generator vco_res_gen (dco_auto_tune_reset, fdiv, reset);
57
adpll_dco_divider_4 vco_div_4 (fdiv4_g, fdiv, dco_auto_tune_enable2);
adpll_dco_counter_div div_cnt (fdiv, cnt_div, reset_out_div);
adpll_dco_counter_ref ref_cnt (fref_s, cnt_ref, reset_out_ref_s);
adpll_dco_synchronizer_reg vco_sync_ref (fref_g, fref_s, fdiv4_g);
adpll_dco_synchronizer_bus vco_sync_cnt_ref (cnt_ref, cnt_ref_s, fdiv,
reset_out_div);
adpll_dco_comparator vco_cmp (fdiv, fref_s, cnt_div, cnt_ref_s, reset,
dco_auto_tune_override, dco_auto_tune_N_override, reset_out_div, reset_out_ref_s,
dco_auto_tune_N_int, dco_auto_tune_done);
endmodule
`timescale 1ns/1fs
module adpll_dco_clock_gating (enable,fref,fdiv4,fref_g,fdiv4_g);
input enable;
input fdiv4;
input fref;
output fdiv4_g;
output fref_g;
reg enable_int1_div4;
reg enable_int2_div4;
reg enable_int1_ref;
reg enable_int2_ref;
58
assign fdiv4_g = fdiv4 && enable_int2_div4;
assign fref_g = fref && enable_int2_ref;
always @ (negedge fdiv4)
begin
enable_int1_div4 <= enable;
//one Flip-flop
enable_int2_div4 <= enable_int1_div4; //another Flip-flop
end
always @ (negedge fref)
begin
enable_int1_ref <= enable;
enable_int2_ref <= enable_int1_ref;
//one Flip-flop
//another Flip-flop
end
endmodule
`timescale 1ns/1fs
module adpll_dco_reset_generator (reset_in,fdiv,reset);
input reset_in;
input fdiv;
output wire reset;
59
reg edge2pulse_1;
reg edge2pulse_2;
reg edge2pulse_3;
reg edge2pulse_4;
always @ (negedge fdiv)
begin
edge2pulse_1 <= reset_in;
edge2pulse_2 <= edge2pulse_1;
end
assign reset = edge2pulse_3 && ~edge2pulse_4;
endmodule
`timescale 1ns/1fs
module adpll_dco_divider_4 (fin,fout,enable);
input fin;
input enable;
output wire fout;
reg [1:0]cnt;
//posedge to pulse converter
60
assign fout = cnt[1];
always @ (posedge fin or negedge enable)
begin
if ( ~enable )
cnt <= 2'b00;
else
cnt <= cnt - 1'b1; // rather than + i.e descending counter in order to obtain aligned
rising edges to increase time budget to 1/4 div cycle rather than 1/8 div cycle
end
endmodule
`timescale 1ns/1fs
module adpll_dco_counter_div (in,out,reset);
input in;
input reset;
output reg [width_atcntr-1:0] out;
always @ (posedge in or posedge reset)
begin
61
if ( reset )
out <= 0;
else
out <= out + 1'b1;
end
endmodule
`timescale 1ns/1fs
module adpll_dco_counter_ref (in,out,reset);
input in;
input reset;
always @ (posedge in or posedge reset)
begin
if ( reset )
out <= 1;
else
out <= out + 1'b1;
end
62
endmodule
`timescale 1ns/1fs
module adpll_dco_synchronizer_reg (in,out,clk);
input in;
input clk;
output reg out;
reg intermediate;
always @ (posedge clk)
begin
intermediate <= in; //one Flip-flop
out <= intermediate; //another Flip-flop
end
endmodule
`timescale 1ns/1fs
module adpll_dco_synchronizer_bus (in,out,clk,reset);
63
input [width_atcntr-1:0] in;
input reset;
input clk;
always @ (posedge reset or posedge clk)
begin
if (reset)
out <= 0;
else
out <= in;
end
endmodule
`timescale 1ns/1fs
module adpll_dco_comparator (div, ref_s, cnt_div, cnt_ref, reset, override, N_override,
reset_out_div, reset_out_ref_s, N, flag);
parameter fcentre = adpll_top_tb.fcentre;
parameter Kdco = adpll_top_tb.Kdco;
64
real fcentre_real = fcentre;
real Kdco_real = Kdco;
real max_count = fcentre_real/0.5/(Kdco_real/1000);
//implemented this way
because "parameter" doesn't accept mathematical operations
real min_count = 4;
input div;
input ref_s;
input reset;
input override;
input [width_atcntr-1:0] cnt_div;
input [width_atcntr-1:0] cnt_ref;
input [width-1-inv_alpha:0] N_override;
output reset_out_div;
output reset_out_ref_s;
output reg [width-1-inv_alpha:0] N;
output reg flag;
reg [width-2-inv_alpha:0] step;
reg [width-2-inv_alpha:0] iteration;
//Could be less than that but this is more than
enough just to make it parameterized
reg reset_in0;
reg reset_in1_div;
// register used in the edge to pulse conversion
reg reset_in2_div;
// register used in the edge to pulse conversion
reg reset_in1_ref_s; // register used in the edge to pulse conversion
reg reset_in2_ref_s; // register used in the edge to pulse conversion
65
wire reset_in3;
wire [width_atcntr-1:0] ref_1s_compliment;
wire [width_atcntr:0] difference;
assign ref_1s_compliment[width_atcntr-1:0] = ~cnt_ref;
assign difference = cnt_div + ref_1s_compliment + 1'b1;
assign reset_in3_div = reset_in0 ^ reset_in2_div;
assign reset_out_div = reset_in3_div | flag | reset;
assign reset_in3_ref_s = reset_in0 ^ reset_in2_ref_s;
assign reset_out_ref_s = reset_in3_ref_s | flag | reset;
always @ (posedge div or posedge reset or posedge override)
begin
if ( reset )
begin
N <= 2**(width-1-inv_alpha);
flag <= 1'b0;
step <= 2**(width-2-inv_alpha);
iteration <= 0;
reset_in0 <= 1'b0;
end
else if ( override )
begin
N <= N_override;
flag <= 1'b1;
step <= 2**(width-2-inv_alpha);
66
iteration <= 0;
reset_in0 <= 1'b0;
end
else if ( (difference[width_atcntr] == 1'b1) && (difference[1:0] > 2'b01) && (iteration
== 0) && (cnt_div > min_count) )
begin
reset_in0 <= !reset_in0;
iteration <= iteration + 1'b1;
end
else if ( (difference[width_atcntr] == 1'b0) && (difference[1:0] < 2'b11) && (iteration
== 0) && (cnt_div > min_count) )
begin
end
else if ( (difference[width_atcntr] == 1'b1) && (difference[1:0] > 2'b01) && (iteration
< width) && (cnt_div > min_count) )
begin
N <= N - step;
//for increasing f with increasing N
step <= step >> 1;
end
else if ( (difference[width_atcntr] == 1'b0) && (difference[1:0] < 2'b11) && (iteration
< width) && (cnt_div > min_count) )
begin
N <= N + step;
//for increasing f with increasing N
67
step <= step >> 1;
end
else if ( (difference[width_atcntr] == 1'b0) && (difference[1:0] < 2'b11) && (N == 1)
&& (cnt_div > min_count) )
begin
N <= 0;
end
else if ( (cnt_div >= 2*max_count) && (iteration == 0) )
// in case the dco is
already oscillating at the desired frequency at the initial tuning curve tried
begin
flag <= 1'b1;
end
else if ( (cnt_div >= max_count) && (iteration > 0) )
begin
flag <= 1'b1;
end
end
always @ (posedge div or posedge reset)
begin
if ( reset )
reset_in1_div <= 1'b0;
else
reset_in1_div <= reset_in0;
68
end
always @ (posedge div or posedge reset)
begin
if ( reset )
reset_in2_div <= 1'b0;
else
reset_in2_div <= reset_in1_div;
end
always @ (posedge ref_s or posedge reset)
begin
if ( reset )
reset_in2_ref_s <= 1'b0;
else
reset_in2_ref_s <= reset_in1_div;
end
endmodule
69
4.8. Simulation Results
In order to verify the proposed algorithm, a simulation example comprising a 2.4GHz DCO
with 5 control bits, i.e. 32 tuning curves with 20MHz spacing between each two curves and
150MHz reference frequency is prepared. Substituting in (4.1) we get NRO = 2.4GHz/10MHz
= 240. So we use 9 bit accumulators to be able to count double that number without overflow.
A regression test bench is prepared to thoroughly test the algorithm in various combinations
of initial phase error and DCO center frequency.
The final DCO center frequency after tuning is shown in Figure 4-4. We can see that all
regression iterations are within the expected 2.4GHz ± 10MHz range except some regression
iterations that are slightly off at the lower end of this range. This is due to the presence of the
Bus Synchronizer which always introduces some retiming error in the same direction. If the
Comparator can be clocked at 600MHz without any setup/hold violations, then we could
remove the Bus Synchronizer and all regression iterations will pass.
The final DCO tuning curve number after tuning is shown in Figure 4-5, while the tuning
time is shown in Figure 4-6. If we wait until we compare the frequencies in the last search
iteration, we get the tuning times indicated in gray. On the contrary, if we terminate the
algorithm before the last search iteration as we mentioned before, we get the optimized tuning
times indicated in black. Note that the shape of these curves has some physical meaning where
the peaks represent the regression iterations where the final frequency is so close to the
desired 2.4GHz frequency. Also the odd peaks (before optimization) are generally higher than
the even peaks indicating the time needed for the extra search iteration. The gain in tuning
time after optimization is clear for the odd tuning curves and curve number 0 where we save
more than 50% of the tuning time. Also we can see that the implemented watchdogs help in
70
limiting the tuning time. It is worth mentioning that in general, we can always decrease tuning
time for the same required accuracy by using a faster reference frequency i.e. decreasing TR.
Simulation results are summarized in Table 4-1. We see that the average tuning time is
4.2µsec while the worst case tuning time is 7.2µsec. This worst case tuning time is so close to
the single reading of 7µsec achieved in [Hegazi 07].
Min
Typ
Max
Unit
Frequency
2.388
2.399
2.410
GHz
Tuning Time
1.716
4.227
7.213
µsec
Table 4-1 Regression Test Bench Results Summary
dco_frequency(GHz)
2.415
2.410
2.405
2.400
2.395
2.390
2.385
1
51
101
151
201
251
301
351
401
451
501
551
601
Regression Iteration
Figure 4-4 Simulated Final DCO Frequency vs. Regression Iteration
651
71
dco_autotune_N
32
28
24
20
16
12
8
4
0
1
51
101
151
201
251
301
351
401
451
501
551
601
651
Figure 4-5 Simulated Tuning Curve Number vs. Regression Iteration
dco_tuning_time(us)
12
Unoptimized
10
Optimized
8
6
4
2
0
1
51
101
151
201
251
301
351
401
451
501
551
601
651
Figure 4-6 Simulated Tuning Time vs. Regression Iteration
4.9. Summary
A fast auto tuning algorithm for DCOs has been presented. Many practical implementation
issues have been shown along with their solutions. A design example comprising a 2.4GHz
DCO has been used to evaluate the algorithm. Regression simulations show a worst case
tuning time of only 7.2µsec with room for improvement.
Chapter 5
KDCO Calibration within the ADPLL
In this chapter, we explain a method of estimating the gain of the DCO. By executing the
calculation algorithm just-in-time at the beginning of every packet, the DCO gain can be
conveniently tracked and compensated. This enables the employment of sophisticated and
fully-digital frequency synthesizers capable of compensating for analog non-idealities.
5.1. Introduction
As discussed previously in chapter 1, the design flow and circuit techniques of conventional
frequency synthesizers for commercial RF wireless applications are analog intensive and utilize
process technologies that are incompatible with a digital baseband (DBB). Nowadays, the
DBB design constantly migrates to the most advanced deep-sub-micrometer digital CMOS
process available, which usually does not offer any analog extensions and has very limited
73
Chapter 5 KDCO Calibration
voltage headroom. Consequently, the aggressive cost and power reductions of high-volume
mobile wireless solutions can only be realistically achieved by the highest level of integration,
and this favors a digitally-intensive approach in the most aggressive deep sub-micrometer
process.
Advanced CMOS process lithography allows us to create extremely small-size but wellcontrolled varactors with switchable capacitance of the finest differential varactor on the order
of tens of Atto Farads. A DCO which deliberately avoids any analog tuning voltage controls
was recently presented in [Staszewski 03d]. Fine frequency resolution is achieved through
high-speed ΣΔ dithering. This allows for its loop control circuitry to be implemented in a fully
digital manner, as demonstrated in [Staszewski 03a]. Other imperfections of analog circuits
are compensated through digital means.
The majority of commercial GFSK (Bluetooth) or GMSK (GSM cellular phones)
transmitters are based on the direct I–Q up-conversion modulation scheme. A chief weakness
of this analog-intensive architecture is that even a small mismatch in phase shift or amplitude
gain between the I and Q paths can significantly impair the system performance. Furthermore,
because of a certain amount of inherent frequency shift between the modulator input and
output, the strong power amplifier signal can cause frequency pulling of the oscillator through
injection locking.
Fractional-N frequency synthesizer architecture [Miller 91], [Riley 93] avoids both of the
above problems and lends itself well to an indirect narrowband frequency modulation which
could be implemented in a more digital manner. As long as the modulation data rate is lower
than the phase locked loop (PLL) bandwidth, the average frequency division ratio (N) digital
command word, which corresponds to a desired channel, could be augmented by the
instantaneous value of the modulation frequency deviation. A method to increase the data rate
74
by compensating for the PLL high-frequency attenuation through boosting the high-frequency
components of the modulation signal was proposed in [Perrott 97]. This architecture,
however, requires precise matching between the digital pre-compensation filter and the analog
PLL transfer function across process and temperature variations. The loop filter transfer
function is set digitally in [Bax 01], but the voltage-controlled oscillator (VCO) gain there still
requires matching. An automatic and continual PLL calibration method using analog
techniques was presented in [McMahill 02]. A two-point direct modulation scheme [Bopp 99]
performs phase compensation of the PLL by digitally integrating the transmit modulating data
bits and using the integrator output to shift the phase of the reference clock signal, while the
Gaussian filtered data directly modulates the VCO frequency. However, this approach is also
quite analog in nature and requires a precise component matching, of not only the VCO but
also the phase shifter. A similar method was also disclosed in [Filiol 01]. Another feed-forward
compensation method, which also requires a precise knowledge of the VCO transfer function
and other analog circuits, was proposed in [Zhang 99]. It uses DSP to calculate inverse of the
VCO transfer function, which is obtained through laboratory measurements, followed by a
high-precision DAC to pre-tune the VCO control voltage to the desired excursion.
In contrast, the work in [Staszewski 06] proposes a DCO gain calibration solution that is
digital in nature, consumes little hardware overhead, and requires only one component
matching, i.e. DCO, which is done just-in-time in a digital manner with a very fine resolution.
Novel methods of both the direct frequency modulation and the calibration of the RF oscillator
transfer function that avoid the above problems are described. These methods could be
employed without regard to any specific digitally intensive synthesizer architecture.
75
5.2. DCO Transfer Function & Gain
The
digitally-controlled
oscillator
[Staszewski 03d]
performs digital-to-frequency
conversion. Its output frequency f is a certain function of the digital oscillator tuning word
(OTW) input. In general, this mapping is a nonlinear function that is not known precisely and
it varies with process spread and environmental factors (voltage and temperature), i.e., process
voltage temperature (PVT). However, within a limited range of operation it could be
approximated by:
f OTW   f o  f  f o  K DCO  OTW
(5.1)
KDCO is specifically defined as a frequency deviation Δf (in hertz) from a certain oscillating
frequency fo in response to 1 least significant bit (LSB) of the input change. Within a linear
range of operation, the DCO gain can also be expressed as:
K DCO  f  
f
OTW
(5.2)
The oscillator gain dependence on PVT and frequency makes it a good choice to estimate it
on a per-needed basis within the actual environment. This is especially important in batteryoperated cellular phones with frequency-hopping operation where, for example, the supply
voltage can vary rapidly with the adaptive transmit power.
5.3. DCO Gain Normalization
At a higher level of abstraction, the DCO oscillator, together with the DCO gain
normalization f R / Kˆ DCO multiplier, logically comprise the normalized DCO (nDCO), as
illustrated in figure 5-1. The DCO gain normalization conveniently decouples the phase and
frequency information throughout the system from the process, voltage and temperature
76
variations that normally affect the KDCO. The frequency information is normalized to the value
of the external reference frequency fR.
Normalized DCO (nDCO)
DCO gain
normalization
Normalized
Tuning Word
(NTW)
DCO
OTW
fR/KDCO
28
Δf from fo
28
[(Hz/LSB)/(Hz/LSB)]
KDCO [(Hz/LSB)]
KnDCO [(Hz/LSB)]
Figure 5-1 Normalized DCO block diagram
The digital input to the nDCO is a fixed-point normalized tuning word (NTW), whose
integer part LSB bit corresponds to fR. Note that the reference frequency is chosen as the
normalization factor because it is the master basis for the frequency synthesis. In addition, the
clock rate and update operation of this discrete-time system are established by the reference
frequency.
The quantity KDCO should be contrasted with the process voltage temperature independent
oscillator gain KnDCO which is defined as the frequency deviation (in hertz units) of the DCO in
response to the 1 LSB change of the integer part of the NTW input. If the DCO gain estimate
K̂ DCO is exact, then KnDCO = fR/LSB, otherwise:
K nDCO 
f R K DCO
f
 R r
LSB Kˆ DCO LSB
(5.3)
Dimensionless ratio r  K DCO / Kˆ DCO is a measure of the DCO gain estimation accuracy.
5.4. Predictive/Closed PLL Operation
The main reason behind the effort of estimating the KDCO gain is a need for predictive loop
operation in order to realize a direct-transmit frequency modulation. Figure 5-2 depicts a
77
digital PLL-based frequency synthesizer [Staszewski 03a] with a digital direct frequency
modulation of the oscillator. The modulating data y[k] (normalized to the reference frequency
fR) directly affects the oscillating frequency by Δf[i], where k  i / N  and N is the frequency
division ratio. The PLL will try to correct this perceived frequency perturbation integrated
over the update period TR=1/fR. This corrective action is compensated by the other
(compensating) y[k] feed that is integrated by the reference phase accumulator.
The compensation is exact if r = 1, i.e., Kˆ DCO  K DCO . In this case, the loop response to y[k]
is all-pass and y[k] directly modulates the DCO frequency in a feed-forward manner such that
it effectively removes the loop dynamics from the modulating transmit path. However, the rest
of the loop, including all error sources, operates under the normal closed-loop regime.
Analysis of the KDCO error on the loop response is deferred until section 5.6.
The immediate and direct DCO frequency control, made possible by accurate prediction of
the DCO transfer function, is combined with the phase compensation of the PLL loop
response. The two factors constitute the hybrid of predictive/closed PLL loop modulation
method.
Cause-effect
Δf
Direct Feed
y[k]
Compensating Feed
y[k]
Reference Phase
Accumulator
Channel Frequency
Control Word
(FCW)
+
ΔOTW
(FCW’)
Σ
Phase
Detector
Proportional
Loop Gain
ΦE[k]
RR[k]
+
DCO Gain
Normalization
d[k]
α
+
Oscillator
+
fR/KDCO
KDCO
(NTW)
(OTW)
-
Sampler with
linear interpolator
RV[k]
DCO Phase
Accumulator
RV[i]
TR
Σ
1
Figure 5-2 Two point modulated ADPLL model [Staszewski 06]
Δf[i] from fo
78
5.5. DCO Gain Estimation using the ADPLL
The DCO gain estimation K̂ DCO could now be conveniently and just-in-time calculated at
the beginning of every packet by forcing the PLL frequency deviation Δf and measuring the
steady-state change in the oscillator tuning word ΔOTW as figure 5-2 suggests
Kˆ DCO  f  
f
OTW
(5.4)
In this architecture, Δf can be accurately produced since fR is known and its respective
frequency control word (FCW = Δf = fR) is computed in a digital manner. Given the accurate
Δf perturbation, the resulting change in the DCO tuning word is measured digitally. For this
reason, this technique can be very accurate. Note that K̂ DCO is actually used in the
denominator of the DCO gain normalization multiplier
fR
Kˆ DCO

fR
 OTW
f
(5.5)
This is quite beneficial since the unknown OTW is in the numerator and the inverse of the
forced Δf is known and could be conveniently pre-calculated. This way, use of an arithmetic
divider is avoided. If the KDCO gain is estimated correctly to start with, the precise frequency
shift will be accomplished in one step, as shown in figure 5-3. However, if the KDCO is not
estimated accurately, then the first frequency jump step will be off target by a
K
DCO

/ Kˆ DCO  1 fraction and one would require a number of clock cycles to correct the
estimation error through the normal PLL loop dynamics.
79
Oscillator Tuning Word (OTW)
single step
feedforward jump
correct
estimate
Δf
overestimate
underestimate
Average M1
samples
Waiting W cycles for the
ADPLL to settle
Average M2
samples
time
ADPLL
settled
ADPLL frequency
changed by Δf
ADPLL
settled
KDCO calibration
done
Figure 5-3 DCO gain estimate by measuring tuning word change in response to a fixed frequency jump.
To lower the measurement variance, it is advantageous to average out the tuning inputs
before and after the transition, as revealed by figure 5-3.
Figure 5-4 shows a DCO gain calculation flowchart. After the desired frequency is acquired,
M1 samples of oscillator tuning word OTW are averaged and the result is stored as OTW1.
Thereafter, a suitable frequency change Δf is imposed and the system waits W clock cycles for
the PLL loop to settle. M2 samples of OTW are then averaged and the result is stored as
OTW2. Finally, the DCO gain estimate K̂ DCO or the normalizing gain f R / Kˆ DCO is computed.
It is very convenient to limit M1 and M2 to power-of-2 integers, since the division operation is
simplified now to a trivial right-bit-shift.
80
Acquire desired frequency
Accumulate M1 samples of OTW
Divide by M1
Store OTW1
Change ADPLL frequency by Δf
Wait for W clock cycles
Accumulate M2 samples of OTW
Divide by M2
OTW2 obtained
Calculate:
KDCO = Δf/(OTW2-OTW1)
or
fR/KDCO = (fR/Δf)*(OTW2-OTW1)
Figure 5-4 DCO gain estimation flowchart.
It should be noted that a frequency jump equal to the full modulation range is beneficial for
two reasons. First, little hardware overhead is required on top of the existing transmit
modulator circuitry to execute the chosen frequency jump. Second, measuring the local gain
value around the expected operational range is bound to provide the most accurate estimate.
In order to further improve the estimate, a larger frequency step of two symbols, thus,
covering the whole data modulation range is performed.
81
5.6. Effect of Incorrect KDCO Estimation
The z domain transfer function from the direct feed of the modulating data y[k] to the
frequency deviation Δf at the PLL output (figure 5-2) is:
H DF z  
ADF z 

1  ADF z  DF z 
fRr
z 1 1
1 fRr

1  z 1 f R
Note that the DCO gain normalization + DCO is a digital to frequency converter, therefore
has units of Hz/LSB, while the Oscillator phase accumulator + Sampler with linear
interpolator is a frequency to digital converter, therefore has units of LSB/ Hz. More
precisely, The DCO gain normalization + DCO model is expressed as fRr Hz/LSB, while the
Oscillator phase accumulator + Sampler with linear interpolator is expressed as z -1/(1-z-1) /fR
LSB/Hz.
Similarly, the z domain transfer function from the compensating feed of the modulating data
y[k] to the frequency deviation Δf at the PLL output is:
H CF z  
ACF z 
z 1
z 1

1  z 1 1  ACF z  CF z  1  z 1
f R r
z 1 1
1  f R r
1  z 1 f R
Thus the overall z domain transfer function from both the direct and the compensating feeds
of the modulating data y[k] to the frequency deviation Δf at the PLL output is:


1


1


f
r
z
R
H z    


1 
1

 1  z  1  r z
1 

1 z 
This could be simplified as follows:


1   f R r 1  z 1 
1
H z    
1
1 

 z  1 1  z  rz 
(5.6)
82
1  f R r z  1
1
 


 z  1  z  1  r 
 z  1      z  1 
 fRr


  z  1   z  1  r 
To reach the transfer function in pole/zero form:
 H z   f R r
z  1   
z  1  r 
(5.7)
So we see that the overall z domain transfer function from both the direct and the
compensating feeds of the modulating data y[k] to the frequency deviation Δf at the PLL
output has a pole at (1 - rα) and a zero at (1 - α) as shown in figure 5-5.
Z=j
decreasing r
r>1 r<1
Z=-1
Z=1
α
rα
Z=-j
Figure 5-5 Complex plane location of the H(z) zero and pole movement with different values of the DCO
gain estimate accuracy r.
The dc gain (at f = 0 Hz, z  e j 2f / f R  1 ) is always fR, which could be readily seen by
inspection:
H z  z 1  f R r
1  1   
 fR
1  1  r 
The high-frequency gain (at f = fR/2 Hz, z  e j 2f / f R  1 ) is:
H z  z 1  f R r
 2 
 2  r
83
Which could be further simplified when the realistic approximation of (α << 1) is assumed


 1  1
H  1  f R r  2     
 2  1  r

2







   r 
 f R r 1  1 

2 
2 

  r r 2
 f R r 1  

2
2
4




r

r  1
 H  1  f R  r 
2


(5.8)
Therefore, for r > 1, H(-1) > fR, while for r < 1, H(-1) < fR
Figure 5-6 shows the direct modulation transfer function H(f) for various cases of the KDCO
estimate accuracy r. In case of the incorrect KDCO estimate, the transfer function is either
somewhat high-pass or low-pass. This is governed both by the single pole and single zero
locations at rαfR/2π and αfR/2π of linear frequency in hertz, respectively. The pole location
happens to be the same as the PLL phase transfer function loop bandwidth fBW of the reference
noise or of the modulating data without the feed-forward y[k] entry. The feed-forward y[k]
path could be simply viewed as placing a compensating zero in the pole’s vicinity.
Note that the difference between the high frequency and low frequency gains is expressed
as:
r

r  1  f R
H  1  H 1  f R  r 
2


r

r  1  1
 fR r 
2


 r 
 H  1  H 1  f R r  11 

2 

and is indicated in Figure 5-6
84
Only when the DCO gain estimate is correct, the pole and the zero coincide letting this
difference tend to zero, and the direct frequency modulation of the PLL loop exhibits truly
wideband all-pass transfer characteristics up to the half of the sampling frequency (fR). This
allows supporting modulation bandwidth of up to fR/2. It should be noted that the presented
idea does work equally well with higher order PLLs.
Figure 5-6 Direct modulation transfer function H(f) where f ≈ (fR/2π)(z-1) for f << fR, with different
values of the DCO gain estimate accuracy r according to [Staszewski 06].
Here we would like to point out that the transfer function shown in Figure 5-6 which is
presented in [Staszewski 06] isn’t strictly accurate, that is because it makes it look like the
zero location for r > 1 is at the pole location for r < 1 equal to the loop bandwidth, while the
pole location for r > 1 is at the zero location for r < 1. While in fact, the zero location in all
cases is the same as it is not a function of r, while the pole location in all cases which is equal
to the loop bandwidth is what varies with r as shown in Figure 5-7.
85
H(f)
fR
r > 1 (KDCO underestimated)
r = 1 (correct KDCO estimated)
1
(r-1)(1+αr/2)
r < 1 (KDCO overestimated)
fR
2π
(r < 1)
rα
α
fR
2π
fR
2π
(r > 1)
rα
fR/2
f
Figure 5-7 Actual direct modulation transfer function H(f) where f ≈ (fR/2π)(z-1) for f << fR, with
different values of the DCO gain estimate accuracy r according to this work.
5.7. Algorithm Verilog Code
`timescale 1ns/1fs
module adpll_gain_est(reset, clk, fcw, dco_gain_est_start, dco_gain_est_done,
cnt_err,cnt_err_correction);
parameter width_fraction = adpll_top_tb.width_fraction;
parameter width_settling = 12;
parameter width_averaging = 8;
parameter settling_samples = 2**width_settling;
parameter averaging_samples = 2**width_averaging;
input reset;
input clk;
output [width-1+width_fraction:0] fcw;
86
input dco_gain_est_start;
output dco_gain_est_done;
input [width-1+width_fraction:0] cnt_err;
output [width-1+width_fraction:0] cnt_err_correction;
reg [width-1+width_fraction:0] fcw;
reg [width_settling+1:0] sample;
reg [width-1+width_fraction+width_averaging:0] accumulator;
reg [width-1+width_fraction:0] average1;
reg [width-1+width_fraction:0] average2;
reg [width-1+width_fraction:0] cnt_err_correction;
reg dco_gain_est_done;
always @ (posedge clk or posedge reset or posedge dco_gain_est_start)
begin
if ( reset )
begin
fcw = 16*2**width_fraction;
sample <= 0;
accumulator <= 0;
average1 <= 0;
average2 <= 0;
cnt_err_correction <= 1;
dco_gain_est_done <= 1'b0;
end
//fr/kdco_cap
87
else if ( dco_gain_est_start )
begin
sample <= sample + 1'b1;
if (sample > 0 && sample <= settling_samples+averaging_samples+2)
if (sample > settling_samples && sample <
settling_samples+averaging_samples+1)
accumulator <= accumulator + {{width_averaging{cnt_err[width–
1+width_fraction]}},cnt_err};
if (sample == settling_samples+averaging_samples+1)
average1 <= accumulator >> width_averaging;
if (sample == settling_samples+averaging_samples+2)
accumulator <= 0;
if (sample > settling_samples+averaging_samples+2 && sample <=
settling_samples+averaging_samples+2+settling_samples+averaging_samples+2)
if (sample > settling_samples+averaging_samples+2+settling_samples && sample
< settling_samples+averaging_samples+2+settling_samples+averaging_samples+1)
accumulator <= accumulator + {{width_averaging{cnt_err[width1+width_fraction]}},cnt_err};
88
if (sample == settling_samples + averaging_samples + 2 + settling_samples +
averaging_samples + 1)
average2 <= accumulator >> width_averaging;
if (sample == settling_samples + averaging_samples + 2 + settling_samples +
averaging_samples + 2)
begin
cnt_err_correction <= ({average1[width-1+width_fraction],average1[width1+width_fraction:0]} - {average2[width-1+width_fraction],average2[width1+width_fraction:0]}) >> 4+width_fraction;
//Divide by delta fcw which is 24-8=16
that is shift right by 4 places
accumulator <= 0;
sample <= 0;
end
end
end
endmodule
`timescale 1ns/1fs
module adpll_gain_norm(cnt_err_ntw,cnt_err_otw,cnt_err_correction);
89
parameter width_fraction = adpll_top_tb.width_fraction;
input [width-1+width_fraction:0] cnt_err_ntw;
wire [width-1+width_fraction:0] cnt_err_ntw_int;
input [width-1+width_fraction:0] cnt_err_correction;
wire
[2*width-1+2*width_fraction:0] cnt_err_otw_int;
output [2*width-1+width_fraction:0] cnt_err_otw;
assign cnt_err_ntw_int = cnt_err_ntw[width – 1 + width_fraction]?
~cnt_err_ntw+1:cnt_err_ntw;
assign cnt_err_otw_int = cnt_err_ntw_int*cnt_err_correction;
assign cnt_err_otw = cnt_err_ntw[width-1+width_fraction]?
~cnt_err_otw_int[2*width-1+2*width_fraction:0]+1:cnt_err_otw_int[2*width1+2*width_fraction:0];
endmodule
90
In this test-bench, KDCO calibration is started with a default value of the gain normalization
factor of 1. It is clear that there is a significant rise and fall time for the OTW when the input is
fed from the compensating feed only. Then at the end of the algorithm, the resulting gain
normalization factor turns out to be 2 and is directly applied. Thus a frequency hit occurred as
could be seen at 60µsec in Figure 5-8.
Then KDCO calibration is started again with the new value of the gain normalization factor of
2. It is clear that there is still rise and fall times for the OTW as the input is still fed from the
compensating feed only but these times are halved as the loop gain is doubled after applying
the new gain normalization factor. Then at the end of the algorithm, the resulting gain
normalization factor is still the same at 2. Thus no frequency hit occurred as could be seen at
130µsec in Figure 5-8.
Then starting from 140µsec, both the direct and compensating feeds are enabled and various
frequency jumps are applied. It is clear that now the transitions in the OTW are instantaneous
as opposed to the transitions during the gain estimation.
91
Figure 5-8 KDCO Calibration Simulation Result
Chapter 6
The ADPLL as an FSK Transmitter
In this chapter we integrate the introduced DCO auto-tuning algorithm and KDCO estimation
and normalization algorithm with the ADPLL model introduced in Chapter 3 and we show
how these algorithms are incorporated in sequence to prepare the ADPLL to be used as an
FSK Transmitter.
6.1. Introduction
The ADPLL based frequency synthesizer when used as an FSK transmitter is shown in
Figure 6-1. As discussed in chapter 4, a multiplexer is used to break the loop and introduce
mid OTW to the DCO. Also gates are used to enable/disable both the direct & compensating
feeds independently.
Chapter 6 The ADPLL as an FSK Transmitter
93
Data
28
Reference Phase
Accumulator
Channel Frequency
Control Word
(FCW)
+
(FCW’)
28
Σ
Phase
Detector
Proportional
Loop Gain
ΦE[k]
RR[k]
+
DCO Gain
Normalization
α
+
+
fR/KDCO
28
28
28
0
Δf[i] from fo
(NTW)
(OTW)
28
(mid_OTW)
-
28
Oscillator
d[k]
1
28
dco_auto_tune_enable
dco_autotune_N
Sampler with
linear interpolator
RV[k]
28
DCO Phase
Accumulator
RV[i]
TR
Σ
28
6
DCO Auto
Tune
FREF
1
28
Figure 6-1 ADPLL-based RF frequency synthesizer when used as an FSK transmitter
6.2. Test Bench Verilog Code
`timescale 1ns/1fs
module adpll_top_tb;
parameter width = 12; // Setting the bus integer widths
parameter width_fraction = 16; // Setting bus fractional widths
parameter fcentre = 2.4;
parameter Kdco = 75;
// GHz
// MHz/Integer_LSB
parameter width_atcntr = 8;
//2**width_atcntr needs to be >
2*fcentre_rel/0.5/(fdelta_real/1000)
reg reset;
reg fref;
reg [width-1+width_fraction:0] fcw;
reg dco_gain_est_start;
wire dco_gain_est_done;
94
reg comp_feed_en;
reg dir_feed_en;
reg [width-1+width_fraction:0] data;
wire fdco;
reg dco_auto_tune_enable1;
reg dco_auto_tune_enable2;
reg dco_auto_tune_reset;
reg dco_auto_tune_override;
reg [width-1-inv_alpha:0] dco_auto_tune_N_override;
wire [width-1-inv_alpha:0] dco_auto_tune_N;
wire dco_auto_tune_done;
initial // Reference Clock Generator
begin
fref = 0;
forever #(0.5/0.15) fref = !fref;
end
initial
begin
reset = 0;
comp_feed_en = 1;
dir_feed_en = 1;
data = 0;
dco_gain_est_start = 1'b0;
//150MHz
95
#5 reset = 1;
#5 reset = 0;
dco_auto_tune_override = 1'b0;
dco_auto_tune_N_override = 10;
fref = 1'b1;
dco_auto_tune_reset = 1'b0;
dco_auto_tune_enable1 = 1'b0;
dco_auto_tune_enable2 = 1'b0;
//DCO Auto-Tuning
#100 dco_auto_tune_enable1 = 1'b1;
#100 dco_auto_tune_reset = 1'b1;
#100 dco_auto_tune_reset = 1'b0;
#100 wait (dco_auto_tune_done == 1'b1);
//DCO Gain Estimation
#3990 dco_gain_est_start = 1'b1;
#1000 wait (dco_gain_est_done == 1'b1);
#12000 dco_gain_est_start = 1'b1;
#1000 wait (dco_gain_est_done == 1'b1);
//FSK Data Transmission @ 2Mbps
#12000 data = 0.0078125*2**width_fraction;
#500 data = -0.0078125*2**width_fraction;
96
#500 data = -0.0078125*2**width_fraction;
#500 data = 0*2**width_fraction;
//FSK Data Transmission @ fref/2 = 75Mbps
#(0.5/0.15)
data = -0.0078125*2**width_fraction;
#(0.5/0.15)
data = 0.0078125*2**width_fraction;
#(0.5/0.15)
data = -0.0078125*2**width_fraction;
#(0.5/0.15)
data = 0*2**width_fraction;
end
always @ (posedge dco_gain_est_done)
begin
if (dco_gain_est_done)
dco_gain_est_start <= 1'b0;
end
adpll_top dut(reset,fref,fcw,dco_gain_est_start,dco_gain_est_done,
comp_feed_en,dir_feed_en,data,fdco,dco_auto_tune_enable1,dco_auto_tune_enable2,
dco_auto_tune_reset,dco_auto_tune_override,dco_auto_tune_N_override,dco_auto_tu
ne_N,dco_auto_tune_done);
endmodule
97
In Figure 6-2, we see the ADPLL going through the various modes of operation: Starting
from DCO Autotuing to KDCO Gain Estimation to Data Transmission at 2Mbps and at fR/2 =
75Mbps. Note that here we apply an exaggerated frequency step just for illustration. Next we
will apply the actual frequency steps and zoom in on each mode of operation.
Auto Tuning KDCO Estimation
KDCO Estimation
FSK Transmission
Figure 6-2 ADPLL output in the various modes of operation
98
In Figure 6-3, we zoom in on the DCO Autotuing period showing the DCO frequency
starting at 2.9GHz at the center tuning curve and approaching the desired 2.4GHz in a binary
search fashion and an open loop configuration with tuning curve number -6 as the final
solution. Then we leave the ADPLL to lock to the desired 2.4GHz by its closed loop
dynamics.
Auto Tuning
Loop Dynamics
Open Loop
Closed Loop
Figure 6-3 Zoom in on the DCO Autotuing period
99
While in Figure 6-4, we zoom in on the KDCO estimation period. We first do a KDCO
estimation and observe the frequency hit reported in Chapter 5 at the end of the gain
estimation due to the sudden change of the DCO tuning word after the end of the KDCO
estimation and normalization process. Then we perform KDCO estimation for the second time
just to illustrate that there is no more frequency hits because the KDCO estimation result is the
same and thus there is no sudden change of the DCO tuning word.
KDCO Estimation
KDCO Estimation
FSK Transmission
Figure 6-4 Zoom in on the KDCO estimation period
100
Note that for best results, we do KDCO estimation using the same frequency deviation
required during transmission. As we see in Figure 6-5, we start from the carrier frequency of
2.4GHz.
KDCO Estimation
KDCO Estimation
FSK Transmission
Figure 6-5 2.4GHz Center frequency at the start of KDCO estimation
101
Then we apply a 1MHz positive frequency shift as shown in Figure 6-6.
KDCO Estimation
KDCO Estimation
Figure 6-6 1MHz positive frequency shift
FSK Transmission
102
Then we apply a 1MHz negative frequency shift as shown in Figure 6-7.
KDCO Estimation
KDCO Estimation
Figure 6-7 1MHz negative frequency shift
FSK Transmission
103
After KDCO estimation and normalization is complete, we are now ready for FSK data
transmission at data rates higher than the ADPLL bandwidth, which is according to Figure 5-7
here is equal to rαfR/2π = 1 x 2-6 x 150 MHz / 2π ≈ 373 KHz as shown in Figure 6-8 where
we see the 2Mbps data transmission.
FSK Transmission at 2Mbps
Figure 6-8 2Mbps data transmission.
104
Here we zoom in more onto the FSK Transmission to see the effectiveness of the KDCO
estimation manifesting itself in the sharp frequency transitions of the transmitted data bits as
shown in Figure 6-9.
Figure 6-9 Zoom in on the FSK data transmission
105
To further exploit the full potential of the KDCO estimation & normalization algorithm, we
do data transmission at fR/2 = 75Mbps were we still see successful data transmission with
sharp frequency transitions in Figure 6-10 after more zooming in.
Figure 6-10 FSK transmission at fR/2
106
6.4. The ADPLL as a Local Oscillator
Spurious tones are one of the major performance measures of any PLL when used as a local
oscillator. In voltage controlled oscillators, evaluating the spurious tones by performing FFT
at the oscillator output is so computationally intensive and in most cases would lead to
inaccurate results due to the large sampling frequency required that is needed to be much
larger than the oscillator output frequency. So instead, the common practice is to perform an
FFT at the oscillator input control voltage and use the narrow band FM rule to evaluate the
spurious tone level at the oscillator output since the VCO is in essence an FM modulator. We
will use the same technique to evaluate the spurious tones of the DCO assuming its output
v DCO t  is a sinusoid rather than a square wave & is expressed as:
t


v DCO t   A  sin  o t   2K DCO NTWm cos m t dt 
0


(6.1)
Where:
A is the oscillation amplitude
 o is the oscillation center frequency
K DCO is the oscillator tuning gain which is equal to Fref/LSB after KDCO calibration
NTWm is the modulating part of the normalized tuning word
 m is the modulation frequency of the normalized tuning word
Doing the integration in 6.1 we get


2K DCO NTWm
v DCO t   A  sin o t 
sin  m t 
m


(6.2)
Using the narrow band FM approximation, 6.2 yields:
v DCO t   A  sin o t   A 
2K DCO NTWm
 sino   m   t   sino   m   t 
2 m
(6.3)
Where the first term corresponds to the center frequency & the second term corresponds to
the spurious tones at the right & left of the center frequency by a frequency offset equal to the
modulation frequency.
107
From 6.3 we can see that the ration between the spurious tone level & the center frequency
level is
Vspur
Vcarrier

2K DCO NTWm K DCO NTWm

2 m
2 fm
(6.4)
Now in order to evaluate the spurious tone level, we zoom in on the NTW after the ADPLL
reaches lock condition to see the modulating part of it. Figure 6-11 shows this modulating
part, it is obtained by subtracting the NTW from the average NTW. It is clear that the
fluctuations in the NTW are within one LSB only of the fractional part.
Figure 6-11 Zoom in on the modulating part of the NTW
108
Then we perform FFT on this modulating NTW to see its frequency content as shown in
Figure 6-12. Note that since Fref is 150MHz, the FFT is plotted from 0 to Fref/2 which is
75MHz. Now the spurious tones appear with the largest of them is located at 46.88MHz.
Figure 6-12 FFT of the modulating part of the NTW
Integrating the output spectrum from 0 to Fref/2 to get the total power of the modulating
part of the NTW yields 0.215 in units of fractional LSB squared. Substituting by this in 6.4 &
assuming that all the power is concentrated at the highest tone (at 46.88MHz offset) for
simplicity yields:
 Vspur 

10 log
V
 carrier 
2
0.215 

2
 150MHz / LSBInteger   16 2 
2


 10 log
2
  98.9dBc


2

46
.
88
MHz






 
(6.5)
109
To compare this with the state-of-the-art, we show in Figure 6-13 the measured output
spectrum of the ADPLL in [Staszewski 03a].
Figure 6-13 ADPLL measured output spectrum from [Staszewski 03a]
≤-112dBc/Hz @ 500KHz offset
2.1 deg
≤-62dBc
≤-80dBc
≤50µsec
Phase Noise
RMS phase error
Close-in spuriour tones
Far-out spurious tones
Settling time
Table 6-1 Measured key synthesizer performance from [Staszewski 03a]
It is clear from Figure 6-13 and also Table 6-1 that the spurious tone level is at -62dBc,
therefore the -98.9dBc obtained in this work is 36.9dB better in terms of spurious tones
without using a better frequency resolution than [Staszewski 03a] as can be observed from
equations 6.6 & 6.7 below.
23KHz
 718Hz
25
(6.6)
150MHz
 2289 Hz
216
(6.7)
f Staszewski 
f This _ Work 
Where in [Staszewski 03a], the fractional part LSB corresponds to 23KHz and a 5 bit sigma
delta modulator are used for dithering. While in this work the integer part LSB is 150MHz &
we use 16 fractional bits without any dithering.
Conclusion
In this work, we have presented mathematical description and operational details of the
phase-domain ADPLL. The architecture is built from the ground up using digital techniques
that exploit high speed and high density of a deep-submicrometer CMOS process while
avoiding its weaker handling of voltage resolution. The conventional phase/frequency detector
and charge-pump combination is replaced by a digital-to-frequency converter and is followed
by a simple digital loop filter that controls a DCO. Modulo arithmetic is used to represent the
phase-domain fixed-point signals.
We have presented the Verilog modeling technique used to describe the various building
blocks of the ADPLL. We used an integer-N ADPLL example with a simple frequency plan to
have more insight into the ADPLL modeling & operation. We have created a test bench for
the ADPLL and used it to observe the locking behavior. The TDC modeling was presented
together with some waveforms to better understand its operation.
A fast auto tuning algorithm for DCOs has been presented. Many practical implementation
issues have been shown along with their solutions. A design example comprising a 2.4GHz
DCO has been used to evaluate the algorithm. Regression simulations show a worst case
tuning time of only 7.2µsec with room for improvement.
111
Conclusion
We studied a fast tuning gain estimation & calibration algorithm. It makes use of the fact
that since the loop control is now digital, it is easier to estimate the tuning gain just in time by
introducing a known frequency step to the All Digital PLL input & monitoring the change on
the Digital Controlled Oscillator tuning input. This tuning gain calibration makes it possible to
use a two point modulation scheme to transmit Frequency Shift Keying data at symbol rates
much higher than the loop bandwidth upto the Nyquist frequency of half the reference
frequency.
The All Digital PLL together with the center frequency automatic tuning algorithm & the
tuning gain estimation & calibration algorithm are all modeled & integrated in Verilog. We
used this model to verify the successful All Digital PLL functionality & performance
transitioning from reset to center frequency automatic tuning to tuning gain estimation &
calibration to Frequency Shift Keying data transmission. Also when used as a local oscillator
for receivers, the implemented All Digital PLL has spurious tones less than -98dBc.
Future Work

Improve the DCO automatic tuning algorithm from the hardware implementation
point of view.

Implement a Gaussian Filter to be used to transmit GFSK signals rather than just FSK

Implement a PRBS generator & use it to transmit Pseudo-Random GFSK data & draw
the eye diagram of the transmitted signal after it is detected.

Implement Dynamic Element Matching techniques to the DCO capacitor banks for
better immunity to process mismatch

Fabricate the described automatic tuning & KDCO calibration techniques & evaluate
their performance in the lab.
References
[Bax 01]
W. T. Bax and M. A. Copeland, A GMSK modulator using a DS
frequency discriminator based synthesizer, IEEE Journal of Solid-State
Circuits, vol. 36, no. 8, pp. 1218–1227, Aug. 2001.
[Behbahani 00]
Behbahani, F., Weeguan Tan, Karimi-Sanjani, A., Roithmeier, A., Asad,
A.A., “A broad-band tunable CMOS channel-select filter for a Low-IF
wireless receiver,” IEEE J. of Solid-State Circuits, vol. 35, no. 4, pp. 476
–489, Apr. 2000.
[Best 93]
R. E. Best, Phase Locked Loops: Design, Simulation and Applications,
2nd ed. New York: McGraw-Hill, 1993.
[Bopp 99]
M. Bopp, M. Alles, and M. Arens et al., “A DECT transceiver chip set
using SiGe technology,” in Proc. IEEE Solid-State Circuits Conf., sec.
MP4.2, Feb. 1999, pp. 68–69.
[Egan 00]
W. F. Egan, Frequency Synthesis by Phase Lock, Wiley, New York,
2000.
[Egan 98]
W. F. Egan, Phase Lock Basics, Wiley, New York, 1998.
References
114
[Filiol 01]
N. Filiol, N. Birkett, and J. Cherry et al., “A 22 mW Bluetooth RF
transceiver with direct RF modulation and on-chip IF filtering,” in Proc.
IEEE Solid-State Circuits Conf., sec. 13.4, Feb. 2001, pp. 202–203.
[Gardner 80]
F. M. Gardner, Charge-pump phase-locked loops, IEEE Transactions on
Communications, vol. 28, pp. 1849–1858, Nov. 1980.
[Hafez 99]
A. N. Hafez and M. I. Elmasry, A low power monolithic subsampled
phase-locked loop architecture for wireless transceivers, Proceedings of
the IEEE Symposium on Circuits and Systems, vol. 2, pp. 549–552,
May–June 1999.
[Hegazi 07]
Hegazi, E., “An algorithm for automatic tuning of PLLs,” IEEE ISCAS
2007, New Orleans, LA, pp. 2260-2263, May 2007.
[Hein 88]
J. P. Hein and J. W. Scott, “z-domain model for discrete-time PLLs,”
IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1393–1400, Nov. 1988.
[Hwang 01]
I. C. Hwang, S. H. Song, and S. W. Kim, A digitally controlled phaselocked loop with a digital phase-frequency detection for fast acquisition,
IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1574–1581,
Oct. 2001.
[Kajiwara 92]
A. Kajiwara and M. Nakagawa, “A new PLL frequency synthesizer with
high switching speed,” IEEE Trans. Veh. Technol., vol. 41, no. 4, pp.
407–413, Nov 1992.
References
115
[Kenny 99]
T. P. Kenny, T. A. Riley, N. M. Filiol, and M. A. Copeland, Design and
realization of a digital delta-sigma modulator for fractional-N frequency
synthesis, IEEE Transactions on Vehicular Technology, vol. 48, no. 2,
pp. 510–521, Mar. 1999.
[Kral 98]
A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS Oscillators with
switched tuning,” Custom IC Conf., Santa Clara, pp. 555-558, May
1998.
[Lee 04]
S. T. Lee, S. J. Fang, D. J. Allstot, A. Bellaouar, A. R. Fridi, and P. A.
Fontaine, A quadband GSM-GPRS transmitter with digital autocalibration, IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp.
2200–2214, Dec. 2004.
[Maneatis 96]
John G. Maneatis, “Low-jitter process-independent DLL and PLL based
on self-biased techniques,” IEEE J. of Solid-State Circuits, vol. 31, no.
11, pp. 1723 -1732, Nov. 1996.
[Matsua 87]
Y. Matsua, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, and T.
Yoshitome, A 16-bit oversampling A/D conversion technology using
triple integration noise shaping, IEEE Journal of Solid-State Circuits, vol.
22, pp. 921–929, Dec. 1987.
[McMahill 02]
D. R. McMahill and C. G. Sodini, “A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK
automatically calibrated ΣΔ frequency synthesizer,” IEEE J. Solid-State
Circuits, vol. 37, pp. 18–26, Jan. 2002.
References
116
[Miller 91]
B. Miller and R. J. Conley, A multiple modulator fractional divider, IEEE
Transactions on Instrumentation and Measurement, vol. 40, no. 3, pp.
578–583, June 1991.
[Perrott 97]
M. H. Perrott, T. Tewksbury, and C. Sodini, A 27-mW CMOS fractionalN synthesizer using digital compensation for 2.5-Mb/s GFSK modulation,
IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 2048–2060,
Dec. 1997.
[Razavi 98]
B. Razavi, RF Microelectronics, Prentice Hall, Upper Saddle River, NJ,
1998.
[Reinhardt 86]
V. Reinhardt, K. Gould, K. McNab, and M. Bustamante, A short survey
of frequency synthesizer techniques, Proceedings of the 40th Annual
Frequency Control Symposium, pp. 355–365, May 1986.
[Riley 93]
T. Riley, M. Copeland, and T. Kwasniewski, Delta–sigma modulation in
fractional-N frequency synthesis, IEEE Journal of Solid-State Circuits,
vol. 28, no. 5, pp. 553–559, May 1993.
[Shennawy 10]
El-Shennawy, M., Hegazi, E., “A fast automatic tuning algorithm for
Voltage
Controlled
Oscillators,”
International
Conference
on
Microelectronics, Cairo, pp. 188 - 191, Dec. 2010.
[Staszewski 03a]
R. B. Staszewski, D. Leipold, K. Muhammad, and P. T. Balsara,
“Digitally controlled oscillator (DCO)-based architecture for RF
frequency synthesis in a deep-submicrometer CMOS process,” IEEE
Trans. Circuits Syst. II, vol. 50, no. 11, pp. 815–828, Nov. 2003.
References
117
[Staszewski 03b]
R. B. Staszewski, C.-M. Hung, D. Leipold, and P. T. Balsara, “A first
multigigahertz digitally controlled oscillator for wireless applications,”
IEEE Trans. Microwave Theory Tech., vol. 51, no. 11, pp. 2154–2164,
Nov. 2003.
[Staszewski 03c]
R. B. Staszewski, D. Leipold, and P. T. Balsara, “Just-in-time gain
estimation of an RF digitally controlled oscillator for digital direct
frequency modulation,” IEEE Trans. Circuits Syst. II, Analog Digit.
Signal Process., vol. 50, no. 11, pp. 887–892, Nov. 2003.
[Staszewski 03d]
R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, “A first
digitally-controlled oscillator in a deep-submicron CMOS process for
multi-GHz wireless applications,” in Proc. IEEE Radio Frequency
Integrated Circuits (RFIC) Symp., sec. MO4B-2, June 2003, pp. 81–84.
[Staszewski 04]
B. Staszewski, C.-M. Hung, K. Maggio, J. Wallberg, D. Leipold, and P.
Balsara, “All-digital phase-domain TX frequency synthesizer for
Bluetooth radios in 0.13-_m CMOS,” in Proc. IEEE Solid-State Circuits
Conf., vol. 527, sec. 15.3, Feb. 2004, pp. 272–273.
[Staszewski 06]
R. B. Staszewski, P. T. Balsara, “All Digital Frequency Synthesizer in
Deep Sub-Micron CMOS,” Wiley, 2006.
[Tan 95]
L. K. Tan and H. Samueli, A 200 MHz quadrature digital
synthesizer/mixer in 0.8µm CMOS, IEEE Journal of Solid-State Circuits,
vol. 30, no. 3, pp. 193–200, Mar. 1995.
References
118
[Tierney 71]
J. Tierney, C. M. Radar, and B. Gold, A digital frequency synthesizer,
IEEE Transactions on Audio Electroaccoustics, vol. 19, pp. 48–57, Mar.
1971.
[Wilson 00]
W. B. Wilson, U. K. Moon, K. R. Lakshmikumar, and L. Dai, A CMOS
self-calibrating frequency synthesizer, IEEE Journal of Solid-State
Circuits, vol. 35, no. 10, pp. 1437–1444, Oct. 2000.
[Wolaver 93]
D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall,
Englewood Cliffs, NJ, 1993.
[Zhang 99]
B. Zhang and P. Allen, “Feed-forward compensated high switching speed
digital phase-locked loop frequency synthesizer,” in Proc. IEEE Symp.
Circuits Syst., vol. 4, 1999, pp. 371–374.

Digital Techniques in Frequency Synthesis A Thesis

Transcription

Similar documents

D E L T A BLUESTM

Events - Missouri Autism Report

D F 1700 Dual Channel, 8x Oversampling DIGITAL FILTER

PRICE TOTAL $ FIBA Shot Clock *pair

5 - Peavey

1. Go to ezlm.adp.com and click the

TGS_ADTS_CENTURION_v2:Layout 1.qxd

The Bytown Times

Argos™ Model 2400 SF Series Tunable Single