18 Shift Registers - users.etech.haw
Transcription
18 Shift Registers - users.etech.haw
hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz 18 FB Elektrotechnik/Informatik Shift Registers • A Johnson counter contains the basic structure of a shift register which is made up by a chain of D- FFs. Beginning with the LSB of a register (a number of D-FFs) each D-FF output can be connected to the data input of the D-FF with next higher weight. • This chain of D-FFs includes the ability to shift the bits of the register to the left (LSB to MSB) or to the right (MSB to LSB). For example, a sequence of bits can be converted into a word by shifting the bits into a register and moving the bits along at each clock edge. After a sufficient number of clock edges, namely the number n of D-FFs, the n bits of a word are available as a single word. This is known as a serial-in and parallel-out register. • Applications of shift registers will be found in serial communication interfaces. The receiver input device will clock in a data stream of sequenced bits and a parallel word will be accessed by internal processes. A sender will clock out a parallel stored word over a serial register output. • Simple multiply and division operations can be performed by a shift register. A multiplication by two will be done with a shift left by one bit. Digital Circuits I B. Schwarz 18-1 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik • Direction of shift is described by the weight of bits: • Shift right: from MSB to LSB • Shift left: from LSB to MSB • The direct chaining of flip-flops is allowed because each time the clock gates of all flip-flops are opened the inputs are connected to stable output signal levels. If the output transition occurs after a certain propagation delay the clock gates are deactivated. serial Input 5 stages 0 0 1 1 0 1 0 0 1 1 • Device example: 8-bit shift register SN74xx91 (8 stages). Serial shift input (LSB) is an AND gate. Shift right result Q is available in uncomplemented and complemented form. serial output 1. clock edge 0 2. clock edge 0 1 0 0 1 1 3. clock edge 0 0 1 0 0 1 4. clock edge Digital Circuits I B. Schwarz 18-2 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik 18.1 3-bit Serial-to-Parallel Converter • In serial communications, such a shift register is used to receive a serial bit stream and support connected components with a parallel data word: 1 bit→ n-bit. • Serial data is read in at the shift input SE which appears at the REG register outputs. • Control signal X distinguishes operational modes: • X = ’0“: shift right, register outputs deactivated. • X = ’1“: no shift, register outputs enabled • Remember: Never delay clock lines with combinational logic! This example is just a symbolic schematic. Give suggestions for a professional solution! Digital Circuits I B. Schwarz 18-3 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik VHDL description of an n-bit serial-to-parallel converter • Parameterised register width with generic-statement. • 2 processes: - clock edge gated internal shift register INTREG, - combinational output logic controlled by signal X and register state. • Shift operation done with a for-loop. Loop subscript I does not need to be declared explicitly. Shift right: INTREG(I) <= INTREG(I-1) entity SRG_NBIT is generic(N : natural :=3); -- number of bits equal to 3 port( CLK, SE, RESET, X: in bit; REG: out bit_vector(N-1 downto 0)); -- register with N flip-flops end SRG_NBIT; Digital Circuits I B. Schwarz 18-4 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik architecture BEHAVE of SRG_NBIT is signal INTREG: bit_vector(N-1 downto 0); begin P1: process(CLK, RESET) -- shift register begin if RESET='1' then INTREG <= (others => '0') after 10 ns; elsif (CLK='1' and CLK'event) then -- positive edge if X='0' then -- professional synchronous enable !!!!! for I in N-1 downto 1 loop -- shift to MSB (left) INTREG(I) <= INTREG(I-1) after 10 ns; end loop; INTREG(0) <= SE after 10 ns; -- shift input copied into LSB end if; end if; end process P1; P2: process(X, INTREG) -- output enable, combinational logic begin if X='1' then REG <= INTREG after 10 ns; else REG <= (others=>'0') after 10 ns; end if; end process P2; end BEHAVE; Digital Circuits I B. Schwarz 18-5 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik Simulation waveform of a 3-bit serial-to-parallel converter • All flip-flops are clocked at the same time. • Shift is enabled if X = ’0“. • Output is enabled if X = '1'. • Reliable shift functionality because of: Propagation delay tpLH is larger than hold time tH. Digital Circuits I B. Schwarz 18-6 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz 18.2 FB Elektrotechnik/Informatik Parallel-to-Serial Converter • Shift registers are used as parallel-to-serial converters in transmitter components of transceiver devices: n-bit→ 1-bit • A parallel load input E[2:0] and a shift output SA = Q(2) is needed. • Control of operation mode by signal X: X='0' : shift left, inputs disabled, LSB will always be loaded with ’0“ X='1' : inputs are enabled, parallel data are stored with the next clock. • All stages are identical therefore only one stage has to be designed → Consider stage 1 Q0 E1 X Combinational Logic D1 X 0 Q0 0 E1 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D1 D1: ¬E1 0 4 5 1 ¬ Q0 2 6 7 3 Q0 ¬X Digital Circuits I B. Schwarz E1 X ¬X 18-7 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik Synthesized schematic of a 3-bit parallel-to-serial converter • Next state forming logic interfaces between adjacent stages are identical . • The LSB stage is driven by ’0“ (Pulldown Resistor) • The MSB will be first seen at the SA output. Digital Circuits I B. Schwarz 18-8 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik VHDL code for a 3-bit parallel-to-serial converter entity PAR_SER is generic(N : natural :=3); -- number of bits, initialised with 3 port( CLK, RESET, X: in bit; E: in bit_vector(N-1 downto 0); -- parallel data input SA: out bit); -- shift output end PAR_SER; architecture VERHALTEN of PAR_SER is signal INTREG: bit_vector(N-1 downto 0); begin P1: process(CLK, RESET) -- shift register begin if RESET='1' then INTREG <= (others => '0') after 10 ns; elsif (CLK='1' and CLK'event) then -- rising edge if X='0' then INTREG <= INTREG(N-2 downto 0) & ’0 after 10 ns; -- shift left else INTREG <= E after 10 ns; -- parallel data load end if; end if; end process P1; SA <= INTREG(N-1); -- MSB: shift output end VERHALTEN; Digital Circuits I B. Schwarz 18-9 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik Simulation waveforms of the parallel-to-serial converter 1 0 1 Digital Circuits I B. Schwarz 0 1 1 18-10 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik 18.3 Linear Feedback Shift Register (LFSR) • A shift register with a feedback path via XOR gates to the LSB input generates pseudorandom test patterns that are useful in testing both combinational and sequential machines. • A 4-bit LFSR which has an XOR feedback of bit numbers 2 and 3, will be initialised with ”0001䀡and it sequences through 15 of the 16 states. It is not allowed to enter the ”0000䀡state since that is a hang state because XOR will not generate a ’1“ which is the start of the pseudorandom sequence. Register width 4 6 7 8 9 10 11 XOR- feedback 2,3 4,5 3,6 2,4 4,8 6,9 8,1 register output 6,7 0 subscripts 12 5,7 10, 11 Digital Circuits I B. Schwarz 4-bit pseudorandom counting pattern Q3 Q2 Q1 Q0 Q/h Y 0 1 1 0 0 0 0 2 0 1 0 0 1 4 0 0 1 0 1 9 1 0 0 1 0 3 1 1 0 0 1 6 0 1 1 0 0 D 1 0 1 1 1 A 0 1 0 1 1 5 1 0 1 0 1 B 1 1 0 1 1 7 1 1 1 0 0 F 1 1 1 1 0 E 0 1 1 1 0 C 0 0 1 1 1 8 0 0 0 1 0 1 1 0 0 0 18-11 hochschule fu r angewandte wissenschaften hamburg Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik Schematic and simulation waveform of a 4-bit LFSR Digital Circuits I B. Schwarz 18-12