Intel 440MX Scalable Low Power Development Kit

Transcription

Intel® 440MX Scalable Low Power
Development Kit
User’s Manual
December 2001
Order Number: 273632-001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 440MX Scalable Low Power Development Kit may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the
license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a
commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2001
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Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer
logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare,
RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In,
TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
Intel® 440MX Scalable Low Power Development Kit User’s Manual
Contents
1
About This Manual ............................................................................................................. 7
1.1
1.2
1.3
1.4
1.5
2
Getting Started .................................................................................................................11
2.1
2.2
2.3
2.4
2.5
2.6
3
Content Overview.................................................................................................. 7
Text Conventions .................................................................................................. 7
Technical Support .................................................................................................9
1.3.1
Electronic Support Systems .................................................................9
1.3.2
Telephone Technical Support .............................................................. 9
Product Literature.................................................................................................. 9
Related Documents.............................................................................................10
Overview .............................................................................................................11
2.1.1
Baseboard Features ...........................................................................11
Included Hardware ..............................................................................................12
Software Key Features........................................................................................13
2.3.1
Embedded BIOS for the Intel® 440MX Scalable Low Power
Development Kit .................................................................................13
2.3.2
Software .............................................................................................14
2.3.2.1
Hard Hat* Linux ....................................................................14
2.3.2.2
Wind River’s VxWorks* Real-Time Operating
System (RTOS) ....................................................................14
Before You Begin ................................................................................................16
Setting up the Evaluation Board..........................................................................17
Configuring the BIOS ..........................................................................................19
Theory of Operation .........................................................................................................21
3.1
3.2
3.3
3.4
Block Diagram .....................................................................................................21
Mechanical Design ..............................................................................................22
Thermal Management .........................................................................................22
System Operation................................................................................................22
3.4.1
Intel® Pentium® III Processor .............................................................22
3.4.2
Intel® Celeron® Processor..................................................................23
3.4.3
Intel® 440MX Chipset .........................................................................23
3.4.4
System Memory SDRAM ...................................................................24
3.4.5
System I/O..........................................................................................24
3.4.5.1
Floppy Disk Drive Support ....................................................24
3.4.5.2
IDE Support ..........................................................................24
3.4.5.3
RS-232 Serial Ports ..............................................................25
3.4.5.4
USB Ports .............................................................................25
3.4.5.5
Audio Subsystem..................................................................25
3.4.5.6
Keyboard/Mouse...................................................................25
3.4.5.7
IR Header .............................................................................25
3.4.6
Expansion Connectors .......................................................................25
3.4.6.1
32-bit/33-MHz PCI Connectors.............................................25
3.4.6.2
Compact Flash Slot ..............................................................25
3.4.7
Post Code Debugger ..........................................................................26
3.4.8
Clock Generation................................................................................26
3.4.8.1
System Clocks ......................................................................26
3
3.5
4
Hardware Reference ........................................................................................................ 29
4.1
4.2
4.3
5
Thermal Management ......................................................................................... 29
4.1.1
Changing the Processor..................................................................... 29
Connector Pinouts............................................................................................... 32
4.2.1
ATX Power Connector........................................................................ 33
4.2.2
Dual Stacked USB Connector ............................................................ 33
4.2.3
PS/2-Style Mouse and Keyboard Connectors.................................... 34
4.2.4
Serial Ports......................................................................................... 34
4.2.5
Audio Connectors............................................................................... 35
4.2.6
Compact Flash Connector.................................................................. 35
4.2.7
IDE Connector.................................................................................... 36
4.2.8
Floppy Drive Connector...................................................................... 37
4.2.9
32-Bit PCI Slot Connector .................................................................. 37
Jumpers .............................................................................................................. 39
4.3.1
CMOS Jumper.................................................................................... 39
4.3.2
ENET Jumper..................................................................................... 39
4.3.3
CF MASTER Jumper.......................................................................... 40
4.3.4
BIOS UNLOCK Jumper...................................................................... 40
BIOS Quick Reference..................................................................................................... 41
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
4
3.4.9
Power Supply Requirements.............................................................. 27
Battery Requirements ......................................................................................... 27
Embedded BIOS Introduction ............................................................................. 41
5.1.1
Features ............................................................................................. 41
5.1.2
PC BIOS Features.............................................................................. 43
5.1.3
Software Compatibility........................................................................ 44
Power On Self Test ............................................................................................. 44
5.2.1
The BIOS User Interface .................................................................... 44
Setup Screen System ......................................................................................... 46
5.3.1
Basic CMOS Configuration Screen .................................................... 46
5.3.2
Configuring Drive Assignments .......................................................... 47
5.3.3
Configuring Floppy Drive Types ......................................................... 47
5.3.4
Configuring IDE Drive Types.............................................................. 48
5.3.5
Custom Configuration Setup Screen.................................................. 50
5.3.6
Shadow Configuration Setup Screen ................................................. 50
5.3.7
Start System BIOS Debugger Setup Screen...................................... 51
5.3.8
Start RS232 Manufacturing Link Setup Screen.................................. 51
5.3.9
Manufacturing Mode........................................................................... 52
5.3.9.1
Sample Manufacturing Mode HOST Program ...................... 52
5.3.9.2
Manufacturing Mode Drive Redirection ................................ 53
Console Redirection............................................................................................ 54
CE-Ready—Windows CE Loader ....................................................................... 54
Integrated BIOS Debugger.................................................................................. 55
Troubleshooting POST........................................................................................ 56
5.7.1
Embedded BIOS POST Codes .......................................................... 57
Critical Error Beep Codes ................................................................................... 60
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Block Diagram .....................................................................................................21
Back Panel I/O Connectors .................................................................................24
View of the Fan/Heat Sink...................................................................................29
Top View of the Heat Sink...................................................................................30
Bottom View of Heat Sink....................................................................................31
Baseboard Layout Diagram.................................................................................32
BIOS POST, the Text-based System ..................................................................45
The Graphical POST ...........................................................................................45
Embedded BIOS Setup Screen Menu.................................................................46
Embedded BIOS Basic Setup Screen.................................................................47
Embedded BIOS Custom Setup Screen .............................................................50
Embedded BIOS Shadow Setup Screen.............................................................50
Standard Diagnostic Routines Setup Screen ......................................................51
Start RS232 Manufacturing Link Setup Screen...................................................52
The CE-Ready Feature .......................................................................................55
Integrated BIOS Debugger..................................................................................56
1
2
3
4
5
6
7
8
9
10
11
12
13
Related Documents.............................................................................................10
Power Connector (ATXPR1) ...............................................................................33
USB Connector Pinout (USB1) ...........................................................................33
PS/2-Style Mouse and Keyboard Pinout (U1) ....................................................34
Serial Port Connector Pinout (COM1 and COM2)...............................................34
Audio Line-Out Connector Pinouts......................................................................35
Audio Line-In Connector Pinouts.........................................................................35
Audio Mic-In Connector Pinouts..........................................................................35
Compact Flash Connector...................................................................................35
IDE Connector Pinouts for IDE1 and IDE2..........................................................36
Floppy Drive Connector Pinouts (FDC1).............................................................37
32-Bit PCI Slot Connector Pinouts ......................................................................38
Bill of Materials ....................................................................................................63
Tables
Revision History
Revision
Date
001
December 2001
Description
First release of document.
5
About This Manual
1
This manual tells you how to set up and use the evaluation board and processor assembly included
in your Intel® 440MX Scalable Low Power Development Kit.
1.1
Content Overview
Chapter 1, “About This Manual” — This chapter contains a description of conventions used in this
manual. The last few sections tell you how to obtain literature and contact customer support.
Chapter 2, “Getting Started”— Provides complete instructions on how to configure the evaluation
board and processor assembly by setting jumpers, connecting peripherals, providing power, and
configuring the BIOS.
Chapter 3, “Theory of Operation” — This chapter provides information on the system design.
Chapter 4, “Hardware Reference” — This chapter provides a description of jumper settings and
functions, and pinout information for each connector.
Chapter 5, “BIOS Quick Reference” — This chapter describes how to configure the BIOS for your
system configuration. A summary of all BIOS menu options is provided.
Appendix A, “Bill of Materials” — This appendix contains the bill of materials for the evaluation
board.
Appendix B, “Schematics” — This appendix contains schematics for selected connectors and
subsystems for the evaluation board.
1.2
Text Conventions
The following notations may be used throughout this manual.
#
The pound symbol (#) appended to a signal name indicates that the
signal is active low.
Variables
Variables are shown in italics. Variables must be replaced with correct
values.
Instructions
Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either
upper- or lowercase.
7
About This Manual
Numbers
Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that
begin with A through F. (For example, FF is shown as 0FFH.) Decimal
and binary numbers are represented by their customary notations. (That
is, 255 is a decimal number and 1111 1111 is a binary number. In some
cases, the letter B is added for clarity.)
Units of Measure
The following abbreviations are used to represent units of measure:
A
Gbyte
Kbyte
KΩ
mA
Mbyte
MHz
ms
mW
ns
pF
W
V
µA
µF
µs
µW
Signal Names
8
amps, amperes
gigabytes
kilobytes
kilo-ohms
milliamps, milliamperes
megabytes
megahertz
milliseconds
milliwatts
nanoseconds
picofarads
watts
volts
microamps, microamperes
microfarads
microseconds
microwatts
Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals
are named CS0#, CS1#, CS2#, and so on; they are collectively called
CSn#. A pound symbol (#) appended to a signal name identifies an
active-low signal. Port pins are represented by the port abbreviation, a
period, and the pin number (e.g., P1.0).
About This Manual
1.3
Technical Support
1.3.1
Electronic Support Systems
Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date technical
information and product support. This information is available 24 hours per day, 7 days per week,
providing technical information whenever you need it.
1.3.2
Telephone Technical Support
In the U.S. and Canada, technical support representatives are available to answer your questions
between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice
telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S.
and Canada, please contact your local distributor.
1.4
1-800-628-8686
U.S. and Canada
916-356-7599
U.S. and Canada
916-356-6100 (fax)
U.S. and Canada
Product Literature
You can order product literature from the following Intel literature centers.
1-800-548-4725
U.S. and Canada
708-296-9333
U.S. (from overseas)
44(0)1793-431155
Europe (U.K.)
44(0)1793-421333
Germany
44(0)1793-421777
France
81(0)120-47-88-32
Japan (fax only)
9
About This Manual
1.5
Table 1.
Related Documents
Related Documents
Document Title
Intel Pentium® III Processor Low Power datasheet
273500
®
®
244453
®
®
273325
®
®
Intel Pentium III Processor Specification Update
Intel Pentium III Processor Thermal Design Guide
10
Order Number
Intel Celeron Processor Low Power/Ultra Low Power datasheet
273509
Intel® Celeron® Processor Specification Update
243748
P6 Family of Processors Hardware Developer’s Manual
244001
Intel Architecture Software Developer’s Manual, Volume1: Basic Architecture
243190
Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference
Manual
243191
Intel Architecture Software Developer’s Manual, Volume 3: System Programming
Guide
243192
Intel Processor Serial Number application note
245125
Getting Started
2
This chapter identifies the evaluation kit’s key components, features and specifications. It also tells
you how to set up the board for operation.
2.1
Overview
The evaluation board consists of a baseboard (with one Intel® Pentium® III processor populated),
440MX chipset, and other system board components and peripheral connectors.
Note:
2.1.1
The evaluation board is shipped as an open system allowing for maximum flexibility in changing
hardware configuration and peripherals. Since the board is not in a protective chassis, take extra
precaution when handling and operating the system.
Baseboard Features
The evaluation board features are summarized below:
CPU
• Supports both Intel® Celeron® processors low power/ultra-low power (300 MHz and above)
and Intel® Pentium® III processors low power (up to 700 MHz); both in the micro-PGA
package.
• Supports a 66 or 100 MHz processor system bus (PSB).
Intel 440MX Chipset
• 82443MX PCIset
• Integrated IDE controller for Ultra DMA/33 Synchronous DMA mode
Memory Support
• 100 MHz system memory interface
• Two 168-pin DIMM sockets support SDRAM (3.3 V, non-ECC) modules
• Supports 8-Mbyte to 256-Mbyte using 16 Mbit/64 Mbit/128 Mbit technology
11
Getting Started
Flash System BIOS ROM
• General Software system BIOS
Power Supply/Management
• Standard ATX power supply connector
• SMRAM space remapping to A0000H (128 Kbyte)
• Optional Extended SMRAM space above 256 Mbyte, additional 512 Kbyte/1 Mbyte TSEG
from top of memory, cacheable
• Stop clock grant and halt special cycle translation from the host to the hub interface
• APIC buffer management
System I/O
•
•
•
•
•
•
•
One floppy connector supporting up to 2.88 Mbytes, and three-mode floppy drives
One Ultra ATA 100/66/33 IDE connector supporting up to two IDE devices
Built-in standard/EPP/ECP parallel port connector
Two built-in 16550 fast UART compatible serial port connectors
Two built-in Universal Serial Bus (USB) connectors
Built-in PS/2-style keyboard and PS/2 mouse (6-pin mini-DIN) connectors
Built-in audio connectors (Line-in, Line-out, MIC-in) with Sigmatel CODEC
Peripheral Connectors
• Three PCI expansion slots
Miscellaneous Features
•
•
•
•
•
•
2.2
Two built-in SMBus headers
Built-In standard IrDA TX/RX header
One built-in FAN power connector
Power/Reset jumpers
Jumper to clear CMOS
Included Hardware
•
•
•
•
•
12
Micro ATX form factor
Evaluation board (baseboard) with battery
One 500, 700 MHz Intel® Pentium® III Processor Low Power with a 100 MHz PSB
One 300 MHz Intel® Celeron® Processor Ultra Low Power with a 100 MHz PSB
One fansink thermal solution
One 128-Mbyte PC100 SDRAM (168-pin)
Getting Started
• ATA66 hard disk drive pre-loaded with an evaluation copy of Hard Hat* from MontaVista*
• 80-pin ATA/66 IDE cable for the hard disk drive
• Intel 69000 graphics card
2.3
Software Key Features
The software in the kit was chosen to facilitate development of real-time applications based on the
components used in the evaluation board. The software tools included in your kit are described in
this section.
Note:
Software in the kit is provided free by the vendor and is only licensed for evaluation purposes.
Refer to the documentation in your evaluation kit for further details on any terms and conditions
that may be applicable to the granted licenses. Customers using the tools that work with Microsoft*
products must license those products. Any targets created by those tools should also have
appropriate licenses. Software included in the kit is subject to change.
Refer to http://developer.intel.com/design/intarch/devkits for details on additional software from
other third-party vendors.
2.3.1
Embedded BIOS for the Intel® 440MX Scalable Low Power
Development Kit
The Intel® 440MX Scalable Low Power Development Kit ships pre-installed with Embedded
BIOS* pre-boot firmware from General Software. Embedded BIOS provides an industry-standard
BIOS platform to run any standard operating system, including DOS*, Windows* NT, NT
Embedded*, Windows 95/98, Windows CE, QNX*, VxWorks*, and Linux* among others. The
Embedded BIOS Application Kit (available through General Software) includes complete source
code, a reference manual, and a Windows-based expert system, BIOStart*, to enable easy and rapid
configuration of customized firmware for your Intel* 440MX Scalable Low Power Development
Kit.
The following features of Embedded BIOS have been enabled in the Intel® 440MX Low Power
Development Kit:
•
•
•
•
•
•
•
•
•
•
•
SDRAM detection, configuration, and initialization
Intel® 440MX chipset configuration
Post codes displayed to port 80H
Two serial ports, one EPP/ECP parallel port
PCI bus and device enumeration and configuration
SMC LPC Super I/O programming
Pentium® III processor microcode update
Integrated debugger
Burn-in diagnostics
Console redirection
Manufacturing mode
13
Getting Started
2.3.2
Software
2.3.2.1
Hard Hat* Linux
The drive comes pre-loaded with Hard Hat Linux. Some of the features of Hard Hat Linux include:
Hard Hat Linux is a cross development platform and a set of tool kits designed specifically for
embedded solutions.
Hard Hat Linux is designed for the scalability, dependability and performance required of welldesigned embedded applications. Hard Hat Linux includes more than 75 Linux Support Packages
(LSPs), 200+ software packages plus a comprehensive set of development tools.
MontaVista Software also makes available valuable technology add-on packages that address
specific customer requirements such as the Java development environment, High Availability
technology, GUI toolkit and more.
Hard Hat Linux supports a variety of capabilities exclusively for embedded applications.
Technologies such as special back-plane communication for CompactPCI allow multiple boardlevel systems to communicate over a common bus interface. Support for headless operation
enables the embedding of Linux in a video display, keyboard or mouse. Networks can be installed
and booted without the need for rotating media. The Flash memory file system supports rugged
solid-state storage needed for very small consumer devices. Run-time instrumentation makes it
easy to monitor system integrity and performance. Hard Hat Linux also includes scaling and
configuration tools that let developers right-size Linux kernel and filesystems to suit their memory
footprint.
2.3.2.2
Wind River’s VxWorks* Real-Time Operating
System (RTOS)
Wind Microkernel
• Efficient task management
— Multitasking, unlimited number of tasks
— Preemptive and round-robin scheduling
— Fast, deterministic context switching
— 256 priority levels
• Fast, flexible intertask communications
— Binary, counting and mutual exclusion semaphores with priority inheritance
— Message queues
— POSIX pipes, counting semaphores, message queues, signals and scheduling
— Control sockets
— Shared memory
• High scalability
• Incremental linking and loading of components
• Fast, efficient interrupt and exception handling
14
Getting Started
• Optimized floating-point support
• Dynamic memory management
• System clock and timing facilities
Networking Support
•
•
•
•
•
•
•
•
•
•
•
BSD 4.4 TCP/IP networking
IP, IGMP, CIDR, TCP, UDP, ARP
RIP v.1/v.2
Standard Berkeley sockets, zbufs (a.k.a., zero-copy sockets)
SLIP, CSLIP, PPP
BOOTP, DNS, DHCP, TFTP
NFS, ONC RPC
FTP, rlogin, rsh, telnet
SNTP
WindNet SNMP v.1/v.2c with MIB compiler—optional
WindNet OSPF v.2—optional
Fast, Flexible I/O and Local File System
•
•
•
•
•
•
SCSI support
MS-DOS compatible file system
Raw disk file system
TrueFFS flash file system—optional
ISO 9660 CD-ROM file system
PCMCIA support
Target Development Features
• Full ANSI C compliance and enhanced C++ features for exception handling and template
support
•
•
•
•
•
•
•
•
•
•
Extensive POSIX 1003.1, .1b compatibility
Interactive C interpreter target shell
Symbolic debugging and disassembly
Powerful performance monitoring
Extensive kernel, task and system information utilities
Dynamic linking loader
Libraries of over 1800 utility routines
Flexible booting from ROM, local disk, or over the network
Highly scalable design allows for a wide range of applications
System-level debugging via Ethernet, serial line, ICE, or ROM emulator
15
Getting Started
Supported VxWorks 5.x Targets
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.4
PowerPC
68K, CPU 32
ColdFire
MCORE
80x86 and Pentium
i960
ARM and StrongARM
MIPS
SH
SPARC
NEX V8xx
M32 R/D
RAD6000
ST 20
TriCore
Before You Begin
Before you set up and configure your evaluation board, you may want to gather some additional
hardware and software.
VGA Monitor: You can use any standard VGA or multi-resolution monitor. The setup instructions
in this chapter assume that you are using a standard VGA monitor.
Keyboard: You need a keyboard with a PS/2-style connector or adapter.
Mouse: Optional. You can use a mouse with a PS/2-style connector or adapter.
Hard Drives andFloppy Drives: You can connect up to two IDE drives and one floppy drive to
the evaluation board. Two devices (master and slave) can be attached to the IDE connector. Only
one hard drive is included in your kit, so you will need to provide the cables for any additional
drives. You may have all these storage devices attached to the board at the same time. The compact
flash is considered an IDE device, so only the compact flash and one IDE hard drive can be used at
the same time.
Video Adapter: You must install a PCI video adapter. It is your responsibility to install the correct
driver software for any video adapters.
Network Adapter: The network adapter is already installed on the board. You may use a different
network card other than the one included in the kit; you are responsible for installing the correct
drivers for such a network card. The evaluation board supports all standard PCI-compatible
network cards. You must supply a network cable to connect to the LAN connector or any other
network card you chose to install.
16
Getting Started
Power Supply: You must use a standard ATX power supply.
Other Devices and Adapters: The evaluation board functions much like a standard desktop
computer motherboard. Most PC compatible peripherals can be attached and configured to work
with the evaluation board.
2.5
Setting up the Evaluation Board
Once you have gathered the hardware described in section Section 2.4, follow the steps below to
set up your evaluation board. This manual assumes you are familiar with the basic concepts
involved with installing and configuring hardware for a personal computer system. Refer to
Figure 6 on page 32 for locations of connectors, jumpers, etc.
1. Create a safe work environment.
Make sure you are in a static-free environment before removing any components from their
anti-static packaging. The evaluation board is susceptible to electrostatic discharge damage,
and such damage may cause product failure or unpredictable operation.
2. Inspect the contents of your kit.
Check for damage that may have occurred during shipment. Contact your sales representative
if any items are missing or damaged.
Caution:
Note:
Connecting the wrong cable or reversing the cable can damage the evaluation board and may
damage the device being connected. Since the board is not in a protective chassis, use caution when
connecting cables to this product.
The evaluation board is a standard micro-ATX form factor. An ATX chassis may be used if a
protected environment is desired.
3. Check the jumper settings.
CMOS jumper is used to clear the CMOS memory (pin 2 and 3). Make sure this jumper is set
for normal operation (jumper pins 21 and 22). Refer to Section 4.3.1, “CMOS Jumper” on
page 39.
4. Make sure the following hardware is populated on your evaluation board:
— One Intel® Pentium® III processor
— One 128-Mbyte PC100 SDRAM DIMM (168-pin)
— One fan (thermal solution)
5. Install the IDE hard disk drive included in your kit:
The evaluation board supports Primary and Secondary IDE interfaces that can each host one or
two devices (master/slave). When you are using multiple devices, such as a hard disk and a
CD-ROM drive, make sure the hard disk drive has a jumper in the master position and the CDROM has a jumper in the slave position. When using a single IDE device with the evaluation
board, ensure that the jumpers are set correctly for single drive operation. For jumper settings
for different configurations, consult the drive’s documentation.
— Connect the hard drive’s IDE cable connector to the IDE1 connector on the evaluation
board.
— Connect the other end of the cable to the hard disk drive.
17
Getting Started
— Connect a power cable to the hard drive.
Caution:
Make sure the tracer on the ribbon cable is aligned with pin 1 on both the hard disk and the IDE
connector header. Connecting the cable backwards can damage the evaluation board or the hard
disk.
6. Connect any additional storage devices to the evaluation board.
Note:
The hard disk is already formatted and is pre-loaded with a customized target image of Hard Hat
Linux by Montavista.
7. Connect a Floppy drive (optional).
— Insert a floppy cable into FDC1 (be sure to orient pin 1 correctly).
— Connect the other end of the ribbon cable to the floppy drive.
— Connect a power cable to the floppy drive.
8. Connect the keyboard and mouse.
Connect a PS/2-style mouse and keyboard (see Figure 6 on page 32 for connector locations).
Note:
The bottom connector is for the keyboard and the top is for the mouse.
9. Connect the Ethernet adapter provided in your kit (optional).
10. Connect the audio speakers (optional).
For audio, connect the audio speakers to the on-board line out connector.
11. Connect the power supply.
Connect an ATX power supply to the evaluation board. Make sure the power supply is not
plugged into the wall (turned off). Insert the board connector of the power supply cord into the
ATXPR1 power supply header on the evaluation board. After connecting the power supply
board connector to the ATXPR1 header, plug the power supply cord into the wall.
12. Power up the board.
Power and reset are implemented on the evaluation board through jumpers located on PN1 and
PN2.
Power Jumper:
The power jumper consists of pins 5 and 7 on the front panel connector.
To power on the evaluation board, briefly short pins 5 and 7, then, release
the short. (To power off, short pins 5 and 7 for about five seconds, until
the power shuts off.)
Reset Jumper:
The reset jumper consists of pins 1 and 3 on the front panel connector.
To reset the evaluation board, short pins 1 and 3 until the board resets,
and then release the short.
Turn on the power to the monitor and evaluation board. Ensure that the fansink on the processor is
operating.
18
Getting Started
2.6
Configuring the BIOS
General Software’s BIOS is pre-loaded on the evaluation board. You will need to make changes to
the BIOS to enable hard disks, floppy disks and other supported features. You can use the Setup
program to modify BIOS settings and control the special features of the system. Setup options are
configured through a menu-driven user interface. Chapter 5, “BIOS Quick Reference” contains a
description of BIOS options. BIOS updates may periodically be posted to Intel’s Developers’ Web
site at:
http://developer.intel.com/design/intarch/devkits/
19
3
Theory of Operation
3.1
Block Diagram
Figure 1. Block Diagram
Micro-PGA Socket Processor
VRM
Clock
DATA
CTRL
ADDR
ITP Socket
Termination
GTL Bus
DATA
CTRL
ADDR
AGP
Connector
Compact
Flash
IDE Primary
IDE
USB Port 1
USB Port 2
USB
PCI CONN 3
PCI
PCI CONN 2
Intel®
440MX
Chipset
Digital Video
PCI CONN 1
2 DIMM
Modules
82559
Ethernet
RJ-45
AC'97 Link
Audio Codec
SIO
Speaker
HP Out
Mic In
Line In
IR Header
Serial 2
Serial 1
Keyboard
Mouse
Floppy
A9312-01
21
Theory of Operation
3.2
Mechanical Design
The evaluation board conforms to the micro-ATX form factor. For extra protection in a
development environment, you may want to install the evaluation board in an ATX chassis. The
evaluation board has three 32 bit/33 MHz PCI connectors, one AGP connector, one CNR
connector, two SDRAM DIMM connectors, and one ABIT V-Bus connector. The system I/O
connectors are in the rear of the board in the defined micro-ATX I/O window.
3.3
Thermal Management
The objective of thermal management is to ensure that the temperature of each component is
maintained within specified functional limits. The functional temperature limit is the range within
which the electrical circuits can be expected to meet their specified performance requirements.
Operation outside the functional limit can degrade system performance and cause reliability
problems.
The development kit is shipped with a heatsink/fan thermal solution pre-installed on the processor
using metal clips. This thermal solution has been tested in an open air environment at room
temperature and is sufficient for evaluation purposes. The designer must ensure that adequate
thermal management is provided for any customer-derived designs.
3.4
System Operation
The Intel® 440MX Scalable Low Power Development Kit is designed to support Intel® Celeron®
processors low power/ultra low power (300 MHz and above) and Intel® Pentium® III processors
low power up to 700 MHz in the BGA2 package. The 440MX chipset includes the GMCH, ICH2,
and the FWH.
3.4.1
Intel® Pentium® III Processor
The Intel® Pentium® III processor is a member of the P6 family in the Intel® IA-32 processor line.
Like the Intel® Pentium® II processor, the Intel® Pentium® III processor implements the Dynamic
Execution microarchitecture — a unique combination of multiple branch prediction, data flow
analysis, and speculative execution. Intel® Pentium® III processor features include the following:
•
•
•
•
Dynamic Execution technology
Includes Intel MMX media enhancement technology
Intel streaming SIMD extensions
Incorporates separate 16 Kbyte level-one caches (32 Kbytes total); one for instructions and
one for data
• 256 Kbytes integrated, full-speed level two cache with error correcting code (ECC)
• 8-way level two cache associativity, which provides improved cache-hit rate on read/store
operations
• Double quad word-wide (256 bit) cache data bus, which provides extremely high throughput
on read/store operations
22
Theory of Operation
• Support for 66 MHz and 100 MHz processor system bus frequencies
• Intel® processor serial number
3.4.2
Intel® Celeron® Processor
The Intel® Celeron® processor family delivers quality, reliability, and compatibility while offering
good performance for today’s most widely-used applications. Intel® Celeron® processor features
include:
•
•
•
•
Dynamic Execution technology
Includes Intel MMX* media enhancement technology
Intel streaming SIMD extensions
Incorporates separate 16 Kbyte level-one caches (32 Kbytes total); one for instructions and
one for data
• Incorporates a 128 Kbyte unified, non-blocking, level-two cache that improves performance
by reducing the average memory access time and providing fast access to recently used
instructions and data
• 66/100 MHz Intel® P6 micro-architecture’s multi-transaction system bus that supports multiple
outstanding transactions to increase bandwidth availability
• A pipelined Floating-Point Unit (FPU) for supporting the 32-bit and 64-bit formats specified
in IEEE standard 754, as well as an 80-bit format
• Parity-protected address/request and response system bus signals with a retry mechanism for
high data integrity and reliability
3.4.3
Intel® 440MX Chipset
Features:
•
•
•
•
•
492 BGA package
66 or 100 MHz Processor System Bus
32-bit host bus addressing
Four deep in-order queue
Processor support
— Celeron® processor low power/ultra low power (128 Kbytes) in a micro-PGA package
— Pentium® III processor low power (256 Kbytes) in a micro-PGA package
• System DRAM controller
— Two DIMM slots
— 100 MHz clock
23
Theory of Operation
3.4.4
System Memory SDRAM
Memory Features:
• Two 168-pin SDRAM DIMM sockets
• Supports 8 Mbyte to 256 Mbyte using 16 Mbit/64 Mbit/128 Mbit/256 Mbit technology
• Supports 100 MHz system memory bus
3.4.5
System I/O
The evaluation board contains the following I/O devices.
•
•
•
•
•
•
•
•
Single floppy controller support
Primary and secondary IDE interface (supports two drives)
Two serial ports
Two USB ports
AC’97 specification compliant audio
Speaker Out, Line IN, and MIC IN connectors
PS/2-style keyboard and mouse ports
IR header
Figure 2. Back Panel I/O Connectors
RJ-45
e
us
Mo
COM1
COM2
rd
oa
b
ey
K
Dual USB
t
e
Lin
Ou
n
eI
Lin
C
MI
In
A9315-01
3.4.5.1
Floppy Disk Drive Support
One 34-pin floppy connector is provided on the evaluation board.
3.4.5.2
IDE Support
The evaluation board supports a primary IDE interface via a 40-pin IDE connectors.
24
Theory of Operation
3.4.5.3
RS-232 Serial Ports
The evaluation board provides two built-in serial ports (COM1 and COM2).
3.4.5.4
USB Ports
The evaluation board provides two USB connectors (USB1).
3.4.5.5
Audio Subsystem
The evaluation board has an integrated (on-board) AC’97 compliant subsystem.
Audio Subsystem Features:
• Line input (back panel)
• Speaker output (back panel)
• Microphone input (back panel)
3.4.5.6
Keyboard/Mouse
The keyboard and mouse connectors are PS/2 style, 6-pin stacked miniature DSUB connectors.
The top connector is for the mouse and the bottom connector is for the keyboard.
3.4.5.7
IR Header
The evaluation board provides one IR header. The IR header can be used in place of COM2. To use
the IR header, the BIOS vendor must modify the BIOS to activate IR and deactivate COM2.
Contact either General Software or your own BIOS vendor to assist with the modification.
3.4.6
Expansion Connectors
The evaluation board contains the following expansion connectors:
• Three PCI 32/33 slots
• One compact flash slot
• Two SMBus headers
3.4.6.1
32-bit/33-MHz PCI Connectors
Three industry standard 32-bit/33-MHz PCI connectors (PCI1, PCI2, and PCI3) are provided on
the evaluation board.
3.4.6.2
Compact Flash Slot
One compact flash slot is included on the board. The compact flash can be used as the IDE master
with the proper jumper setting.
25
Theory of Operation
3.4.7
Post Code Debugger
An on-board Post-Code Debugger is implemented on the evaluation board.
3.4.8
Clock Generation
The clock synthesizer on the baseboard generates and distributes the clocks used by the entire
system.
3.4.8.1
System Clocks
The CK Intel® 815E Chipset: 3 DIMM Clock Synthesizer is the primary source of clock generation
for most of the clocks on the baseboard. The following clock groups are found on the Intel® 815E
Scalable Performance Board Development Kit:
26
CPU
66 MHz/100 MHz
PCI
33 MHz
SDRAM
100 MHz
3V66
66 MHz (3.3 V)
USB
48 MHz
DOT
48 MHz
REF
14.31818 MHz
APIC
33 MHz
Theory of Operation
3.4.9
Power Supply Requirements
The Intel® 440MX Scalable Low Power Development Kit uses a standard ATX power supply.
3.5
Battery Requirements
A type 2032, socketed, 3 V lithium coin cell battery is used on this evaluation board. The battery
has a shelf life of greater than three years.
27
Hardware Reference
4
This section provides reference information on the hardware, including connector pinout
information and jumper settings.
4.1
Thermal Management
The development kit is shipped with a heatsink/fan thermal solution pre-installed on the processor
using metal clips. This thermal solution has been tested in an open-air environment at room
temperature and is sufficient for evaluation purposes. The designer must ensure that adequate
thermal management is provided for any customer-derived designs.
For additional thermal design information refer to the following documents:
• Pentium® III Processor for the PGA370 Socket at 500 MHz to 1.0B GHz Datasheet (order
number 245264)
• Intel® Pentium® III Processor Thermal Design Guide (order number 273325)
• Intel® Celeron® Processor up to 850 MHz datasheet (order number 243658)
• Intel® Celeron® Processor Thermal Design Guide (order number 273421)
4.1.1
Changing the Processor
If you wish to change the processor, follow these instructions to remove the heat sink assembly.
1. Disconnect the fan cable from the ATX power supply.
2. Remove the pins from the body on the four attachment rivets (see Figure 3) with needle-nose
pliers.
Figure 3. View of the Fan/Heat Sink
29
Hardware Reference
3. Remove the body of the attachment rivets with needle-nose pliers.
Warning:
Be sure to support the board directly around the hole that a rivet is being removed from. Failure to
do so could result in too much deflection and damage to the board.
4. Remove the heat sink assembly from the board.
5. Replace the processor by turning the screw on the socket to loosen the processor.
Note:
Before replacing the heat sink assembly, it is very important to remove all thermal interface
material (TIM) from the heat sink and processor. Be sure to clean the heat sink surface and surface
of the die with isopropyl alcohol before re-installation.
6. Place the attachment shroud over the heat sink, as shown in Figure 4.
Figure 4. Top View of the Heat Sink
7. Turn the heat sink over so that the bottom is facing up.
8. Remove the protective liner from one side of the thermal interface material. It should come off
fairly easy from the strips.
9. Place the protective liner on the bottom of the heat sink with ‘rolling finger pressure.’
10. Remove the remaining protective liner. To remove the protective liner, place a piece of tape at
one corner (as shown in Figure 5) and pull up at a 180-degree angle.
30
Hardware Reference
Figure 5. Bottom View of Heat Sink
11. Place the heat sink on top of the die, making sure to align the holes in the shroud with those on
the board.
12. Place the body of the rivet through the hole in the attach shroud. Ensure the spring is on the
body and above the tab on the shroud.
13. Push the body through the hole in board. It is easiest to insert the rivet using a mechanical
pencil or some other object that will allow you to push with even pressure. Be sure to insert the
rivets in opposite corners, so even pressure on the die is maintained.
Warning:
Be sure to support the board directly around the hole that a rivet is being inserted into. Failure to do
so could result in too much deflection and could damage the board.
14. After all rivet bodies are inserted into the board, push the pins all the way into the body. It
should look like Figure 3.
15. Plug the fan cable into the ATX power supply.
31
Hardware Reference
4.2
Connector Pinouts
COM A
PS/2
RJ-45
MOUSE
KEYBD
COM B
USB 1
USB 0
ENET
LM1877
RS232
CD IN
RS232
XTAL
Dual USB
SPKR OUT
3.3v
FUSE
45H11
PCI SLOT 1
93C46
Intel
82559
’LVC14
PCI SLOT 2
FUSE
PCI SLOT 3
MOUSE
LINE IN
FUSE
MIC IN
AC97
Codec
KEYBD
Figure 6. Baseboard Layout Diagram
’LVC06
Crystal
THMC10
120
FET
Driver
CPU FAN
Pulse
PE53591
Intel
443MX
5 mohm
340
Switcher
4420
4420
uPGA Socket
ITP
SMSC
SuperIO
SMBus 2
+
+ SMBus 1
’HC00
DIMM 0
DIMM 1
CLK100
28F004
COMPACT FLASH
22V10
RST PWR SLP HD LED +
P LED +
SPKR +
Crystal
IrDA
+
22V10
PWR
PRIMARY IDE
CompactFlash
Type II
FUSE
FLOPPY
ENET
DIS EN
CMOS
CLR NRM
CF MASTER
SBY
POST CODE
BIOS UNLOCK
A9443-01
32
Hardware Reference
4.2.1
ATX Power Connector
Table 2 lists the signals assigned to the ATX style power connector.
Table 2.
4.2.2
Power Connector (ATXPR1)
Pin
Name
Function
1
3.3 V
3.3 V
2
3.3 V
3.3 V
3
GND
Ground
4
+5V
+5 V VCC
5
GND
Ground
6
+5 V
+5 V VCC
7
GND
Ground
8
PWRGD
Power Good
9
5 VSB
Standby 5 V
10
+12 V
+12 V
11
3.3 V
3.3 V
12
-12 V
-12 V
13
GND
Ground
14
PS_ON#
Soft-off control
15
GND
Ground
16
GND
Ground
17
GND
Ground
18
-5 V
-5 V
19
+5 V
+5 V VCC
20
+5 V
+5 V VCC
Dual Stacked USB Connector
Table 3 lists the signals assigned to the dual stacked USB connector (USB1).
Table 3.
USB Connector Pinout (USB1)
Pin
Signal Name
1,5
Power (fused)
2,6
USBP0# [USBP1#]
3,7
USBP0 [USBP1]
4,8
GND
33
Hardware Reference
4.2.3
PS/2-Style Mouse and Keyboard Connectors
Table 4 lists the signals assigned to the keyboard and mouse connector (U1). The mouse port is on
the top and the keyboard port is on the bottom.
Table 4.
PS/2-Style Mouse and Keyboard Pinout (U1)
Pin
4.2.4
Signal Name
1
Data
2
No Connect
3
GND
4
+5 V (fused)
5
Clock
6
No Connect
Serial Ports
Table 5 lists the signals assigned to the serial port connectors (COM1 and COM2).
Table 5.
Serial Port Connector Pinout (COM1 and COM2)
Pin
34
Signal Name
1
DCD
2
Serial In (SIN)
3
Serial Out (SOUT)
4
DTR
5
GND
6
DSR
7
RTS
8
CTS
9
RI
Hardware Reference
4.2.5
Audio Connectors
Refer to Figure 2 on page 24 for the connectors referenced in this section.
Table 6 lists the signals assigned to the audio line-out connector.
Table 6.
Audio Line-Out Connector Pinouts
Pin
Signal Name
Sleeve
GND
Tip
Audio Left Out
Ring
Audio Right Out
Table 7 lists the signals assigned to the audio line-in connector.
Table 7.
Audio Line-In Connector Pinouts
Pin
Signal Name
Sleeve
GND
Tip
Audio Left In
Ring
Audio Right In
Table 8 lists the signal assigned to the audio mic-in connector.
Table 8.
4.2.6
Table 9.
Audio Mic-In Connector Pinouts
Pin
Signal Name
Sleeve
GND
Tip
Mono In
Ring
Mic bias voltage
Compact Flash Connector
Compact Flash Connector (Sheet 1 of 2)
Pin
Signal Name
Pin
Signal Name
1
Ground
26
Ground
2
Host Data 3
27
Host Data 11
3
Host Data 4
28
Host Data 12
4
Host Data 5
29
Host Data 13
5
Host Data 6
30
Host Data 14
6
Host Data 7
31
Host Data 15
7
IDEPDCS1#
32
IDEPDCS3#
8
Ground
33
N/C
35
Hardware Reference
Table 9.
4.2.7
Compact Flash Connector (Sheet 2 of 2)
9
Ground
34
IDEPDIOR#
10
Ground
35
IDEPDIOW#
11
Ground
36
VCC
12
Ground
37
IDEPDIRQ
13
VCC
38
VCC
14
Ground
39
IDEPCSEL1#
15
Ground
40
N/C
16
Ground
41
IDERST#
17
Ground
42
IDEPDIORDY
18
Addr 2
43
N/C
19
Addr 1
44
VCC
20
Addr 0
45
IDEPDASP#
21
Host Data 0
46
IDEPDIAG#
22
Host Data 1
47
Host Data 8
23
Host Data 2
48
Host Data 9
24
IDEIOCS16#
49
Host Data 10
25
Ground
50
Ground
IDE Connector
Table 10 lists the signals assigned to the IDE connectors (IDE1 and IDE2).
Table 10. IDE Connector Pinouts for IDE1 and IDE2 (Sheet 1 of 2)
36
Pin
Signal Name
Pin
Signal Name
1
Reset IDE
21
DRQ3
2
Ground
22
Ground
3
Host Data 7
23
I/O Write#
4
Host Data 8
24
Ground
5
Host Data 6
25
I/O Read#
6
Host Data 9
26
Ground
7
Host Data 5
27
IOCHRDY
8
Host Data 10
28
Ground
9
Host Data 4
29
DACK3#
10
Host Data 11
30
Ground
11
Host Data 3
31
IRQ14
12
Host Data 12
32
IOCS16#
13
Host Data 2
33
Addr1
14
Host Data 13
34
PDIAG
15
Host Data 1
35
Addr 0
Hardware Reference
Table 10. IDE Connector Pinouts for IDE1 and IDE2 (Sheet 2 of 2)
4.2.8
Pin
Signal Name
Pin
Signal Name
16
Host Data 14
36
Addr 2
17
Host Data 0
37
Chip Select 0#
18
Host Data 15
38
Chip Select 1#
19
Ground
39
Activity
20
N/C
40
Ground
Floppy Drive Connector
Table 11 lists the signals assigned to the floppy drive connector (FDC1).
Table 11. Floppy Drive Connector Pinouts (FDC1)
4.2.9
Pin
Signal Name
Pin
Signal Name
1
Ground
2
DRVDENO
3
Ground
4
Reserved
5
N/C
6
DRVDEN1
7
Ground
8
Index
9
Ground
10
Motor Enable A#
11
Ground
12
Drive Select B#
13
Ground
14
Drive Select A#
15
Ground
16
Motor Enable B#
17
Ground
18
DIR#
19
Ground
20
STEP#
21
Ground
22
Write Data#
23
Ground
24
Write Gate#
25
Ground
26
Track 00#
27
Ground
28
Write Protect#
29
N/C
30
Read Data#
31
Ground
32
Side 1 Select#
33
N/C
34
Diskette Change#
32-Bit PCI Slot Connector
Table 12 lists the signals assigned to the 32-Bit PCI slot connectors (PCI1, PCI2, and PCI3).
37
Hardware Reference
Table 12. 32-Bit PCI Slot Connector Pinouts
Pin
A01
38
Signal
Name
GND
Pin
B01
Signal
Name
-12 V
Pin
A32
Signal
Name
Pin
Signal
Name
AD16
B32
AD17
A02
+ 12 V
B02
GND
A33
3.3 V
B33
CBE2#
A03
VCC
B03
GND
A34
FRAME#
B34
GND
A04
VCC
B04
No
Connect
A35
GND
B35
IRDY#
A05
VCC
B05
VCC
A36
TRDY#
B36
3.3 V
A06
PIRQ1#
B06
VCC
A37
GND
B37
DEVSEL#
A07
PIRQ3#
B07
PIRQ2#
A38
STOP#
B38
GND
A08
VCC
B08
PIRQ0
A39
3.3 V
B39
LOCK#
A09
No Connect
B9
PRSNT1B
#
A40
SDONE
B40
PERR#
A10
VCC
B10
No
Connect
A41
SBO#
B41
3.3V
A11
No Connect
B11
PRSNT2B
#
A42
GND
B42
SERR#
A12
GND
B12
GND
A43
PAR
B43
3.3 V
A13
GND
B13
GND
A44
AD15
B44
CBE1#
A14
No Connect
B14
No
Connect
A45
3.3V
B45
AD14
A15
RST#
B15
GND
A46
AD13
B46
GND
A16
VCC
B16
PCLK3
A47
AD11
B47
AD12
A17
GNT1#
B17
GND
A48
GND
B48
AD10
A18
GND
B18
REQ#
A49
AD9
B49
GND
A19
PPME#
B19
VCC
A50
KEY
B50
KEY
A20
AD30
B20
AD31
A51
KEY
B51
KEY
A21
3.3 V
B21
AD29
C52
CBEO#
D52
AD8
A22
AD28
B22
GND
C3
3.3 V
D53
AD7
A23
AD26
B23
AD27
C54
AD6
D54
3.3 V
A24
GND
B24
AD25
C55
AD4
D55
AD5
A25
AD24
B25
3.3 V
C56
GND
D56
AD3
A26
IDSEL
B26
CBE3#
C57
AD2
D57
GND
A27
3.3 V
B27
AD23
C58
AD0
D58
AD1
A28
AD22
B28
GND
C59
VCC
D59
VCC
A29
AD20
B29
AD21
C60
N/C
D60
ACK64#
A30
GND
B30
AD19
C61
VCC
D61
VCC
A31
AD18
B31
3.3 V
C62
VCC
D62
VCC
Hardware Reference
4.3
Jumpers
Front Panel Connector
RST
PWR
SLP
HD LED
Pin 1
+
Pin 2
Pin 19
Pin 20
SPKR
+
P LED
+
FRONT VIEW
1
RESET BUTTON (GND)
2
RESET BUTTON (NON-RESUME)
3
5
RESET BUTTON (RESUME WELL)
POWER BUTTON
4
6
ONBOARD SPEAKER IN (-)
SPEAKER (-)
7
POWER BUTTON
8
GND
9
SLEEP BUTTON
10
N.C.
11
SLEEP BUTTON
12
SPEAKER (+)
13
N.C.
14
N.C.
15
N.C.
16
POWER LED (-)
17
HD LED (-)
18
N.C.
19
HD LED (+)
20
POWER LED (+)
NOTES:
1. Normal RESET should connect between pins 1 and 3.
Alternate reset connects between 1 and 2, but RESUME well
will not be reset in this case.
2. Onboard speaker is enabled with a jumper on pins 4 and 6.
To use an external speaker, remove jumper and connect cable
to pins 6, 8, 10, and 12.
4.3.1
CMOS Jumper
The CMOS jumper controls the power to the battery backed-up CMOS memory. This CMOS
memory stores system information required by the BIOS during startup. For normal operation,
jumper pins 1 and 2. To clear the CMOS RAM, perform the following steps:
1. Shut down the system.
2. Disconnect the power supply (ATXPR1).
3. Remove jumper from pins 21 and 22. Short pins 20 and 21 (clear CMOS).
4. Wait 10 seconds.
5. Replace the jumper on pins 21 and 22 (normal operation).
6. Reconnect the power supply (ATXPR1).
7. Boot the system and enter the BIOS setup screen to reconfigure the system.
4.3.2
Short Pins 21 and 22
Normal Operation (default)
Short Pins 20 and 21
Clear saved CMOS data
ENET Jumper
When using the Ethernet controller you must short pins 18 and 19 on the ENET jumper. To
deactivate, short pins 17 and 18.
39
Hardware Reference
4.3.3
CF MASTER Jumper
To make the compact flash the IDE master, short pins 23 and 24.
4.3.4
BIOS UNLOCK Jumper
You can choose to lock access to the BIOS by shorting 25 and 26.
40
BIOS Quick Reference
5
The evaluation board is licensed with a single copy of Embedded BIOS and Embedded DOS
software from General Software, Inc. This software is provided for demonstration purposes only
and must be licensed directly from General Software, Inc. for integration with new designs.
General Software may be reached at (800) 850-5755, on the Web at http://www.gensw.com, or via
e-mail at [email protected].
BIOS updates may periodically be posted to the Intel Developers’ Web site at
http://developer.intel.com/.
5.1
Embedded BIOS Introduction
General Software’s Embedded BIOS brand BIOS (Basic Input/Output System) pre-boot firmware
is the industry’s standard product used by most designers of embedded x86 computer equipment in
the world today. Its superior combination of configurability and functionality enables it to satisfy
the most demanding ROM BIOS needs for embedded designers. Its modular architecture and high
degree of configurability make it the most flexible BIOS in the world.
Although Embedded BIOS can be made to behave like a PC BIOS, it has a fundamentally different
role. The goal of a PC BIOS is to provide the same standard user experience for all the systems it
runs on. For example, this allows a wide range of users to intuitively use any notebook computer,
regardless of brand. The goal of Embedded BIOS is completely different—it allows the embedded
equipment manufacturer to differentiate its product from competing products in a way that is quick
and cost effective—allowing the manufacturer to pass savings on to the end user.
This operating guide describes all of the possible user features of Embedded BIOS. Most of these
features are included in the demonstration BIOS on this platform, but not all can be included, either
due to space limitations or because features have conflicting requirements. Some features require
hardware support that is not present in all designs. You can see a list of included and available
features in the BIOS browser included in your demonstration BIOS. Instructions for accessing the
BIOS Browser are found later in this guide.
Once you move from the demonstration BIOS to your own custom adaptation, you may choose to
incorporate some or all applicable features, modifying them as necessary to fit your application.
Therefore, some of the features discussed in this operating guide may not apply to your system’s
Demonstration BIOS.
5.1.1
Features
Dedicated to the embedded 80x86-based market, Embedded BIOS offers special-purpose features
not provided by typical PC BIOS implementations.
Embedded BIOS’s CPU-specific personality modules allow support of high-integration processors
that have on-board timers, DMA controllers, serial ports, watchdog timers, power management,
and other features.
41
With chipset support, virtually any add-on chipset, or CPU with on-board chipset can be supported
by Embedded BIOS. Traditionally, chipsets provide DRAM memory management, bus control,
and address space management. The Embedded BIOS architecture provides for chipset personality
modules that can be selected for a project.
Embedded BIOS’s board-level support provides for the OEM to control the BIOS’s access to
chipset and CPU modules in major or subtle ways. Essentially a routing module, the board module
contains routines, which call associated routines in the chipset and CPU personality modules. The
board module routines can be modified as needed to replace the calls to the underlying CPU and
chipset modules with custom code, as needed for hardware designs that work differently than
standard reference designs supported by General Software.
Embedded BIOS is implemented in hand-optimized 80x86 assembly language, with special code
paths for many generations of processors. The code paths have been hand-tuned to minimize the
interrupt latency commonly found in desktop BIOS implementations, and many of the “hot paths”
of the BIOS have been straight-line optimized for the common case.
ROM disk software is integrated directly with the system BIOS itself, eliminating the need to
populate the ROM scan area with ROM BIOS extensions to simulate one or more floppy or hard
disks in ROM. Instead, with the ROM disk configuration feature enabled, an image of a floppy or
hard disk can be stored in ROM anywhere in the address space of the TARGET and treated as a
solid-state drive. If the ROM disk feature is enabled, the ROM disk can be selectively turned on or
off in the setup screen.
RAM disk software is also integrated directly into the system BIOS to support PCMCIA SRAM
cards and other RAM areas as floppy or hard disk emulators. SETUP even has a formatting screen
for the RAM disk.
The system BIOS supports a Resident Flash Disk (RFD) that provides read/write access to sectored
Flash devices as though they were a floppy or hard disk of up to 32 Mbytes in size. The inclusion
of this software makes it easy to support Flash in embedded and hand-held consumer electronics.
Multiple RFDs can be supported in the same TARGET.
The integrated BIOS debugger gives the engineer bringing up new hardware the capability of
debugging the hardware with powerful tools like a disassembler, breakpoints, CMOS editing, A20line gating commands, cache control commands, PCI bus management commands, and Super I/O
controls. The debugger is very useful for debugging chipset modules, CPU class modules, and
initialization of user ROM extensions and hardware. Like the setup screen, the integrated BIOS
debugger can run directly on a PC keyboard and video screen, or it can be redirected over an RS232 serial link.
Embedded systems deployed into more inaccessible areas need watchdog timer support, so that
they can automatically restart in the event that application or system software fails. Embedded
BIOS provides watchdog timer control functions to allow operating systems and application
programs to use watchdog timer hardware found in chipsets and certain CPU classes.
Keyboard and video output may be selectively redirected over RS-232 serial links for different
system components. For example, standard console I/O, such as that used by DOS and DOS
applications, can be redirected over any COM port, including those built-into high-integration
CPUs. Debugger I/O and setup screen I/O can also be redirected over the same or different RS-232
serial links.
42
A special Manufacturing Mode feature provides the necessary provisions for programming
electronics products through a high-speed serial link, and then testing and repairing the same items
in the field at service centers. The OEM can write custom software that uses Embedded BIOS
Manufacturing Mode functions to perform virtually any maintenance or programming task on the
TARGET under host control.
5.1.2
PC BIOS Features
Embedded BIOS provides a comprehensive Power-On Self-Test (POST) algorithm that is
automatically configured for the peripherals and capabilities selected by the adaptation engineer.
During POST, hardware is initialized and tested, including the CPU, RAM, and peripherals. POST
provides beep code diagnostics for errors when a display is not available, as well as error message
diagnostics on the display when available. POST can also be configured to output status report
codes to a manufacturing port (typically, port 80h) so that automated Q/A equipment can determine
the status of a system during POST. A special set of ASCII POST status codes are also available
through a serial port, for flexibility in the debugging process when new hardware is being brought
up. Either POST code system, or both, can be used during debugging.
The Embedded BIOS SETUP screen system is configurable at the source level by the adaptation
engineer to contain any combination of subscreens, including basic CMOS configuration, custom
configuration, shadow configuration, diagnostics screens, manufacturing mode, debugger access,
and formatting of drive emulators such as RAM and RFD drives. Setup screens can also be
customized at the source level (in the board personality module) to contain custom fields as
required by the application.
The BIOS browser is also available for your use. Selectable as a boot action or from within setup, it
can present HTML files to your end users to document the platform, provide contact information
for your company, etc. This provides a convenient means of providing information to help users
recover from hardware problems, like a failed hard drive.
Also available is a password protection system, so that a password must be provided by the enduser before POST allows booting of an operating system. The password is stored in CMOS, is oneway encrypted, and can be modified in a setup screen.
The ability to shadow slower ROM devices with DRAM or SRAM is selectable in the shadow
setup screen and calls chipset-specific code to enable shadowing for the BIOS ROM itself or for
feature ROMs on a 16 Kbyte region basis. DRAM may take the form of FP, EDO, SDRAM,
RDRAM, or other technologies.
Embedded BIOS provides extensive support for both internal CPU cache control (i486 and above)
and external cache control (typically chipset-controlled). Internal cache is managed by the CPU
class personality modules, whereas external cache is managed by the cache manager, which directs
peripherals (chipset, 8042, custom I/O ports, or CPU integrated peripherals) to manage the cache.
Keyboard controls on the PC/AT keyboard are implemented for enabling and disabling the cache
on the fly (while the system is running). The BIOS provides cache control services to applications
that allow operating systems and user code to control and inspect the status of the cache.
CPU speed controls are handled by the system BIOS by routing control through the appropriate
logic (chipset, 8042, custom I/O ports, or CPU integrated peripherals). As with cache control, CPU
speed is controllable while the system is running at the keyboard or via programming interfaces.
43
5.1.3
Software Compatibility
Embedded BIOS offers a high degree of compatibility with past and current BIOS standards,
allowing it to run off-the-shelf operating system software and application software.
Embedded BIOS has been tested with all industry-standard operating systems, including versions
of Windows, Linux, DOS, and real time operating systems.
Embedded BIOS is rigorously tested with programs such as AMI Diag, MSD, Check-It, Manifest,
Q/A Plus, ensuring its compatibility with established desktop application standards.
In addition to its standard data structures and programming interfaces, Embedded BIOS provides
support for industry-standard initiatives, including ACPI, APM, El Torito, Legacy USB, MP, PCI,
PMM, PXE, and SMBIOS (formerly DMI).
5.2
Power On Self Test
When the TARGET is powered on, Embedded BIOS tests and initializes the hardware and
programs the chipset and other peripheral components. During this time, Power On Self Test
(POST) progress codes are written by the system BIOS to I/O port 80h, allowing the user to
monitor the progress with a special monitor. Section 5.7.1, “Embedded BIOS POST Codes” on
page 57 lists the POST codes and their meanings.
During early POST, no video is available to display error messages should a critical error be
encountered; therefore, POST uses beeps on the speaker to indicate the failure of a critical system
component during this time. Consult Section 5.8, “Critical Error Beep Codes” on page 60 for a list
of beep codes used by the TARGET’s BIOS.
5.2.1
The BIOS User Interface
The TARGET BIOS can use the standard keyboard and video device, or use console redirection to
demonstrate headless operation. For headless operation, remove the standard keyboard and screen
devices and the system will boot unattended. If an RS232 cable is attached to COM1, a PC/ATstyle character-based POST is available from HyperTerminal, PROCOMM, or any other terminal
emulator software that supports VT100 emulation.
When a keyboard and video device are attached, the TARGET can display either a traditional
character-based PC BIOS display with memory count-up, or it can display a graphical POST with
splash screen and progress icons. Both POST displays accept a <DEL> key press to enter the setup
screen, and both display boot-time progress activity displays. The graphical display shows the
status of file system devices and even OEM-defined devices (when the OEM adapts the BIOS to a
particular OEM platform), but omits character-based PCI resource display. The text-based POST
displays the memory count-up and the PCI resource assignment table.
Figure 7 shows the format of the text-based POST display. The display is very similar if console
redirection through a COM port is used instead.
44
Figure 7. BIOS POST, the Text-based System
Figure 8 shows the graphical version of POST. The BIOS decompresses the main image, and can
display multiple overlaid graphics at various points in POST. The OEM can define the entire
sequence and control the timing of the system for an embedded application, and can arrange to
have different graphics displayed on each successive boot of the system. This feature is ideal for
embedded systems that must show evidence of operation during startup, while the application loads
underneath the splash screen. Once the application begins writing to the screen, the splash screen
relinquishes control, providing a seamless graphical progression for the end user.
Figure 8. The Graphical POST
45
When the TARGET is powered on for the first time, you’ll need to configure the system through
the Setup Screen System (described later) before peripherals, such as disk drives, are recognized by
the BIOS. The information is written to battery-backed CMOS RAM on the board’s Real Time
Clock. Should the board’s battery fail, this information will be lost and the board will need to be
reconfigured.
The TARGET’s Basic Setup Screen provides an option to disable the graphical POST and switch to
the legacy text-based version. This feature may not permanently disable the graphical POST if the
BIOS adaptation calls for reverting to the graphical form after so many boots. If you find that the
graphical POST comes back after several boots, it is because this option is enabled for this
platform. Naturally, the OEM can use the Embedded BIOS Adaptation Kit to control whether
Setup can be used to dictate the policy, and whether it is permanent or temporary.
5.3
Setup Screen System
The TARGET is configured from within the Setup Screen System, a series of menus that can be
invoked from POST by pressing the <DEL> key if the main keyboard is being used, or by pressing
Ctrl C (^C) if the console is being redirected to a terminal program.
Figure 9. Embedded BIOS Setup Screen Menu
Once in the Setup Screen System (Figure 9), the user can navigate with the UP and DOWN arrow
keys from the main console or use the Ctrl E (^E) and Ctrl X (^X) keys from the remote terminal
program to accomplish the same thing. TAB and ENTER are used to advance to the next field, and
‘+’ and ‘-’ keys cycle through values, such as those in the Basic Setup Screen or the Diagnostics
Setup Screen.
5.3.1
Basic CMOS Configuration Screen
The TARGET’s drive types, boot activities, and POST optimizations are configured from the Basic
Setup Screen (Figure 10). To use disk drives with your system, you must select appropriate
assignments of drive types in the left-hand column. Then, if you are using true floppy and IDE
drives (not memory disks that emulate these drives), you need to configure the drive types
themselves in the Floppy Drive Types and IDE Drive Geometry sections. Finally, you’ll need to
configure the boot sequence in the middle of the screen. Once these selections have been made,
your system is ready to use.
46
Figure 10. Embedded BIOS Basic Setup Screen
5.3.2
Configuring Drive Assignments
Embedded BIOS allows the user to map a different file system to each drive letter. The BIOS
allows file systems for each floppy (Floppy0 and Floppy1), each IDE drive (Ide0, Ide1, Ide2, and
Ide3), and memory disks when configured (Flash0, ROM0, RAM0, etc.). Figure 10 shows how the
first floppy drive (Floppy0) is assigned to drive A: in the system, and then shows how the first IDE
drive (Ide0) is assigned to drive C: in the system.
To switch two floppy disks around or two hard disks around, map Floppy0 to B: and Floppy1 to A:,
and for hard disks map Ide0 to D: and Ide1 to C:.
Caution:
Take care to not skip drive A: when making floppy disk assignments, as well as drive C: when
making hard disk assignments. The first floppy should be A:, and the first hard drive should be C:.
Also, do not assign the same file system to more than one drive letter. Thus, Floppy0 should not be
used for both A: and B:. The BIOS permits this to allow embedded devices to alias drives, but
desktop operating systems may not be able to maintain cache coherency with such a mapping in
place.
A special field in this section entitled “Boot Method: (Windows CE/Boot Sector)” is used to
configure the CE Ready feature of the BIOS. For normal booting (DOS, Windows NT, etc.), select
“Boot Sector” or “Unused.”
5.3.3
Configuring Floppy Drive Types
If true floppy drive file systems (and not their emulators, such as ROM, RAM, or Flash disks) are
mapped to drive letters, then the floppy drives themselves must be configured in this section.
Floppy0 refers to the first floppy disk drive on the drive ribbon cable (normally drive A:), and
Floppy1 refers to the second drive (drive B:).
47
5.3.4
Configuring IDE Drive Types
If true IDE disk file systems (and not their emulators, such as ROM, RAM, or Flash disks) are
mapped to drive letters, then the IDE drives themselves must be configured in this section. The
following table shows the drive assignments for Ide0-Ide3:
Controller
Master/
Slave
Ide0
Primary
(1f0h)
Master
Ide1
Primary
(1f0h)
Slave
Ide2
Secondary
(170h)
Master
Ide3
Secondary
(170h)
File System Name
Slave
To use the primary master IDE drive in your system (the typical case), configure Ide0 in this
section, and map Ide0 to drive C: in the Configuring Drive Assignments section.
The IDE Drive Types section lets you select the type for each of the four IDE drives: None, User,
Physical, LBA, or CHS.
The User type allows the user to select the maximum cylinders, heads, and sectors per track
associated with the IDE drive. This method is now rarely used since LBA is now in common use.
The Physical type instructs the BIOS to query the drive’s geometry from the controller on each
POST. No translation on the drive’s geometry is performed, so this type is limited to drives of
512 Mbytes or less. Commonly, this is used with embedded ATA PC cards.
The LBA type instructs the BIOS to query the drive’s geometry from the controller on each POST,
but then translate the geometry according to the industry-standard LBA convention. This supports
up to 128 Gbyte drives. Use this method for all new drives.
The CHS type instructs the BIOS to query the drive’s geometry from the controller on each POST,
but then translate the geometry according to the Phoenix CHS convention. Using this type on a
drive previously formatted with LBA or physical geometry might show data as being missing or
corrupted.
EMBEDDED BIOS supports user-defined steps in the boot sequence. When the entire system has
been initialized, POST executes these steps in order until an operating system successfully loads.
In addition, other pre-boot features can be run before, after, or between operating system load
attempts. The following actions are supported:
• Drive A: - D:
Boot operating system from specified drive. If “Loader” is set to “BootRecord” or “Unused,”
then the standard boot record will be invoked, causing DOS, Windows95, Windows 98,
Windows ME, Windows 2000, Windows NT, Windows XP, Linux, or other industry-standard
operating systems to load. If “Boot Method” is set to “Windows CE“, then the boot drive’s
boot record will not be used, and instead the BIOS will attempt to load and execute the
Windows CE Kernel file, NK.BIN, from the root directory of each boot device.
• CDROM
48
Boot from the first IDE CDROM found that contains an El Torito bootable CDROM.
• Debugger
Launch the Integrated BIOS Debugger. To return exit the debugger environment, type “G” at
the debugger prompt and press ENTER.
• MFGMODE
Initiate Manufacturing Mode, allowing the system to be configured remotely via an RS232
connection to a host computer.
• WindowsCE
Execute a ROM-resident copy of Windows CE, if available. This feature is not applicable
unless configured by the OEM in the BIOS adaptation.
• DOS in ROM
Execute a ROM-resident copy of DOS, if available. This feature is not applicable unless an
XIP copy of DOS has been stored in the BIOS boot ROM.
• Alarm
Generate an alarm by beeping the speaker and sending a signal to a Firmware Application
running in the firmbase environment. The application can perform whatever processing is
necessary to handle the alarm, including taking local action, interacting with other tightly
coupled computers, or even notifying other systems on the network, for example. These
applications are beyond the scope of the Embedded BIOS Adaptation Kit.
• Maintenance
Enter maintenance mode by sending a signal to a firmware application running in the firmbase
environment. The application can perform whatever processing is necessary to implement the
maintenance mode, which is largely defined to mean some state where the system is capable of
being diagnosed and/or repaired in the field. These applications are beyond the scope of the
Embedded BIOS Adaptation Kit.
• RAS
Enter remote access mode by sending a signal to a firmware application running in the
firmbase environment. The application can perform whatever processing is necessary to
implement the RAS mode, which is largely defined to mean some state where the system
accepts remote connections for normal operation; not specifically for field maintenance. These
• Power Off
Cause the TARGET to switch off its power with a “soft off” feature, and signal firmware
applications running in the firmbase environment that power is going down. These
• Reboot
Reboot the TARGET, and send a signal to a Firmware Application running in the Firmbase
environment indicating that the TARGET is rebooting. These applications are beyond the
scope of the Embedded BIOS Adaptation Kit.
• CLI
Enter command line mode by calling a special Board Module Function (BoardPostControl)
that can be used to implement an OEM-defined Command Language Interpreter. The design of
such an interpreter is beyond the scope of the Embedded BIOS Adaptation Kit.
• None
49
No action; POST proceeds to the next activity in the sequence.
5.3.5
Custom Configuration Setup Screen
The TARGET’s hardware-specific features are configured with the Custom Setup Screen
(Figure 11). All features are straightforward except for the Redirect Debugger I/O option, which is
an extra embedded feature that allows the user to select whether the Integrated BIOS Debugger
should use standard keyboard and video or RS232 console redirection for interaction with the user.
If no video is available, the debugger is always redirected.
Figure 11. Embedded BIOS Custom Setup Screen
5.3.6
Shadow Configuration Setup Screen
The TARGET’s Shadow Configuration Setup Screen (Figure 12) allows the selective enabling and
disabling of shadowing in 16 Kbyte sections, except for the top 64 Kbytes of the BIOS ROM,
which is shadowed as a unit. Normally, shadowing should be enabled at C000/C400 (to enhance
VGA ROM BIOS performance) and then E000-F000 should be shadowed to maximize system
ROM BIOS performance.
Figure 12. Embedded BIOS Shadow Setup Screen
50
Embedded systems may require automated burn-in testing in the development cycle. This facility is
provided directly in the TARGET’s system BIOS through the Standard Diagnostics Routines Setup
Screen (Figure 13). To use the system, selectively enable or disable features to be tested, and then
enable the “Tests Begin on ESC?” option to cause the system test suite to be invoked. To repeat the
system test battery continuously, you should also enable the “Continuous Testing” option. When
continuous testing is started, the system will continue until an error is encountered.
Caution:
Warning:
The disk I/O diagnostics perform write operations on those drives; therefore, only spare drives
should be used that do not contain data that could be harmed by the test.
The keyboard test may fail when in fact the hardware is operating within reasonable limits. This is
because although the device may produce occasional errors, the BIOS retries operations when
failures occur during normal operation of the system.
Figure 13. Standard Diagnostic Routines Setup Screen
5.3.7
Start System BIOS Debugger Setup Screen
The Embedded BIOS Integrated Debugger may be invoked from the Setup Screen main menu, as
well as a boot activity. Once invoked, the debugger will display the debugger prompt:
EBDEBUG:
and await debugger commands. To resume back to the Setup Screen main menu, type the
following command, which instructs the debugger to “go”:
EBDEBUG: G (ENTER)
5.3.8
Start RS232 Manufacturing Link Setup Screen
The Embedded BIOS Manufacturing Mode may be invoked from the Setup Screen main menu, as
well as a boot activity. Once invoked, Manufacturing Mode takes over the system and freezes the
system console (Figure 14). The host can resume operation of the system and give control back to
the TARGET Setup Screen system with special control software.
51
Figure 14. Start RS232 Manufacturing Link Setup Screen
5.3.9
Manufacturing Mode
The TARGET’s BIOS may provide a special mode, called Manufacturing Mode, which allows the
TARGET to be controlled by a host computer such as a laptop or desktop PC. Running special
software supplied by General Software, the host can access the TARGET’s drives and manage the
file systems on the TARGET, reprogram Flash memories, and test the TARGET hardware.
There are several methods by which the TARGET can enter Manufacturing Mode. These methods
are detailed elsewhere in this manual and others.
Once the TARGET has entered Manufacturing Mode, the host PC may cause the TARGET to
perform functions by issuing commands in protocol over the RS-232 connection. There are two
ways to access the TARGET from the host PC.
5.3.9.1
Sample Manufacturing Mode HOST Program
The first way is to run a program that accesses the host-side Manufacturing Mode functions. An
example of such a program is HOST.EXE, which can be obtained from General Software. This
program runs under DOS and, using a full-screen windowing interface, illustrates the basic
functionality of the Manufacturing Mode protocol. It should be noted that this program is a
working example program, and is not intended to be a production-quality control tool.
Run the HOST program on a “host” computer, so that its main menu is displayed. By default
HOST connects via COM1 (3F8h). The default baud rate is set to “auto,” meaning it will use
whatever baud rate the TARGET is set to. You can change both of these by using command line
switches. Type “HOST /?” for the available switches.
On the host, select “Get Target Attention,” within a couple seconds of selecting the manufacturing
mode on the TARGET. You should see the host program immediately display a yellow status box
that shows that the connection has been established.
52
If the connection has not been established, try the connection again on the host side, or reboot the
TARGET and try again, this time having the host program get the TARGET’s attention within
about two seconds of the TARGET’s entering of manufacturing mode. If this still fails, check that
your null modem serial cable is connected securely to the proper ports. You may also want to lower
the baud rate for the manufacturing mode on the TARGET, since a higher baud rate may be more
error prone.
Once you have established a connection, you can use HOST to test the link by continuously
exercising it, or scanning the TARGET’s drives, or uploading files in Flash, and more.
5.3.9.2
Manufacturing Mode Drive Redirection
The second way to access the TARGET through Manufacturing Mode is to install the MFGDRV.SYS
device driver on the host system. This device driver loads under MS-DOS and Windows 98 DOS
mode, and maps a new drive letter on the host to a drive on the TARGET. It is a DOS-only driver,
and will not operate under Linux or Windows, not even in a Windows DOS box.
The INT 13h redirection support in the Manufacturing Mode protocol can be exposed by loading
the MFGDRV.SYS device driver on the host by using the following CONFIG.SYS line:
DEVICE=MFGDRV.SYS /BAUD=rate /PORT=COMn /UNIT=u /AUTO
This device driver runs under any DOS-compatible operating system, and creates a drive letter on
your host PC (usually D: if your last hard drive is C:) that can be used to interact with the specified
INT 13h unit.
The u parameter specifies the BIOS unit number of the floppy disk, RAM disk, RFD drive, or
ROM disk to be redirected, where 0 corresponds to drive A: and 1 for drive B. By default, this
value is 80 (a hex number without a “0x” in front or ‘h’ appended to it), which corresponds with the
unit for the first hard drive or emulator.
The /BAUD=rate parameter can be used to match the baud rate used by the TARGET’s BIOS.
Legal values are 19K, 28K, 38K, 56K, and 115K. If this parameter is not specified, then the baud
rate is autodetected.
The /AUTO parameter, if specified, tells MFGDRV.SYS to automatically format the remote drive if it
determines that it is unformatted. By default, MFGDRV.SYS will not automatically format the
remote drive, and will instead examine the media for a pre-existing format. If not found, then
MFGDRV.SYS asks the host PC operator if the remote drive should be formatted.
Once the connection is established, you can read and write the TARGET’s drive as if it were simply
another drive on your host system. The only difference is that it will be a bit slower over the serial
connection.
Note:
MFGDRV.SYS assumes that other software does not reprogram the COM port being used on the host
for its purposes, and that it has exclusive access to it. If you run other software, such as terminal
53
emulation programs, they may disable the COM port UART, causing MFGDRV.SYS to appear to
stop working. It is best to avoid running such software on the host when MFGDRV.SYS is loaded.
Note:
HOST.EXE is an example of such a program, since it takes over the UART for its own purposes. If
you run HOST.EXE when MFGDRV.SYS is loaded, you must reboot the host PC for the
MFGDRV.SYS driver to reestablish its control over the UART.
A full discussion of the uses of Manufacturing Mode is beyond the scope of this manual. Complete
documentation and host-side software are available directly from General Software. For more
information, visit the General Software web site at www.gensw.com.
5.4
Console Redirection
The TARGET can operate either with a standard PC/AT or PS/2 keyboard and VGA video monitor,
or with a special emulation of a console over an RS232 cable connected to a host computer running
a terminal program. To see an example session with HYPERTERMINAL, see the debugger
section’s screen display.
To use the Console Redirection feature, remove the video display card from the system so that no
video ROM is available for the BIOS to detect. In the absence of any video support, the BIOS
automatically switches its keyboard and screen functions to serial I/O over COM1 on the board.
The hardware connection to the host computer requires a null modem cable.
The software on the TARGET can be any terminal emulation program that supports ANSI terminal
mode, using 9600 baud, no parity, and one stop bit (Note: This can be modified by the OEM during
BIOS adaptation.) The program must be set to not use flow control, or the console may seem to
stall or not accept input.
Caution:
5.5
Hyperterminal’s default setting is to use flow control, which will render the console inoperative. To
change this, create a new session, change the flow control setting to “none,” save the session, and
exit Hyperterminal. Then reinvoke Hyperterminal with the session and it will operate with the new
flow control setting.
CE-Ready—Windows CE Loader
Your TARGET’s BIOS is CE-Ready and can directly boot Windows CE without loading an
intermediate operating system such as DOS and LOADCEPC. Instead, the NK.BIN file can be
placed on a disk drive or drive emulator, and then the BIOS can be configured through the Basic
CMOS Configuration Setup Screen to boot the NK.BIN file from the boot drives instead of the
boot records on those drives.
To configure your system to boot Windows CE natively from a disk drive, set the Boot Method
field to “Windows CE” in the Basic CMOS Configuration Setup Screen. Then, place a copy of
NK.BIN suitable for execution by LOADCEPC in the root directory of your normal boot drive,
such as drive C:. Then, reboot the system. The configuration box should be displayed (Figure 15)
followed by the message “Loading Windows CE…” This indicates that the loading process is
continuing. Once fully loaded, Windows CE takes over the system and runs using the standard PC
keyboard, screen, and PS/2 mouse.
54
Figure 15. The CE-Ready Feature
5.6
Integrated BIOS Debugger
The TARGET’s BIOS contains a built-in debugger that can be a valuable tool to aid the board
bring-up process on new designs similar to the reference board. It supports a DOS SYMDEB-style
command line interface, and can be used on the main console’s keyboard and screen, or over a
redirected connection to a terminal program (see Section 5.4, above).
To activate the debugger at any time from the main console, press the left shift and the control keys
together. A display similar to the one in the Hyperterminal session below (Figure 16) will appear,
containing the title, “Embedded BIOS Debugger Breakpoint Trap” and a snapshot of the CPU
general registers.
55
Figure 16. Integrated BIOS Debugger
To leave the debugger and resume the interrupted activity (whether POST, BIOS, DOS, Windows,
or an application program), enter the “G” command (short for “go”) and press ENTER. If you were
at a DOS prompt when you entered the debugger, then DOS will still be waiting for its command,
and will not prompt again until you press ENTER again.
The debugger can also be entered from the Setup Screen System, and as a boot activity (see Basic
CMOS Setup Screen), as a last ditch effort during board bring-up and development if no bootable
device is available.
If your version of DOS, an application, or any OEM-supplied BIOS extensions have debugging
code (i.e., “INT 3” instructions) remaining, then these will invoke the debugger automatically,
although this is not an error. To continue, use the “G” command. When Embedded BIOS is adapted
by the OEM, the debugger can be removed from the final production BIOS, and superfluous
debugging code in the application will not cause the debugger to be invoked.
A complete discussion of the debugger is beyond the scope of this chapter; however, complete
documentation is available from General Software.
5.7
Troubleshooting POST
This section provides a reference for debug aids useful in diagnosing booting.
56
5.7.1
Embedded BIOS POST Codes
To provide information to OEM developers about system faults, Embedded BIOS writes progress
codes, also known as POST codes, to I/O port 80h during POST. These POST codes may be
monitored by a port 80h card in either an ISA slot or PCI slot; they are not displayed on the screen.
For more information about POST codes, contact General Software. Please note that the Embedded
BIOS adaptation may be configured to reroute these codes over another I/O port or device.
Mnemonic Code
Code
System Progress Report
POST_STATUS_START
00h
Start POST (BIOS is executing)
POST_STATUS_CPUTEST
01h
Start CPU register test
POST_STATUS_DELAY
02h
Start power-on delay
POST_STATUS_DELAYDONE
03h
Power-on delay finished
POST_STATUS_KBDBATRDY
04h
Keyboard BAT finished
POST_STATUS_DISABSHADOW
05h
Disable shadowing & cache
POST_STATUS_CALCCKSUM
06h
Compute ROM CRC, wait for KBC
POST_STATUS_CKSUMGOOD
07h
CRC okay, KBC ready
POST_STATUS_BATVRFY
08h
Verifying BAT command to KB
POST_STATUS_KBDCMD
09h
Start KBC command
POST_STATUS_KBDDATA
0ah
Start KBC data
POST_STATUS_BLKUNBLK
0bh
Start pin 23,24 blocking & unblocking
POST_STATUS_KBDNOP
0ch
Start KBC NOP command
POST_STATUS_SHUTTEST
0dh
Test CMOS RAM shutdown register
POST_STATUS_CMOSDIAG
0eh
Check CMOS checksum
POST_STATUS_CMOSINIT
0fh
Initialize CMOS contents
POST_STATUS_CMOSSTATUS
10h
Initialize CMOS status for date/time
POST_STATUS_DISABDMAINT
11h
Disable DMA, PICs
POST_STATUS_DISABPORTB
12h
Disable Port B, video display
POST_STATUS_BOARD
13h
Initialize board, start memory detection
POST_STATUS_TESTTIMER
14h
Start timer tests
POST_STATUS_TESTTIMER2
15h
Test 8254 T2, for speaker, port B
16h
Test 8254 T1, for refresh
17h
Test 8254 T0, for 18.2Hz
POST_STATUS_MEMREFRESH
18h
Start memory refresh
POST_STATUS_TESTREFRESH
19h
Test memory refresh
POST_STATUS_TEST15US
1ah
Test 15usec refresh ON/OFF time
POST_STATUS_TEST64KB
1bh
Test base 64 Kbytes memory
POST_STATUS_TESTDATA
1ch
Test data lines
POST_STATUS_TESTADDR
20h
Test address lines
POST_STATUS_TESTPARITY
21h
Test parity (toggling)
POST_STATUS_TESTMEMRDWR
22h
Test Base 64 Kbytes memory
57
58
Mnemonic Code
Code
POST_STATUS_SYSINIT
23h
Prepare system for IVT initialization
POST_STATUS_INITVECTORS
24h
Initialize vector table
POST_STATUS_8042TURBO
25h
Read 8042 for turbo switch setting
POST_STATUS_POSTTURBO
26h
Initialize turbo data
POST_STATUS_POSTVECTORS
27h
Modification of IVT
POST_STATUS_MONOMODE
28h
Video in monochrome mode verified
POST_STATUS_COLORMODE
29h
Video in color mode verified
POST_STATUS_TOGGLEPARITY
2ah
Toggle parity before video ROM test
POST_STATUS_INITBEFOREVIDEO
2bh
Initialize before video ROM check
POST_STATUS_VIDEOROM
2ch
Passing control to video ROM
POST_STATUS_POSTVIDEO
2dh
Control returned from video ROM
POST_STATUS_CHECKEGAVGA
2eh
Check for EGA/VGA adapter
POST_STATUS_TESTVIDEOMEMORY
2fh
No EGA/VGA found, test video memory
POST_STATUS_RETRACE
30h
Scan for video retrace signal
POST_STATUS_ALTDISPLAY
31h
Primary retrace failed
POST_STATUS_ALTRETRACE
32h
Alternate found
POST_STATUS_VRFYSWADAPTER
33h
Verify video switches
POST_STATUS_SETDISPMODE
34h
Establish display mode
POST_STATUS_CHECKSEG40A
35h
Initialize ROM BIOS data area
POST_STATUS_SETCURSOR
36h
Set cursor for power-on msg
POST_STATUS_PWRONDISPLAY
37h
Display power-on message
POST_STATUS_SAVECURSOR
38h
Save cursor position
POST_STATUS_BIOSIDENT
39h
Display BIOS identification string
POST_STATUS_HITDEL
3ah
Display “Hit <DEL> to ...” message
POST_STATUS_VIRTUAL
40h
Prepare protected mode test
POST_STATUS_DESCR
41h
Prepare descriptor tables
POST_STATUS_ENTERVM
42h
Enter virtual mode for memory test
POST_STATUS_ENABINT
43h
Enable interrupts for diagnostics mode
POST_STATUS_CHECKWRAP1
44h
Initialize data for memory wrap test
POST_STATUS_CHECKWRAP2
45h
Test for wrap, find total memory size
POST_STATUS_HIGHPATTERNS
46h
Write extended memory test patterns
POST_STATUS_LOWPATTERNS
47h
Write conventional memory test patterns
POST_STATUS_FINDLOWMEM
48h
Find low memory size from patterns
POST_STATUS_FINDHIMEM
49h
Find high memory size from patterns
POST_STATUS_CHECKSEG40B
4ah
Verify ROM BIOS data area again
POST_STATUS_CHECKDEL
4bh
Check for <DEL> pressed
POST_STATUS_CLREXTMEM
4ch
Clear extended memory for soft reset
POST_STATUS_SAVEMEMSIZE
4dh
Save memory size
POST_STATUS_COLD64TEST
4eh
Cold boot: Display 1st 64 Kbytes memtest
Mnemonic Code
Code
POST_STATUS_COLDLOWTEST
4fh
Cold boot: Test all of low memory
POST_STATUS_ADJUSTLOW
50h
Adjust memory size for EBDA usage
POST_STATUS_COLDHITEST
51h
Cold boot: Test high memory
POST_STATUS_REALMODETEST
52h
Prepare for shutdown to real mode
POST_STATUS_ENTERREAL
53h
Return to real mode
POST_STATUS_SHUTDOWN
54h
Shutdown successful
POST_STATUS_DISABA20
55h
Disable A20 line
POST_STATUS_CHECKSEG40C
56h
Check ROM BIOS data area again
POST_STATUS_CHECKSEG40D
57h
Check ROM BIOS data area again
POST_STATUS_CLRHITDEL
58h
Clear “Hit <DEL>“ message
POST_STATUS_TESTDMAPAGE
59h
Test DMA page register file
POST_STATUS_VRFYDISPMEM
60h
Verify from display memory
POST_STATUS_TESTDMA0BASE
61h
Test DMA0 base register
POST_STATUS_TESTDMA1BASE
62h
Test DMA1 base register
POST_STATUS_CHECKSEG40E
63h
Checking ROM BIOS data area again
POST_STATUS_CHECKSEG40F
64h
Checking ROM BIOS data area again
POST_STATUS_PROGDMA
65h
Program DMA controllers
POST_STATUS_INITINTCTRL
66h
Initialize PICs
POST_STATUS_STARTKBDTEST
67h
Start keyboard test
POST_STATUS_KBDRESET
80h
Issue KB reset command
POST_STATUS_CHECKSTUCKKEYS
81h
Check for stuck keys
POST_STATUS_INITCIRCBUFFER
82h
Initialize circular buffer
POST_STATUS_CHECKLOCKEDKEYS
83h
Check for locked keys
POST_STATUS_MEMSIZEMISMATCH
84h
Check for memory size mismatch
POST_STATUS_PASSWORD
85h
Check for password or bypass setup
POST_STATUS_BEFORESETUP
86h
Password accepted
POST_STATUS_CALLSETUP
87h
Entering setup system
POST_STATUS_POSTSETUP
88h
Setup system exited
POST_STATUS_DISPPWRON
89h
Display power-on screen message
POST_STATUS_DISPWAIT
8ah
Display “Wait...” message
POST_STATUS_ENABSHADOW
8bh
Shadow system & video BIOS
POST_STATUS_STDCMOSSETUP
8ch
Load standard setup values from CMOS
POST_STATUS_MOUSE
8dh
Test and initialize mouse
POST_STATUS_FLOPPY
8eh
Test floppy disks
POST_STATUS_CONFIGFLOPPY
8fh
Configure floppy drives
POST_STATUS_IDE
90h
Test hard disks
POST_STATUS_CONFIGIDE
91h
Configure IDE drives
POST_STATUS_CHECKSEG40G
92h
Checking ROM BIOS data area
POST_STATUS_CHECKSEG40H
93h
Checking ROM BIOS data area
59
5.8
Mnemonic Code
Code
POST_STATUS_SETMEMSIZE
94h
Set base & extended memory sizes
POST_STATUS_SIZEADJUST
95h
Adjust low memory size for EBDA
POST_STATUS_INITC8000
96h
Initialize before calling C800h ROM
POST_STATUS_CALLC8000
97h
Call ROM BIOS extension at C800h
POST_STATUS_POSTC8000
98h
ROM C800h extension returned
POST_STATUS_TIMERPRNBASE
99h
Configure timer/printer data
POST_STATUS_SERIALBASE
9ah
Configure serial port base addresses
POST_STATUS_INITBEFORENPX
9bh
Prepare to initialize coprocessor
POST_STATUS_INITNPX
9ch
Initialize numeric coprocessor
POST_STATUS_POSTNPX
9dh
Numeric coprocessor initialized
POST_STATUS_CHECKLOCKS
9eh
Check KB settings
POST_STATUS_ISSUEKBDID
9fh
Issue keyboard ID command
POST_STATUS_RESETID
0a0h
KB ID flag reset
POST_STATUS_TESTCACHE
0a1h
Test cache memory
POST_STATUS_DISPSOFTERR
0a2h
Display soft errors
POST_STATUS_TYPEMATIC
0a3h
Set keyboard typematic rate
POST_STATUS_MEMWAIT
0a4h
Program memory wait states
POST_STATUS_CLRSCR
0a5h
Clear screen
POST_STATUS_ENABPTYNMI
0a6h
Enable parity and NMIs
POST_STATUS_INITE000
0a7h
Initialize before calling ROM at E000h
POST_STATUS_CALLE000
0a8h
Call ROM BIOS extension at E000h
POST_STATUS_POSTE000
0a9h
ROM extension returned
POST_STATUS_DISPCONFIG
0b0h
Display system configuration box
POST_STATUS_INT19BOOT
00h
Call INT 19h bootstrap loader
POST_STATUS_LOWMEMEXH
0b1h
Test low memory exhaustively
POST_STATUS_EXTMEMEXH
0b2h
Test extended memory exhaustively
POST_STATUS_PCIENUM
0b3h
Enumerate PCI busses
Critical Error Beep Codes
Embedded BIOS tests much of the hardware early in POST before messages can be displayed on
the screen. When system failures are encountered at these early stages, POST uses beep codes (a
sequence of tones on the speaker) to identify the source of the error.
The following is a comprehensive list of POST beep codes for the system BIOS. BIOS extensions,
such as VGA ROMs and SCSI adapter ROMs, may use their own beep codes, including short/long
sequences, or possibly beep codes that sound like the ones below. When diagnosing a system
failure, remove these adapters if possible before making a final determination of the actual POST
test that failed.
60
Mnemonic Code
Beep Count
Description of Problem
POST_BEEP_REFRESH
1
Memory refresh is not working
POST_BEEP_PARITY
2
Parity error found in 1st 64KB of memory
POST_BEEP_BASE64KB
3
Memory test of 1st 64KB failed
POST_BEEP_TIMER
4
T1 timer test failed
POST_BEEP_CPU
5
CPU test failed
POST_BEEP_GATEA20
6
Gate A20 test failed
POST_BEEP_DMA
7
DMA page/base register test failed
POST_BEEP_VIDEO
8
Video controller test failed
POST_BEEP_KEYBOARD
9
Keyboard test failed
POST_BEEP_SHUTDOWN
10
CMOS shutdown register test failed
POST_BEEP_CACHE
11
External cache test failed
POST_BEEP_BOARD
12
General board initialization failed
POST_BEEP_LOWMEM
13
Exhaustive low memory test failed
POST_BEEP_EXTMEM
14
Exhaustive extended memory test failed
POST_BEEP_CMOS
15
CMOS restart byte test failed
POST_BEEP_ADDRESS_LINE
16
Address line test failed
POST_BEEP_DATA_LINE
17
Data line test failed
POST_BEEP_INTERRUPT
18
Interrupt controller test failed
POST_BEEP_PASSWORD
1
Incorrect password used to access SETUP
61
Bill of Materials
A
Table 13. Bill of Materials (Sheet 1 of 7)
Reference Description
R45-46,R49,R108-110,
R122,R302
Description
Quantity
Manufacturer
Manufacturer
Part Number
Resistor, 100, 1%, 1/16W, 100PPM,
0603
8
DALE/VISHAY
CRCW0603-1000FRT1
Resistor, 1K, 1%, 1/16W, 100PPM,
0603
36
DALE/VISHAY
CRCW0603-1001FRT1
R4,R6,R8,R13,R5761,
R72,R77,R87,R8993,
R116,R128,R137,R139,
R158,R173,R184185,
R188189,R192,
R195-196,R200,202,
R212,R215,R220,
R232,R261-262,
R268,R277,R284,R292,
R296,R299,R500503,
R506,R514-517
Resistor, 10K, 1%, 1/16W, 100PPM,
0603
54
DALE/VISHAY
CRCW0603-1002FRT1
R95,R115,R127,R33
Resistor, 100K, 1%, 1/16W, 100PPM,
0603
4
DALE/VISHAY
CRCW0603-1003FRT1
R102,R117,R126,R129
Resistor, 1.21K, 1%, 1/16W, 100PPM,
0603
4
DALE/VISHAY
CRCW0603-1211FRT1
R187,R191,R308-309
Resistor, 150, 1%, 1/16W, 100PPM,
0603
4
DALE/VISHAY
CRCW0603-1500FRT1
Resistor, 1.5K, 1%, 1/16W, 100PPM,
0603
12
DALE/VISHAY
CRCW0603-1501FRT1
R156-157,R162,R164
Resistor, 15K, 1%, 1/16W, 100PPM,
0603
4
DALE/VISHAY
CRCW0603-1502FRT1
R149,R167,R170
Resistor, 2K, 1%, 1/16W, 100PPM,
0603
3
DALE/VISHAY
CRCW0603-2001FRT2
R37,R50,R94,R505
Resistor, 221, 1%, 1/16W, 100PPM,
0603
4
DALE/VISHAY
CRCW0603-2210FRT1
R5,R7,R10,R301
Resistor, 2.21K, 1%, 1/16W, 100PPM,
0603
4
DALE/VISHAY
CRCW0603-2211FRT1
R15,R43,R81
Resistor, 22.1K, 1%, 1/16W, 100PPM,
0603
3
DALE/VISHAY
CRCW0603-2212FRT1
Resistor, 232K, 1%, 1/16W, 100PPM,
0603
8
DALE/VISHAY
CRCW0603-2323FRT1
Resistor, 243, 1%, 1/16W, 100PPM,
0603
3
DALE/VISHAY
CRCW0603-2430FRT1
R3,R9,R11-12,R20,
R22-23,R7476,R7980,
R85,R97-99,R105,
R113,R124,R144,
R166,R168,R186,R194,
R198,R204,R259-260,
R263-266,R294,R298,
R303,R504
R106,R111,R118-120,
R125,R134-136,R146,
R148,R199
R16,R19,R21,R24,R44,
R96,R509-510
R175-176,R213
63
Bill of Materials
Manufacturer
Manufacturer
Part Number
Description
Quantity
Resistor, 2.74K, 1%, 1/16W, 100PPM,
0603
21
DALE/VISHAY
CRCW0603-2741FRT1
Resistor, 332, 1%, 1/16W, 100PPM,
0603
19
DALE/VISHAY
CRCW0603-3320FRT1
R112
Resistor, 3.92K, 1%, 1/16W, 100PPM,
0603
1
DALE/VISHAY
CRCW0603-3921FRT2
R18,R3334,R3841,R86,
R171,R174,R197,
R207-211,R214,
R216-219,R248,R267
Resistor, 4.75K, 1%, 1/16W, 100PPM,
0603
23
DALE/VISHAY
CRCW0603-4751FRT1
R31
Resistor, 47.5K, 1%, 1/16W, 100PPM,
0603
1
DALE/VISHAY
CRCW0603-4752FRT2
R36,R42
Resistor, 475K, 1%, 1/16W, 100PPM,
0603
2
DALE/VISHAY
CRCW0603-4753FRT1
R30,R314
Resistor, 549, 1%, 1/16W, 100PPM,
0603
2
DALE/VISHAY
CRCW0603-5490FRT1
R238,R293
Resistor, 5.62K, 1%, 1/16W, 100PPM,
0603
2
DALE/VISHAY
CRCW0603-5621FRT1
R35,R54
Resistor, 562K, 1%, 1/16W, 100PPM,
0603
2
DALE/VISHAY
CRCW0603-5623FRT1
R28,R103
Resistor, 619, 1%, 1/16W, 100PPM,
0603
2
DALE/VISHAY
CRCW0603-6190FRT1
R29
Resistor, 66.5K, 1%, 1/16W, 100PPM,
0603
1
DALE/VISHAY
CRCW0603-6652FRT1
R32,R88,R131133,
R138,R141-143,
R153,R161,R511-512
Resistor, 8.25K, 1%, 1/16W, 100PPM,
0603
13
DALE/VISHAY
CRCW0603-8251FRT1
R121,R123
Resistor, 10, 1%, 1/16W, 200PPM,
0603
2
DALE/VISHAY
CRCW0603-10R0FRT1
Resistor, 22.1, 1%, 1/16W, 200PPM,
0603
13
DALE/VISHAY
CRCW0603-22R1FRT1
Resistor, 27.4, 1%, 1/16W, 200PPM,
0603
4
DALE/VISHAY
CRCW0603-27R4FRT1
Resistor, 33.2, 1%, 1/16W, 200PPM,
0603
29
DALE/VISHAY
CRCW0603-33R2FRT1
R190,R193
Resistor, 47.5, 1%, 1/16W, 200PPM,
0603
2
DALE/VISHAY
CRCW0603-47R5FRT1
R101,R172,R205
Resistor, 56.2, 1%, 1/16W, 200PPM,
0603
3
DALE/VISHAY
CRCW0603-56R2FRT2
Resistor, ZERO ohm, .05 ohm MAX,
0603
16
DALE/VISHAY
CRCW0603-000RT1
R25-26,R47-48,R51-52,
R55-56,R82-84,R107,
R114,R130,R145,
R178-183
R53,R104,R305,R310,
R312-313,R315322,
R324,R325,R327-329
R203,R269,R279-282,
R285-291
R159-160,R163,R165
R140,R154,R222-230,
R234-237,R239-242,
R249-257,R297
R17,R67-71,R206,
R270-276,R278,R513
64
Bill of Materials
Description
Quantity
Manufacturer
Manufacturer
Part Number
R169
Resistor, 1M, 1%, 1/8W, 100PPM,
1206
1
DALE/VISHAY
CRCW1206-1004FRT2
R100
Resistor, 10, 1%, 1/8W, 100PPM,
1206
1
DALE/VISHAY
CRCW1206-10R0FRT1
R306-307
Resistor, 75, 1%, 1/8W, 100PPM,
1206
2
DALE/VISHAY
CRCW1206-75R0FRT1
R150-151,R507-508
Resistor, 2.7ohm, 5%, 1/8W,
400PPM, 1206
4
DALE/VISHAY
CRCW1206-2R7JRT2
R177
Resistor, .005, 1%, 2W, 20PPM, smt
1
IRC
OARS1R005FTR
No loads
21
C1,C5-8,C13-16,
C35-37,C44-45,C51,
C99,C112,C115,C157,
C192,C204
Capacitor, mon cer, 1uF, +80-20, 25V,
1206
21
AVX
12063G105ZAT2A
C73,C300,C308,C311
Capacitor, mon cer, 10PF, 10%, 50V,
0603
4
AVX
06035A100KAT2A
Capacitor, mon cer, 100P, 5%, 50V,
0603
23
AVX
06035A101JAT2A
0603
6
AVX
06035A220JAT2A
0603
6
AVX
06035A470JAT2A
0603
9
AVX
06035A471JAT2A
0603
9
AVX
06035C102KAT2A
Capacitor, mon cer, 0.01uF, 20%,
50V, 0603
43
AVX
06035C103K(M)AT2A
R6266,R78,R147,R152,
R155,R231,R233,
R243-R247,R258,R283,
R295,R300,R326
C18-33,C38,C40-41,
C53-55,C167
C63-64,C107-108,
C240-241
C174-175,C219-220,
C224,C231
C34,C50,C57-60,C294,
C297,C304
C74,C86,C156,C163,
C165,C299,C301-302,
C305
C39,C52,C79,C83-85,
C90-92,C101-103,
C136-144,C177-178,
C181-182,C226,C228230,C244,C255-257,
C261-262,C266,
C317-323
65
Bill of Materials
Manufacturer
Manufacturer
Part Number
Description
Quantity
Capacitor, mon cer, 0.1uF, 20%, 16V,
0603
168
AVX
0603YC104K(M)AT2A
C164
Capacitor, mon cer, 1500p, 10%, 50V,
0603
1
AVX
06035C152KAT2A
C3,C10,C147
Capacitor, mon cer, 2200PF, 10%,
50V, 0603
3
AVX
06035C222KAT2A
Capacitor, alum, 1200uF, 20%, 25V,
.197 radial
7
PANASONIC
EEUFC1E122
SANYO
25MV1200AX or -GX
C56,C67
.197 radial
2
PANASONIC
EEUFC1E221B
C104,C111
.138 radial
2
PANASONIC
EEUFC1V151
C66,C109-110,C151,
C155,C186-187,C216,
C242-243,C252-253,
C267,C272,C278,C290,
C293,C309,C312
Capacitor, tant, 4.7UF, 20%, 10V,
3528
19
KEMET
T491B475K010AS
C81-82,C303,C500
Capacitor, tant, 22U, 20%, 16V, 7343
4
KEMET
T491D226K025AS-TR
C258
Capacitor, tant, 33U, 20%, 16V, 7343
1
KEMET
T491D336M016ASTAPE
FB1-23
Inductor, ferrite bead, 3A,
30ohm@100MHz, 0805
23
MURATA
ELECTR
BLM21P300SPT
L2
Inductor, 1.68uH, 13.9A, smt
1
PULSE
PE-53691T
L1
Inductor, 4.7uH, 10%, 30mA,
DCR=1ohm, 0805
1
MURATA
ELECTR
LQG21N4R7K10T1
D2-3
Diode, signal, 30V, 500mA, SOT23
2
GENERAL
SEMICON
BAT54C
C2,C4,C9,C11-12,C17,
C46-49,C61-62,C65,
C68-72,C75-78,C80,
C87-89,C93-97,C100,
C105-106,C113-114,
C116-135,C145-146,
C148-150,C152-154,
C158-161,C166,C169173,C176,C179-180,
C183-185,
C188-191,C193-195,
C197-199,C201-203,
C205-215,C217218,
C221,C225,C227,
C232-239,C245-251,
C259-260,C263-265,
C268-271,C273-277,
C279-289,C291-292,
C295-296,C298,
C306-307,C310,
C313-316,C324-325,
C501-505
C162,C168,C196,C200,
C222-223,C254
PHILIPS
66
BAT54C
Bill of Materials
Description
Quantity
DS1
Diode, rectifier, 3A, 40V, smt
1
D1
Diode, signal, 150mA, 75V, SOT23
1
Y3
Crystal, 32.768KHz tuning fork, thruhole
1
Y4
Crystal, 14.318 MHz, .005%, smt
1
Y1
Crystal, 24.567MHz, 50PPM,
Y2
U9
Manufacturer
Manufacturer
Part Number
ON SEMI
MBRS340T3
VISHAY
MMBD4148-7
FAIRCHILD
MMBD4148
FOX
NC-38,32.768KHz
M-TRON
MMCC-1
FOX
FPX-143-14.318MHz T/
R
M-TRON
SX2050P-14.31818MHz
T/R
1
FOX
FE245F-20
Crystal, smt, 25.000MHz, .005%
1
EPSON
MA-406-25.000M-G
IC, Digital temp monitor, SSOP16
1
TI
THMC10DBQR
U2-3
IC, Digital RS232 Driver, SO20
2
TI
SN75C185DWR
U7
IC, Digital LVC Hex Inverter, SO14
1
TI
SN74LVC06AD
U8
IC, Digital LVC Hex Inverter Schmitttrigger, SO14
1
TI
SN74LVC14ADR
U50
IC, Digital HC Nand Gate, SO14
1
TI
SN74HC00ADR
U4
IC, Audio amplifier, stereo, 2W/ch,
SOL14
1
NATIONAL
SEMI
LM1877M-9
VR1
IC, Voltage Regulator, 3.3V@250mA,
SOT223
1
SEMTECH
EZ5Z3L-S3.3 TR
U6
IC, EEPROM, 64X16, I2C, SO8
1
ATMEL
AT93C46-10SC-1.8
T&R
CATALYST
CAT93C46BS-TE13
U13
IC, 440MX chipset, 100MHz, BGA492
1
INTEL
FW82443MX100
U5
IC, 10/100 Ethernet controller, PCI,
BGA196
1
INTEL
GD82559
U14
IC, Super I/O, PC98/99, 5V, PQFP100
1
SMC
FDC37M812 QFP
U15
IC, System clock generator, SSOP56
1
ICS
ICS9250BF-19
U12
IC, Power FET drivers, TSSOP14
1
ANALOG
DEVICES
ADP3410KRU
U10
IC, Switching power regulator,
TSSOP28
1
ANALOG
DEVICES
ADP3421JRU
Q8-9
Transistor, FET, 30V, 12.5A,
9mohm@10v, SO8
2
SILICONIX/
VISHAY
SI4420DY
Q3-4
Transistor, FET, 60V, 115mA, SOT23
2
ON SEMI
2N7002LT1
Q7
Transistor, npn, 200V, 320mA,
SOT223
1
ZETEX
ZVNL120GTA
Q1-2,Q12
Transistor, npn, 40V, 200mA, SOT23
3
ON SEMI
MMBT3904LT1
Q6
Transistor, pnp, 60V, 600mA, SOT23
1
ON SEMI
MMBT2907ALT1
Q5
Transistor, pnp, 80V, 8A, DPAK
1
ON SEMI
MJD45H11T4
S1
Audio speaker, 5v, 2.7KHz, thru-hole
1
GOLDEN
PACIFIC
GB-0905EP-1
67
Bill of Materials
D6-7
LED, green, 7-seg display, 10pin
Quantity
2
Manufacturer
AGILENT
Manufacturer
Part Number
HDSP-7801
D4
LED, green, 1206-smt
1
STANLEY
BG1101W-TR
D8
LED, yellow, 1206-smt
1
STANLEY
AY1101W-TR
F3
Fuse, resettable, 1.5A, 15V, smt
1
RAYCHEM
SMD150-2
F1-2,F4
Fuse, resettable, 1.1A, 30V, smt
3
RAYCHEM
SMD100-2
KYCON
GSP-B-S2-GG-9100
AMPHENOL
RJMG-7326-71-01
BEL FUSE
0812-1X1T-03
J7
68
Description
Connector, Stacked RJ45 and Dual
USB, with
10/100Base-T magnetics, and status
LEDs
1
U1
IC, Audio codec, ’AC97, LQFP48
1
SIGMATEL
STAC9721T
J18
Connector, CompactFlash Type-II
socket, r/a
1
3M
N7E50-7516HG-40
J9-11
Connector, PCI Edge Socket, 5V/32bit
3
AMP
145154-8
J12
Connector, ITP Debug Header, 30pin
1
AMP
104068-3
J8
Connector, CD-ROM Audio Header,
4pin
1
JST
B 4B-PH-K
J4
Connector, PS/2 Dual Stack, 6pin
mini-din
1
KYCON
KMDG-6S/6S-S4N
P1
Connector, CPU Fan, 3P w/ friction
lock
1
AMP
640456-3
MOLEX
22-23-2031
J1-3
Connector, 3.5mm Stereo Jack, r/a
3
RDI
SJ510C
J19
Connector, 10x2 r/a header, 0.1"
spacing
1
MOLEX
10-88-3201
J16
Connector, Floppy Header, 34pin,
shrouded
1
AMP
103308-7
J17
Connector, IDE Header, 40pin,
shrouded
1
AMP
103308-8
J5-6
Connector, Serial 9pin Sub-D Plug, r/
a
2
AMP
788754-2
J13
Connector, ATX Power, 20pin,
straight, shrouded
1
MOLEX
39-29-9202
E1-26
Machine-applied pin
26
AMP
87623-4
U16
Socket, TSOP40, smt, w/ cover
1
YAMAICHI
IC197-4004-2000
J14-15
Socket, DIMM, 168pin, 3.3v nonbuffered
2
AMP
390074-6
U11
Socket, uPGA-2, ZIF, 495pin
1
FOXCONN
PZ49505-2141-02
BS1
Battery Socket, 2032-type coin, w/
eject tab
1
MEMORY
PROT DEV
BA2032
U17-18
IC, PLD, PAL22V10, PLCC28 (needs
programmed)
2
LATTICE
PALCE22V10H-15JC/4
XU16
IC, flash, 512kx8, 80ns, TSOP40
(needs prog’d)
1
MICRON
MT28F004B5VG-6T
Schematics
B
Schematics are provided for the following items listed below. Schematics are available from the
Intel Developer’s Web site in PDF format.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Block diagram
Routing guidelines
Processor Part 1 and 2
ITP socket
440MX part 1 and 2
DIMM sockets
Super I/O, BIOS and post code display
IDE, Compact Flash and floppy connectors
Serial, keyboard, mouse, USB connectors
Power and front panel connectors
82559 Ethernet
AC’97 CODEC and sound I/O
PCI 1 and 2
PCI 3
Voltage regulators
Pullup/Pulldown resistors
69
D
C
B
A
PAGE
14
15
16
17
18
19
AC97 CODEC AND SOUND I/O
PCI CONNECTORS 1 AND 2
PCI CONNECTOR 3
VOLTAGE REGULATORS
PULLUP/PULLDOWN RESISTORS
6
5
4
THE MISUSE OF THIS INFORMATION.
3
2
END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR
HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN
THIS DRAWING CONTAINS INFORMATION THAT
NOTE: ALL RESISTORS +/- 1%, ALL CAPACITORS +/- 20% UNLESS OTHERWISE NOTED
THIS SCHEMATIC IS PROVIDED "AS-IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,
FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted
herein. Intel disclaims all liability, including liability for infringement of any proprietary rights,
relating to use of information in this specification. Intel does not warrant or represent that such use will
not infringe such rights.
13
9
DIMM SOCKETS
82559 ETHERNET
8
SYSTEM CLOCK & STRAPPING OPTIONS
12
7
440MX 2 OF 2
POWER AND FRONT PANEL CONNECTORS
6
440MX 1 OF 2
11
5
PROCESSOR 2 OF 2
SERIAL, KEYBOARD, MOUSE, USB CONNECTORS
4
PROCESSOR 1 OF 2 AND ITP SOCKET
IDE, COMPACTFLASH, AND FLOPPY CONNECTORS
3
ROUTING GUIDELINES
10
2
BLOCK DIAGRAM
SUPER I/O, BIOS, AND POST CODE DISPLAY
1
TABLE OF CONTENTS
TITLE
2
B
1
1
440MX SCALABLE LOW POWER BOARD
DRAWING
TABLE OF CONTENTS
Intel Corporation
5000 W. Chandler Blvd.
Chandler, AZ 85226
05/30/01
DATE
TITLE
B 09-20-01 Changes to the following:
Changed TEST# pullup on MX to 3VSB
Super I/O: added circuitry to generate AEN during DMA cycles (needed on SMSC SIO)
A 08-06-01 Initial Revision A Schematics
3
TABLE OF CONTENTS
4
REVISION HISTORY
5
INTEL(R) 440MX SCALABLE LOW POWER BOARD
6
SHEET
LAST
REV
1 OF 19
09/20/01
10:29 AM
B
D
C
B
A
D
C
B
A
6
BLOCK DIAGRAM
PCI Slot 2
Sheet 16
5
Sheet 14
RJ-45
Sheet 14
82559 Ethernet
PCI Slot 1
PCI
Sheet 16
PCI Slot 3
Sheet 17
Sheets 4,5
Low Power
Celeron(R)
Processor
Sheet 12
Sheet 10
3
2
Sheet 12
PS/2 Keyboard and Mouse
Sheet 13
IR Header
Sheet 11
Floppy
Sheet 15
Mic In
Sheet 15
Line In
Sheet 15
Spkr/HP Out
Sheet 11
CompactFlash
Sheet 11
IDE (40 pin)
Sheet 9
B
1
1
DRAWING
BLOCK DIAGRAM
Intel Corporation
Chandler, AZ 85226
05/30/01
DATE
TITLE
Sheet 18
Sheet 8
DIMM Sockets (2)
System Power
2
System Clock
Sheet 10
Sheet 10
Super I/O
Sheet 15
IDE
MEM
AC97 Sound
3
Serial RS232 (2)
Sheets 6,7
440MX100 Integrated
Chipset
512kB Flash
BIOS
4
Sheet 4
ITP Socket
4
POST Code
Display
5
GTL+
X-Bus
6
AC97 Link
SHEET
LAST
REV
2 OF 19
09/20/01
10:29 AM
B
D
C
B
A
D
C
B
A
5
GTL+ signals between the CPU and 440MX should be between 1.9” and 4.3” long.
Route GTL+ signals on layer adjacent to GND, and do not change layers.
Signals between the CPU and 440MX must not differ in length by more than 1”.
Spacing between adjacent signals should be as large as possible > 10 mils except for short distances for
fanout. Total distance for fanout allowance is 250 mil.
Route VREF_GTL signal as a minimum 25 mil trace, and keep 25 mil from other traces.
Route CPU_PLL[2:1] using 25 mil trace, minimize loop area, and keep 25 mil from other traces.
•
•
•
•
•
•
•
•
•
•
6
5
4
Series damping resistors must be less than 0.5” from clock IC.
Clock traces should be routed on inner layers, with layer transitions at an absolute minimum.
Spacing between clock trace and any other trace should be > 12 mils, serpentine spacing > 18 mils.
MX_HCLK must be between 3.25” and 5.85” long, and CPU_HCLK must be 877 mils +/- 1 mil
longer than MX_HCLK.
ITP_HCLK should be the same length as CPU_HCLK.
PCI clocks to the slots should be the same length, +/- 2”, but less than 12.5” long.
Onboard PCI device clocks same as above, but 2.5” longer than PCI clocks to slots.
MEM_CLKs to the DIMMs should be the same length, +/- 0.1”, and between 1.0” and 4” long.
CLK_DCLKOUT should be the same length as the MEM_CLKs, +/- 0.1”.
CLK_DCLKIN should be 2.5” longer than CLK_DCLKOUT, +/- 0.1”.
Clock Specific Routing Requirements
•
•
•
•
•
•
CPU Routing Requirements
•
Nominal trace impedance must be 65 ohms +/- 10%.
Vias for decoupling capacitors must be kept as close as possible to capacitor pad.
Finished board thickness is .062” +/- .007”.
Outer layers must be ½ oz copper before plating, inner layers must be 1 oz copper.
Series termination resistors must be kept as close to the driving pins as possible
Signals with multiple endpoints should be daisy-chained, signal should not split into branches.
GND plane must not be split
Bypass capacitors on signals going to I/O connectors should be located as close to the connector as
possible
Check specific schematic pages for additional routing information
3
2
B
1
DRAWING
ROUTING GUIDELINES
Intel Corporation
Chandler, AZ 85226
05/30/01
DATE
TITLE
SHEET
LAST
REV
3 OF 19
09/20/01
10:29 AM
B
PCI signals should be similar length, routed in a daisy-chain fashion together to each component, with
the 440MX as the last component.
Total length of PCI signals must be less than 25”.
•
•
PCI Bus Routing Requirements
•
•
Length of MEM Bus lines should be between 1” and 4”.
Spacing between other MEM Bus traces should be 10mil, spacing should be 5 mil for no more than
0.5”.
Spacing to non-MEM Bus traces should be atleast 20 mil.
MEM Bus traces should not transition between layers, except to get to the topside for the chipset.
Memory Bus Routing Requirements
•
•
1
Keep all unrelated signals and power planes away from switching regulator and related circuitry.
Power input and output traces should be routed with minimal length while maximizing width.
•
•
2
Switching Power Supply Routing Requirements
3
•
•
•
•
•
•
•
•
4
General Board Design Requirements
ROUTING GUIDELINES
6
D
C
B
A
D
C
B
6
4,6
8
4,6,19
6,19
6,19
6,19
19
6,19
13
6,19
6,19
19
6,19
6,19
6
6
6
6
6
6
6
6
6
6
6
19
6
6
6
6
6
GTL_HREQ#0
VREF_GTL
CPU_HCLK
GTL_CPURST#
CPU_INIT#
CPU_NMI
CPU_INTR
CPU_SLP#
CPU_STPCLK#
CPU_PWRGD
CPU_SMI#
CPU_IGNNE#
CPU_FLUSH#
CPU_FERR#
CPU_A20M#
GTL_HTRDY#
GTL_RS#2
GTL_RS#1
GTL_RS#0
GTL_DEFER#
GTL_HITM#
GTL_HIT#
GTL_HLOCK#
GTL_BNR#
GTL_BPRI#
GTL_BREQ0#
CPU_IERR#
GTL_ADS#
GTL_HREQ#4
GTL_HREQ#3
GTL_HREQ#2
GTL_HREQ#1
VIA30
SMT0603
6
VIA8
VIA18
VIA31
VIA33
VIA32
VIA29
VIA16
VIA20
VIA17
VIA19
GTL_HA#31
GTL_HA#30
GTL_HA#29
GTL_HA#28
GTL_HA#27
GTL_HA#26
GTL_HA#25
GTL_HA#24
GTL_HA#23
GTL_HA#22
GTL_HA#21
GTL_HA#20
GTL_HA#19
GTL_HA#18
GTL_HA#17
GTL_HA#16
GTL_HA#15
GTL_HA#14
GTL_HA#13
GTL_HA#12
GTL_HA#11
GTL_HA#10
GTL_HA#9
GTL_HA#8
L1
L4
M3
A6
AA10
AC19
AB18
AB12
AC11
V5
AB10
AC13
AC9
AC12
AD10
U2
Y1
W1
AA2
U1
U3
Y4
V1
R1
T4
U4
C6
AD9
V21
E6
Y2
AB1
AA1
AB2
W2
W5
W3
V2
V4
T2
C5
B4
A5
A4
C2
B2
A3
B3
C1
C3
D4
D5
E2
D1
D3
C4
E1
F2
F4
F1
E4
H1
G1
K4
J3
J1
K1
K5
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
D35#
D36#
D37#
D38#
REQ1#
REQ2#
REQ3#
REQ4#
D41#
ADS#
D44#
D45#
D46#
D47#
D48#
AP0#
AP1#
BERR#
BINIT#
IERR#
D51#
D52#
D53#
D54#
D55#
D56#
BPRI#
BNR#
LOCK#
HIT#
HITM#
DEFER#
D60#
D61#
D62#
RS2#
RSP#
TRDY#
DEP1#
DEP2#
DEP3#
DEP4#
FLUSH#
IGNNE#
SMI#
PWRGOOD#
NMI/LINT1
BCLK
RESET#
EDGECTRLP
BSEL1
BSEL0
THERMDC
THERMDA
DRDY#
INTR/LINT0
INIT#
DEP7#
DBSY#
SLP#
DEP6#
STPCLK#
DEP5#
DEP0#
FERR#
D63#
D59#
RS1#
A20M#
D58#
RS0#
D57#
D50#
BREQ0#
D49#
D43#
AERR#
D42#
D40#
RP#
D39#
D34#
REQ0#
D33#
D24#
D23#
A27#
A26#
D22#
D4#
A7#
Mobile PIII/Celeron
1 of 4
D3#
A6#
A25#
D2#
A5#
GTL_HD#6
GTL_HD#7
GTL_HD#8
GTL_HD#9
GTL_HD#10
GTL_HD#11
GTL_HD#12
GTL_HD#13
GTL_HD#14
GTL_HD#15
GTL_HD#16
GTL_HD#17
GTL_HD#18
GTL_HD#19
GTL_HD#20
GTL_HD#21
GTL_HD#22
GTL_HD#23
GTL_HD#24
GTL_HD#25
GTL_HD#26
GTL_HD#27
GTL_HD#28
GTL_HD#29
GTL_HD#30
GTL_HD#31
GTL_HD#32
GTL_HD#33
GTL_HD#34
GTL_HD#35
GTL_HD#36
GTL_HD#37
GTL_HD#38
GTL_HD#39
GTL_HD#40
GTL_HD#41
GTL_HD#42
GTL_HD#43
GTL_HD#44
GTL_HD#45
GTL_HD#46
GTL_HD#47
GTL_HD#48
GTL_HD#49
GTL_HD#50
GTL_HD#51
GTL_HD#52
GTL_HD#53
GTL_HD#54
GTL_HD#55
GTL_HD#56
GTL_HD#57
GTL_HD#58
GTL_HD#59
GTL_HD#60
GTL_HD#61
GTL_HD#62
GTL_HD#63
C10
B11
C12
B13
A14
B12
E12
B16
A13
D13
D15
D12
B14
E14
C13
A19
B17
A18
C17
D17
C18
B19
D18
B20
A20
B21
D19
C21
E18
C20
F19
D20
D21
H18
F18
J18
F21
E20
H19
E21
J20
H21
L18
G20
P18
G21
K18
K21
M18
L21
R19
K19
T20
J21
L20
M19
U18
R18
VIA4
VIA6
VIA3
VIA9
VIA1
VIA2
VIA5
T21
U21
R21
V18
P21
P20
U19
AA16
AB15
AA12
5
SMT0603
SMT0603
THERMDA
THERMDC
GTL_DBSY#
GTL_DRDY#
AB16
T1
AA15
AA3
R123
VIA7
V20
10
GTL_HD#5
A9
R122
GTL_HD#4
B9
100
GTL_HD#3
C8
4
4
6
6
6
VCC3
8
4
4
13
4,6,19
CPU_BSEL1
CPU_BSEL0
ITP_HCLK
ITP_TMS
ITP_TCK
ITP_RST#
8
8
Reserved
10
4
133 MHz (NOT Supported)
100 MHz
01
11
66 MHz
00
System Bus Freq
SMT0603
R190
SMT0603
R193
47R5
SMT0603
R175
47R5
243
BSEL[1:0]
GTL_CPURST#
VCC3
2. The ITP connector should be located near the processor
14
16
18
20
22
24
26
28
13
15
17
19
21
23
25
27
SMT0603
R213
VCC3
VCC3
SMT0603
SMBUS Address: 1001 110x
THERMDC
THERMDA
243
R205
VCC3
4
4
4
4
4
8
7
6
10
4
3
2
STBY#
11
14
12
15
3
0
SMT0603
R78
EMPTY
4.7UF
C242
SMB_CLK
SMT0805
2
L1
6,8,9,13,14,19
7,19
SMT0603
VIA10
VIA11
VIA12
VIA13
VCC1_5
VIA28
SMT0603
VCC1
VCC2
PICCLK
VCC5
VCC6
VCC7
BP3#
BPM0#
BPM1#
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
TDI
TDO
TMS
TRST#
PREQ#
PRDY#
VCC20
CMOSREF2
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VREF2
VREF3
VREF4
VREF5
VREF6
VREF7
VCC39
VCC40
TESTLO1
TESTLO2
VCC44
VCC45
TESTP3
TESTP4
PLL2
PLL1
VCC43
TESTP2
+12
B
CPU FAN
AB19
U15
U13
U11
U9
U7
T16
T14
T12
T10
T8
R15
R13
R11
R9
R7
P16
P14
P12
P10
P8
N15
N13
N11
N9
N7
M16
M14
M12
M10
M8
L15
L13
L11
L9
L7
K16
K14
K12
K10
K8
J15
J13
J11
J9
J7
H16
H14
H12
H10
H8
1
DRAWING
P1
2.54MM HEADER
3
2
1
Mobile PIII/Celeron
2 of 4
RSVD
VCC49
VCC48
VCC47
VCC46
VCC42
TESTP1
VCC41
VCC38
TESTHI
VCC37
VCC36
VCC28
VREF1
VCC27
VCC26
VCC25
VCC24
VCC23
VCC22
VREF0
GHI#
RTTIMPEDP
VCC19
CMOSREF1
VCC21
VCC18
CLKREF
VCC17
VCC16
VCC9
TCK
VCC8
VCC4
BP2#
VCC3
VCC0
PICD1
1
PICD0
VCC
M2
L2
G4
AA17
H4
AD20
N5
Y5
AD17
Y18
Y17
U5
F17
F5
E17
E16
E5
R2
AD19
AD18
AA9
P2
W20
AB20
AA14
AD14
AC15
AD13
AA11
W19
W21
Y21
AA21
AA18
Y20
AB21
U11
PROCESSOR 1 OF 2 AND ITP SOCKET
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
CPU_PLL2
C258
16v 33UF
CPU_PLL1
VIA26
VIA14
VIA27
VIA15
Place between CPU and MX
MLF2012A4R7
4.7UH
VCC1_5
ITP_PRDY#
ITP_PREQ#
ITP_TRST#
ITP_TMS
ITP_TDO
ITP_TDI
6,8,9,13,14,19
VCC1_5
SMB_ALERT#
4
4
4
4
4
4
4
ITP_TCK
VREF_CMOS
2
VREF_GTL
SMT0603
SMB_DATA
4,6
SMT0603
ALERT#
SMBCLK
SMBDATA
NC:1,5,9,13,16
THMC10DBQR
GND1
GND
ADD1
ADD0
DXN
DXP
VCC
U9
VCC3
CPU THERMAL MONITOR
ITP_PRDY#
ITP_PREQ#
ITP_TRST#
ITP_TDO
ITP_TDI
10v
VREF_CLK
VCC2_5
4
4
ITP DEBUG PORT
AMP 104068-3
30
12
11
29
10
8
6
4
2
9
7
5
3
1
J12
VCC1_5
1. Terminating resistors on the ITP signals should be located within 1" of the ITP connector
ROUTING NOTES - ITP
SMT0603
GTL_HA#7
GTL_HD#2
C7
GTL_HD#[63:0]
SMT0603
GTL_HA#6
D1#
A4#
GTL_HD#1
D11
SMT0603
J2
GTL_HD#0
D10
R176
243
D0#
R198
1K
A3#
R186
1K
SMT0603
U11
SMT0603
L3
R204
1K
A
SMT0603
R187
150
GTL_HA#5
SMT0603
R191
150
K3
SMT0603
TANT_3528
R170
2K
R167
2K
SMT0603
SMT0603
R136
1.5K
R144
1K
GTL_HA#4
R125
1.5K
SMT0603
C195
0.1UF
R97
1K
GTL_HA#3
SMT0603
SMT0603
R194
1K
2200PF C147
SMT0603
R99
1K
C161
0.1UF
3
SMT0603
4
TANT_D
GTL_HA#[31:3]
5
R124
1K
SMT0603
SMT0603
R79
SMT0603
SMT0603
R98
1K
R149
2K
R101
56.2
R199
1.5K
SMT0603
1K
SMT0603
SMT0603
6
C232
0.1UF
C202
0.1UF
C123
0.1UF
C169
0.1UF
C236
0.1UF
C133
0.1UF
SMT0603
SMT0603
SMT0603
R111
1.5K
R168
1K
SMT0603
SMT0603
R77
10K
R166
1K
6
SMT0603
56.2
C146
0.1UF
R206
0
SMT0603
SMT0603
SHEET
LAST
REV
VCCCORE1
4 OF 19
09/20/01
10:29 AM
B
D
C
B
A
D
C
B
6
N2
M20
M15
M13
M11
M9
M7
L19
L16
L14
L12
L10
L8
L5
K20
K15
K13
K11
K9
K7
K2
J19
J16
J14
J12
J10
J8
J4
H20
H15
H13
H11
H9
H7
H2
G19
G3
F20
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F3
E19
E13
E11
E10
E9
E8
E7
E3
D9
D7
D6
D2
C19
C16
C15
C11
C9
B18
B15
B10
B8
B7
B6
B5
B1
A21
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
MTG1
MTG2
MTG3
MTG4
MTG5
MTG6
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS13
VSS14
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
496
497
498
499
500
501
AD21
AD16
AD5
AD1
AC21
AC18
AC16
AC14
AC10
AC5
AC2
AC1
AB17
AB14
AB13
AB11
AB9
AB5
AB3
AA20
AA13
AA4
Y19
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y3
W18
W4
V19
V3
U20
U16
U14
U12
U10
U8
T19
T18
T15
T13
T11
T9
T7
T5
T3
R20
R16
R14
R12
R10
R8
R5
R4
R3
P19
P15
P13
P11
P9
P7
P5
N20
N19
N18
N16
N14
N12
N10
N8
N4
N3
4.7UF
C151
4.7UF
C253
10v
4.7UF
C110
VCC1_5
10v
VCCCORE1
10v
VCCCORE1
10v
10v
10v
5
4.7UF
C243
4.7UF
C252
4.7UF
C109
10v
4.7UF
C216
10v
4.7UF
C155
VCCCORE1
VCCCORE1
VCC1_5
C145
0.1UF
VSS83
C251
0.1UF
VSS82
C179
0.1UF
VSS81
C154
0.1UF
VSS80
C184
0.1UF
VSS3
C206
0.1UF
VSS2
4
C130
0.1UF
VSS1
C118
0.1UF
VSS0
C120
0.1UF
A8
C172
0.1UF
A7
C119
0.1UF
A2
C152
0.1UF
W11
W10
W9
W8
W7
W6
V17
V16
V15
V14
V13
V12
V11
V10
V9
V8
V7
V6
U17
U6
T17
T6
R17
R6
P17
P6
P1
N17
N6
M17
M6
L17
L6
K17
K6
J17
J6
H17
H6
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
NC24
NC23
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
VID4
VID3
VID2
VID1
VID0
VCCT71
VCCT70
VCCT69
VCCT68
VCCT67
VCCT66
VCCT65
VCCT64
VCCT63
VCCT62
VCCT61
VCCT60
VCCT59
VCCT58
VCCT57
VCCT56
VCCT55
VCCT54
VCCT53
VCCT52
VCCT51
4 of 4
Intel Mobile Celeron/PIII
VCCT50
VCCT49
VCCT48
VCCT47
VCCT46
VCCT45
VCCT44
VCCT43
VCCT42
VCCT41
VCCT40
VCCT39
VCCT38
VCCT37
VCCT36
VCCT35
VCCT34
VCCT33
VCCT32
VCCT31
VCCT30
VCCT29
VCCT28
VCCT27
VCCT26
VCCT25
VCCT24/VCC
VCCT23
VCCT22
VCCT21
VCCT20
VCCT19
VCCT18
VCCT17
VCCT16
VCCT15
VCCT14
VCCT13
VCCT12
VCCT11
VCCT10
VCCT9
VCCT8
VCCT7
VCCT6
VCCT5
VCCT4
VCCT3
VCCT2
VCCT1
VCCT0
U11
AD15
AC20
AC17
AC3
AA19
AA5
P4
P3
M5
M4
J5
H5
H3
G18
G5
G2
E15
D16
D14
D8
C14
A17
A16
A15
AB4
AC4
AD4
AD3
AD2
AD8
AD7
AD6
AC8
AC7
AC6
AB8
AB7
AB6
AA8
AA7
AA6
Y8
Y7
Y6
W17
W16
W15
W14
W13
W12
VCC1_5
SMT0603
0
0
SMT0603
R70
SMT0603
R68
3
VCC3
VCC3
VCC3
2
VCC3
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
2
SMT0603
R71
SMT0603
R69
SMT0603
R67
0
0
0
VCC3
R61
10K
A12
C189
0.1UF
SMT0603
SMT0603
0
EMPTY
R66
R60
10K
A
C198
0.1UF
VCC1_5
C117
0.1UF
VCCCORE1
C127
0.1UF
3
C124
SMT0603
SMT0603
0
EMPTY
R65
R59
10K
U11
4
C149
0.1UF
5
C121
0.1UF
SMT0603
SMT0603
0
EMPTY
R64
R58
10K
0
R63
R57
10K
R62
EMPTY
SMT0603
SMT0603
6
TANT_3528
TANT_3528
TANT_3528
SMT0603
SMT0603
SMT0603
TANT_3528
TANT_3528
TANT_3528
C126
0.1UF
C201
0.1UF
C218
0.1UF
SMT0603
SMT0603
SMT0603
C235
0.1UF
C134
0.1UF
SMT0603
SMT0603
SMT0603
C234
0.1UF
C215
0.1UF
SMT0603
SMT0603
SMT0603
C214
0.1UF
C180
0.1UF
SMT0603
SMT0603
SMT0603
C129
0.1UF
C211
0.1UF
SMT0603
SMT0603
SMT0603
C122
0.1UF
C237
0.1UF
SMT0603
SMT0603
SMT0603
C171
0.1UF
C135
0.1UF
SMT0603
SMT0603
SMT0603
C128
0.1UF
C173
0.1UF
SMT0603
SMT0603
SMT0603
C148
0.1UF
C185
0.1UF
SMT0603
SMT0603
SMT0603
C247
0.1UF
C207
0.1UF
SMT0603
SMT0603
SMT0603
C250
0.1UF
C239
0.1UF
SMT0603
SMT0603
SMT0603
C210
0.1UF
C190
0.1UF
SMT0603
SMT0603
SMT0603
C249
0.1UF
C170
0.1UF
SMT0603
SMT0603
SMT0603
C158
0.1UF
C199
0.1UF
SMT0603
SMT0603
SMT0603
C131
0.1UF
C132
0.1UF
SMT0603
SMT0603
SMT0603
C233
0.1UF
C159
0.1UF
SMT0603
SMT0603
SMT0603
C125
0.1UF
C153
0.1UF
SMT0603
SMT0603
SMT0603
C160
0.1UF
C150
0.1UF
0.1UF
C248
0.1UF
C203
0.1UF
SMT0603
SMT0603
SMT0603
SMT0603
SMT0603
C246
0.1UF
C238
0.1UF
SMT0603
SMT0603
0
EMPTY
TANT_3528
TANT_3528
B
1.90v
1.85v
1.80v
1.75v
1.70v
1.65v
1.60v
1.55v
1.50v
00010
00011
00100
00101
00110
00111
01000
01001
01010
1.200v
1.175v
1.150v
1.125v
1.100v
1.075v
1.050v
1.025v
1.000v
0.975v
0.950v
0.925v
No CPU
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
1.250v
10011
1.275v
10001
1.225v
No CPU
10000
10010
1.30v
01111
1.35v
1.40v
01110
01101
01100
1.45v
1.95v
00001
01011
2.00v
00000
1
DRAWING
PROCESSOR 2 OF 2
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
18
18
18
18
18
VCC CPU
VID[4:0]
CORE VOLTAGE
1
SHEET
LAST
REV
5 OF 19
09/20/01
10:29 AM
B
D
C
B
A
D
C
B
4
4
4
4
4
4
4
4
4
4
4
4
8
4
4
4
4,19
4
4
4
4
4
4,6
4,6
GTL_RS#2
GTL_RS#1
GTL_RS#0
VREF_GTL
GTL_HTRDY#
GTL_HREQ#4
GTL_HREQ#3
GTL_HREQ#2
GTL_HREQ#1
GTL_HREQ#0
GTL_HLOCK#
GTL_HITM#
GTL_HIT#
MX_HCLK
GTL_DRDY#
GTL_DEFER#
GTL_DBSY#
GTL_CPURST#
GTL_BREQ0#
GTL_BPRI#
GTL_BNR#
GTL_ADS#
GTL_HA#[31:3]
6
GTL_HA#31
GTL_HA#30
GTL_HA#29
GTL_HA#28
GTL_HA#27
GTL_HA#26
GTL_HA#25
GTL_HA#24
GTL_HA#23
GTL_HA#22
GTL_HA#21
GTL_HA#20
GTL_HA#19
GTL_HA#18
GTL_HA#17
GTL_HA#16
GTL_HA#15
GTL_HA#14
GTL_HA#13
GTL_HA#12
GTL_HA#11
GTL_HA#10
GTL_HA#9
GTL_HA#8
GTL_HA#7
GTL_HA#6
GTL_HA#5
GTL_HA#4
GTL_HA#3
SMT0603
V21
V24
W26
T24
U25
V25
T22
T23
T26
U23
U26
V23
J24
U22
R22
U21
J26
W25
R24
R26
V26
K25
K26
L24
N23
H23
J23
M26
L25
K22
M25
L23
K23
N25
J21
L26
L22
N26
P26
M22
M23
M24
P23
T25
N24
P22
R25
N22
R23
P25
F20
K21
RS2#
RS1#
RS0#
HTRDY#
HREQ4#
HREQ3#
HREQ2#
HREQ1#
HREQ0#
HLOCK#
HITM#
HIT#
HCLKIN
DRDY#
DEFER#
DBSY#
CPURST#
BREQ0#
BPRI#
BNR#
ADS#
HA31#
HA30#
HA29#
HA28#
HA27#
HA26#
HA25#
HA24#
HA23#
HA22#
HA21#
HA20#
HA19#
HA18#
HA17#
HA16#
HA15#
HA14#
HA13#
HA12#
HA11#
HA10#
HA9#
HA8#
HA7#
HA6#
HA5#
HA4#
HA3#
VTTB
VTTA
GTLREF
82443MX100
1 of 4
STPCLK#
SMI#
RCIN#
NMI
INTR
INIT#
IGNNE#
FERR#
A20M#
A20GATE
HD63#
HD62#
HD61#
HD60#
HD59#
HD58#
HD57#
HD56#
HD55#
HD54#
HD53#
HD52#
HD51#
HD50#
HD49#
HD48#
HD47#
HD46#
HD45#
HD44#
HD43#
HD42#
HD41#
HD40#
HD39#
HD38#
HD37#
HD36#
HD35#
HD34#
HD33#
HD32#
HD31#
HD30#
HD29#
HD28#
HD27#
HD26#
HD25#
HD24#
HD23#
HD22#
HD21#
HD20#
HD19#
HD18#
HD17#
HD16#
HD15#
HD14#
HD13#
HD12#
HD11#
HD10#
HD9#
HD8#
HD7#
HD6#
HD5#
HD4#
HD3#
HD2#
HD1#
HD0#
5
GTL_HD#42
GTL_HD#43
GTL_HD#44
GTL_HD#45
GTL_HD#46
GTL_HD#47
GTL_HD#48
GTL_HD#49
GTL_HD#50
GTL_HD#51
GTL_HD#52
GTL_HD#53
GTL_HD#54
GTL_HD#55
GTL_HD#56
GTL_HD#57
GTL_HD#58
GTL_HD#59
GTL_HD#60
GTL_HD#61
GTL_HD#62
GTL_HD#63
A21
B21
D20
D19
E20
F18
E19
C20
E16
A22
C18
A20
E17
D18
D17
B19
A19
E18
B18
F17
A18
D16
MX_FERR#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
XBUS_RCIN#
CPU_SMI#
CPU_STPCLK#
B1
A2
B2
B3
A3
D4
C2
E3
CPU_A20M#
GTL_HD#41
B20
XBUS_A20GATE
GTL_HD#40
C17
B4
GTL_HD#39
D22
C4
GTL_HD#38
GTL_HD#25
E22
F19
GTL_HD#24
B24
GTL_HD#37
GTL_HD#23
H22
D21
GTL_HD#22
G22
GTL_HD#36
GTL_HD#21
C24
B22
GTL_HD#20
D23
GTL_HD#35
GTL_HD#19
D26
A24
GTL_HD#18
D25
GTL_HD#34
GTL_HD#17
F24
C21
GTL_HD#16
B25
GTL_HD#33
GTL_HD#15
H25
B23
GTL_HD#14
F26
GTL_HD#32
GTL_HD#13
C25
GTL_HD#31
GTL_HD#12
G23
GTL_HD#30
GTL_HD#11
F23
GTL_HD#29
GTL_HD#10
G25
E21
GTL_HD#9
J22
B26
GTL_HD#8
H21
E23
GTL_HD#7
E25
A25
GTL_HD#6
J25
GTL_HD#28
GTL_HD#5
F25
A23
GTL_HD#4
H26
GTL_HD#27
GTL_HD#3
D24
C23
GTL_HD#2
E26
GTL_HD#26
GTL_HD#1
G26
C26
GTL_HD#0
4,19
4,19
10,19
4,19
4,19
4,19
4,19
4,19
10,19
4,19
CPU_FERR#
ZVNL120
VCC3
2
4
SMT0603
G24
4
R116
10K
F22
GTL_HD#[63:0]
3
4
VCC1_5
Q7
1
SMT0603
VREF_GTL
SMT0603
R117
1.21K
SMT0603
U13
AE19
AC18
AB18
AD20
AE20
AF20
AE21
AE22
AD21
AF21
AF22
MEM_MAA3
MEM_MAA4
MEM_MAA5
MEM_MAA6
MEM_MAA7
MEM_MAA8
MEM_MAA9
MEM_MAA10
MEM_MAA11
MEM_MAA12
MEM_MAA13
AF19
AE17
AD19
AC16
AB25
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
CLK_DCLKIN
AF17
AD26
AC26
MEM_DQM5
MEM_DQM6
MEM_DQM7
IDE_PDIORDY_R
IDE_PDIOW#_R
IDE_PDIOR#_R
IDE_PDDRQ_R
IDE_PDDACK#_R
AA5
AB7
AF6
AF5
AB5
AC6
AF7
IDE_PDD13_R
IDE_PDD15_R
AA9
IDE_PDD12_R
AE8
AE7
IDE_PDD14_R
AC8
AA8
IDE_PDD7_R
AB9
AB8
IDE_PDD6_R
AA10
AC7
IDE_PDD5_R
IDE_PDD11_R
AE5
IDE_PDD4_R
IDE_PDD10_R
AD8
IDE_PDD3_R
IDE_PDD9_R
AD5
IDE_PDD2_R
IDE_PDD8_R
AE6
AC5
IDE_PDCS3#_R
IDE_PDD1_R
AB6
IDE_PDCS1#_R
AA7
AD7
IDE_PDA2_R
IDE_PDD0_R
AA6
IDE_PDA1_R
IDE_PDD[15:0]_R
AF8
IDE_PDA0_R
AA19
AE15
MEM_DQM4
MEM_WE#
AC25
MEM_DQM3
AE16
AD25
MEM_DQM2
MEM_RAS#
AF16
MEM_DQM1
AF18
AD16
MEM_DQM0
MEM_CAS#
MEM_DQM[7:0]
AC24
AC20
MEM_CKE3#
SMT0603
AB19
MEM_CKE2#
CLK_DCLKOUT
AB17
MEM_CKE1#
CLK_DCLKO_R
AC19
MEM_MAA2
R203
AC17
MEM_MAA1
AA18
22.1
AE18
MEM_MAA0
MEM_CKE0#
MEM_MAA[13:0]
SMT0603
PIORDY
PDIOW#
PDIOR#
PDDRQ
PDDACK#
PDD15
PDD14
PDD13
PDD12
PDD11
PDD10
PDD9
PDD8
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
PDCS3#
PDCS1#
PDA2
PDA1
PDA0
WE#
SRAS#
SCAS#
DQM7
DQM6
DQM5
DQM4
DQM3
DQM2
DQM1
DQM0
DCLKO
DCLK
CS3#
CS2#
CS1#
CS0#
CKE3#
CKE2#
CKE1#
CKE0#
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
U13
TEST#
RTCX2
RTCX1
VCCRTC
SMBCLK
SMBDATA
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
K5
M3
M1
N2
J3
J2
V22
Y26
Y25
Y24
AB24
AA25
AA26
AB26
AF25
AE26
AD23
AE25
AF24
AF23
AE24
AE23
AD17
AC15
AB16
AB15
AC14
AD12
AC13
AB14
AD13
AB12
AD11
AC12
AB11
AC11
AB10
AC9
W24
Y23
W23
W21
W22
Y22
AA23
AB23
AC22
AC23
AA22
Y21
AB21
AB22
AC21
AB20
AE14
AF15
AF14
AE13
AD15
AE12
AF13
AF12
AF11
AE11
AC10
AD9
AE10
AF10
AF9
AE9
3
SMT0603
4.75K R174
SMT0603
R169
SMT1206
Y3
32.768KHZ
1M
SMB_CLK
SMB_DATA
MEM_MD63
MEM_MD62
MEM_MD61
MEM_MD60
MEM_MD59
MEM_MD58
MEM_MD57
MEM_MD56
MEM_MD55
MEM_MD54
MEM_MD53
MEM_MD52
MEM_MD51
MEM_MD50
MEM_MD49
MEM_MD48
MEM_MD47
MEM_MD46
MEM_MD45
MEM_MD44
MEM_MD43
MEM_MD42
MEM_MD41
MEM_MD40
MEM_MD39
MEM_MD38
MEM_MD37
MEM_MD36
MEM_MD35
MEM_MD34
MEM_MD33
MEM_MD32
MEM_MD31
MEM_MD30
MEM_MD29
MEM_MD28
MEM_MD27
MEM_MD26
MEM_MD25
MEM_MD24
MEM_MD23
MEM_MD22
MEM_MD21
MEM_MD20
MEM_MD19
MEM_MD18
MEM_MD17
MEM_MD16
MEM_MD15
MEM_MD14
MEM_MD13
MEM_MD12
MEM_MD11
MEM_MD10
MEM_MD9
MEM_MD8
MEM_MD7
MEM_MD6
MEM_MD5
MEM_MD4
MEM_MD3
MEM_MD2
MEM_MD1
MEM_MD0
2
82443MX100
2 of 4
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
11
11
11
11
11
11
11
11
11
11
11
9
9
9
9
8
8
9
9
9
9
9
9
9
9
8,9
SMT0603
3VSB
4,8,9,13,14,19
4,8,9,13,14,19
CLR
E20
E21
3
E22
NRM
CMOS CLR
MEM_MD[63:0]
B
440MX 1 OF 2
9
2
D3
1
SOT23
BAT54C
2
1
3VSB
3
1
1
DRAWING
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
SMT0603
2
SMT0603
3
C245
0.1UF
SMT0603
4
C241
22PF
C240
22PF
R302
100
R303
1K
VCC1_5
5
BA2032
A
C209
0.1UF
C183
0.1UF
C188
0.1UF
C213
0.1UF
C217
0.1UF
C197
0.1UF
6
BS1
SMT0603
SMT0603
SHEET
LAST
REV
6 OF 19
09/20/01
10:29 AM
B
D
C
B
A
D
C
B
A
3VSB
19
15,19
15
12
12
12
12
12
12
8
10
10
10
10,19
10
8,10
10,19
10,19
11,19
19
19
19
19
19
19
19
10,19
10,19
10,19
10,19
10,19
19
10
U4
R1
Y4
U3
AD2
Y3
AF3
W6
Y2
AE3
AF2
F5
U1
U2
XBUS_DREQ2
XBUS_IOCHRDY
XBUS_IOR#
XBUS_IOW#
XBUS_IRQ1
XBUS_IRQ3
XBUS_IRQ4
XBUS_IRQ5
XBUS_IRQ6
XBUS_IRQ7
XBUS_IRQ12
XBUS_IRQ14
XBUS_MEMR#
XBUS_MEMW#
XBUS_SA0
V1
XBUS_DREQ1
M4
J1
L4
K2
L2
USB_P1_OC#
USB_P0+_R
USB_P0-_R
USB_P1+_R
USB_P1-_R
D2
E1
AC_SDIN0
6
C1
AC_BITCLK
AC_SDIN1
K1
L1
L5
AD4
V3
N1
SMT0603
R513
XBUS_SYSCLK
USB_P0_OC#
0
U5
XBUS_SA18
T1
W4
XBUS_SA17
XBUS_SD7
U6
XBUS_SA16
T3
Y1
XBUS_SA15
XBUS_SD6
W2
XBUS_SA14
V4
AC3
XBUS_SA13
XBUS_SD5
W5
XBUS_SA12
V6
AC2
XBUS_SA11
XBUS_SD4
AA1
XBUS_SA10
R2
W1
XBUS_SA9
XBUS_SD3
AB3
XBUS_SA8
T2
AC4
XBUS_SA7
XBUS_SD2
AA3
XBUS_SA6
V2
AB2
XBUS_SA5
XBUS_SD1
AA2
XBUS_SA4
V5
AE2
XBUS_SA3
XBUS_SD0
AD1
XBUS_SA2
USB_CLK48
XBUS_TC
VIA44
XBUS_SD[7:0]
AE1
XBUS_SA1
AC1
T4
XBUS_RSTDRV
XBUS_SA[18:0]
R4
XBUS_BIOSCS#
AB4
AE4
XBUS_DREQ0
XBUS_OSC
AB1
XBUS_DACK#2
AC_DATA_IN1
AC_DATA_IN0
AC_BIT_CLK
VSSUSB
USBP1-
USBP1+
USBPO-
USBPO+
OC1
OC0
CLK48
VCCUSB
TC
SYSCLK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
RSTDRV
BIOSCS#
OSC
MEMW#
MEMR#
IRQ14
IRQ12
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ1
IOW#
IOR#
IOCHRDY
DREQ2
DREQ1
DREQ0
DACK2#
82443MX100
3 of 4
5
AC_SYNC
AC_SDATA_OUT
AC_RST#
VREF
TRDY#
STOP#
SERR#
PREQ2#
PREQ1#
PREQ0#
PLOCK#
PIRQB#
PIRQA#
PGNT2#
PGNT1#
PGNT0#
PCIRST#
PCICLK
PAR
IRDY#
FRAME#
DEVSEL#
CLKRUN#
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCI_AD2
D1
G5
F2
F7
F10
F9
D8
AC_SYNC
AC_SDOUT
AC_RST#
PCI_TRDY#
PCI_STOP#
PCI_SERR#
PCI_REQ#2
PCI_REQ#1
A14
E14
PCI_REQ#0
PCI_LOCK#
PCI_IRQ#B
PCI_IRQ#A
PCI_GNT#2
PCI_GNT#1
PCI_GNT#0
PCI_RST#
PCI_CLKF
PCI_PAR
PCI_IRDY#
PCI_FRAME#
PCI_DEVSEL#
PCI_CLKRUN#
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
PCI_AD[31:0]
D15
F8
E5
D5
D14
C16
E15
E12
A15
B12
D9
A12
E8
B17
D13
A13
B10
B6
PCI_AD31
C15
PCI_AD29
PCI_AD30
PCI_AD28
B13
B16
PCI_AD27
A17
PCI_AD26
C13
PCI_AD25
A16
B15
PCI_AD24
PCI_AD23
D12
C11
PCI_AD22
PCI_AD21
C12
E13
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
B14
C10
E10
D11
C9
B11
A10
A11
PCI_AD12
E9
PCI_AD9
PCI_AD8
PCI_AD11
PCI_AD10
D10
C8
A8
B9
PCI_AD7
PCI_AD6
A6
A7
PCI_AD5
A9
PCI_AD4
PCI_AD3
PCI_AD1
B7
E7
B8
PCI_AD0
A5
D7
15
15
15
10v
4.7UF
C267
VCC3
14,16,17,19
14,16,17,19
14,16,17,19
16,19
16,19
14,19
16,17,19
16,17,19
16,17,19
16,19
16,19
14,19
11,14,16,17
8
14,16,17
14,16,17,19
14,16,17,19
14,16,17,19
14,19
14,16,17
14,16,17
14,16,17
14,16,17
14,16,17
10v
4.7UF
C186
10v
4.7UF
C187
10v
MX_VREF
VCC
4.7UF
C272
SMT0603
DACK1#
TANT_3528
R85
1K
DACK0#
4
VCC3
SMT0603
U13
TANT_3528
C113
0.1UF
Y5
VCC3
13
14
13,14
10,13
13,19
8
17,19
17,19
19
13,19
14,16,17,19
16,17,19
19
13,15
12
19
19
4,19
10,19
19
19
19
19
19
19
10,14,16,17,19
G2
PM_SUSB#
VIA23
F4
D6
C5
J5
MX_GPIO1
MX_GPIO2
MX_GPIO3
MX_GPIO4
J4
PM_RI#
B5
PCI_GNT#3
P4
P5
A4
3VSB
MX_GPIO28
VIA41
VIA42
R5
MX_GPIO26
VIA43
PCI_REQ#3
MX_GPIO27
T5
MX_GPIO25
E2
PM_EXTSMI#
K3
MX_GPIO20
VIA35
E6
N4
MX_GPIO19
VIA38
PCI_IRQ#D
G4
MX_GPIO18
VIA25
C6
K4
MX_GPIO17
VIA34
PCI_IRQ#C
P3
P2
N5
MX_GPIO16
VIA37
P1
MX_GPIO15
VIA39
MX_GPIO21
MX_SPKR
H3
MX_GPIO11
R3
H4
MX_GPIO10
MX_GPIO13
H6
VIA40
F6
SMB_ALERT#
J6
H5
MX_GPIO6
PCI_SERIRQ
AF4
F1
PCI_PME#
MX_GPIO5
G1
PM_SUSC#
MX_GPIO9
G3
PM_SUSA#
VIA36
VIA22
H1
L3
PM_SUSCLK
M5
PM_RSMRST#
PM_SUSSTAT#
VIA24
M2
E4
D3
PM_PWROK
PM_PCISTP#
H2
VIA21
PM_PWRBTN#
PM_CPUSTP#
3
*
*
*
*
*
*
*
*
*
*
*
*
82443MX100
4 of 4
3
VCCC3
VSSF21
VSSK24
VSSAD22
VSSAA24
VSSAD14
VSSAF26
VSSA26
VSSAA20
VSSU24
VSSP24
VSSC14
VSSH24
VSSE24
VSSR15
VSSC22
VSSM15
VSSR12
VSSC19
VSSAD18
VSSM12
VSSAD10
VSSR16
VSSM16
VSST15
VSSP15
VSSN15
VSSL15
VSSR14
VSSP14
VSSN14
VSSM14
VSSR13
VSSP13
VSSN13
VSSM13
VSST12
VSSP12
VSSN12
VSSL12
VSSR11
VSSM11
VSSC7
VSSAD6
VSSW3
VSSN3
VSSAF1
VSSF3
VSSA1
VCCSUS
VCCAD24
VCCT16
VCCP16
VCCN16
VCCL16
VCCAA21
VCCG21
VCCT14
VCCL14
VCCT13
VCCL13
VCCAA17
VCCAB13
VCCT11
VCCP11
VCCN11
VCCL11
VCCE11
VCCY6
VCCG6
VCCAD3
F21
K24
AD22
AA24
AD14
AF26
A26
AA20
U24
P24
C14
H24
E24
R15
C22
M15
R12
C19
AD18
M12
AD10
R16
M16
T15
P15
N15
L15
R14
P14
N14
M14
R13
P13
N13
M13
T12
P12
N12
L12
R11
M11
C7
AD6
W3
N3
AF1
F3
A1
K6
AD24
T16
P16
N16
L16
AA21
G21
T14
L14
T13
L13
AA17
AB13
T11
P11
N11
L11
E11
Y6
G6
AD3
C3
VCC3
3VSB
2
2
GPIO30/GNT3#
GPIO29/REQ3#
GPIO28/DACK3#
GPIO27/DRQ3
GPIO26/KBCCS#
GPIO25/MCCS#
GPIO24/EXTSMI#
GPIO23/PIRQD#
GPIO22/PIRQC#
GPIO21/ZEROWS#
GPIO20
GPIO19/PCS0#
GPIO18
GPIO17
GPIO16/PCS1#
GPIO15
GPIO14/SPKR
GPIO13
GPIO12/RI#
GPIO11/BATLOW#
GPIO10/LID
GPIO9
GPIO8/THERM#
GPIO7/SERIRQ
GPIO6/IRQ8#
GPIO5
GPIO4
GPIO3/GNTA#
GPIO2/REQA#
GPIO1
GPIO0/PME#
SUSC#
SUSB#
SUSA#
SUSCLK
SUS_STAT#
RSMRST#
PWROK
PWRBTN#
PCISTP#
CPUSTP#
U13
SMT0603
AA4
SMT0603
VIA45
SMT0603
XBUS_DACK#1
SMT0603
10
4
SMT0603
5
SMT0603
6
C270
0.1UF
C269
0.1UF
C259
0.1UF
C271
0.1UF
C194
0.1UF
C260
0.1UF
C193
0.1UF
C221
0.1UF
C205
0.1UF
3
C225
1
SMT0603
SOT23
0.1UF
2
BAT54C
D2
SMT0603
SMT0603
SMT0603
TANT_3528
TANT_3528
B
440MX 2 OF 2
1
DRAWING
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
1
SHEET
LAST
REV
7 OF 19
09/20/01
10:29 AM
B
D
C
B
A
6
C311
C308
10PF
10PF
MEM_CLK7
MEM_CLK6
MEM_CLK5
MEM_CLK4
MEM_CLK3
MEM_CLK2
0
0
0
0
C300
SMT0603
R270
0
R272
SMT0603
SMT0603
SMT0603
SMT0603
CLK_XTAL_OUT
CLK_XTAL_IN
R_MEM_CLK7
R_MEM_CLK6
R_MEM_CLK5
R_MEM_CLK4
R_MEM_CLK3
R_MEM_CLK2
R_MEM_CLK1
R_MEM_CLK0
6
5
24
25
32
33
18
19
21
22
35
36
38
39
40
41
43
44
46
17
SMT0603
R273
0
R278
SMT0603
R271
R276
SMT0603
0
SMT0603
R274
SMT0603
TANT_3528
R275
0
SMT0603
R_CLK_DCLKIN
SMT0603
XTALOUT
XTALIN
SDR_15
SDR_14
SDR_13
SDR_12
SDR_11
SDR_10
SDR_9
SDR_8
SDR_7
SDR_6
SDR_5
SDR_4
SDR_3
SDR_2
SDR_1
SDR_0
SDR_F
BUF_IN
SMT0603
VDDPCI_1
5
ICS9250BF-19
CLK100
SDATA
SCLK
FS2#/REF1
PCI_STOP#/REF0
CPUSTOP#
APIC_F
APIC_0
24MHZ/FS0#
48MHZ/FS1#
PCICLK_5
PCICLK_4
PCICLK_3
PCICLK_2
PCICLK_1
FS3#/PCICLK_0
MODE/PCICLK_F
CPUCLK_2
CPUCLK_1
CPUCLK_F
R_CPUMX_HCLK
R_PCI_CLK1
R_PCI_CLK2
R_PCI_CLK3
R_PCI_CLK4
11
12
13
14
R284
R503
4
3
22.1
22.1
22.1
22.1
22.1
22.1
R288
SMT0603
R291
EMPTY
SMT0603
R269
SMT0603
R282
SMT0603
R285
SMT0603
R290
SMT0603
0
22.1
22.1
22.1
22.1
22.1
SMT0603
R283
SMT0603
R279
SMT0603
R281
SMT0603
R287
SMT0603
R286
SMT0603
R289
CPU_BSEL0
USB_CLK48
PCI_CLK4
PCI_CLK3
PCI_CLK2
PCI_CLK1
PCI_CLK0
PCI_CLKF
MX_HCLK
CPU_HCLK
ITP_HCLK
4
XBUS_OSC
GND_6
GND_5
GND_4
GND_3
GND_2
GND_1
GND_0
CAP GND PAD
6,9
MEM_MAA[13:0]
VIA TO GND
EMPTY
MEM_MAA8
EMPTY
10K
10K
10K
10K
3
R233
SMT0603
R247
SMT0603
R246
SMT0603
R232
SMT0603
R244
SMT0603
R243
SMT0603
R231
SMT0603
R245
SMT0603
VCC3
2
Clear the RTC CMOS
Install to Reprogram the BIOS
Install to Set the CompactFlash as Master
Enable or Disable the Ethernet Controller
CMOS CLR
BIOS UNLOCK
CF MASTER
ENET ENA/DIS
2
Default
Disable
One
66MHz
A20M# Low
IGNNE# Low
INTR Low
B
Reserved
Enable
Max
100MHz
A20M# High
IGNNE# High
INTR High
NMI High
PULLUP
ENA = Enabled
Installed = CF Master
Installed = Unlocked
CLR = Clear
NRM = Normal
PULLDOWN
PULLUP
PULLUP
PULLDOWN
PULLDOWN
PULLDOWN
PULLDOWN
PULLDOWN
1
SHEET
LAST
REV
440MX DEFAULT
DIS = Disabled
8 OF 19
09/20/01
10:29 AM
B
Not Installed = CF Slave
Not Installed = Locked
DRAWING
1
JUMPER INSTALLATION OPTIONS
SYSTEM CLOCK & STRAPPING OPTIONS
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
Board Stuffing Default
Quick Start Select
MA10
Reserved
In-Order Queue Depth Enable
MA11
MA8
Host Frequency Select
Processor Core/Bus Ratio Select (not used)
MA12
MA1
MA7
NMI Low
MA13
MA9
PULLDOWN
FUNCTION
SIGNAL
STRAPPING OPTIONS
Indicates Default Jumper Location
FUNCTION
JUMPER
JUMPER DEFINITION TABLE
MEM_MAA10
MEM_MAA11
EMPTY
10K
EMPTY
MEM_MAA1
MEM_MAA12
10K
EMPTY
MEM_MAA7
10K
EMPTY
MEM_MAA9
10K
EMPTY
MEM_MAA13
4,6,9,13,14,19
4,6,9,13,14,19
7,10
7
4
7
14
17
16
16
10
7
6
4
4
CAP PWR PAD
VIA TO PWR
PM_CPUSTP#
CPU_BSEL1
IC PIN
4. Power trace should run from IC pin to cap pad, then through via to power island as shown
3. Connection from power pin to bypass capacitors must be as short as and wide as possible.
2. The two clock powers should be separate islands on the power plane under the corresponding pins of the IC
1. Place a copper area under the clock IC body on the component side, and connect it to GND through several vias
ROUTING NOTES - SYSTEM CLOCK
SMB_DATA
SMT0603
27
SMT0603
SMB_CLK
R_XBUS_OSC
VCC2_5
BLM21P300SPT
FB22
4
SMT0603
28
2
3
47
54
55
30
29
R_USB_CLK48
R_PCI_CLK0
9
16
R_PCI_CLKF
8
49
R_ITP_HCLK
SMT0603
51
TANT_3528
52
4.7UF
10v C309
R500
CLK_VCC2_5_L
SMT0603
GND_7
D
C
9
9
9
9
9
9
9
MEM_CLK1
MEM_CLK0
R280
SMT0603
SMT0603
VDDREF
9
22.1
VDD48
CLK_DCLKIN
VDDPCI_0
CLK_DCLKOUT
SMT0603
U15
VDDSDR_0
6
6
4.7UF
10v C293
VDDSDR_1
B
BLM21P300SPT
CLK_VCC3_L
R501
FB18
R502
VCC3
SMT0603
5
SMT0603
A
6
VDDSDR_2
Y4
VDDAPIC
14.318MHZ
VDDCPU
10PF
C296
0.1UF
C299
0.001UF
C298
0.1UF
C301
0.001UF
C310
0.1UF
C302
0.001UF
C305
0.001UF
C307
0.1UF
C306
0.1UF
7
10K
15
10K
1
10K
31
10K
20
10K
37
R292
45
SMT0603
56
10K
50
53
48
42
34
26
23
10
4
D
C
B
A
D
C
B
TANT_3528
6
6
10v
4.7UF
C278
VCC3
MEM_MD[63:0]
MEM_DQM7
MEM_DQM6
MEM_DQM5
MEM_DQM4
MEM_DQM3
MEM_DQM2
MEM_DQM1
MEM_DQM0
SMT0603
MEM_MAA[13:0]
MEM_DQM[7:0]
VCC3
MEM_MAA12
MEM_MAA11
MEM_MAA13
MEM_MAA12
MEM_MAA13
MEM_MAA10
MEM_MAA9
MEM_MAA8
MEM_MAA7
MEM_MAA6
MEM_MAA5
MEM_MAA4
MEM_MAA3
MEM_MAA2
MEM_MAA1
MEM_MAA0
MEM_MD15
MEM_MD14
MEM_MD13
MEM_MD12
MEM_MD11
MEM_MD10
MEM_MD9
MEM_MD8
MEM_MD7
MEM_MD6
MEM_MD5
MEM_MD4
MEM_MD3
MEM_MD2
MEM_MD1
MEM_MD0
MEM_MD47
MEM_MD46
MEM_MD45
MEM_MD44
MEM_MD43
MEM_MD42
MEM_MD41
MEM_MD40
MEM_MD39
MEM_MD38
MEM_MD37
MEM_MD36
MEM_MD35
MEM_MD34
MEM_MD33
MEM_MD32
VCC3
168
157
143
133
84
73
59
49
124
110
102
90
41
40
26
18
6
20
19
17
16
15
14
13
11
10
9
8
7
5
4
3
2
104
103
101
100
99
98
97
95
94
93
92
91
89
88
87
86
24
25
31
44
48
50
51
61
80
81
109
108
145
39
122
131
130
113
112
47
46
29
28
132
126
123
38
121
37
120
36
119
35
118
34
117
33
DIMM168 SOCKET
VCC168
VCC157
VCC143
VCC133
VCC84
VCC73
VCC59
VCC49
VCC124
VCC110
VCC102
VCC90
VCC41
VCC40
VCC26
VCC18
VCC6
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
NC24
NC25
NC31_OE0
NC44_OE2
NC48_WE2
NC50
NC51
NC61
NC80
NC81
NC109
NC108
NC145
BA1_A12
BA0_A11
DOMB7_CAS7
DOMB6_CAS6
DOMB5_CAS5
DOMB4_CAS4
DOMB3_CAS3
DOMB2_CAS2
DOMB1_CAS1
DOMB0_CAS0
A13_DU
A12_DU
A11_A13
A10_AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
J14
5
DIMM 0
VSS162
VSS152
VSS148
VSS138
VSS127
VSS116
VSS107
VSS96
VSS85
VSS78
VSS68
VSS64
VSS54
VSS43
VSS32
VSS23
VSS12
VSS1
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DU_CLK3
DU_CLK2
DU_CLK1
DU_CLK0
DU_RAS#
DU_CAS#
WE0#
RAS0_S0#
RAS1_S1#
RAS2_S2#
RAS3_S3#
SDA
SCL
SA2
SA1
SA0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
DU_CKE0
NC_CKE1
REGE
NC134
NC135
NC146
NC164
NC62
MEM_MD63
MEM_MD62
MEM_MD61
MEM_MD60
MEM_MD59
MEM_MD58
MEM_MD57
MEM_MD56
MEM_MD55
MEM_MD54
MEM_MD53
MEM_MD52
MEM_MD51
MEM_MD50
MEM_MD49
MEM_MD48
163
79
125
42
162
152
148
138
127
116
107
96
85
78
68
64
54
43
32
23
12
1
77
76
75
74
72
71
70
69
67
66
65
60
58
57
56
55
MEM_MD31
MEM_MD30
MEM_MD29
MEM_MD28
MEM_MD27
MEM_MD26
MEM_MD25
MEM_MD24
MEM_MD23
MEM_MD22
MEM_MD21
MEM_MD20
MEM_MD19
MEM_MD18
MEM_MD17
MEM_MD16
MEM_RAS#
MEM_CLK3
MEM_CLK2
MEM_CLK1
MEM_CLK0
115
161
160
159
158
156
155
154
153
151
150
149
144
142
141
140
139
MEM_WE#
MEM_CAS#
111
MEM_CS#0
30
27
MEM_CS#1
SMB_DATA
SMB_CLK
114
45
129
82
83
167
166
165
MEM_CKE0#
128
137
136
106
105
53
52
22
21
MEM_CKE1#
63
147
134
135
146
164
62
8
8
8
8
6,9
6,9
6,9
6
6
4
4,6,8,9,13,14,19
4,6,8,9,13,14,19
6
6
4.7UF
SMT0603
SMT0603
TANT_3528
VCC3
MEM_MAA12
MEM_MAA11
MEM_MAA13
MEM_MAA12
MEM_MAA13
MEM_MAA10
MEM_MAA9
MEM_MAA8
MEM_MAA7
MEM_MAA6
MEM_MAA5
MEM_MAA4
MEM_MAA3
MEM_MAA2
MEM_MAA1
MEM_MAA0
DIMM168 SOCKET
VCC168
VCC157
VCC143
VCC133
VCC84
VCC73
VCC59
VCC49
VCC124
VCC110
VCC102
VCC90
VCC41
VCC40
VCC26
VCC18
VCC6
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
NC24
NC25
NC31_OE0
NC44_OE2
NC48_WE2
NC50
NC51
NC61
NC80
NC81
NC109
NC108
NC145
BA1_A12
BA0_A11
DOMB7_CAS7
DOMB6_CAS6
DOMB5_CAS5
DOMB4_CAS4
DOMB3_CAS3
DOMB2_CAS2
DOMB1_CAS1
DOMB0_CAS0
A13_DU
A12_DU
A11_A13
A10_AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
J15
DIMM 1
3
REGE
NC134
NC135
NC146
NC164
NC62
2
VSS162
VSS152
VSS148
VSS138
VSS127
VSS116
VSS107
VSS96
VSS85
VSS78
VSS68
VSS64
VSS54
VSS43
VSS32
VSS23
VSS12
VSS1
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DU_CLK3
DU_CLK2
DU_CLK1
DU_CLK0
DU_RAS#
DU_CAS#
WE0#
RAS0_S0#
RAS1_S1#
RAS2_S2#
RAS3_S3#
SDA
SCL
SA2
SA1
SA0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
DU_CKE0
NC_CKE1
2
TITLE
MEM_CS#2
45
MEM_MD63
MEM_MD62
MEM_MD61
MEM_MD60
MEM_MD59
MEM_MD58
MEM_MD57
MEM_MD56
MEM_MD55
MEM_MD54
MEM_MD53
MEM_MD52
MEM_MD51
MEM_MD50
MEM_MD49
MEM_MD48
MEM_CS#3
162
152
148
138
127
116
107
96
85
78
68
64
54
43
32
23
12
1
77
76
75
74
72
71
70
69
67
66
65
60
58
57
56
55
B
8
8
8
8
6,9
6,9
6,9
6
6
4,6,8,9,13,14,19
4,6,8,9,13,14,19
1
1
DRAWING
DIMM SOCKETS
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
MEM_CLK7
MEM_CLK6
MEM_CLK5
MEM_CLK4
163
79
125
42
MEM_MD31
MEM_MD30
MEM_MD29
MEM_MD28
MEM_MD27
MEM_MD26
MEM_MD25
MEM_MD24
MEM_MD23
MEM_MD22
MEM_MD21
MEM_MD20
MEM_MD19
MEM_MD18
MEM_MD17
MEM_MD16
MEM_RAS#
115
161
160
159
158
156
155
154
153
151
150
149
144
142
141
140
139
MEM_CAS#
111
27
30
MEM_WE#
SMB_DATA
SMB_CLK
114
6
6
129
VCC3
MEM_CKE2#
MEM_CKE3#
82
83
167
166
165
137
136
106
105
53
52
22
21
128
63
147
134
135
146
164
62
168
157
143
133
84
73
59
49
124
110
102
90
41
40
26
18
6
20
19
17
16
15
14
13
11
10
9
8
7
5
4
3
2
MEM_MD15
MEM_MD14
MEM_MD13
MEM_MD12
MEM_MD11
MEM_MD10
MEM_MD9
MEM_MD8
MEM_MD7
MEM_MD6
MEM_MD5
MEM_MD4
MEM_MD3
MEM_MD2
MEM_MD1
MEM_MD0
VCC3
104
103
101
100
99
98
97
95
94
93
92
91
89
88
87
86
MEM_MD47
MEM_MD46
MEM_MD45
MEM_MD44
MEM_MD43
MEM_MD42
MEM_MD41
MEM_MD40
MEM_MD39
MEM_MD38
MEM_MD37
MEM_MD36
MEM_MD35
MEM_MD34
MEM_MD33
MEM_MD32
24
25
31
44
48
50
51
61
80
81
109
108
145
39
122
131
130
113
112
47
46
29
28
132
126
123
38
121
37
120
36
119
35
118
34
117
33
10v
C290
VCC3
MEM_DQM7
MEM_DQM6
MEM_DQM5
MEM_DQM4
MEM_DQM3
MEM_DQM2
MEM_DQM1
MEM_DQM0
SMT0603
A
6
SMT0603
R261
3
SMT0603
6,8
SMT0603
4
SMT0603
5
SMT0603
SMT0603
6
C284
0.1UF
C280
0.1UF
C279
0.1UF
C288
0.1UF
SMT0603
SMT0603
R268
10K
SMT0603
10K
C286
0.1UF
C277
0.1UF
C291
0.1UF
C285
0.1UF
C289
0.1UF
C283
0.1UF
C292
0.1UF
C287
0.1UF
R262
10K
SMT0603
SMT0603
SHEET
LAST
REV
9 OF 19
09/20/01
10:29 AM
B
D
C
B
A
D
C
B
A
19
7,14,16,17,19
7,19
7,19
7,19
7,10
7,8
12
12
12
12
12
12
12
12
11
11
11
11
11
7
7,10
7,10
19
10
7,10,19
7,19
8
6
6
XBUS_SD0
4
45
XBUS_SD1
33
44
XBUS_SD2
PS2_P17
43
XBUS_SD3
PCI_PME#
42
PCI_SERIRQ
40
XBUS_SD4
55
39
XBUS_SD5
46
38
XBUS_SD6
XBUS_IOCHRDY
37
81
83
82
67
78
79
80
66
77
19
85
84
87
90
89
86
91
88
17
15
13
14
16
54
47
49
51
34
36
35
32
20
31
30
29
28
27
26
25
24
23
22
21
XBUS_SD7
XBUS_SA11
XBUS_SA0
XBUS_SA1
XBUS_SA2
XBUS_SA3
XBUS_SA4
XBUS_SA5
XBUS_SA6
XBUS_SA7
XBUS_SA8
XBUS_SA9
XBUS_SA10
SMT0603
XBUS_RSTDRV
XBUS_SD[7:0]
XBUS_OSC
SER_TXDA
SER_RXDA
SER_RTS#A
SER_RI#A
SER_DTR#A
SER_DSR#A
SER_DCD#A
SER_CTS#A
FLOP_DSKCHG#
FLOP_WRTPRT#
FLOP_INDEX#
FLOP_TRK#0
FLOP_RDATA#
XBUS_TC
XBUS_DACK#1
XBUS_DACK#2
PS2_P16
XBUS_AEN
XBUS_IOW#
XBUS_IOR#
PCI_CLK0
XBUS_SA[18:0]
R504
1K
IO_PME#
SER_IRQ
P17
VSS_76
VSS_60
VSS_41
5
VSS_7
VTR
IRRX2
IRTX2
A20M
KBRST
MCLK
MDAT
KCLK
KDAT
TXD2/IRTX
RXD2/IRRX
CTS2#/SA13
RTS2#/SA12
RI2#/P16
DCD2#/P12
DTR2#/SA14
DSR2#/SA15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
DRVDEN1
DRVDEN0
DIR#
STEP#
DS0#
MTR0#
HDSEL#
WGATE#
WDATA#
DRQ1
DRQ2
DRQ3/P12
VCC_93
VCC_65
VCC_53
SMSC FDC37M812
IOCHRDY
RESET_DRV
D0
D1
D2
D3
D4
D5
D6
D7
BUSY
ALF#
STROBE#
INIT#
ERROR#
SLCT
PE
SLCTIN#
ACK#
CLOCKI
TXD1
RXD1
RTS1#/SYSOPT
RI1#
DTR1#
DSR1#
DCD1#
CTS1#
DSKCHG#
WPRT#
INDEX#
TRK0#
RDATA#
TC
DACK1#
DACK2#
DACK3#/P16
AEN
IOW#
IOR#
PCI_CLK
CS#/SA11
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
FLOP_DRVDEN#0
1
SER_DTR#B
SER_DSR#B
93
65
53
76
60
41
7
18
61
62
63
U50
7,10
7,10
6
VCC;14
SN74HC00AD
13
12
8
11
SN74HC00AD
U50
VCC;14
10
9
4
2
XBUS_DACK#1
U50
VCC
3
VCC;14
SN74HC00AD
1
XBUS_DACK#2
SN74HC00AD
U50
VCC;14
5
13
13
6,19
6,19
12
12
12
12
12
12
12
12
12
12
12
12
11
11
11
11
11
11
11
11
11
7,19
7,19
19
XBUS_AEN
VCC
7,10,19
7,10
7,10
7,13
7
7,19
7,19
7,10
VCC
XBUS_IOW#
XBUS_SA[18:0]
XBUS_SD[7:0]
PM_PWROK
XBUS_BIOSCS#
XBUS_MEMR#
XBUS_MEMW#
XBUS_SA[18:0]
SMT0603
SMT0603
SMT0603
SMT0603
1
2
3
4
5
6
36
7
8
14
15
16
17
18
19
20
21
XBUS_SA16
XBUS_SA15
XBUS_SA14
XBUS_SA13
XBUS_SA12
XBUS_SA11
XBUS_SA10
XBUS_SA9
XBUS_SA8
XBUS_SA7
XBUS_SA6
XBUS_SA5
XBUS_SA4
XBUS_SA3
XBUS_SA2
XBUS_SA1
XBUS_SA0
5
6
7
9
10
11
12
13
XBUS_SD2
XBUS_SD3
XBUS_SA1
XBUS_SA2
XBUS_SA3
XBUS_SA4
XBUS_SA5
XBUS_SA6
11
12
3
VCC;28
GND;14
22V10
VCC;28
GND;14
22V10
PLCC28
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0/CLK
U17
PLCC28
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0/CLK
U18
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
17
18
19
20
21
23
24
25
26
27
17
18
19
20
21
23
24
25
26
27
VPP
NC_38
NC_37
NC_29
NC_13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND_23
GND_39
VCC_30
11
38
37
29
13
25
26
27
28
32
33
34
35
23
39
30
31
12
+12
2
EMPTY
XBUS_SA18
VCC
16
13
9
10
7
XBUS_SA0
XBUS_SA11
6
XBUS_SD7
XBUS_SA10
5
XBUS_SA9
4
XBUS_SD6
XBUS_SA8
3
XBUS_SD5
2
XBUS_SD4
XBUS_SA7
4
16
3
2
XBUS_SD1
DU
VCC_31
MT28F004B5VG-6T
TSOP40
RP#
CE#
OE#
WE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
U16
XBUS_SD0
10
22
24
9
40
XBUS_SA17
10
SMSC Super I/O requires AEN to be high during DMA transfers
IR_TX
IR_RX
XBUS_A20GATE
XBUS_RCIN#
PS2_MOUSECLK
56
64
PS2_MOUSEDATA
PS2_KEYBDCLK
PS2_KEYBDDATA
SER_TXDB
57
58
59
96
SER_RXDB
SER_CTS#B
99
95
SER_RTS#B
SER_RI#B
SER_DCD#B
98
92
94
100
97
75
74
73
72
71
70
69
68
FLOP_DRVDEN#1
FLOP_DIR#
2
FLOP_STEP#
FLOP_DS#0
FLOP_MTR#0
FLOP_HDSEL#
FLOP_WGATE#
FLOP_WDATA#
XBUS_DREQ1
8
4
PS2_P12
XBUS_DREQ2
9
5
3
12
11
10
48
50
52
2
R323
100K
7,10
VCC
SMT0603
3
SMT0603
e
f
HDSP-7801
DP#
G#
F#
E#
D#
C#
B#
A#
d
g
a
c
dp
b
AN2
AN1
7,10
B
1
6
1
VCC
I4
I3
I2
I1
IO9
I11
I10
I9
I8
I7
I6
I5
BCD8
BCD4
BCD2
BCD1
R325
R322
R316
332
332
332
R320
332
R327
R318
332
332
R313
R329
332
332
7
3
2
4
5
8
9
10
HDSP-7801
DP#
G#
F#
E#
D#
C#
B#
A#
1
d
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
g
a
c
dp
b
AN2
AN1
Q7
D7
CLK
Q6
D6
LED_g
I0/CLK
Q5
Q4
D5
D4
Q3
LED_f
LED_e
D3
DRAWING
e
f
Q1
LED_d
Q2
Q0
D7
LATCH
D1
D2
D0
LED_b
LED_c
LED_a
IO8
6
1
VCC
09/20/01
10:29 AM
B
10 OF 19
SHEET
LAST
REV
Both parts programmed the same
DECODE
BCD-to-7 SEG DECODE
EN
EN6#
EN5#
EN4#
EN3#
EN2#
EN1#
EN0#
ADDRESS DECODE
22V10 Internal Programming
XBUS_SD[7:0]
SUPER I/O, BIOS, AND POST CODE DISPLAY
09/18/01
DATE
7
3
2
4
5
8
9
10
D6
BIOS UNLOCK
Intel Corporation
Chandler, AZ 85226
R326
R319
R315
R324
R328
R321
R312
R310
TITLE
332
332
332
332
332
332
332
332
XBUS_SD0
XBUS_SD1
XBUS_SD2
XBUS_SD3
XBUS_SD4
XBUS_SD5
XBUS_SD6
XBUS_SD7
E25
E26
VCC
SMT0603
U14
SMT0603
C324
0.1UF
4
SMT0603
5
SMT0603
6
C503
0.1UF
C315
0.1UF
C316
0.1UF
C314
0.1UF
C282
0.1UF
C281
0.1UF
C295
0.1UF
C325
0.1UF
D
C
B
A
D
C
B
6
6
13
6
6
6
7,19
6
6
6
6
6
7,14,16,17
6
IDE_PDCS1#_R
IDE_PDCS3#_R
IDE_ACTLED#
IDE_PDA0_R
IDE_PDA1_R
IDE_PDA2_R
XBUS_IRQ14
IDE_PDDACK#_R
IDE_PDDRQ_R
IDE_PDIORDY_R
IDE_PDIOR#_R
IDE_PDIOW#_R
PCI_RST#
IDE_PDD0_R
IDE_PDD1_R
IDE_PDD2_R
IDE_PDD3_R
IDE_PDD4_R
IDE_PDD5_R
IDE_PDD6_R
IDE_PDD7_R
IDE_PDD8_R
IDE_PDD9_R
IDE_PDD10_R
IDE_PDD11_R
IDE_PDD12_R
IDE_PDD13_R
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
33.2
R240
SMT0603
R224
SMT0603
R235
SMT0603
R297
SMT0603
R241
SMT0603
R223
SMT0603
R254
SMT0603
R154
SMT0603
R234
SMT0603
R226
SMT0603
R222
SMT0603
R239
SMT0603
R250
SMT0603
R140
SMT0603
R249
SMT0603
R237
SMT0603
R236
SMT0603
R228
SMT0603
R225
SMT0603
R253
SMT0603
R255
SMT0603
R252
SMT0603
R230
SMT0603
R242
SMT0603
R256
SMT0603
R227
SMT0603
R257
SMT0603
IDE_PDCS1#
IDE_PDCS3#
IDE_PDASP#
IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_PDIRQ
IDE_PDDACK#
IDE_PDDRQ
IDE_PDIORDY
IDE_PDIOR#
IDE_PDIOW#
IDE_RST#
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
11
11
11
11
11
11
11
11
11
11
11
11
11
IDE_PDD[15:0]
5
11
11
11
11
11
11
11
11
11
11
11
IDE_PDASP#
IDE_PDCS1#
IDE_PDA0
IDE_PDA1
IDE_PDIRQ
IDE_PDDACK#
IDE_PDIORDY
IDE_PDIOR#
IDE_PDIOW#
IDE_PDDRQ
IDE_RST#
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
VCC
VCC
14
16
18
20
22
24
26
28
30
32
34
36
38
40
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2.54MM HEADER
12
8
7
10
6
5
9
4
3
11
2
1
J17
PRIMARY IDE
4
IDE_PDD9
IDE_PDD8
IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
IDE_PDD10
IDE_PCSEL0#
2. Trace width between IDE and CompactFlash connectors should be less than 2"
1. Series terminating resistor of each data signal should be located within 1" of the chipset
ROUTING NOTES - IDE
R298
1K
IDE_PDD15
SMT0603
R229
SMT0603
R251
SMT0603
SMT0603
5.62K R238
R294
1K
SMT0603
SMT0603
33.2
5.62K R293
33.2
SMT0603
IDE_PDD14_R
R295
549
IDE_PDD15_R
VCC
SMT0603
IDE_PDD[15:0]_R
EMPTY
R296
10K
4
10v
11
11
11
11
VCC
IDE_PDIAG#
IDE_PDASP#
IDE_PDIORDY
IDE_RST#
IDE_PDIRQ
IDE_PDIOW#
IDE_PDIOR#
IDE_PDCS3#
IDE_PDD10
IDE_PDD9
IDE_PDD8
E24
E23
CF MASTER
CONNECT TO MAKE CF MASTER
11
11
11
11
11
11
11
11
IDE_PDD15
IDE_PDD14
IDE_PDD13
IDE_PDD12
IDE_PDD11
3
SMT0603
VCC
14
15
16
17
40
41
42
25
50
VCC
IDE_PDD2
IDE_PDD1
IDE_PDD0
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
3
22
24
26
28
30
32
34
23
25
27
29
31
33
20
21
19
16
15
18
14
13
17
12
8
7
10
6
9
4
5
11
2
3
J16
1
2
IDE_IOCS16#
IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_PDCS1#
2
11
11
11
11
11
2.54MM HEADER
3M N7E50-7516HG-40
24
23
22
21
20
19
49
48
47
46
45
44
18
13
39
43
12
38
8
33
11
7
32
37
6
31
36
5
30
9
4
29
10
3
28
35
2
27
34
1
26
J18
COMPACTFLASH
ONE DRIVE ONLY
FLOPPY
4.7UF
C312
VCC
IDE_PDCS3#
IDE_PDA2
IDE_PDIAG#
IDE_IOCS16#
TANT_3528
A
6
5
SMT0603
6
C313
0.1UF
IDE_PCSEL1#
R314
549
R263
1K
SMT0603
R260
1K
SMT0603
SMT0603
VCC
FLOP_DSKCHG#
FLOP_HDSEL#
FLOP_RDATA#
FLOP_WRTPRT#
FLOP_TRK#0
FLOP_WGATE#
FLOP_WDATA#
FLOP_STEP#
FLOP_DIR#
FLOP_DS#0
FLOP_MTR#0
FLOP_INDEX#
FLOP_DRVDEN#1
FLOP_DRVDEN#0
1
10
10
10
10
10
10
10
10
10
10
10
10
10
10
B
1
DRAWING
IDE, COMPACTFLASH, AND FLOPPY CONNECTORS
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
R264
1K
VCC
SMT0603
VCC
R265
1K
VCC
SMT0603
VCC
R266
1K
09/20/01
10:29 AM
B
11 OF 19
SHEET
LAST
REV
D
C
B
A
D
C
B
7
7
7
7
10
10
10
10
6
PS2_KEYBDDATA
PS2_KEYBDCLK
PS2_MOUSEDATA
PS2_MOUSECLK
USB_P1+_R
USB_P1-_R
USB_P0+_R
USB_P0-_R
VCC
4.75K R41
C220
47PF
C219
47PF
USB_P1_OC#
C231
VCC
4.75K R38
7
SMT0603
47PF
SMT0603
C224
VCC
47PF
SMT0603
VCC
VCC
SMT0603
USB_P0_OC#
4.75K R40
7
SMT0603
A
4.75K R39
1
R160
R159
R165
R163
BLM21P300SPT
FB12
BLM21P300SPT
FB9
BLM21P300SPT
FB11
BLM21P300SPT
FB10
SMT0603
27.4
SMT0603
27.4
SMT0603
27.4
SMT0603
27.4
SMD100-2
F2
FUSE=1A
C74
0.001UF
C86
2
R36
475K
PS2_KEYBDDATA_L
PS2_KEYBDCLK_L
PS2_MOUSEDATA_L
PS2_MOUSECLK_L
0.001UF
SMT0603
SMT0603
SMT0603
C81
C82
16v 22UF
USB1_VCC_F
TANT_D
TANT_D
R35
562K
R42
475K
SMT0603
SMT0603
SMT0603
SMT0603
R54
562K
R157
15K
R156
15K
R164
5
15K
FB15
BLM21P300SPT
R162
15K
SMT0603
SMT0603
C75
0.1UF
C77
0.1UF
FB14
USB1_VCC_F_L
USB0_VCC_F_L
SMT0603
BLM21P300SPT
BLM21P300SPT
16v 22UF
USB1_GND 4
USB_P1+ 3
USB_P1- 2
CLK_T
5_T
CLK_B
5_B
NC6_T
NC6_B
6_B
1
USB0_GND 8
USB_P0+ 7
4_T
2_T
1_T
3_T
RJMG-7326-71-01
GND_B
DATA+B
DATA-B
VCC_B
GND_T
DATA+T
DATA-T
VCC_T
J7
NC_B
+5V_F_B
4_B
2_B
1_B
1 of 2
SGND_B3
SGND_B4
SGND_T1
SGND_T2
DUAL USB
9
10
11
12
VCC
4
KEYBD
MOUSE
5. The pairs should be atleast 25 mils from other traces and the other pair
4. The pairs should stay on the same layer, adjacent to ground, to the extent possible
3. Series terminating resistor of each data signal should be located within 1" of the chipset
2. Each trace in the pair must be routed exactly the same, and have the same length
1. Each pair should be routed with 90ohm differential impedence
ROUTING NOTES - USB DIFFERENTIAL PAIRS
GND_B
3_B
DATA_B
J4
+5V_F_T
NC_T
DATA_T
GND_T
STACKED PS/2
FB1
6_T
5
USB_P0- 6
BLM21P300SPT
USB0_VCC_F
SMT0603
C50
470PF
C34
470PF
2
FUSE=1.5A
FB13
F1
FUSE=1A
SMD150-2
F3
BLM21P300SPT
SMT0603
SMD100-2
SMT0603
SMT0603
SMT0603
C59
470PF
470PF C60
SMT0603
SMT0603
C58
470PF
470PF C57
PS2_VCC_F
PS2_VCC_F_L
C61
0.1UF
1
VCC
+12
10
10
10
10
10
10
10
10
7
10
10
10
10
10
10
10
10
16
15
14
13
12
SER_RTS#A
SER_TXDA
SER_CTS#A
SER_DTR#A
SER_RI#A
18
17
16
15
14
SER_DSR#B
SER_RXDB
SER_RTS#B
SER_TXDB
SER_CTS#B
13
12
SER_DTR#B
SER_RI#B
-12
19
SER_DCD#B
PM_RI#
17
19
SER_RXDA
SMT0603
18
SMT0603
SER_DSR#A
SER_DCD#A
3
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
2
Q1
3
3VSB
2N3904
1
3
10K
10K
R6
SMT0603
R8
SMT0603
2
2
-12;10
+12;1
SN75C185DWR
GND;11
VCC;20
U3
2
Q2
3
1
-12;10
2N3904
GND;11
+12;1
SN75C185DWR
VCC;20
U2
C24
SMT0603
SMT0603
VCC
SMT0603
4
SMT0603
SMT0603
5
SMT0603
RI
CGND2
CGND1
GND
5
4
DTR
SOUT
3
SIN
2
1
DCD
RI
CGND2
GND
5
CGND1
4
DTR
SOUT
3
SIN
2
1
DCD
9P SUB-D PLUG
11
10
9
CTS
8
RTS
7
DSR
6
J6
9P SUB-D PLUG
11
10
9
CTS
8
RTS
7
DSR
6
J5
COM B
COM A
1
B
1
DRAWING
SERIAL, KEYBOARD, MOUSE, USB CONNECTORS
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
C33
R13
10K
C25
100PF
R7
C23
100PF
2.2K
100PF
R5
C32
100PF
6
C72
0.1UF
C68
0.1UF
C47
0.1UF
C46
0.1UF
C49
0.1UF
C48
0.1UF
SMT0603
C31
100PF
2.2K
C22
C30
100PF
100PF
C20
C29
100PF
100PF
C21
100PF
C19
C28
100PF
C18
100PF
100PF
C27
100PF
100PF
C26
100PF
SMT0603
G5
G4
G3
G2
G1
FB8
SMT0603
SMT0603
SMT0603
SMT0603
09/20/01
10:29 AM
B
12 OF 19
SHEET
LAST
REV
D
C
B
A
D
C
6
FP_RST#
VR_PWRGD
PS_POK
ITP_RST#
3VSB
13
18
13
4
3VSB
SMT0603
R81
VCC3
22.1K
SMT0603
B
SMT0603
R506
10K
221
1
4148
SOT23
3
3VSB
D1
C99
1UF
U7
R94
8
3VSB;14
U8
-12
2
3VSB;14
U8
3VSB;14
U8
U7
+12
SN74LVC14AD
11
3VSB;14
U8
SN74LVC06AD
13
3VSB;14
SN74LVC14AD
13
SMT0603
3VSB;14
U8
5
10
12
12
8
4
VCC3
SN74LVC14AD
3
SN74LVC14AD
9
SN74LVC14AD
1
SN74LVC06AD
9
3VSB;14
SMT1206
PM_SUSC#
SMT0603
5VSB
221
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
U7
U7
U7
U7
VCC3
SN74LVC06AD
1
3VSB;14
SN74LVC06AD
3
3VSB;14
SN74LVC06AD
5
3VSB;14
SN74LVC06AD
11
3VSB;14
R505
2
12
2
4
6
10
VCC
ATX PWR CONN
1
J13
11
VCC3
VCC
SN74LVC14AD
5
6
+12
3VSB;14
U8
5VSB
1
2N7002
4
2
3
Q4
VCC2_5
1
2N7002
2
3
Q3
7,14
13
3VSB
PM_RSMRST#
PS_POK
2
VCC
FP_RSMRST#
PM_PWRBTN#
PM_EXTSMI#
IDE_ACTLED#
1
2
1
SMT0603
Power LED
SMT0603
R309
150
18
16
14
12
10
8
6
4
2
17
15
13
11
9
7
5
3
1
IrDA
SMBus 2
SMBus 1
20
19
J19
2.54MM HEADER, R/A
3
PWRLED +
SMT0603
+12
VCC_SMBIF_F
E12
E13
E14
E15
E16
E3
E5
E7
E9
BLM21P300SPT
FB19
BLM21P300SPT
FB20
VCC_IRDA_F
VCC_SMBIF_F
E11
E1
E2
E4
E6
E8
E10
FB23
BLM21P300SPT
VCC
C323
2
FB21
R308
VCC
VCC
3
1
IR_TX
IR_RX
VCC
10
10
4,6,8,9,14,19
4,6,8,9,14,19
AC97SPKR
MX_SPKR
speaker
S1
15
7,15
B
1
1
DRAWING
POWER AND FRONT PANEL CONNECTORS
2
SMB_DATA
SMB_CLK
EMPTY
SMT0603
2.2K R300
SMT0603
2.2K R301
F4
FUSE=1A
1
SMD100-2
2N3904
VCC
Intel Corporation
Chandler, AZ 85226
2
Q12
09/18/01
DATE
TITLE
C303
16v 22UF
VCC_IRDA
13
SMT1206
R306
SMT1206
R307
SMT0603
FP_RST#
BLM21P300SPT
75
150
75
BLM21P300SPT
FB17
SMT0603
SMT0603
YEL
Standby LED
7,10
4
5VSB
PM_PWROK
CPU_PWRGD
7,19
7,19
11
VCC
HDLED
SLP
PWR
RST
7
SMT0603
R87
SMT0603
A
C114
0.1UF
C116
0.1UF
C115
1UF
4.75K R86
SMT0603
SMT1206
C275
.1UF
C265
.1UF
SMT0603
SMT0603
SMT0603
VCC3
SMT0603
R74
1K
VCC3
SMT0603
SMT0603
VCC -12
SMT0603
R72
10K
R80
1K
C317
0.01UF
C319
0.01UF
C320
0.01UF
C322
0.01UF
C321
0.01UF
C318
0.01UF
+
SPKR
+
+
+
SMT0603
SMT0603
SMT0603
C273
0.1UF
0.01UF
SMT0603
470PF C304
SMT0603
5VSB
SMT0603
2
TANT_D
3
470PF C294
4
SMT0603
5
SMT0603
R317
332
D8
R305
332
GRN
D4
10K
C264
.1UF
C274
.1UF
C268
.1UF
C276
.1UF
C263
.1UF
6
470PF C297
+
09/20/01
10:29 AM
B
13 OF 19
SHEET
LAST
REV
D
C
B
A
D
C
B
4
10
11
12
SLOT 1
SLOT 2
SLOT 3
7
ENET
DEV NUM
SLOT
440MX
6
A, B, C, D
AD23
C, D, A, B
B, C, D, A
D, A, B, C
AD22
AD21
A, B, C, D
INT[A,B,C,D]#
AD15
AD18
IDSEL
PCI RESOURCES
3
2
1
4
0
PCICLK
REQ/GNT
3
2
1
0
n/a
J2
PCI_PERR#
PCI_SERR#
G1
PCI_RST#
PCI_CLK4
E17
DIS
E18
C9
PM_SUSSTAT#
A10
SMB_DATA
SMT0603
SMB_CLK
B10
C8
C5
A6
PCI_PME#
PCI_CLKRUN#
A9
PM_RSMRST#
B9
J3
C2
PCI_GNT#0
VCC3
C3
PCI_REQ#0
5
H2
A2
PCI_IRQ#D
ENA
R76
J1
PCI_PAR
E19
1K
H1
PCI_STOP#
A4
H3
PCI_DEVSEL#
R45
G3
PCI_TRDY#
SMT0603
F1
PCI_IRDY#
100
F2
PCI_FRAME#
B8
PCI_AD31
C4
A8
PCI_AD30
PCI_CBE#3
C7
PCI_AD29
F3
C6
PCI_AD28
PCI_CBE#2
B6
PCI_AD27
L3
B5
PCI_AD26
PCI_CBE#1
ENET ENA/DIS
7
4,6,8,9,13,19
4,6,8,9,13,19
7,19
7,10,16,17,19
7,13
8
7,11,16,17
7,19
7,19
7,16,17,19
16,17,19
7,16,17,19
7,16,17
7,16,17,19
7,16,17,19
7,16,17,19
7,16,17,19
7,16,17,19
7,16,17
7,16,17
7,16,17
7,16,17
A5
PCI_AD25
M4
B4
PCI_AD24
B1
B2
C1
PCI_AD22
PCI_AD23
PCI_AD21
PCI_CBE#0
PCI_AD15
PCI_AD18
D3
E3
D1
PCI_AD17
D2
K1
PCI_AD16
PCI_AD20
L2
PCI_AD15
PCI_AD19
L1
N3
PCI_AD9
PCI_AD14
P3
PCI_AD8
M3
N4
PCI_AD7
M2
P4
PCI_AD6
PCI_AD13
M5
PCI_AD5
PCI_AD12
N5
PCI_AD4
N2
P5
PCI_AD3
M1
P6
PCI_AD2
PCI_AD11
M7
PCI_AD1
PCI_AD10
N7
PCI_AD0
SMBD
SMBCLK
SMBALRT#
CLKRUN#
RDN
RDP
TDN
TDP
SPEEDLED
X2
X1
RBIAS100
RBIAS10
VREF
TO
TI
TCK
TEXEC
TEST
FLWE#
FLOE#
FLCS#/AEN
EECS
FLD0
FLD1
FLD2
FLD3
FLD4
FLD5
FLD6
FLD7
FLA0/PCIMODE#
FLA1/AUXPWR
FLA2
FLA3
FLA4
FLA5
FLA6
FLA7/CLKEN
FLA8/IOCHRDY
FLA9/MRST
FLA10/MRING#
FLA11/MINT
FLA12/MCNTSM#
FLA13/EEDI
FLA14/EEDO
FLA15/EESK
FLA16/CLK25
82559
1 of 2
CSTSCHG/WOL
PME#
ALTRST#
ISOLATE#
CLK
RST#
GNT#
REQ#
IDSEL
SERR#
PERR#
INTA#
PAR
STOP#
DEVSEL#
TDRY#
IRDY#
FRAME#
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
P11
N11
B13
B14
C12
B12
D12
D14
D13
A13
M9
M8
N9
P7
F14
F13
F12
G12
H14
H13
H12
J14
J13
J12
K14
L14
L13
L12
M14
M13
N14
P13
N13
M12
M11
P10
N10
M10
P9
E14
E13
C14
C13
B11
C11
619
549
R29
4
SMT0603
R28
SMT0603
R30
SMT0603
66.5K
RJ45_RDN
RJ45_RDP
RJ45_TDN
RJ45_TDP
RJ45_SPEEDLED#
RJ45_ACTLED#
RJ45_LINKLED#
100
100
SMT0603
R49
SMT0603
R46
Y2
25.000MHZ
4
3
2
1
U6
NC
7
6
ORG
VCC3;8
93C46
DO
DI
CLK
EECS
VCC3
R75
TANT_3528
10v
4.7UF
C66
VCC3
SMT0603
21
TD+
17
RDC
18
RD-
19
RD+
20
TD-
22
TDC
100Base-T Magnetics
221
R37
RJMG-7326-71-01
2 of 2
J7
75
0.01
13
LED2
LED1
14
16
15
AMB
J8
J7
J6
J5
J4
J3
J2
J1
YEL
VCC3
GRN
RJ-45
3
SMT0603
SMT0603
C71
SMT0603
SMT0603
2
2
SMT0603
SMT0603
1K
A12
C73
10PF
LILED
SMT0603
C76
0.1UF
ACTLED
SMT0603
VIO
SMT0603
G2
C69
0.1UF
PCI_AD[31:0]
C97
0.1UF
7,16,17
SMT0603
A
6. The pairs should stay on the same layer, adjacent to ground, to the extent possible
5. The pairs should be atleast 25 mils from other traces and the other pair
4. The trace length of the pairs should be minimized, less than two inches preferred
SMT0603
C88
3. The termination resistor between the signals in the pair should be close to the 82559
C95
0.1UF
SMT0603
2. Each trace in the pair must be routed exactly the same, and have the same length
C105
0.1UF
0.1UF
1. Each pair should be routed with 100ohm differential impedence
C89
0.1UF
U5
SMT0603
ROUTING NOTES - ETHERNET DIFFERENTIAL PAIRS
C78
0.1UF
221
25
23
VCC
SMT0603
R50
SMT0603
3
C100
0.1UF
26
24
C70
0.1UF
4
C93
0.1UF
5
C87
0.1UF
6
C107
22PF
C108
22PF
C106
0.1UF
R53
0.1UF
332
SMT0603
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VCC26
VCC25
VCC24
VCC23
VSS25
VSS26
VCC22
VCC21
VCC20
VCC19
VCC18
VCC17
VCC16
VCC15
VCC14
VCC13
VCC12
VCC11
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VCCPP6
VCCPP5
VCCPP4
VCCPP3
VCCPP2
VCCPP1
VCCPT
VCCPL4
VCCPL3
VCCPL2
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSSPP6
VSSPP5
VSSPP4
VSSPP3
VSSPP2
VSSPP1
VSSPL4
VSSPL3
VSSPL2
VSSPL1
NC10
NC9
NC8
VCCPL1
82559
2 of 2
VSSPT
NC4
NC3
NC7
NC6
NC5
E12
J11
L10
L9
L5
L4
K11
K4
G5
K10
K9
K8
K7
K6
K5
J10
J9
J8
J7
J6
J5
H8
H7
H6
H5
G6
P2
N6
K3
E1
A7
A3
A11
P12
N8
K13
G13
P14
P1
L8
L7
J4
H4
B
1
DRAWING
82559 ETHERNET
Intel Corporation
Chandler, AZ 85226
L11
L6
H11
G11
E11
E4
F11
F4
D11
D8
D7
D6
D5
D4
H10
H9
G10
G9
G8
G7
F10
F9
F8
F7
F6
F5
E10
E9
E8
E7
E6
E5
N1
M6
K2
E2
B7
B3
P8
N12
K12
G14
C10
D9
A14
NC2
NC1
NC0
09/18/01
DATE
TITLE
A1
G4
D10
U5
VCC3
1
09/20/01
10:29 AM
B
14 OF 19
SHEET
LAST
REV
D
C
B
A
D
C
B
BLM21P300SPT
FB7
LINEOUT_L
LINEOUT_R
AC97SPKR
CDIN_REF
CDIN_L
CDIN_R
MICIN
LINEIN_L
VCC3
VCC
15
15
13
15
15
15
15
15
AGND
6
R4
SMT0603
AVCC
10K
R31
AGND
C16
C37
C36
C14
C6
AGND
SMT1206
1UFSMT1206
C8
1UF
SMT1206
1UF
SMT1206
1UFSMT1206
C45
1UFSMT1206
C44
1UF
SMT1206
1UF
SMT1206
1UFSMT1206
C15
1UF
AGND
AGND
C51
SMT1206
1UF
VCC3
7
4
9
1
42
26
38
25
40
44
43
39
41
35
36
37
13
15
14
16
17
19
18
20
22
21
23
24
12
DVSS2
DVSS1
DVDD2
DVDD1
AVSS2
AVSS1
AVDD2
AVDD1
NC_40
NC_44
NC_43
AGND
0
SMT0603
R17
RESET#
AFILT_1
AFILT_2
FILT_L
FILT_R
RX3D
CX3D
VREF
VREF_OUT
XTAL_OUT
XTAL_IN
CHAIN_IN
MODE
CS0
CS1
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
29
30
32
31
33
34
27
28
3
2
47
48
45
46
6
10
8
5
11
5
C9
C13
SMT0603
SMT0603
2200PF
C3
2200PF C10
SMT1206
1UFSMT1206
C5
1UF
SMT0603
0.1UF
PLACE CLOSE TO AUDIO IC
AC97 CODEC
LNLVL_OUT_L
LNLVL_OUT_R
LINE_OUT_L
LINE_OUT_R
MONO_OUT
PHONE_IN
AUX_R
AUX_L
VIDEO_L
VIDEO_R
CD_GND_REF
CD_L
CD_R
MIC2
MIC1
LINE_IN_L
LINE_IN_R
PC_BEEP
U1
2
1
LINEIN_R
SMT0603
AGND
C63
C64
AGND
SMT0603
22PF
SMT0603
22PF
AGND
SMT1206
AGND
MIC_VREF
AC_BITCLK
AC_SYNC
AC_SDIN0
AC_SDOUT
AC_RST#
AGND
15
7
7
7,19
7
7
5. The SPKROUT traces from the audio amplifier need to be sized to handle 1A each
SMT0603
15
SMT0603
SMT0603
4. Non-audio signals should be kept 25mils from audio signals and also AGND
SMT0603
SMT0603
4.75K R18
AGND
4
3. AGND should be a copper pour on the component side surrounding the audio traces and components
24.576MHZ
C2
0.1UF
R3
2. AVCC should be a power plane division under the audio portion of the IC and all audio traces and components
C4
0.1UF
47.5K
SMT0603
1. The audio portion of the codec includes all signals coming from pins 13 thru 44 of the codec
SMT0603
Y1
AVCC
C1
1UF
SMT0603
SMT1206
ROUTING NOTES - AUDIO SIGNALS
SMT1206
MX_SPKR
C12
0.1UF
C17
0.1UF
C11
0.1UF
1K
C35
1UF
C7
1UF
15
15
15
15
15
15
15
15
15
CDIN_R
CDIN_L
CDIN_REF
MICIN
MIC_VREF
LINEIN_L
LINEIN_R
LINEOUT_L
LINEOUT_R
10K
10K
R515
SMT0603
R514
SMT0603
R516
10K
SMT0603
SMT0603
C505
C504
SMT0603
0.1UF
SMT0603
0.1UF
AGND
FB16
22.1K
22.1K
BLM21P300SPT
+12
SMT0603
SMT0603
R43
SMT0603
R15
AGND
AGND
AGND
3
R16
V+
14
U4
1/2 LM1788
BIAS
AGND
AGND
AGND
C79
13
AGND
AGND
SPKROUT_L
SPKROUT_R
AGND
LM1877M-9
2
SMT0603
0.01UF
R44
C52
SMT0603
0.01UF
SMT0603
AGND
232K
SMT0603
232K R509
AGND
C500
16v 22UF
9
8
1
6
7
SMT0603
1/2 LM1788
SMT0603
232K R510
232K
VCC_AUDAMP
AGND
AGND
TANT_D
3
1K
2.2K
1K
1K
EEUFC1E221B
R23
1K
SMT0603
R20
SMT0603
1K SMT0603
R22
1K
SMT0603
R9
SMT0603
R10
SMT0603
R11
SMT0603
R12
EEUFC1E221B
2
FB4
FB3
BLM21P300SPT
FB2
BLM21P300SPT
FB5
2
4
3
2
1
J8
AGND
1
2
10
11
3
AGND
1
2
10
11
3
1
2
10
AGND
B
AC97 AUDIO
09/18/01
DATE
TITLE
3
11
3.5MM PHONO
J1
3.5MM PHONO
J2
3.5MM PHONO
J3
MIC IN
LINE IN
1
09/20/01
10:29 AM
B
15 OF 19
SHEET
LAST
REV
HEADPHONE / SPKR OUT
1
DRAWING
Intel Corporation
Chandler, AZ 85226
CD IN
SPKROUT_L_AMP_F
2MM HEADER
SPKROUT_R_AMP_F
BLM21P300SPT
SPKROUT_L_AMP_C
BLM21P300SPT
FB6
BLM21P300SPT
SPKROUT_R_AMP_C
AGND
AGND
C502
AGND
R517
10K
C80
0.1UF
4
SMT0603
C41
100PF
C39
0.01UF
C40
100PF
C38
100PF
SMT0603
5
R19
232K
GND1
GND2
GND3
GND4
GND5
GND6
C53
100PF
C501
6
SMT0603
3
4
5
10
11
12
R21
232K
SMT0603
SMT1206
7,13
SMT0603
C54
100PF
SMT0603
SMT1206
A
C62
0.1UF
C65
0.1UF
R24
232K
0.1UF
R507
2.7
SMT0603
0.1UF
R508
2.7
25v
220UF
C55
C67
100PF
220UF
25v
C56
D
C
B
A
D
C
B
PCI_CBE#1
PCI_SERR#
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY#
PCI_CBE#2
PCI_CBE#3
PCI_REQ#1
PCI_CLK1
PCI_IRQ#D
7
4
ENET
10
11
12
SLOT 1
SLOT 2
SLOT 3
6
DEV NUM
SLOT
440MX
AD23
AD22
AD21
AD15
AD18
IDSEL
C, D, A, B
B, C, D, A
A, B, C, D
D, A, B, C
A, B, C, D
INT[A,B,C,D]#
PCI RESOURCES
PCI_AD[31:0]
SMT0603
2.74K R182
7,14,16,17
VCC
7,14,16,17
7,14,16,17,19
14,16,17,19
7,16,17,19
7,14,16,17,19
7,14,16,17,19
7,14,16,17
7,14,16,17
7,19
8
7,14,16,17,19
7,16,17,19
PCI_IRQ#B
3
2
1
4
0
PCICLK
REQ/GNT
3
2
1
0
n/a
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_AD10
PCI_AD12
PCI_AD14
PCI_AD17
PCI_AD19
PCI_AD21
PCI_AD23
PCI_AD25
PCI_AD27
PCI_AD29
PCI_AD31
VCC
VCC3
D62
D61
D60
D59
D58
D57
D56
D55
D54
D53
D52
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
PCI, 32-BIT, 5V
+5V_D62
+5V_D61
ACK64#
+5V_D59
AD1
GND_D57
AD3
AD5
3_3V_B54
AD7
AD8
GND_B49
AD10
AD12
GND_B46
AD14
C_BE1#
3_3V_B43
SERR#
3_3V_B41
PERR#
LOCK#
GND_B38
DEVSEL#
3_3V_B36
IRDY#
GND_B34
C_BE2#
AD17
3_3V_B31
AD19
AD21
GND_B28
AD23
C_BE3#
3_3V_B25
AD25
AD27
GND_B22
AD29
AD31
+5V_B19
REQ#
GND_B17
CLK
GND_B15
RSV_B14
GND_B13
GND_B12
PRSNT2#
RSV_B10
PRSNT1#
INTD#
INTB#
+5V_BO6
+5V_B05
TD0
GND
TCK
-12V
J11
+12
+5V_C62
+5V_C61
REQ64#
+5V_C59
AD0
AD2
GND_C56
AD4
AD6
3_3V_C53
C_BEO#
AD9
GND_A48
AD11
AD13
3_3V_A45
AD15
PAR
GND_A42
SBO#
SDONE
3_3V_A39
STOP#
GND_A37
TRDY#
GND_A35
FRAME#
3_3V_A33
AD16
AD18
GND_A30
AD20
AD22
3_3V_A27
IDSEL
AD24
GND_A24
AD26
AD28
3_3V_A21
AD30
PME#
GND_A18
GNT#
+5V_A16
RST#
RSV_A14
GND_A13
GND_A12
RSV_A11
+5V_A10
RSV_A09
+5V_A08
INTC#
INTA#
+5V_A05
TDI
TMS
+12V
TRST#
-12
5
PCI_AD20
A29
PCI_AD4
C55
PCI_AD2
PCI_AD0
C58
C62
C61
C60
C59
C57
C56
PCI_AD6
C54
C53
C52
A49
PCI_AD9
PCI_AD11
A47
A48
PCI_AD13
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
PCI_AD15
PCI_AD16
A32
A33
PCI_AD18
A31
A30
PCI_AD22
A28
A27
A26
A25
PCI_AD24
PCI_AD26
A23
A24
PCI_AD28
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
PCI_AD21
PCI_PME#
PCI_GNT#1
PCI_RST#
PCI_IRQ#C
PCI_AD30
3VSB
A07
VCC3
PCI_IRQ#A
VCC
A06
A05
A04
A03
A02
A01
+12
7,14,16,17
7,14,16,17
SMT0603
VCC
7,14,16,17,19
7,14,16,17,19
7,14,16,17,19
2.74K R183
PCI_CBE#0
PCI_PAR
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
7,10,14,16,17,19
7,19
7,11,14,16,17
7,16,17,19
7,16,17,19
SMT0603
B01
C257
R110
100
A
SMT0603
SMT0603
C141
0.01UF
C85
VCC -12
SMT0603
SMT0603
VCC3
SMT0603
SMT0603
4
4
DEV NUM
7
4
10
11
12
SLOT
440MX
ENET
SLOT 1
SLOT 2
SLOT 3
AD23
AD22
AD21
AD15
AD18
IDSEL
C, D, A, B
B, C, D, A
A, B, C, D
D, A, B, C
A, B, C, D
INT[A,B,C,D]#
PCI RESOURCES
3
2
1
0
REQ/GNT
n/a
VCC
VCC3
PCI_AD[31:0]
SMT0603
B48
D53
PCI_AD7
+12
-12
PCI, 32-BIT, 5V
+5V_D62
+5V_D61
ACK64#
+5V_D59
AD1
GND_D57
AD3
AD5
3_3V_B54
AD7
AD8
GND_B49
AD10
AD12
GND_B46
AD14
C_BE1#
3_3V_B43
SERR#
3_3V_B41
PERR#
LOCK#
GND_B38
DEVSEL#
3_3V_B36
IRDY#
GND_B34
C_BE2#
AD17
3_3V_B31
AD19
AD21
GND_B28
AD23
C_BE3#
3_3V_B25
AD25
AD27
GND_B22
AD29
AD31
+5V_B19
REQ#
GND_B17
CLK
GND_B15
RSV_B14
GND_B13
GND_B12
PRSNT2#
RSV_B10
PRSNT1#
INTD#
INTB#
+5V_BO6
+5V_B05
TD0
GND
TCK
-12V
3
J10
+5V_C62
+5V_C61
REQ64#
+5V_C59
AD0
AD2
GND_C56
AD4
AD6
3_3V_C53
C_BEO#
AD9
GND_A48
AD11
AD13
3_3V_A45
AD15
PAR
GND_A42
SBO#
SDONE
3_3V_A39
STOP#
GND_A37
TRDY#
GND_A35
FRAME#
3_3V_A33
AD16
AD18
GND_A30
AD20
AD22
3_3V_A27
IDSEL
AD24
GND_A24
AD26
AD28
3_3V_A21
AD30
PME#
GND_A18
GNT#
+5V_A16
RST#
RSV_A14
GND_A13
GND_A12
RSV_A11
+5V_A10
RSV_A09
+5V_A08
INTC#
INTA#
+5V_A05
TDI
TMS
+12V
TRST#
2
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
C52
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
+12
2
D62
D61
D60
D59
D58
D57
D56
PCI_AD3
PCI_AD1
D55
PCI_AD5
D54
D52
PCI_AD8
B49
B47
PCI_AD10
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
PCI_AD12
PCI_AD14
PCI_AD17
B30
B31
B29
PCI_AD19
B28
B27
B26
PCI_AD21
PCI_AD23
B24
PCI_AD25
B25
B23
PCI_AD27
B22
B21
PCI_AD29
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B20
VCC -12
PCI_AD31
VCC3
3
2
1
4
0
PCICLK
PCI_CBE#1
PCI_SERR#
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY#
PCI_CBE#2
PCI_CBE#3
PCI_REQ#2
PCI_CLK2
PCI_IRQ#A
2.74K R181
7,14,16,17
VCC
7,14,16,17
7,14,16,17,19
14,16,17,19
7,16,17,19
7,14,16,17,19
7,14,16,17,19
7,14,16,17
7,14,16,17
7,19
8
7,16,17,19
7,16,17,19
3
PCI_IRQ#C
C256
5
SMT0603
SMT0603
C139
VCC
PCI_IRQ#B
PCI_AD22
PCI_PME#
PCI_GNT#2
PCI_RST#
PCI_IRQ#D
7,10,14,16,17,19
7,19
7,11,14,16,17
7,14,16,17,19
7,16,17,19
7,14,16,17
7,14,16,17
B
1
1
DRAWING
PCI CONNECTORS 1 AND 2
SMT0603
VCC
7,14,16,17,19
7,14,16,17,19
7,14,16,17,19
2.74K R180
PCI_CBE#0
PCI_PAR
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
Intel Corporation
Chandler, AZ 85226
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD6
PCI_AD9
PCI_AD11
PCI_AD13
PCI_AD15
PCI_AD16
PCI_AD18
PCI_AD20
PCI_AD22
PCI_AD24
PCI_AD26
PCI_AD28
PCI_AD30
3VSB
09/18/01
DATE
TITLE
VCC3
SMT0603
6
SMT0603
SMT0603
C103
0.01UF
C142
0.01UF
0.01UF
C230
0.01UF
C182
0.01UF
SMT0603
SMT0603
0.01UF
C92
0.01UF
SMT0603
SMT0603
C102
0.01UF
C140
0.01UF
0.01UF
C229
0.01UF
0.01UF
C181
0.01UF
SMT0603
SMT0603
C84
0.01UF
C91
0.01UF
R109
100
09/20/01
10:29 AM
B
16 OF 19
SHEET
LAST
REV
D
C
B
A
D
C
B
11
12
6
10
SLOT 3
4
ENET
SLOT 2
7
SLOT 1
DEV NUM
SLOT
B21
PCI_AD29
PCI_CBE#1
PCI_SERR#
AD23
AD22
AD21
AD15
AD18
IDSEL
C, D, A, B
B, C, D, A
A, B, C, D
D, A, B, C
A, B, C, D
INT[A,B,C,D]#
PCI RESOURCES
PCI_AD[31:0]
SMT0603
B48
PCI_AD10
D53
PCI_AD7
3
2
1
4
0
PCICLK
3
2
1
0
REQ/GNT
n/a
+5V_D62
+5V_D61
ACK64#
+5V_D59
AD1
GND_D57
AD3
AD5
3_3V_B54
AD7
AD8
GND_B49
AD10
AD12
GND_B46
AD14
C_BE1#
3_3V_B43
SERR#
3_3V_B41
PERR#
LOCK#
GND_B38
DEVSEL#
3_3V_B36
IRDY#
GND_B34
C_BE2#
AD17
3_3V_B31
AD19
AD21
GND_B28
AD23
C_BE3#
3_3V_B25
AD25
AD27
GND_B22
AD29
AD31
+5V_B19
REQ#
GND_B17
CLK
GND_B15
RSV_B14
GND_B13
GND_B12
PRSNT2#
RSV_B10
PRSNT1#
INTD#
INTB#
+5V_BO6
+5V_B05
TD0
GND
TCK
-12V
J9
PCI, 32-BIT, 5V
VCC
D62
D61
D60
D59
D58
D57
D56
PCI_AD3
PCI_AD1
D55
PCI_AD5
D54
D52
PCI_AD8
B49
B47
PCI_AD12
B46
B45
B44
B43
B42
B41
B40
PCI_PERR#
B38
B37
B36
B35
B34
B33
B32
B39
PCI_AD14
PCI_AD17
B30
B31
B29
PCI_AD19
B28
B27
B26
PCI_AD21
PCI_AD23
B24
PCI_AD25
B25
B23
PCI_AD27
B22
B20
PCI_AD31
B19
B18
B17
B16
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY#
PCI_CBE#2
PCI_CBE#3
PCI_REQ#3
PCI_CLK3
B15
B14
B13
B12
B11
B10
B09
B08
PCI_IRQ#B
2.74K R178
440MX
7,14,16
VCC
7,14,16
7,14,16,19
14,16,19
7,16,19
7,14,16,19
7,14,16,19
7,14,16
7,14,16
7,19
8
7,16,19
7,14,16,19
B07
PCI_IRQ#D
B06
B05
B04
B03
B02
VCC3
C255
B01
C101
0.01UF
A
VCC -12
SMT0603
SMT0603
VCC3
SMT0603
SMT0603
TDI
TMS
+12V
TRST#
5
+12
+5V_C62
+5V_C61
REQ64#
+5V_C59
AD0
AD2
GND_C56
AD4
AD6
3_3V_C53
C_BEO#
AD9
GND_A48
AD11
AD13
3_3V_A45
AD15
PAR
GND_A42
SBO#
SDONE
3_3V_A39
STOP#
GND_A37
TRDY#
GND_A35
FRAME#
3_3V_A33
AD16
AD18
GND_A30
AD20
AD22
3_3V_A27
IDSEL
AD24
GND_A24
AD26
AD28
3_3V_A21
AD30
PME#
GND_A18
GNT#
+5V_A16
RST#
RSV_A14
GND_A13
GND_A12
RSV_A11
+5V_A10
RSV_A09
+5V_A08
INTC#
INTA#
+5V_A05
5
-12
PCI_RST#
PCI_AD24
PCI_AD22
PCI_AD20
A29
PCI_AD16
PCI_AD4
C55
PCI_AD2
PCI_AD0
C58
C62
C61
C60
C59
C57
C56
PCI_AD6
C54
C53
C52
A49
PCI_AD9
PCI_AD11
A47
A48
PCI_AD13
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
PCI_AD15
PCI_AD18
A32
A33
A31
A30
A28
A27
A26
A25
7,14,16
7,14,16
7,14,16,19
7,14,16,19
7,14,16,19
SMT0603
VCC
7,10,14,16,19
7,19
7,11,14,16
7,16,19
7,16,19
2.74K R179
PCI_CBE#0
PCI_PAR
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_AD26
A23
A24
PCI_AD28
PCI_AD23
PCI_PME#
PCI_GNT#3
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
PCI_IRQ#A
PCI_AD30
3VSB
PCI_IRQ#C
VCC3
A07
VCC
A06
A05
A04
A03
A02
A01
+12
SMT0603
6
SMT0603
SMT0603
C136
0.01UF
C228
0.01UF
0.01UF
C177
0.01UF
C137
0.01UF
SMT0603
SMT0603
C83
0.01UF
C90
0.01UF
R108
100
4
4
3
2
2
3
B
1
DRAWING
PCI CONNECTOR 3
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
1
09/20/01
10:29 AM
B
17 OF 19
SHEET
LAST
REV
D
C
B
A
D
C
13
5
5
5
VCC2_5
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
VR_PWRGD
6
35v
C111
150UF
VCC1_5
35v
C104
150UF
VCC3
4
Q5
3
3
Q6
1
1
MJD45H11
MMBT2907
2
100K
R96
R95
SMT0603
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FB15
BASE15
FB25
BASE25
EN
PWRGD
UVLO
SSL
SSC
CORE
DACOUT
GND
VID0
VID1
VID2
VCC
RAMP
OUT
ADP3421
REG
CS+
CS-
VID3
VID4
LTB
LTI
LTO
CLSET
HYS
U10
15
16
17
18
19
20
21
22
23
24
25
26
27
28
5
C165
C163
4
VR1
2
1
NC
3
VOUT
VIN
SMT0603
3.3V
EZ5Z3L-S3.3
NC1
C156
SMT0603
0.001UF
SMT0603
0.001UF
SMT0603
1500PF C164
SMT0603
0.001UF
C167
100PF
SMT0603
R113
1K
232K
2.74K R107
R115
100K
SMT0603
SMT0603
SMT1206
SMT0603
R112
3.92K
R100
SMT0603
5VSB
SMT0603
3VSB
1.21K
SMT0603
2.74K R114
4
SMT0603
R129
VCC
VCC
7
6
5
4
3
2
1
ADP3410
VCC
GATEL
PGND
SRMON
DRN
GATEH
BST
8
9
10
11
12
13
14
C212
2.7
2.7
SMT1206
R150
SMT1206
R151
SMT0603
0.1UF
VCC
3A_40V
DS1
4
4
Q8
Q9
PULSE PE-53691T
L2
3
R177
WSL2512-0.002-5%
0.002
SMT0603
25v
EEUFC1E122
C200
1200UF
SMT0603
2
25v
C168
EEUFC1E122
25v
C162
1200UF
25v 1200UF
25v
C222
25v 1200UF
C196
1200UF
EEUFC1E122
VR_SENSE+
C254
25v 1200UF
C223
1200UF
B
VCCCORE1
Place close to CPU
SMT1206
1
1
DRAWING
VOLTAGE REGULATORS
Intel Corporation
Chandler, AZ 85226
09/18/01
DATE
TITLE
EFFECTIVE ESR REQUIRED FOR CAPS < 10mohm
3 2 1
8765
3 2 1
8765
+12
VCCGD
DLY
SMOD
IN
GND
EN
OVPSET
U12
VCC
5. The core voltage sense resistor and parallel capacitor must be located close to the CPU, but far from the switcher
4. Avoid routing any signals, including power supply control signals, over the switching power path loop
SMT1206
3. Add multiple vias where high current traces switch layers to reduce resistance and inductance and improve heat dissipation
2. Connection between components in the high current path must be sized to handle 25A
1. Distance from MOSFETs to driver IC should be as small as placement allows
ROUTING NOTES - POWER SUPPLY
SMT1206
SMT0603
SMT0603
R102
SMT0603
C175
47PF
R128
10K
C192
1UF
1.21K
SMT0603
C208
0.1UF
VCC3
R127
100K
2
EEUFC1E122
3
EEUFC1E122
+12
C176
0.1UF
5
SMT1206
C174
47PF
5
EEUFC1V151
C204
1UF
SI4410DY
SI4410DY
4
EEUFC1E122
C227
0.1UF
EEUFC1E122
B
C112
1UF
R126
1.21K
10
C166
0.1UF
C191
0.1UF
SMT0603
SMT0603
A
5
SMT0603
C157
1UF
6
C94
0.1UF
C96
0.1UF
R121
10
MBRS340
SMT0603
2.74K R130
SMT0603
SMT0603
SMT0603
EEUFC1V151
09/20/01
10:29 AM
B
18 OF 19
SHEET
LAST
REV
D
C
B
A
D
C
B
A
X8
X1
6
6
X5
X4
VCC
VCCCORE1
C262
C261
C178
C226
C144
C266
C138
C244
C143
X7
X10
SMT0603
0.01UF
SMT0603
0.01UF
SMT0603
0.01UF
SMT0603
0.01UF
SMT0603
0.01UF
SMT0603
0.01UF
SMT0603
0.01UF
SMT0603
0.01UF
SMT0603
0.01UF
VCC3
VCC3
X2
X11
POWER PLANE DECOUPLING
X6
5
5
7
7,10
7,10
6,10
6,10
7,10
7,10
7,10
7,10
7,10
7,10
7
7
7
7
7
7
7
7,11
7,10
7,10
7,10
7,10
7,10
7,10
7,10
7,10
XBUS_DREQ0
XBUS_DREQ1
XBUS_DREQ2
XBUS_A20GATE
XBUS_RCIN#
XBUS_IOCHRDY
XBUS_MEMW#
XBUS_MEMR#
XBUS_IOW#
XBUS_IOR#
XBUS_RSTDRV
XBUS_IRQ1
XBUS_IRQ3
XBUS_IRQ4
XBUS_IRQ5
XBUS_IRQ6
XBUS_IRQ7
XBUS_IRQ12
XBUS_IRQ14
XBUS_SD0
XBUS_SD1
XBUS_SD2
XBUS_SD3
XBUS_SD4
XBUS_SD5
XBUS_SD6
XBUS_SD7
4
R207
R197
SMT0603
4.75K
SMT0603
4.75K
SMT0603
R214
SMT0603
R147
SMT0603
R152
SMT0603
R259
SMT0603
R277
SMT0603
R299
SMT0603
R212
SMT0603
R220
SMT0603
R215
SMT0603
R195
SMT0603
R188
SMT0603
R200
SMT0603
R184
SMT0603
R192
SMT0603
R196
SMT0603
R201
SMT0603
4.75K
8.25K
8.25K
1K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
R173
SMT0603
4.75K R216
SMT0603
4.75K R208
SMT0603
4.75K R217
SMT0603
4.75K R209
SMT0603
4.75K R218
SMT0603
4.75K R210
SMT0603
4.75K R219
SMT0603
4.75K R211
10K
XBUS
4
EMPTY
EMPTY
VCC3
VCC
PS2_P17
PS2_P16
PS2_P12
8.25K
R83
R82
SMT0603
R512
SMT0603
R138
SMT0603
R141
SMT0603
R143
SMT0603
R142
SMT0603
R133
SMT0603
R132
SMT0603
R153
SMT0603
R131
SMT0603
R161
SMT0603
2.74K
8.25K
R84
SMT0603
2.74K
8.25K
R26
SMT0603
2.74K
8.25K
R47
SMT0603
2.74K
8.25K
R48
SMT0603
2.74K
8.25K
R51
SMT0603
2.74K
8.25K
R55
SMT0603
2.74K
8.25K
R52
SMT0603
2.74K
SMT0603
2.74K
8.25K
R25
R145
SMT0603
2.74K
SMT0603
2.74K
8.25K
R56
SMT0603
2.74K
SMT0603
4.75K R267
SMT0603
4.75K R248
SMT0603
4.75K R258
SUPER I/O
PCI_CLKRUN#
PCI_GNT#3
PCI_GNT#2
PCI_GNT#1
PCI_GNT#0
PCI_IRQ#D
PCI_IRQ#C
PCI_IRQ#B
PCI_IRQ#A
PCI_SERIRQ
PCI_REQ#3
PCI_REQ#2
PCI_REQ#1
PCI_REQ#0
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_LOCK#
PCI_SERR#
PCI_PERR#
EMPTY
VCC
VCC3
VCC
3
7
7,15
7
7
7
7
7
7
7
7
7
7
MX_GPIO21
MX_GPIO11
MX_GPIO6
MX_GPIO5
MX_GPIO4
MX_GPIO3
MX_GPIO2
MX_GPIO1
SMB_ALERT#
PCI_PME#
PM_EXTSMI#
PM_PWRBTN#
SMB_DATA
SMB_CLK
AC_SDIN1
AC_SDIN0
MX_GPIO27
MX_GPIO10
4,7
7,10,14,16,17
7,13
7,13
4,6,8,9,13,14
4,6,8,9,13,14
2
2
10K
10K
10K
10K
SMT0603
R32
SMT0603
R88
SMT0603
R511
SMT0603
R91
SMT0603
R158
SMT0603
R155
SMT0603
R189
SMT0603
4,6
4,6
4,6
4,6
4,6
4
4,6
4,6
4
4,6
4
4,6
GTL_CPURST#
CPU_STPCLK#
CPU_INIT#
CPU_NMI
CPU_INTR
CPU_SLP#
CPU_SMI#
CPU_IGNNE#
CPU_FLUSH#
CPU_FERR#
CPU_IERR#
CPU_A20M#
B
VCC1_5
SMT0603
R172
SMT0603
R103
SMT0603
R105
SMT0603
R119
SMT0603
R106
SMT0603
R135
R104
SMT0603
R118
SMT0603
R148
SMT0603
R134
SMT0603
R146
SMT0603
R120
1
1
DRAWING
56.2
680
1K
1.5K
1.5K
1.5K
332
1.5K
1.5K
1.5K
1.5K
1.5K
GTL+ BUS
PULLUP/PULLDOWN RESISTORS
09/18/01
DATE
TITLE
3VSB
Intel Corporation
Chandler, AZ 85226
VCC3
3VSB
EMPTY
SMT0603
R185
SMT0603
R89
SMT0603
R92
SMT0603
R202
SMT0603
R93
SMT0603
R137
SMT0603
R139
SMT0603
R90
10K
10K
10K
10K
10K
10K
10K
10K
SMT0603
4.75K R171
8.25K
8.25K
8.25K
4.75K R33
SMT0603
4.75K R34
MX CHIPSET
10
10
10
7,14
7,17
7,16
7,16
7,14
7,14,16,17
7,16,17
7,16,17
7,16,17
7,10
7,17
7,16
7,16
7,14
7,14,16,17
7,14,16,17
7,14,16,17
7,14,16,17
7,14,16,17
7,16,17
7,14,16,17
14,16,17
PCI BUS
3
09/20/01
10:29 AM
B
19 OF 19
SHEET
LAST
REV
D
C
B
A

Intel 440MX Scalable Low Power Development Kit

Transcription

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