Bonding Technologies for 3D-Packaging

Transcription

Dresden University of Technology / Electronics Packaging Laboratory
Karsten Meier, Klaus-Juergen Wolter
NanoZEIT seminar @ SEMICON Europa 2011 Dresden
October 12th 2011
System integration by SoC or SiP solutions offer advantages regarding
design efforts, performance, power efficiency, device size, package &
process cost, …
[Eniac: European technology platform nanoelectronics, http//:nano.sdu.dk/PDF/Nanoelectronics-SRA(2).pdf, 2005, p. 31.]
October 12th 2011
slide 2
Electronics
Packaging
Laboratory
Content
Introduction
3D-integration technologies
Bonding technologies for Package-on-Package
Die-to-Wafer technologies
Conclusions
October 12th 2011
slide 3
Electronics
Packaging
Laboratory
Introduction: Status of System in Package
[Roellig M., Beiträge zur Bestimmung von
mechanischen Kennwerten an produktkonformen
Lotkontakten
der
Elektronik,
Dissertation,
Technische Universität Dresden, 2008]
October 12th 2011
slide 4
Electronics
Packaging
Laboratory
Introduction: Young Researchers Group
Production
Technology
Research focusing on
- concepts
- technology
- production
Concepts
of/for highly reliable 3D-Microsystems
[Tummala, R., PRC Georgia Tech, USA]
October 12th 2011
slide 5
Electronics
Packaging
Laboratory
Content
Introduction
Conclusions
October 12th 2011
slide 6
Electronics
Packaging
Laboratory
Package-on-Package: Principles
Stacked BGA-PoP with wire bonds or FC interconnects
FC interconnect
[Pahlke S., Beiträge zur Second-LevelCharakterisierung von 3D-Package-on
Package, Diploma Thesis, Technische
Universität Dresden, 2011]
wire bonds
Interposer-PoP
[Das R. N. et al., ECTC, 2011]
TMV-PoP
[Smith L., Solid State
Technology, Vol. 54,
Issue 7, 2011]
[Cheah B. E. et al., ECTC, 2011]
TSV-PoP
October 12th 2011
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Electronics
Packaging
Laboratory
Package-on-Package
Pro’s & Con’s:
+ Compatible to common SMT processes
+ Integration of passive components
+ Chip design independent from package
+ Testability, cost effective, high reliability
- Limited integration density compared to SiC solutions
- Warpage of sub-packages
Applications:
Smart phones, tablet PCs, SSD drives, …
Memory (die stack) on top of logic/processor unit (single die)
High density memory package (multiple die stack PoP)
October 12th 2011
slide 8
Electronics
Packaging
Laboratory
Package-on-Package: Reliability of Solder Bonds
PoP devices in e.g. smart phones
face moderate thermal cycles but
serious mechanical drops
Solder joints still remain one of the
major failure sites, especially at the
bottom package
Detailed
knowledge
on
solder
material behaviour (creep, high
strain rate) leads to optimised
reliability
Selection of solder alloy essentially
effects the PoP lifetime
63 %-lifetime of 14x14 mm² PoP under -40/+125 °C
30 min dwell TCT and 12x12 mm² PoP under drop
impact
*up to 1750 TCT cycles no significant failure
October 12th 2011
slide 9
Electronics
Packaging
Laboratory
Package-on-Package: Reliability of Solder Bonds
The use of underfiller significantly
enhances the PoP solder joint
reliability
Application to all PoP-levels
prevent a failure site shift
to
Selection of underfiller has to match
both thermo-cycling and drop loads
as well as processing and cost needs
Adhesion
important
to
the
package
is
63 %-lifetime of 14x14 mm² PoP under -40/+125 °C
30 min dwell TCT and 12x12 mm² PoP under drop
impact without or with underfill
*up to 1750 TCT cycles no significant failure
October 12th 2011
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Electronics
Packaging
Laboratory
Package-on-Package: Future Developments
PoP design - Integration of novel interconnect technologies:

Ö
solder ball or Cu pillar (2nd level)
Ö
TSV (interposer or 1st level)
Ö
SLID (stacked dies)
nanowire-filled adhesive film (ACANWF, bottom die) Ö
Ö
organic or silicon interposer
compliancy
high density, short
high density, no re-melt
very high density, TIM
matching CTE
stacked thin dies
SLID interconnects
ACANWF interconnect
Si-interposer
TSVs
TMVs
organic interposer
solder balls
October 12th 2011
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Electronics
Packaging
Laboratory
Content
Introduction
Conclusions
October 12th 2011
slide 12
Electronics
Packaging
Laboratory
Die-to-Wafer: SLID – Motivation & Concept
Cu-Sn phase diagram
thermostable joints (IMCs)
Cu-Sn
Au-Sn
Cu-SnAg
…
enables multistacking of chips
small joints (<10µm)
low bond loads
relatively simple processing
www.metallurgy.nist.gov
SLID
low-lost technology
1. before bonding
October 12th 2011
slide 13
2. bonding
3. complete transition to IMCs
Electronics
Packaging
Laboratory
Die-to-Wafer: SLID
Research goals:

Study diffusion kinetics
Adjust cleaning process
Optimisation of bonding conditions
Reliability characterisation
Backscattered SEM image of the Cu/Sn
interconnect
showing
intermetallic
phases (Cu6Sn5, Cu3Sn) and voids
October 12th 2011
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Electronics
Packaging
Laboratory
Die-to-Wafer: Self Alignment – Principles
Self-alignment for electronics packaging:
Well-known phenomenon with SMT: self-alignment by liquid solder
Reflow
Various research on self-alignment in the past:
magnetic:
by liquid:
surface
tension
Capillary
action
S.B. Shetye et al.,
University of Florida
Basic principle:
October 12th 2011
slide 15
electrostatic:
J. Dalin, J. Wilde
Universität Freiburg
force on the component to minimise free energy
Electronics
Packaging
Laboratory
Die-to-Wafer: z-Self Alignment
3D die stacking – assembly of warped thin dies:
z-self alignment to reduce die warpage
Use capillary action

Influence of intitial warpage
Wetting behaviour
Geometry effects (pitch, gap height, volume of the liquid)
Behaviour of the liquid (viscosity, curing demands)
Temperature effects (intrinsic stresses)
Enable integrated interconnect process
warped die
liquid
substrate
October 12th 2011
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Electronics
Packaging
Laboratory
Die-to-Wafer: z-Self Alignment
Orientation of the initial warpage (die size 10x10 mm², 50 µm; warpage 47 µm)
initial state
under capillary action
die warpage [µm]
50
die warpage
orientation:
40
30
23.8
Warpage reduction by >85%
20
5.7
10
convex
0
concave
October 12th 2011
slide 17
concave
convex
Electronics
Packaging
Laboratory
Die-to-Wafer: Nanowire arrays for 3D bonding
Film filled with vertically oriented nano-scaled interconnects:
Ongoing demand for higher I/Os and smaller size
Need for compliant interconnects
Need for thermal management
Template processing (thinning, create nano-sized pores)
Pore filling
Transition of nanowires into film (ACANWF)
Chip level
ACANWF
TSV Passivation layer
SiO2
Adhesion promoter
(SiO2, TaN, …)
Si
TSV (Cu)
October 12th 2011
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Active die
Cu bumps
ACANWF
Interposer
Electronics
Packaging
Laboratory
Die-to-Wafer: Nano Wire Arrays for 3D Bonding
p = 100 nm, d = 50 nm
a)SEM images of AAO template
b)Scheme of the electrodeposition
of NWs in AAO membranes
l = 20 µm
c) SEM images of electrodeposited
Ag NWs still inside the template
October 12th 2011
slide 19
Electronics
Packaging
Laboratory
Die-to-Wafer: TSV - dimensions
TSV-layers

Typical diameters: 5…20 µm
Aspect ratio: up to 1:10 (ITRS predicts 20:1)
Isolation (SiO2) 400 nm
Barrier-Layer (Ta/TaN) respectively 80 nm
Seed-Layer (Cu) 600 nm
Etched Si (Bosch process)
[Lerner et al., FutureFab, Issue 26, 2008]
Scallops in Si and SiO2isolation layer
unfilled TSVs
(d=5µm)
Cu-filled TSVs
(d=20µm)
[Wolf et al., ESTC, 2010]
[Powel et al., IITC, 2008]
[Laviron et al., ECTC, 2009]
October 12th 2011
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[Wolf et al., ESTC, 2010]
Electronics
Packaging
Laboratory
Die-to-Wafer: TSV – Cu grain structure
Cu grain structure influences mechanical behaviour

Strong anisotropy depending on crystal orientation
Small size TSVs potentially contain only a few grain orientations
Mechanical behaviour is essential for simulation work (FEM)
Model performance restricts covering actual grain structure
Analyse Cu grain structure depending on TSV size, processing
and annealing conditions (EBSD)
Model a characteristic section of one TSV
Determine an effective material description
EBSD mapping: [001] Inverse pole figure
October 12th 2011
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Electronics
Packaging
Laboratory
Die-to-Wafer: TSV - FEM
Cu grain structure influences mechanical behaviour
2D FEM model automatically build from a EBSD measurement
(grain structure and orientation)
Application of tensile loads
Determine effective elastic behaviour
Early result: Important for smaller TSVs (<10 µm)
σyy
October 12th 2011
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Electronics
Packaging
Laboratory
Content
Introduction
Conclusions
October 12th 2011
slide 23
Electronics
Packaging
Laboratory
Conclusions
Two major SiP approaches within 3D integration:
die stacks – KGD, performance, high integration, …
PoP – testability, cost effective, flexibility, medium integration, …
PoP technology:
Package for mobile applications – ongoing development & improvement
Good TCT and drop reliability – design for low warpage
Potential D2W-technologies:
SLID for die stacking w/o re-melting – key factors planarity and cleaning
z-self alignment by capillary action for warpage reduction
ACANWF shows potential for high density interconnections
TSV simulation studies demand detailed but efficient material models
October 12th 2011
slide 24
Electronics
Packaging
Laboratory
Thank you!
[email protected]
+49 351 463 36 594

Bonding Technologies for 3D-Packaging

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