High-Speed Digital Design and Verification

High-Speed Digital
Design and Verification
Russ McHugh
Senior Application Engineer,
High Speed Digital and
Analog Test
How to characterize and debug high speed digital links on
your physical prototype?
What part of your design is eating up your Eye margins?
Signal Integrity Challenges
TP0
Tx
-
EQ
TXn
TP2
Channel
TP3
Connector
+
Connector
TXp
TP1
RXp
+
RXn
Inter-Symbol Interference (ISI)
Probing Effects
Impedance Mismatches and Reflections
Cross Talk
Loss
Methods to Compensate for Measurements
Calibration
Mathematical Signal Processing
De-embedding/Embedding Techniques
2
TP4
EQ
Rx
-
Separating out the Transmitter Effects
TX
Channel
RX
Capturing an eye diagram
The easiest way to get an overall idea of the quality of the serial signal
Created relative to a clock (explicit, recovered)
Eye Diagram is the superposition of all the bit transitions
Clock Recovery settings greatly effect the shape of the eye
101 Sequence
011 Sequence
Overlay of all combinations
What represents “good enough”?
The Eye Mask
The eye-mask is the common industry approach to measure the eye opening
Failures usually occur at mask corners
• But what is cause of failure?
Violating USB FS 12Mb/s Eye Diagram
Good Displayport Eye Diagram
Types of Jitter
Jitter
Bounded
UnBounded
Deterministic
(DJ)
Correlated with Data
(DDJ)
Uncorrelated with
Data
Duty Cycle
Distortion
Inter Symbol
Interference
(DCD)
(ISI)
Tr, Tf D
BW Limits
Xtalk
Reflections
Non Linear
CR
Tx
Threshold
Random (RJ)
Aperiodic Periodic
(ABUJ)
(PJ)
Events
Clocks
Uncorrelated with
Data
Skewed
Gaussian
Thermal
Shot
1/f
Burst
Measuring Jitter: Bit Error Ratio (BER) Testing
 The only way to directly
measure Total Jitter is
with a Bit Error Ratio
(BER) test.
 Sample at various points
along unit interval,
directly measure BER at
each point. Plot “bathtub”
curve.
0.5
BER
10-3
Gaussian
Tails
10-6
10-9
Eye Opening at
BER=10-12
10-12
W
0
0.5TB
TB /UI
Can be slow depending on the
data rate
TJ(BER) = UI – W
Time Interval Error
(a) Clock Reference
time
(b) Source Waveform
voltage
measurement
threshold
0
time
time error
(c) Time Interval Error (TIE)
0
Measures total
jitter of the
acquisition. The
more transitions
you measure,
the greater TIE
will become.
time
Waveform transitions deviate from expected transition time
Generate Time Interval Error (TIE) by measuring transitions versus
reference clock
Dual Dirac Model – Total Jitter
BER
n
1x10-8
5.73
1x10-10
6.47
1x10-12
7.13
1x10-14
7.74
L
[ ( x   L )
Total Jitter
n=

R
+
 ( x   R )] 
TJ(BER) =
RJpp / 2
DJ
JDJ
PP

(  = RJrms)

 x2 
exp 

2 2 

UI – W
7


L
R
 (x   L )2 
 (x   R )2 
exp 
  expdirectly


2
TJ can
be
measured
2

2 2 



using a BER test
OR
TJ(BER) = 2n*RJrms + DJ
TJ can be calculated using RJ
and DJ in the Dual Dirac
model
Tail Fit
Problem
Total Jitter Histogram
RJ/PJ/ABUJ
Histogram
1
The spectral method lumps ABUJ
in with RJ and greatly
overestimates TJ.
0.9
0.8
0.7
Solution
0.6
0.5
0.4
1. Perform Gaussian Tail fit on
RJ/PJ/ABUJ Histogram to get
RJrms directly
RJrms
0.3
0.2
2. Spectral fit gives
(RJ+ABUJ)rms & PJrms
0.1
0
-30
-20
-10
0
10
20
30
3. Subtract RJ rms to get
ABUJrms
EZJIT Plus – Advanced Jitter Decomposition
 Easy to use
wizard guides
you through
jitter
measurement
setup
 Fully compatible
with Infiniium
Software such
as Equalization,
PrecisionProbe,
and InfiniiSim
 Customizable
jitter views
Jitter Measurement Demonstration
Page 12
Why is vertical noise floor important ?
Let’s consider theoretical signals with Zero jitter and fixed voltage noise
with three different edge speeds and crossing a Threshold at 50%
1)Voltage noise translates directly to Timing uncertainty (Jitter)
2)Higher Vertical Noise Floor translates to higher Timing uncertainty
3)At constant amplitude noise floor, slower edge speed translates to higher
timing uncertainty
EZJIT Complete – Vertical Noise Decomposition
 Vertical slice of
real time eye
allows for noise
decomposition
using the same
concepts and
algorithms as
timing jitter
 Analyze One
level, Zero
level, or both
Vertical Noise Measurement Demonstration
Page 15
Separating out the Channel Effects
TX
Channel
RX
Analyzing a serial Link
TX
Clean Source Signal
Channel
Channel
Frequency Response
We are going to analyze a 12Gb/s Link
Channel will be 9 Inch FR4 PCB
Page 17
RX
Closed Eye
Received Signal
Eye & Jitter Break Down Analysis on TX output
Transmitter 12Gb/s
Intrinsic Jitter Analysis
33GHz 80GSa/s Scope
RJ: 500fs (RMS)
PJ: 740fs
DCD: 660fs
ISI: 10.52ps
AGILENT SI Seminar 2012
by Pascal GRISON
Page 18
Eye Diagram on TX output and Channel Output
Depending on Link
Target Data rate &
Transmission Channel
Losses
AGILENT SI Seminar 2012
by Pascal GRISON
AGILENT SI Seminar 2012
by Pascal GRISON
Even with Perfect TX Eye
Opening…
You may end up with a
completely closed
at Receiver Side
Why is the RX Eye
Closed? ISI Jitter!
Does that mean that this
link will never Work?
Well it Depends….
Page 19
What is Inter-Symbol Interference?
AGILENT SI Seminar 2012
by Pascal GRISON
ISI Jitter is coming from Signal Distortions in Transmission Channel
Page 20
Scope can Emulate Receiver EQUALIZATION
Modern SerDes are incorporating
Reciever Equalization
Using Oscilloscope Equalization
we can emulate most DUT RX EQ
configurations:
AGILENT SI Seminar 2012
by Pascal GRISON
• Feed Forward Equalizer
Continuous Time Linear Equalizer
• Decision Feedback Equalizer
Page 21
Emulate Receiver EQUALIZATION on Oscilloscope
From almost Zero RX
Eye Opening
with no TX DeEmphasis and
No RX EQ
AGILENT SI Seminar 2012
by Pascal GRISON
RX Eye Opening of
132mV X 65ps
Was achieved with
EQUALIZATION
You MUST Emulate your RX Equalization in Oscilloscope to Analyze True RX Eye Diagram
Page 22
Commonly Encountered Insertion Losses
Typical Insertion Loss Through FR4
100MHz …….. 2 dB/m
(20%/m)
500MHz …….. 4 dB/m
(37%/m)
1GHz ………… 7 dB/m
(55%/m)
5GHz ………… 25 dB/m
(94%/m)
10GHz ……….. 45 dB/m or 1.14 dB/in
(99%/m)
100MHz ……..
1GHz …………
5GHz ………...
10GHz ……….
20GHz ……….
Typical Insertion Loss Through SMA
0.25 dB/m
(2.8%/m)
0.8 dB/m
(8.8%/m)
2 dB/m
(20%/m)
3 dB/m
(29%/m)
5 dB/m
(44%/m)
Loss increases exponentially with frequency.
Non-idealities you could ignore at <1GHz now severely erode design margins
Same Measurement Setup, VERY Different Results
Corrected
Uncorrected
• PCI Express 2, SATA, and Custom
• Compliance Requirement for Gen 2
Tx
PHY
25
Channel
S4P
Connector
• Compensate for Probing and Fixture
Loss – Add Margin to Transmitter
Characterization
Connector
De-embedding – Loss Compensation or Gain
Function (De-convolve)
Rx
PHY
De-embedding the DDR2 BGA Probe
26
Probe at VIA
De-embed Probe
Probe at BGA
RT BGA = 390 ps
RT VIA = 183 ps
RT De-embed = 175 ps
27
Embedding – Loss Function (Convolve)
Pin
Rx
TP1
TP2
TP3
Virtual Probe and Deemphasis/Equalization
• Simulate Equalization/De-emphasis at
Rx
Connector
• Simulate Channel Loss on Signal
Measured at Tx
Tx
PHY
Tx
Signal
Virtual Probe
Rx
Equalization
TP1
TP3
TP2
28
Channel
Connector
Connector
Channel.s4p+
conn.s4p+package.s4p
Rx
PHY
Separating out the Receiver Effects
TX
Channel
RX
How do we ensure ‘Error Free’ operation?
How can we specify to the transmitter plus channel design the quality of
the signal that the receiver needs?
Answer - We need to measure the Receiver’s tolerance to jitter.
30
Characteristic eye closure by sinusoidal Jitter
Eye Diagram
BER Scan
31
Receiver Jitter Tolerance
with Loopback
JBERT up to 28Gb/s PRBS Generation
with Calibrated Jitter insertion
and integrated adjustable ISI channel
DUT SerDes in
Loopback Mode
RX Data
Receiver
Rx latch
AGILENT SI Seminar 2012
by Pascal GRISON
ISI
Channel
DLL
Rx
PLL
Transmitter
Tx latch
JBERT Real time Error Detector allow
thorough BER Analysis
Tx
DLL
TX Data
Customers are using J-BERT to characterize SERDES receiver susceptibility
to ISI, Random Jitter, Periodic Jitter, and BUJ
32
RX Testing with asycronous devices
(SER / FER Support)
Error detector supports 8B/10B encoded data, and
can deal with re-timed data and filler symbols
Data-out with fBERT
Re-timed data with fProduct
D+ D- D+ F+ F+ D+ D- D+
D+ D- D+ F+ D+ D- D+
EQ
Clock
FF
CDR
Elastic
buffer
Receiver
CDR
Loopback
Transmitter
Product under test
Expected data with fproduct
D
D
D D
Device
function
D
D
Loopback data with fproduct
and new disparity
D- D+ D- F- D- D+ D-
Clock
Rx Compliance and Jitter Tolerance
Testing
34
Summary
•
TX characterization is frequently captured with eye diagrams.
•
The Dual Dirac model allows us to extrapolate jitter measurements to low
BER rates.
•
Amplitude noise can contribute to random jitter.
•
ISI is a dominant source of eye closure at high data rates.
•
De-embedding and virtual probing can correct for fixture and provide
measurements at inaccessible locations.
•
Equalizers are a key feature of receivers.
•
Receiver jitter tolerance testing is becoming a requirement.
•
Asynchronous systems require the BER error detector to handle filler
symbols.
Page 36
Questions
Page 37