How to Reduce the Need for Guardbanding a Flash ADC Design

How to Reduce the Need for Guardbanding
a Flash ADC Design
Karen Chow, Mentor Graphics Inc.
For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is
growing with the increasing interactions among devices and interconnects that are in close
proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction
is critical for first silicon success. New 3D parasitic extraction technology applied to a flash
ADC circuit design reduces the need for extra guardbanding and ensures that it will work
according to the specifications when manufactured.
Flash ADC Architecture
Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications
such as satellite communications, sampling oscilloscopes, and radar detection. The main benefit
of using a flash ADC over other ADC architectures is that it is extremely fast. Other
architectures rely on a series of stages that narrow in on the correct results, whereas a flash ADC
is read immediately. Also flash ADC architecture is quite simple. Its main disadvantage is that it
requires a lot of converters for higher accuracy requirements with a large number of bits (a ratio
of twice as many converters per bit), which increases the size of the chip, thereby the cost.
Layout Matching
The constraints used to lay out a flash ADC is extremely important because differential pairs
must have symmetrical layouts, the same capacitors must have equal values, and the resistors
must be matched. For example, if a resistor gets over-etched because of process variations, all of
the resistors need to be over-etched in the same way so that the taps off the resistor ladder are
still the correct voltage value. Several rules of thumbs can help improve layout matching.
First, matched devices should be laid out close to each other. That way, if a certain layer is
thinner or thicker than the specification, the devices will be altered equally and will have the
same characteristics.
Also, matched devices should be oriented in the same direction. Lines leading up to the gates of
a differential pair should be exactly the same so that the same parasitic resistances and
capacitances lead up to the differential pair. Using 3D parasitic extraction is crucial in ensuring
that the interconnect is exactly the same.
Second, devices that need to be matched can be interdigitated, which means that they are divided
up into smaller components and then woven into the matched pair. For example, if two 1 kΩ
resistors need to be tightly matched, each 1 kΩ resistor could be split into two 500 Ω resistors in
series. Then there would be four 500 Ω resistors that could be interdigitated. This would spread
out the process variations between the resistors and would create more tightly matched resistors.
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However, the wiring between the interdigitated components would need to match as well. To
verify that the resistors are well-matched, use a layout-vs.-schematic (LVS) tool to measure the
value of the designed resistors and a field solver to calculate the parasitic RC values of the
connections.
Third, dummy devices can be placed on the outside edges of the array of devices. Because the
edges of blocks etch differently than the middle of the block, if you put a dummy device on the
outside, those will be etched the most aggressively. This is fine because the devices that matter
are on the inside.
Common centroid is another layout technique that helps matching. Devices are placed around a
central point; and because of the symmetry both in the x and y direction, good matching is
assured.
Need for Accurate 3D Modeling and Elimination of Double-Counting
Once the layout is completed, parasitic extraction can be performed using a highly accurate fieldsolver. For example, Calibre xACT 3D is a field solver that is a hybrid of the boundary element
method (BEM) and finite element method (FEM) methodologies. (See referenced papers for
more detail on field solver technology.) Because field solvers use highly accurate algorithms, we
can be confident that the flash ADC design will meet the performance specifications.
When setting up, make sure no double counting is occurring between the device models and the
interconnect extracted by the parasitic extraction tool. Capacitances around the MOS transistors
are in the device model that is used for simulation. If your extraction tool also extracts these
capacitances, then those capacitances will be counted twice. So to ensure no double counting,
match the device model with the LVS and parasitic extraction deck.
Typically, the proper device blocking is set up by the foundry. But if the foundry is not providing
rule files, the CAD engineer needs to set this up.
When setting up the rule file for parasitic extraction, device handling is a concern. Even though
Calibre xRC and the field solver use the same rule file, they handle device blocking differently.
You can tell the rule-based tool to only block the fringe capacitance or to only block the plate
capacitance. But a field solver has no concept of fringe or plate. It sees the entire 3D shape and
calculates field lines.
So to set up device blocking, use the concept of a “device” and what polygons are inside or
outside of the device. The new field solver lets you ignore specified interactions inside the device
area, while still capturing effects between different transistors and between the devices and
interconnect.
Next, we run a configuration step to automatically generate device blocking statements for all
devices in the LVS rule deck. This configuration step creates device blocking statements that
match the most typical device model but can be modified as needed if the device model is not a
standard one.
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Modeling Process Variation
Modeling process variation is also an important verification step. Even though foundries do as
much as possible to minimize manufacturing variability, the variation will always be there, and
foundries model this variation in the form of in-die variation tables. xCalibrate can be used to
generate rule files. It takes the variation data for local density, width, and spacing and makes
adjustments to the drawn shapes. These adjusted shapes are used when calculating parasitic
effects. The in-die variation tables can be defined for parameters such as width, thickness, sheet
resistance, resistivity, temperature coefficients tc1 and tc2, gate fringe, and contact bias.
Layout-Dependent Stress Effects
Trench isolation techniques can induce comprehensive stress in the diffusion layer, affecting the
mobility and saturation velocity of carriers. Stress effects should be measured to include this
phenomenom in the device models.
The stress-effect parameters are extracted using LVS and enclosure_vector commands, which
enables more accurate simulations. Figure 1 is an example of a transistor in the output netlist that
includes the following parameters.
Figure 1: Example of transistor in the output netlist.
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At 90 nm, only well-enclosure measurements were required (SA, SB). At 45 nm and 65 nm,
measurements that span across to a neighboring device are needed. Some examples include
active to active, gate to poly, and gate to contact (not drawn).
Simulation Results
In the example shown here, a 5-bit flash ADC was designed in a 45 nm CMOS technology, using
Virtuoso, Calibre DRC/LVS/xACT 3D, and Eldo. The ADC uses a linear voltage ladder with a
comparator at each stage of the ladder to compare the input voltage to each set level tapped from
the resistor chain. Each comparator represents 1 least significant bit (LSB), and the output code
can be determined in one compare cycle. The comparator chain is followed by a thermometer
decoder block composed of digital logic cells. A set of latches follows the thermo-decoder and is
the final 5-bit output stage.
The field solver was run on the design, both in RCC mode and in C + CC mode. The design was
also run on the rule-based extraction tool for comparison. The rule-based simulation results show
some delay in the B0 bit, and the field solver shows more delay (Figure 2).
Figure 2: Delay caused by parasitic effects.
The recreated sine wave Vout from the DAC was plotted for the extraction and field-solver runs,
as well as the input sine wave Vin (Figure 3). There are some small differences in the output
signal. And when comparing the results, differences can be seen in many of the bits, causing
slight differences in Vout (Figure 4).
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Figure 3: Detailed simulation waveforms showing the difference between the
rule-based and field-solver tools.
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Figure 4: Differences in output between the rule-based extraction tool and the field-solver based tool.
In reviewing the capacitance values of the 32 comparator inputs, we can seen that the
capacitance values are quite close, which means that the lines are well-matched (Table 1). This
means that the layout engineer has done a good job with matching the lines, and that the delay in
reaching the comparator will be the same for all 32 comparators. With the field solver runs, it
shows that the layout matching techniques were effective in reducing mismatch.
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Table 1: Capacitance Values of the 32 Comparator Inputs
Net Name
Capacitance
% Difference vs. Reference
C0
4.51508E-16
0.03
C1
4.51335E-16
-0.01
C10
4.51500E-16
0.03
C11
4.51380E-16
0.00
C12
4.51407E-16
0.01
C13
4.51354E-16
-0.01
C14
4.51500E-16
0.03
C15
4.51391E-16
0.00
C16
4.51468E-16
0.02
C17
4.51354E-16
-0.01
C18
4.51500E-16
0.03
C19
4.51201E-16
-0.04
C2
4.51500E-16
0.03
C20
4.51500E-16
0.03
C21
4.51201E-16
-0.04
C22
4.51500E-16
0.03
C23
4.51201E-16
-0.04
C24
4.51500E-16
0.03
C25
4.51201E-16
-0.04
C26
4.51500E-16
0.03
C27
4.51201E-16
-0.04
C28
4.51500E-16
0.03
C29
4.51201E-16
-0.04
C3
4.51201E-16
-0.04
C30
4.51500E-16
0.03
C31
4.51502E-16
0.03
C32
4.51405E-16
0.01
C4
4.51500E-16
0.03
C5
4.51201E-16
-0.04
C6
4.51500E-16
0.03
C7
4.51201E-16
-0.04
C8
4.51500E-16
0.03
C9
4.51201E-16
-0.04
Conclusion
Designing flash ADCs requires careful tradeoffs between speed, accuracy, and power. Highly
accurate parasitic extraction ensures that the parasitics will not cause the ADC to behave
incorrectly and that the ADC will still meet all of the design specifications.
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References
W. Shi, J. Liu, N. Kakani, and T. Yu, “A Fast Hierarchical Algorithm for Three-Dimensional
Capacitance Extraction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, Vol. 21, No. 3, March 2002.
S. Shi and F. Yu, “A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction,” IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 8,
August 2004.
S. Yan, V. Sarin, W. Shi, “Sparse Transformations and Preconditioners for 3-D Capacitance
Extraction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 24, No. 9, September 2005.
S. Yan, V. Sarin, W. Shi, “Fast 3-D Capacitance Extraction by Inexact Factorization and
Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 25, No. 10, October 2006.
Y. Zhou, Z. Li, W. Shi, “Fast Capacitance Extraction in Multilayer, Conformal and Embedded
Dielectric using Hybrid Boundary Element Method,” Design Automation Conference, June 4–8,
2007.
About the Author
Karen Chow is a Technical Marketing Engineer for Calibre xRC and Calibre xACT 3D at
Mentor Graphics in Wilsonville, Orego Before Mentor Graphics, she worked at Nortel Networks
in Ottawa, Canada, focusing on synchronization for optical switches and analog IC design for
telephony applications. Ms. Chow has her BSc in electrical engineering from the University of
Calgary and her MBA from Marylhurst University.
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