ECE 274a – HW 6 Problem Set

ECE 274a – HW 6 Problem Set
1. What is the largest 16-bit binary number that can be represented with
(a) unsigned numbers?
(b) two’s complement numbers?
(c) sign/magnitude numbers?
2.
Convert the following decimal numbers to 6-bit two’s complement binary numbers and add them. Indicate
whether or not the sum overflows a 6bit result.
(a) 16 + 9
(b) 27 + 31
(c) -4 + 19
(d) 3 + -32
(e) -16 + -9
(f) -27 + -31
3.
Design a system with an 8-bit input I that can be stored in 8-bit registers A, B, and/or C when input La, Lb,
and/or Lc is 1, respectively. For example, If inputs La and Lb are 1, then registers A and B will be loaded with
input I, but register C will keep its current value. Furthermore, if input R is 1, then registers swap values such that
A = B, B = C, and C = A. Input R has priority over the L inputs. The system has one clock input.
4.
Using only flip-flops, multiplexers, and logic gates, design a 4-bit register with a preset input, pst, a load input,
ld, and a load negative input, ldn. When pst is 1, the register should store the 4-bit value 1101. Otherwise,
when ld is 1, the register will load the 4-bit input I. If ldn is 1, the register will load the two’s complement on
the 4-bit input I. If none of the inputs are asserted the register will maintain its present value. Your register
should have separate control inputs for each operation
5.
Assuming three 4-bit two’s complement signed inputs, A, B, and C. Design a circuit that outputs the largest
distance between any pair of values. For example, if A = 5, B = -3, and C = 7. The largest (absolute) distance
is between inputs B and C, thus your circuit will output 10. Make sure you label each of your components,
inputs/output of these components, as well as wire sizes.
You may assume you have the following datapath components available (unsigned only) – decoders, encoders, muxes, parallel
load registers, adders, equality comparators, magnitude comparators, array style multipliers, subtractors, ALUs, shifters, and logic
gates.
6.
Design a 3-bit up/down-counter that has three control inputs: cnt_up enables counting up, cnt_down enables
counting down, and set_val sets the counter to 510. A user should be able to specify the desired operation of
your counter through separate control inputs, the order of highest to lowest priority is cnt_up, cnt_down, and
set_val. Note, your up/down-counter should also support a terminal count (tc) output. If the counter is not
currently configured to count up or count down, the terminal count should default to zero.
You may assume you have the following datapath components available (unsigned only) – decoders, encoders, muxes, parallel
load registers, adders, equality comparators, magnitude comparators, array style multipliers, subtractors, ALUs, shifters, and logic
gates.
7.
Given the up-counter shown below, what value should be assigned to input Reload to achieve a 2 kHz output
(ClkOut), and what is the minimum bit-width needed for the counter to work as specified.
Reload
?
L
load
1
1 MHz
cnt
tc
?-bit
up-counter
C
unused
ClkOut
(2 kHz)
8.
Build a 3x8 register file with one write port and one read port. Make sure you label each of your components,
inputs/output of these components, as well as wire sizes.
You may assume you have the following datapath components available (unsigned only) – decoders, encoders, muxes, parallel
load registers, adders, equality comparators, magnitude comparators, array style multipliers, subtractors, ALUs, shifters, and logic
gates.
Optional Exercises
9.
Using only logic gates provide the internal structure of a full adder. Using full adders as your building blocks,
design a 3-bit carry-ripple adder. Assume the delay can be estimated as 1 ns times the number of gate inputs,
what is the total delay of the 3-bit carry-ripple adder?
10. Provide the Boolean equations for a magnitude comparator. Assuming the delay of a gate can be estimated as 1 ns
times the number of gate inputs, what is the total delay of the 3-bit magnitude comparator? Consider all gates in
your calculation, including NOT gates.
11. Create a circuit to calculate F = 10A using the fewest number of 4-bit adders. Assume A is a 4-bit input.