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1/page - 6.004
Synthesis of Combinational Logic
A
B
• 
• 
• 
• 
• 
• 
Sum of products
Inverting logic
Logic minimization
Karnaugh Maps
Muxes/Table Lookup
Read-only Memories
6.004 Computation Structures
Today’s handouts:
•  Lecture slides
Notes:
•  Lab #1 due Thursday
L4: Logic Synthesis, Slide #1
Functional Specifications
There are many ways of specifying the function of a
combinational device, for example:
A
B
C
Argh… I’m tired of word games
If C is 1 then
copy B to Y,
otherwise copy
A to Y
Y
Truth Table
Concise alternatives:
•  truth tables are a concise description of the
combinational system’s function.
•  Boolean expressions form an algebra in whose
operations are AND (multiplication), OR
(addition), and inversion (overbar).
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
0
1
1
Y = CBA + CBA + CBA + CBA
Any combinational (Boolean) function can be specified as
a truth table or an equivalent sum-of-products Boolean
expression!
6.004 Computation Structures
L4: Logic Synthesis, Slide #2
Here’s a Design Approach
Truth Table
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
0
1
1
-it’s systematic!
-it works!
-it’s easy!
-are we done yet???
6.004 Computation Structures
1. Write out our functional spec as a
truth table
2. Write down a Boolean expression with
terms covering each ‘1’ in the output:
Y = CBA + CBA + CBA + CBA
3. Wire up the gates, call it a day, and
declare success!
This approach will always give us
Boolean expressions in a particular form:
SUM-OF-PRODUCTS
L4: Logic Synthesis, Slide #3
Sum-of-products Building Blocks
A Z
INVERTER:
A
€
Z = A⋅ B
B
€
€
€
Z = A+ B
B
€
€
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
A B Z
A
OR:
0
A B Z
€
A
AND:
6.004 Computation Structures
Z=A
€
0
0
0
0
1
1
1
0
1
1
1
1
L4: Logic Synthesis, Slide #4
Straightforward Synthesis
We can implement
SUM-OF-PRODUCTS
with just three levels of
Logic:
1. Inverters
2. ANDs
3. OR
A
B
C
A
B
C
Y
A
B
C
A
B
C
Propagation delay -No more than 3 gate delays? *
*assuming gates with an arbitrary number of inputs
which, as we’ll see, isn’t a good assumption!
6.004 Computation Structures
L4: Logic Synthesis, Slide #5
ANDs and ORs with > 2 Inputs
Replace 2-input AND gates with 2input OR gates to create large fan-in
OR gates
A
B
C
€
€
€
€
€
€
€
€
€
Chain: Propagation delay
increases linearly with number
of inputs
€
A
B
C
D
Z = A⋅ B⋅C⋅ D
Which one should I use?
€
A
B
Z = A⋅ B⋅C⋅ D
C
D
6.004 Computation Structures
€
€
Z = A⋅ B⋅C
€
Tree: Propagation delay increases
logarithmically with number of inputs
L4: Logic Synthesis, Slide #6
More Building Blocks
NAND (not AND)
A
Z = A⋅ B
B
0 0 1
0 1 1
A
1 0 1
B
1 1 0
Z = A+ B
0 1 0
1 0 0
1 1 0
€
€
€ outputs and vice-versa,
In a CMOS gate, rising inputs lead to falling
so CMOS gates are naturally€inverting. Want to use NANDs and NORs
€
€
A B Z
NOR (not OR)
0 0 1
€
€
A B Z
in CMOS designs…
XOR (exclusive OR)
A B Z
0
A
0
0
Z=A⊕B 0 1 1
B
€
6.004 Computation Structures
1
0
1
1
1
0
XOR is very useful when
implementing parity and arithmetic
logic. Also used as a “programmable
inverter”: if A=0, Z=B; if A=1, Z=~B
Wide fan-in XORs can be created with
chains or trees of 2-input XORs.
L4: Logic Synthesis, Slide #7
Universal Building Blocks
NANDs and NORs are universal:
=
=
=
=
=
=
Any logic function can be implemented using only
NANDs (or, equivalently, NORs). Note that chaining/
treeing technique doesn’t work directly for creating
wide fan-in NAND or NOR gates. But such gates can
be created with trees involving both NANDs, NORs and
inverters.
6.004 Computation Structures
L4: Logic Synthesis, Slide #8
CMOS
♥︎ Inverting Logic
http://6004.mit.edu/currentsemester/handouts/tool_docs/stdcell.html
AND4:
tPD = 0.16 ns, size = 20μ2
NAND4 + INV:
tPD = 0.09 ns, size = 27μ2
Demorgan’s A ⋅ B = A + B
Laws: A + B = A ⋅ B
2*NAND2 + NOR2:
tPD = 0.08 ns, size = 30μ2
6.004 Computation Structures
L4: Logic Synthesis, Slide #9
CMOS Sum-of-products Implementation
“Pushing Bubbles”
AB=A+B
NAND-NAND
C
C
A
A
≡
Y
B
NOR-NOR
B
AC + AB + BC
AB=A+B
C
C
A
A
Y
B
You might think all these extra inverters
would make this structure less attractive.
However, quite the opposite is true.
6.004 Computation Structures
≡
Y
Y
B
AC + AB + BC
L4: Logic Synthesis, Slide #10
Logic Simplification
Can we implement the same function with fewer gates? Before
trying we’ll add a few more tricks in our bag.
BOOLEAN ALGEBRA:
OR rules:
a + 1 = 1, a + 0 = a, a + a = a
AND rules:
a1 = a, a0 = 0, aa = a
Commutative:
a + b = b + a, ab = ba
Associative:
(a + b) + c = a + (b + c), (ab)c = a(bc)
Distributive:
a(b+c) = ab + ac, a + bc = (a+b)(a+c)
Complements:
Absorption:
a + a = 1, aa = 0
a + ab = a, a + ab = a + b
Reduction:
ab + ab = b, (a + b)(a + b) = b
DeMorgan’s Law: a + b = ab,
6.004 Computation Structures
a(a + b) = a, a(a + b) = ab
ab = a + b
L4: Logic Synthesis, Slide #11
Boolean Minimization
Can’t he come up
with a new example???
Let’s (again!) simplify
Y = C B A + CB A + CBA + C BA
Using the identity
αA + α A = α
For any expression
α and variable A:
Y = C B A + CB A + CBA + C BA
Hey, I could write
A program to do
That!
Y = C B A + CB + C BA
Y = C A + CB
6.004 Computation Structures
L4: Logic Synthesis, Slide #12
The Case for a Non-minimal SOP
A(1)
C(1)
C B A Y
0 0 0 0
B(1)
0 0 1 1
0 1 0 0
0
0
Y(1)
1
A
B
C
Y
That’s
what we
call a
“glitch” or
“hazard”
Y = C A + CB
CA
NOTE: The steady state
behavior of these circuits is
identical. They differ in their
transient behavior.
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
BA
6.004 Computation Structures
A
C
CB
Y
B
A
B
C
Y
Y = CA + CB + AB
Now it’s
LENIENT!
L4: Logic Synthesis, Slide #13
Truth Tables with “Don’t Cares”
One way to reveal the opportunities for a more compact
implementation is to rewrite the truth table using “don’t
cares” (-- or X) to indicate when the value of a particular input is
irrelevant in determining the value of the output.
C B A Y
C B A Y
0 0 0 0
0 -- 0 0
0 0 1 1
0 1 0 0
0 1 1 1
0 -- 1 1
1 0 -- 0
1 0 0 0
1 1 -- 1
1 0 1 0
-- 0 0 0
1 1 0 1
-- 1 1 1
1 1 1 1
6.004 Computation Structures
CA
CB
Note: Some input
combinations (e.g.,
000) are matched by
more than one row in
the “don’t care” table.
It would be a bug if all
the matching rows
didn’t specify the
same output value!
BA
L4: Logic Synthesis, Slide #14
Karnaugh Maps: A Geometric Approach
K-Map: a truth table arranged so that terms which differ by exactly one
variable are adjacent to one another so we can see potential reductions
easily.
Here’s the layout of a 3-variable K-map
Truth Table
filled in with the values from our truth
C A B Y
Why did he
table:
shade that
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
C\AB 00
01
11
10
0
0
0
1
1
1
0
1
1
0
row Gray?
010
It’s cyclic. The left edge is adjacent to the
right edge. (It’s really just a flattened out
cube).
6.004 Computation Structures
000
110
100
011
001
111
101
L4: Logic Synthesis, Slide #15
On To Hyperspace
4-variable K-map for a multipurpose
logic gate:
A ×B
if CD = 00
A +B
if CD = 01
B
if CD = 10
Y =
A
⊕
B
if CD = 11
\AB
CD\
00
01
11
10
00 01 11 10
0
0
1
0
0
1
1
1
0
1
0
1
1
0
0
1
Again it’s cyclic. The left edge is adjacent to the right
edge, and the top is adjacent to the bottom.
6.004 Computation Structures
L4: Logic Synthesis, Slide #16
Finding Subcubes
We can identify clusters sharing “irrelevant” variables by
circling adjacent subcubes of 1s. A subcube is just a lower
dimensional cube.
C\AB 00
01
11
10
0
0
0
1
1
1
0
1
1
0
\AB
CD\
00
01
11
10
00 01 11 10
0
0
1
0
0
1
1
1
0
1
0
1
1
0
0
1
The best strategy is generally a greedy one.
- Circle the largest N-dimensional subcube (2N adjacent 1’s)
- Continue circling the largest remaining subcubes
(even if they overlap previous ones).
- Circle smaller and smaller subcubes until no 1s are left.
6.004 Computation Structures
L4: Logic Synthesis, Slide #17
Write Down Equations
Picking just enough clusters/subcubes to cover all the 1’s in the
KMap, write down a product term for the portion of each
cluster/subcube that is invariant.
C\AB 00
01
11
10
0
0
0
1
1
1
0
1
1
0
\AB
CD\
00
01
11
10
6.004 Computation Structures
00 01 11 10
0
0
1
0
0
1
1
1
0
1
0
1
1
0
0
1
Y = CA + CB
We’re done!
Y = ABC + ABD
+ ABD + BCD
L4: Logic Synthesis, Slide #18
Recap: K-map Minimization
1.  Copy truth table into K-Map
2.  Identify subcubes, selecting the largest available subcube at
each step, even if it involves some overlap with previous
cubes, until all ones are covered. (Try: 4x4, 2x4 and 4x2, 1x4
and 4x1, 2x2, 2x1 and 1x2, finally 1x1)
3.  Write down the minimal SOP realization
JARGON: The circled terms are called
implicants. An implicant not completely
contained in another implicant is called a
prime implicant.
Truth Table
C
B
A
Y
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
6.004 Computation Structures
C\BA 00
01
11
10
0
0
1
1
0
1
0
0
1
1
Y = CA + CB
L4: Logic Synthesis, Slide #19
We’ve Been Designing a Mux
Truth Table
D0
0
D1
1
S
0
0
0
0
1
1
1
1
DS
S
2-input Multiplexer
MUXes can be generalized to
2k data inputs and k select
inputs …
D00
D01
D10
D11
00
01
10
11
S0
S1
6.004 Computation Structures
DS1S0
D1 D0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
DS
0
1
0
1
0
0
1
1
… and implemented
as a tree of smaller
MUXes:
D00
D01
0
0
1
1
0
0
1
1
S
D10
D11
0
0
1
1
Y
S
S
S0
S1
L4: Logic Synthesis, Slide #20
Systematic Implementation Strategies
Consider implementation of some arbitrary Boolean function,
F(A,B,C) ... using a MULTIPLEXER as the only circuit element:
Full-Adder
Carry Out Logic
A
0
0
0
0
1
1
1
1
B Cin Cout
0 0 0
0 1 0
1 0 0
1 1 1
0 0 0
0 1 1
1 0 1
1 1 1
6.004 Computation Structures
0
0
0
1
0
1
1
1
A,B,Cin
0
1
2
3
4
5
6
7
Cout
L4: Logic Synthesis, Slide #21
Synthesis By Table Lookup
A
Muxes are universal!
B
10
0
01
1
AB Fn(A,B)
00
01
10
11
0
1
1
0
Y
=
A
Y
S
A
MUX
Logic
Fn(A,B)
00
0
B1
1
A
= B
Y
Y= A
B
Y
Y
S
A
Generalizing:
In theory, we can build any 1-output
combinational logic block with multiplexers.
2N
For an N-input function we need a _____ input
mux.
Is this practical for BIG truth tables?
How about 10-input function? 20-input?
B0
0
11
1
S
A
In future
technologies muxes
might be the
“natural gate”.
B0
0
B1
1
Y
What
does that
one do?
S
6.004 Computation Structures
A
L4: Logic Synthesis, Slide #22
A New Combinational Device
D0
D1
DECODER:
•  k SELECT inputs,
•  N = 2k DATA OUTPUTs.
Select inputs choose one of the
DN-1 Dj to assert HIGH, all others
will be LOW,,
k
Have I
mentioned
that HIGH
is a synonym
for ‘1’ and
LOW means
the same
as ‘0’
NOW, we are well on our way to building a
general purpose table-lookup device.
We can build a 2-dimensional ARRAY of
decoders and selectors as follows ...
6.004 Computation Structures
L4: Logic Synthesis, Slide #23
Read-only Memory (ROM)
Each column is large fan-in “NOR”
Note location of pulldowns correspond
to a “1” output in the truth table!
Full Adder
A B
Co
FA
Ci
000
S
A
B
Ci
S
Co
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
6.004 Computation Structures
Shared
decoder
001
010
011
100
101
110
For K inputs,
decoder produces 2K
signals, only 1 of
which is asserted at
a time -- think of it
as one signal for
each possible
product term.
111
A
B
CIN
S
COUT
One column
for each
output
L4: Logic Synthesis, Slide #24
Read-only Memory (ROM)
Full Adder
LONG LINES slow down propagation
times…
A B
Co
FA
The best way to improve this is to build
square arrays, using some inputs to
drive output selectors (MUXes):
Ci
S
A
B
Ci
S
Co
00
0
0
0
0
0
01
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
10
A
B
CIN
11
0
1
S
0
1
COUT
2D Addressing: Standard for ROMs, RAMs, logic arrays…
6.004 Computation Structures
L4: Logic Synthesis, Slide #25
Logic According to ROMs
ROMs ignore the structure of combinational functions ...
• Size, layout, and design are independent of function
• Any Truth table can be “programmed” by
minor reconfiguration:
- Metal layer (masked ROMs)
- Fuses (Field-programmable PROMs)
- Charge on floating gates (EPROMs)
... etc.
ROMs tend to
generate “glitchy”
outputs. WHY?
Model: LOOK UP value of function in truth table...
Inputs: “ADDRESS” of a T.T. entry
ROM SIZE = # TT entries...
2N x #outputs
... for an N-input boolean function, size ≅ __________
6.004 Computation Structures
L4: Logic Synthesis, Slide #26
Summary
•  Sum of products
•  Any function that can be specified by a truth table or,
equivalently, in terms of AND/OR/NOT (Boolean expression)
•  “3-level” implementation of any logic function
•  Limitations on number of inputs (fan-in) increases depth
•  SOP implementation methods
•  NAND-NAND, NOR-NOR
•  Muxes used to build table-lookup
implementations
•  Easy to change implemented function -- just change
constants
•  ROMs
•  Decoder logic generates all possible product terms
•  Selector logic determines which terms are ORed together
6.004 Computation Structures
L4: Logic Synthesis, Slide #27

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