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CSE 237A – Winter 2015 – Homework 3 Submission:
Submit a hard copy of your homework in class on 3/3/2015. Problem 1 SDF Given the above SDF, a. Draw the incidence matrix.
Use columns to represent the nodes and rows to represent the edges. b. Find a PASS schedule (assume alphabetical order of tasks) c. For the PASS schedule in part b: i. Show the initial condition of each edge buffer ii. Show the minimum buffer size required by each edge Problem 2 Petri Nets Assume you have a Petri Net N, with P places, T transitions and F flows: P = {P
, P
, P
, P
, P
, P
} 1
2
3
4
5
6
T = {T
, T
, T
, T
, T
}
1 2 3 4 5
F = {(P
, T
),(P
, T
),(P
, T
),(P
, T
),(P
, T
),(P
, T
),(P
, T
),(T
, P
), (T
, P
), (T
, P
), (T
, P
), 1
1
1
3
2
2
3
2
4
4
5
4
6
5
1
2
2
4
3
5
4
3
(T
, P
), (T
, P
)} 4 6
5 1
Initial marking M
= [0, 0, 0, 1, 1, 0] 0
a. Draw the specified Petri Net b. Draw the reachability tree c. Is this net
safe
? Is it
bounded?
Problem 3 Statecharts a. Redraw the above statechart as a finite state machine. b. Given this sequence of inputs, what will be the final state? i. b, w, a, b, w ii. b, w, y, e, r iii. b, w, y, e, s Problem 4 Sampling Assume a linear ADC converter supplies voltage samples between 0V and 3V at 333kHz. a. What is the maximum frequency of the analog input signal that can be accurately detected? b. What is the quantization error for an input voltage of 2.77 if the ADC uses i. 4 bits of resolution ii. 8 bits of resolution c. If it takes 100 instructions to obtain each sample and pass it to application code, what is the % CPU utilization expected on a 800MHz RISC processor that executes 1 instruction per cycle? Problem 5 Memory technologies List 3 major advantages of Magnetoresistive Random Access Memory (MRAM) over traditional SRAM and DRAM for embedded systems. What sort of applications would it
not be appropriate for? Spintransfer torque memory (STTRAM) is a particular type of magnetic RAM. Discuss its key characteristics and outline what type of applications it is wellsuited for, and why. Problem 6 Hardware description languages This is an architectural component as described with VHDL: Describe the intended functionality of this component (you probably need 56 sentences). Discuss if there is a zero delay loop problem in this design that is NOT solvable using microticks (delta delay)? Problem 7 Esterel Examine the following Esterel code and draw the corresponding FSM. await O; emit A; emit B; present B then emit C; await L; suspend loop emit D; await E; pause; end when P Hint
: be mindful of the differences between instantaneous statements and delayed statements Problem 8 PID control Given a controller with all three
proportional
,
derivative
, and
integral
terms: ● If the system movement towards desired setpoint is too slow, we can __________ the proportional gain or ___________ derivative gain. ● If there is steadystate error, we can add a little of __________ gain. ● If the motion overshoots the setpoint and oscillates, we can __________ the derivative gain or reduce __________ gain and __________ gain.
