Design and Test of Core-Based Systems

Transcription

Design and Test of Core-Based Systems
ECE 260C
VLSI Advanced Topics:
System-on-Chip Design
Spring 2015
Sujit Dey
ECE Department
UC San Diego
[email protected]
http://esdat.ucsd.edu
ECE 260C
Sujit Dey
Spring 2015 ECE 260C
• Objective: System-on-Chip Design:
Advanced Topics on SoC design and methodologies
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Lectures: Tuesday, Thursday 2:00pm-3:20pm
– Location: WLH 2207
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Professor Sujit Dey
– Office Hours : Tuesday, Thursday 1:00pm-2:00pm
– Office : Jacobs Hall 4404
– E-mail: [email protected]
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TA: Cong Zhao
– TA/Lab Hours: Monday, Wednesday, Friday 1:00-2:00pm
– Office: EBU1 4307
– Email: [email protected]
ECE 260C
Sujit Dey
Topics
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Introduction to System-on-Chip Design
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System Design Objectives and Design Alternatives
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Hardware Design and Behavioral/RTL Synthesis
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Hardware/Software Co-Design
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General Purpose, Domain-Specific Platforms
Multi-core Processors (Embedded, Mobile, Servers, …)
Multi-Processor System-on-Chip (MPSoC)
Network-on-Chip Design
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ECE 260C
Methodologies, Design Flow, Design Trade-offs
Hardware-Software Co-Simulation and Co-Verification
SoC Platforms, and Multi-core, Multi-Processor SoCs
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Specifications, Scheduling, Resource Sharing and Assignment
On-Chip Communication Architectures, Protocols, and Analysis
Network on Chip Design Techniques; Case Studies
On-chip routers and routing protocols
Sujit Dey
Topics - 2
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Low Power System Design/Green Computing
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Designing System-on-Chips using Nano-meter Technologies
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ECE 260C
Introduction to Low Power Design
Low Power Processor/Software Design
Power Management Techniques for SoCs
Battery Aware Mobile/Embedded Devices
Power Electronics for Renewable Energy, Smart Grids
Smart Power Management Systems
Energy Efficient Servers/Data Centers, Thermal Management
Roadmap and Issues
Leakage Current: Design Techniques
Variability due to Process Variations, and Variability Tolerant Design
Nano-meter Test Issues and Techniques
Design for Reliability (Self-Repair etc)
Sujit Dey
Design Projects
• Requirement:
• Working knowledge of Verilog
– no Verilog lessons will be given in this course
• Schedule:
• Project 1: April 14; Due: May 12
• Project 1 Presentation: May 12, 14, 19
• Project 2: May 14
• Due: May 28
ECE 260C
Sujit Dey
Grading
Design Projects
Project 1
Project 1 Presentation
Project 2
Final Demonstration
25%
10%
15%
10%
Project group size: 2 students
Topic Survey and Research:
• Term Paper
20%
• Presentation
20%
ECE 260C
Sujit Dey
ECE 260C Lab
• Assigned ACS Lab
• EBUI-4307
• 24-hour/day access with combination
• Toolset: Mentor Graphics, Synopsys, ARM
• Hardware Simulators and Synthesis Tools
• Embedded Software Design Tools
• Hardware-Software Co-Design/Simulation Tools
ECE 260C
Sujit Dey