Design and Verification of Speed-Independent Multiphase Buck

Design and Verification of
Speed-Independent
Multiphase Buck Controller
Danil Sokolov1 , Victor Khomenko1 , Andrey Mokhov1 ,
Alex Yakovlev1 , David Lloyd2
1
Newcastle University, UK; 2 Dialog Semiconductor, UK
Motivation
•
Efficient implementation of power converters is paramount
•
•
•
Extending the battery life of mobile gadgets
Reducing the energy bill for PCs and data centres
(5+3% of global electricity production)
Need for responsive and reliable control circuitry - little digital
Millions of control decisions per second for years
• An incorrect decision may permanently damage the circuit
•
•
Poor EDA support
Synthesis is optimised for data processing - big digital
• Ad hoc solutions are prone to errors and cannot be verified
•
2 / 19
Basic buck converter: Schematic
over-current (oc)
I_max
Th_pmos
buck
control
gp_ack
gp
PMOS
oc
uv
zc
R_load
gn_ack
NMOS
gn
Th_nmos
zero-crossing (zc)
V_0
under-voltage (uv)
•
V_ref
In the textbook buck a diode is used instead of NMOS transistor
3 / 19
Basic buck converter: Informal specification
current
PMIN
NMIN
NMIN
PMIN
PMIN
UV ZC
OC
ZC
late ZC
N
FF
O
UV
O
S
O
S
O
M
O
O
PM OS
M
N
FF
PM
O
PMOS OFF
NMOS OFF
N
S
ON F
OS OF
NM OS
N
PM
no ZC
OC
N
O F
S
F
O
O
NM OS
UV
PM
N
PM MO
O SO
S
O N
FF
P
NM MO
O SO
S
O N
FF
I_max
time
OC
early ZC
no ZC – under-voltage without zero-crossing
• late ZC – under-voltage before zero-crossing
• early ZC – under-voltage after zero-crossing
•
4 / 19
Multiphase buck converter: Schematic
over-current (oc)
I_max
Th_pmos
gp_ack1
buck
oc1
gp1
PMOS[1]
NMOS[1]
gn1
zc1
gn_ack1
Th_nmos
V_0
control
I_max
Th_pmos
gp_ackN
ocN
PMOS[N]
uv
NMOS[N]
R_load
gpN
hl
gnN
zcN
gn_ackN
Th_nmos
zero-crossing (zc)
V_0
under-voltage (uv)
high-load (hl)
V_min
V_ref
5 / 19
Multiphase buck converter: Informal specification
•
Normal mode
Phases are activated sequentially
• Phases may overlap
•
•
High-load mode
•
•
All phases are activated simultaneously
Benefits
Faster reaction to the power demand
• Heat dissipation from a larger area
• Decreased ripple of the output voltage
• Smaller transistors and coils
•
6 / 19
Synchronous design
•
Two clocks: phase activation (~5MHz) and sampling (~100MHz)
Easy to design (RTL synthesis flow)
Response time is of the order of clock period
Power consumed even when idle
Non-negligible probability of a synchronisation failure
•
Manual ad hoc design to alleviate the disadvantages
Verification by exhaustive simulation
7 / 19
Asynchronous design
•
Event-driven control decisions
Prompt response (a delay of few gates)
No dynamic power consumption when the buck is inactive
Other well known advantages
Insufficient methodology and tool support
• Our goals
•
•
•
•
Formal specification of power control behaviour
Reuse of existing synthesis methods
Formal verification of the obtained circuits
Demonstrate new advantages for power regulation
(power efficiency, smaller coils, ripple and transient response)
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High-level architecture: Token ring
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High-level architecture: Stage
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High-level architecture: Activation
11 / 19
High-level architecture: Activation
11 / 19
WAIT element
12 / 19
WAIT element
•
STG specification
•
ME-based solution
Read-consume conflict
between output and input.
•
Gate-level implementation
can be removed
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High-level architecture: Charging
13 / 19
High-level architecture: Charging
ZC
ZC
O
S
O
S
O
N
FF
PMOS OFF
NMOS OFF
O
S O
O
PM OS
M
N
FF
PM
O
ON F
OS OF
NM OS
PM
N
NMIN
M
PMIN
N
NMIN
N
O F
S
F
O
O
NM OS
PM
N
PM MO
O SO
S
O N
FF
P
NM MO
O SO
S
O N
FF
PMIN
UV
early ZC
OC
13 / 19
Synthesis flow
•
Manual decomposition of the system into modules
To create formal specification from informal requirements
(feedback loop with engineers)
• To simplify specification and synthesis
• Some modules are reusable
• Some modules (WAIT and O PPORTUNISTIC M ERGE) are
potential standard components
•
Each component is specified using STGs
• Automatic synthesis into speed-independent circuits
•
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ZC_HANDLER module
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ZC_HANDLER module
•
STG specification
15 / 19
ZC_HANDLER module
•
Speed-independent implementation
15 / 19
Formal verification
•
STG verification
All standard speed-independence properties
• PMOS and NMOS are never O N simultaneously
(no short circuit)
• Some timers are used in a mutually exclusive way
and can be shared
•
•
Circuit verification
Conforms to the environment
• Deadlock-free and hazard-free under the given environment
•
16 / 19
Tool support: W ORKCRAFT
•
Framework for interpreted graph models (STGs, circuits, FSMs,
dataflow structures, etc.)
Interoperability between models
• Elaborated GUI
•
•
Includes many backend tools
P ETRIFY – STG and circuit synthesis, BDD-based
• P UNF – STG unfolder
• MPS AT – unfolding-based verification and synthesis
• PC OMP – parallel composition of STGs
•
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Tool support: W ORKCRAFT
18 / 19
Conclusions
•
Fully asynchronous design of multiphase buck controller
Quick response time: few gate delays, all mutexes are
outside the critical path
• Reliable: no synchronisation failures
•
•
Design flow is automated to large extent
•
•
•
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Automatic logic synthesis
Formal verification at the STG and circuit levels
New standard components (WAIT and O PPORTUNISTIC M ERGE)
Future work
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•
•
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Measurements!
Development of WORKCRAFT to support hierarchical design
Co-simulation and co-verification of digital/analogue circuits
Better integration with the Synopsys and Cadence flows
19 / 19