PDF of the presentation materials are available here

Transcription

Trends In Materials: The
Smartphone Driver
Smartphone ICs Driving Technology to 3D Stacked Devices/Chips, 3-D FinFET
Transistors and High Mobility Channel
Material From 20/22nm Production to
5/7nm Exploratory Research
John Ogawa Borland
J.O.B. Technologies
Aiea, Hawaii
www.job-technologies.com
April 30, 2015
J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
1
Outline
• Introduction: Smartphone as new technology driver
– 2012: iPhone 5 uses Sony’s 3-D stacked backside CMOS image sensor camera
– 2015: 1) Samsung Galaxy S6 and Apple iPhone 6s A9 application processors
switches to 14/16nm 3-D FinFET. 2) Samsung Galaxy S6 introduces 3-D ePoP
(embedded package on package)
• 22/20nm Node: Smartphone Application Processor 2014-2015
using 3-D bulk-FinFET from Intel (China low end smartphones),
2-D planar by TSMC and Samsung (A8-iPhone6 & Galaxy-S5)
3-D bulk-FinFET 1st generation by TSMC & Samsung (GalaxyS6 and A9-iPhone6s), 2nd generation by Intel
• 10/7nm Node: High mobility material SiGe or Ge Fin channel
Formation
• Exploratory Research 5nm Node: High mobility material
Nano-wire channel formation
• Dopant Activation and Junction Leakage in Ge and SiGe
2
• Summary
2014=$336B
2014 total smartphone sales were 1.24B units.
Q4/14=367.5B smartphones
Q1/15=71.7B PC/tablets
Marketing, Sales &
Technology)
3
Marketing, Sales &
Technology)
4
USA Today March
4, 2015
S3
i4s
S4
i5
S5
i5s&5c
S6
i6
2014 total=1.24B smartphones
#1 Samsung=26% (307M units)
#2 Apple=15% (191M units)
Company
4Q14 4Q14 Market
Units
Share (%)
Apple
74,832
Samsung
73,032
Lenovo*
24,300
Huawei
21,038
Xiaomi
18,582
Others
155,701.6
Total
367,484.5
Marketing, Sales
&
Technology)
20.4
19.9
6.6
5.7
5.1
42.4
100.0
Gartner, March 6, 2015
5
2014: 1.87B Total Mobile Phones
(Smartphones + standard cell phones)
Company
Samsung
Apple
Microsoft
Lenovo*
LG Electronics
Huawei
TCL Communication
Xiaomi
ZTE
Sony
Micromax
Others
Total
Company
Smartphones
Samsung
Apple
Lenovo*
Huawei
LG Electronics
Others
Technologies (Strategic
Total J.O.B.
Marketing, Sales &
Technology)
2014
1000x Units
392,546
191,426
185,660
84,029
76,096
70,499
64,026
56,529
53,910
37,791
37,094
629,360
1,878,968
2014
1000x Units
307,597
191,426
81,416
68,081
57,661
538,710
1,244,890
2014 Market
Share (%)
20.9
10.2
9.9
4.5
4.0
3.8
3.4
3.0
2.9
2.0
2.0
33.5
100.0
2013 2013 Market Share
1000x Units
(%)
444,472
24.6
150,786
8.3
250,835
13.9
66,463
3.7
69,094
3.8
53,296
2.9
49,538
2.7
13,423
0.7
59,903
3.3
37,596
2.1
25,431
1.4
587,764
32.5
1,808,600
100.0
2014 Market
2013
Cell-P Share (%)
1000x Units
85M
24.7
299,795
0M
15.4
150,786
3M
6.5
57,424
2M
5.5
46,609
19M
4.6
46,432
43.3
368,675
634M
100.0
969,721
Gartner, March 6, 2015
2013 Market
Cell-P Share (%)
145M
30.9
0M
15.5
5.9
4.8
4.8
38.0
6
839M
100.0
2005 2007 2009 2012 2014
Jan 16, 2013 Intel announced at Consumer
Electronics Show new Atom platform for
rapidly growing low-end smartphone market
Marketing, Sales &
in China!
Technology)
7
& msec Flash
SF-stressor
Intel, Sept. 6, 2011
A5 A6 A7 A8 A9
45nm 32nm 28nm 20nm 14/16nm
Altera to use Intel 14nm Foundry reported by EETimes Feb 26, 2013: The “Mobile Foundry” will ramp
to billions of IC chip units across many suppliers while the PC chip TAM is only 400M units so mobile
8
chip market
potential
Marketing,
Sales & to be 10x larger in size than PC and Intel wants to get part of this to continue their
Technology)
growth which
was -1% in 2012! (Q1/2015 smartphone AP= >5x PC!)
9/9/14: Apple announces A8 SOC for iPhone 6 & 6+:
Apple’s A8 is their first SoC built on 20nm node technology with 2B
transistors and is 13% smaller than the A7 for 25% faster CPU than the A7. Compared
to iPhone 1, iPhone 6 CPU performance is 50x as shown in the slide photo below left
and table below.
iPhone 5 uses A7: 28nm node technology from Samsung/foundry
iPhone 6 uses A8: 20nm node technology from TSMC
Next iPhone Sept 2015 will use A9: 14nm node FinFET from Samsung
& 16nm FF+ from TSMC
Marketing, Sales &
Technology)
9
3-D stacked devices
-CMOS image sensor
-Flash
-DRAM
Low leakage
3-D FinFET
Marketing, Sales &
Technology)
Wakabayashi
10
Marketing, Sales &
Technology)
11
Sony Front-Side versus BackSide Illumination Patent
Application US 2003/0025160A1
No Micro-Lensing for
Backside Illumination
3-D
Buried Photodiode
(Silicon on Glass)
Poly
n+
n+
Poly
Silicon
n+
(Thin or Thick)
Oxide
Contact
Light Shield
(Opaque)
Buried Photodiode
Transparent Electrode (ITO)
Color Filter Optional
Infrared Filter
Quartz
J.O.B.Technologies
(StrategicMarketing,Sales&Te
chnology)
Borland & Tokoro, Nov 2004, Asia Pacific,
Solid State Technology, p. S18
12
Jan & July 2012
J.O.B. Technology (Strategic
Marketing, Sales &
Technology)
13
DRAM 3-D Capacitor Cell
1999 Samsung DRAM HSGpoly-Si Stack Capacitor Cell
1987 IBM 4Mb DRAM Trench Capacitor Cell:
1st high volume production use of CMP for
planarization of poly trench fill and selective
silicon for local strap/interconnect.
Marketing, Sales &
Technology)
14
DRAM 3-D Memory Array Transistor
Marketing, Sales &
Technology)
15
IBM 32nm 3-D Stacked
DRAM-Die + Logic-Die
in 1 Package with TSV
(through-silicon-via)
Marketing, Sales &
Technology)
16
IEDM-2014 Paper 3.8 by Lin of IBM/EFK not Alliance on “High Performance 14nm
SOI FinFET CMOS Technology with 0.0174um2 embedded DRAM and 15 Levels of
Cu Metallization”.
eSiGe
Marketing, Sales &
Technology)
17
256Gb
128Gb
2015
$0.50
Marketing, Sales &
Technology)
18
Bez, ST, IEDM-2011 short course
3-D NAND Flash market delayed was reported Feb 19, 2015 in Semiconductor Engineering:
Only Samsung in production with 3-D NAND Flash since 2013. Micron/Intel will start
production 2nd half of 2015 and SK Hynix plans pilot production later in 2015. SanDisk/Toshiba
3-D NAND not until 2016 and Spansion/XMC not until 2017. Today Samsung has 128Gb Flash
using 16nm node technology and can achieve same die area at 128Gb with 32-layer 3-D NAND
based on 40nm technology node but to compete price per bit with 3-D NAND requires >48layers! 128Gb Flash memory stick $64 at Best Buy (50¢/Gb). Below is Samsung’s 32-layer 3-D
NAND chip reported by Chipworks Aug 2014.
Marketing, Sales &
Technology)
19
Samsung mass producing high-density ePoP memory for
Smartphones
Samsung on Feb10, 2015 announced that they will be mass producing the extremely
thin ePoP (embedded package on package) memory, a single memory package
consisting of 3GB LPDDR3 DRAM, 32GB eMMC and a controller for use in high-end
smartphones. Replacing that set-up with a Samsung ePoP reportedly decreases the total
area used by approx. 40%. Samsung is basically stacking all the memory, both RAM
and NAND, on a single ePoP module that’s then positioned on top of the processor,
rather than beside it as shown below. It is rumored to be spec’ed in the Galaxy S6 and
other top mobile devices later this year.
Solid State Technology reported Feb 10, 2015
Marketing, Sales &
Technology)
Samsung Galaxy S6 to be introduced on April 10, 2015
20
Outline
Formation
21
• Summary
Intel 22-nm nMOS Epi or Not? To
understand Intel’s 22nm FinFET
process details you must know
what they did for 32nm planar!
Borland disagree, I say amorphous
implant EOR defects not n+ SEG
Dick James, X-TEM, Chipworks, April, 2012
22
Intel IEDM-2012 paper 3.1 on 22nm Tri-gate
SoC Technology
Like for 32nm planar production in 2009!
-pMOS: SDE-implant, S/D recess etch then eSiGe
-nMOS: SDE-implant, S/D -implant with amorphous-P+Carbon+ Stacking Fault stressor and
raised S/D epi
Marketing, Sales &
Technology)
23
Looks like 45nm eSiGe
Looks like 65nm eSiGe
Defect layer?
?
Intel-SoC, IEDM-2011 & 2012
Marketing, Sales &
Technology)
24
Intel 32nm PC Chip
Below
detection
Below
detection
As n+SDE
below
detection
Marketing, Sales &
Technology)
Prof. Ogura, Meiji Univ. July -2012
25
Chipworks Teardown of Intel
22nm pMOS FinFET
32nm
26
Dick James, Chipworks, Semicon/West 2013 WCJUG meeting
Ge-channel
Next?
Mobility
Relax-Si
1
Strain-Si 10x
Relax-Ge 4x
Strain-Ge 25x
ID
1
1.8x
2x
2.5x
Kirshnamohan et al., Stanford Univ. ,
VLSI Sym 2006, section 18.1
Kuhn, Intel,, ECS Oct 2010
17%
22%
90nm
65nm
30%
40%
55%
32nm 22nm
S. Thompson, U of F, VLSI Sym 2006 short course
14nm
Maxed out need Ge!
Marketing, Sales &
Technology)
45nm
27
32nm
Chipworks Teardown of Intel
22nm nMOS FinFET
32nm
Ogura, Meiji Univ.
Phos doped Epi S/D has no recess etch!
Amorphous S/D stressor implant
Phos-implant?
Need to look for As also!
28
Dick James, Chipworks, Semicon/West 2013 WCJUG meeting
But Pss~1.8E21/cm3 so this
must be chemical and not
electrical!
Marketing, Sales &
Technology)
29
IIT-2014 nFinFET Doping Paper by Intel
Dick James, Chipworks
Pipes et al., Intel, IIT-2014, p. 37
4/27/2015
30
Ogura, Meiji Univ.
Pss=1.5E20/cm3
32nm
2.3nm/decade
5.8nm/decade
15.1nm/decade
Box-like profile for P
when C dose increases
between 1-2E15/cm2
Dick James, Chipworks
22nm
Marketing, Sales &
Technology)
31
Nagayama, Nissin, IWJT-2010 paper 3.4
Amorphous implant boosts C-stressor by 50%!
Marketing, Sales &
Technology)
32
Borland et al., JOB/Nissin/Applied/KT/EAG/Toshiba, IEEE-RTP-2009
Arsenic-SDE and Phos-S/D causes amorphization of
Fin so SPE forms Carbon+Stacking Fault Stressor
Marketing, Sales &
Technology)
33
Dick James, Chipworks, Semicon/West 2014 discussions
Ohmi, Tokoku Univ, SSDM-2013
My Sony contact in July 2012
said 8 degree Fin slope for (551)
plane reported
by Tokoku Univ
Marketing, Sales &
Technology)
in 6/2007!
34
FinFET Doping Options
3-D FinFET require some form of S/D extension doping under the side wall
spacer for gate overlap control. Two basic method of doping are either:
•Direct junction doping by implantation with or without diffusion using:
1)Beam-line high tilt implantation for electrical conformal doping using amorphous
SPE dopant activation (JOB Tech Insight-2009 and Intel doing for 22nm FinFET)
2)Plasma implantation for chemical conformal doping (IMEC and others reported
not really conformal)
3)Plasma deposition followed by tilted beamline knock-in doping (SEN SSDM-10)
•Deposited doped layer requiring lateral dopant diffusion using:
1)Plasma deposition doping and diffusion (IMEC reported, limited by dopant solid
solubility)
2)Doped epi deposition and diffusion (IBM reported, limited by dopant solid
solubility)
3)Monolayer deposition and diffusion (Sematech/CNSE reported, poor dopant
solid solubility limited)
Hydrogen surface passivation for highest retained dose and controlled amorphous
junction depth <10nm for highest SPE dopant activation.
Single & Multi-FINFET Double-Gate Devices
Plasma Doping for Multi-FIN Gate/Poly
High Tilt Implant For LG-SS/D
Y.K. Choi et al, IEDM-2001
Asymmetric n+/p+ Poly/Gate
Marketing, Sales &
Technology)
Borland, Moroz, Iwai, Maszara & Wang, Varian/Synopsys/TIT/AMD/TSMC,
36
Solid State Technology, June 2003
Intel IIT-2014: Very good conformal Fin doping with 45 Applied IIIT-2014: Poor 10x worse conformal Fin
degree tilted As-implantation.
doping with plasma!
IWJT-2011 paper S8-2 by
Vandervorst of IMEC
showing very good
conformal carrier
concentration
Marketing, Sales &
Technology)
IWJT-2011 paper S2-1 by
Sue Felch of IBS severe
loss of plasma dopant after
annealing!
37
Marketing, Sales &
Technology)
38
SEN, SSDM-2010
Any deposition doping requires lateral
diffusion which will be limited by dopant
solid solubility activation unless amorphous
SPE or LPE as shown by Intel.
5.7E20/cm3
Kennel, Intel, IEEE/RTP 2006
With SPE Non-Equilibrium
Activation of Boron >>Bss
But Requires Amorphization!
Boron activation limited
by low Bss (Boron solid
solubility) and not by
implanted dose
Marketing, Sales &
Technology)
39
High Tilt p+ & n+ Molecular
Implantation For 3-D Structures:
Retained Chemical Dose Versus
Electrical Activation Limited
Conformal Doping
John Ogawa Borland
Especially with
J.O.B. Technologies, Aiea, Hawaii
msec Annealing
&
Masayasu Tanjyo, Tsutomu Nagayama and Nariaki Hamamoto
Nissin Ion Equipment, Kyoto, Japan
INSIGHTS 2009
April 28, 2009
Marketing, Sales &
Technology)
40
B Needs PAI or MSA >1300C!
Marketing, Sales &
Technology)
41
IWJT-2011 paper
S8-2 by IMEC
Marketing, Sales &
Technology)
42
Dummy Fin
Thinner
Photoresist
Duffy et al., INSIGHTS May 2007
Tri-Gate Aspect Ratio
1 to 1 so 45 to 63.5
degree tilt is OK
Bulk FinFET
Oxide &
Not BOX Silicon!
Influence of Surface Passivation on B,
B18H22 and B36H44 Retained Dose for USJ
My IWJT-2011 S7-3 paper. My message was that for Tri-Gate with a 1
to 1 aspect ratio a dual mode 63.5 degree tilt implant for the Fin will
give you equal 100% chemical conformality on the top and side wall of
the Tri-gate Fin especially when you use hydrogen surface passivation
compared to oxide surface passivation at high tilt angles and/or low
energies. (NOT AN ISSUE WITH ROUNDED FIN-TOP)
Flat Fin-Top
Marketing, Sales &
Technology)
Round Fin-Top
44
PCOR-SIMS Analysis Of Surface Oxide &
Retained Dose
Surface Passivation Oxide Thickness (nm)
3.0
P
P4
B36(R)
B18(R)
2.5
2.0
As & As4
B(R)
1.5
1.0
B(R)
Hydrogen Bake
Surface Passivation
1 month later
0.5
B18 & B36(R)
0.0
0
10
20
30
40
50
60
70
80
90
100
Implant Retained Dose %
45
Proof Of Surface Reflectance/Backscatter On
Retained Dose Limit & Implant Oxide Growth
Implant oxide growth
Ge shift due to oxide growth
H2
B
B18
B36
Ox
B
B18
B36
Marketing, Sales &
Technology)
Ge
6.9nm
7.0nm
6.9nm
6.9nm
6.9nm
7.0nm
6.7nm
6.9nm
Ox
0.2nm
0.57nm
0.45nm
0.46nm
1.8nm
2.05nm
2.18nm
2.3nm
Xj
R.Dose
8.3nm 8.89E14
7.7nm 8.44E14
8.6nm 8.35E14
7.7nm 8.0E14
7.6nm 6.09E14
9.6nm 5.96E14
46
Renesas/JOB/EAG, SSDM-2010
Hydrogen Annealing of Si & Ge Surface
Round Top
4/27/2015
LER (line-edgeroughness)
Advanced Integrated Photonics, Inc. Proprietary
Smooth Sidewall
47
Hydrogen Bake Causes Si-surface Migration and
Si/oxide Under-cut! Good for Bulk not SOI FinFET
44) M. Arst, J. Chen, K. Ritz, J. Borland and J. Hann, “A Novel Simultaneous Single/Poly Deposition (SSPD)
Technique For New And Scaled-Down Device Structures”, Semiconductor Silicon 1990, the Electrochemical
Society, PV 90-7, p.794, 1990.
45) M. Arst, K. Ritz, S. Redkar, J. Borland and J. Hann, “Surface Planarity And Microstructure Of Low Temperature
Silicon SEG And ELO”, Journal of Materials Research, the Materials Research Society, vol.6, no.4, p.784, April
1991.
H2 Bake Reduce LER (line-edge-roughness) Not With
SOI-FinFET!
4/27/2015
48
iPhone 6 Mother board
Marketing, Sales &
Technology)
49
iPhone 6+ Mother board
TSMC 20nm Node: Stacking Fault-Stressor 4/5 years
after Intel’s 32nm Node in 2009
TSMC, US Patent #8,674,453 B2, 3/18/14
D. James, Chipworks, Oct 2014
Is SF-stressor+eSiP
epi stressor better?
Marketing, Sales &
Technology)
Intel 32nm
50
Outline
Formation
51
• Summary
Intel can still use Bi-mode up to 41 degree tilt
implant or Quad-mode >45-60 degree tilt!
For 14nm I
estimate Intel can
use up to 41 degree
tilt if twist is 0
degree for bi-mode
but if twist is 45
degree then Quadmode >45-60
degree is OK!
For 22nm I
said 3 years
ago Intel
could use up
to 52 degree
high tilt
implant.
8 degree taper=(551) plane &
45+8=53 degree effective tilt
Marketing, Sales &
Technology)
52
Intel 8/11/14
IEDM-2014 Paper 3.7 by Natarajan of Intel on “A 14nm Logic Technology
Featuring 2nd Generation FinFET Transistors, Air-Gapped Interconnects,
Self-Aligned Double Patterning and a 0.0588um2 SRAM cell size”.
sub-fin doping technique of high performance transistor by solid source doping for better punchthrough stopper dopants. Idsat & Idlin for nMOS +15% & +30% and for pMOS +41% & +38%
No discussion on p+ or n+ eS/D stressor! Chipworks
says eSiGe=55% like 22nm node
First time Intel is using embedded n+epi for
nS/D which is full of epi stacking faults
Marketing, Sales &
Technology)
53
Intel 14nm nMOS FinFET
Dick James, Chipworks, Feb 2015
Marketing, Sales &
Technology)
54
IEDM-2014 Paper 3.1 by Wu of TSMC on “An Enhanced 16nm
CMOS Technology Featuring 2nd Generation FinFET Transistors
and Advanced Cu/low-k Interconnect for Low Power and High
Performance Applications”.
A disappointment this year as in last year in that
TSMC showed no images nor listed any dimensions
of the FinFET structure so as Dick James of
Chipworks stated in his blog with NO images of the
FinFET we have no idea what the FinFET looks
like (ie tapered or vertical Fins, recess/raised S/D
WITH DUAL EPITAXY PROCESSING).
Marketing, Sales &
Technology)
55
Samsung
Galaxy S6
ePOP
Battery
Dick James, Chipworks, April 6, 2015
Marketing, Sales &
Technology)
56
Samsung Galaxy S6
Dick James, Chipworks, April 6, 2015
eSiGe?
Marketing, Sales &
Technology)
57
Source: IHS Technology April 2015
SAMSUNG GALAXY S6 EDGE SM-G925V Top Cost Drivers
Itemized Components
MfgName
Description
Total Cost
Display
SAMSUNG
Display / Touchscreen Module, 5.1″
Quad HD Super AMOLED,
2560×1440 Pixels, 577PPI, Dual Edge
$85.00
Apps Processor
SAMSUNG
Apps Processor – Octa-Core, 64-Bit, 14nm, PoP
$29.50
Baseband IC
QUALCOMM
Baseband Processor – Multi-Mode, 28nm, PoP
$15.00
NAND (eMMC, MLC, …)
SAMSUNG
Flash – UFS NAND, 64GB, PoP
$25.00
DRAM
SAMSUNG
SDRAM – LPDDR4, 3GB, PoP
IC Content
Memory
39¢/Gb!
$27.50
Power Management Ics
$5.40
RF / PA Section
$12.50
User Interface Ics
$9.95
Sensors
$4.80
Modules
Primary Camera Module
Rear Camera Module – 16MP, BSI CMOS, OIS
$18.50
Secondary Camera Module
Front Camera Module – 5MP, BSI CMOS
$3.00
BT / WLAN Module(s)
MURATA
BT / WLAN Module
$4.00
Battery Pack(s)
ITM
Li-Polymer, 3.85V, 2600mAh, 10.01Wh
$3.50
Other Noteworthy Items
Box Contents
Marketing, Sales &
Technology)
Enclosure elements
58
$6.20
Die-Cast Aluminum Center Piece &
$12.00
Outline
Formation
59
• Summary
Marketing, Sales &
Technology)
60
Samsung Logic Roadmap, Dec. 2014
*2014: SiGe-FinFET at 14nm
*2016: Ge-FinFET at 10nm
*2018: Nano-wire at 5nm (Si,
SiGe and Ge)
IEDM-2013 short course
4/27/2015
Advanced Integrated Photonics, Inc. Proprietary
61
IEDM-2014 Paper 16.1 by Hashemi of IBM/GF on “First Demonstration
of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS
FinFETs with High Hole Mobility and Aggressively Scaled Fin
Dimensions and Gate Lengths for High Performance Applications”.
Fig.14 shows hole mobility increases by 2.2x from uh=160 to 400 with
decreasing Fin width (WFIN) due to the transformation of strain from biaxial to
uniaxial. The uh=160 corresponds to a 1E18/cm3 channel doping level for 50%
SiGe in the literature. The uh=400 would be for 80-100% SiGe channel at the
same doping level.
Need >50% Ge to enhance
hole mobility?
(Strategic
Oct J.O.B.
2014Technologies
ECS IBM
Alliance paper P7-1791
Marketing, Sales &
Technology)
62
Electron mobility
Hole mobility
H2 anneal
Sb-JOB laser
Ge-Cz
U of Tokyo
B-JOB laser
IBM
50%
SiGe
p+Fin
4/27/2015
P-JOB laser
P or As
Excico
63
See large variation in reported Ge electron & hole mobilities reported in the literature!
Blanket Ge-layer first
then Ge-Fin etch
Selective Ge-epi Fin
Borland: Localized GeLPE by Laser Melt
Oct 2004 ECS: GeGCIB/Infusion (E17/cm2)
June 2013 IWJT: Ge-plasma
implant (1E17/cm2)
Oct 2014 ECS: Ge-beamline
implant (5E16/cm2)
64
4/27/2015
IEDM-2013 short course
SSDM-2013 Univ of Tokyo Si-Photonics paper K-1-1 on “Ge Active Photonic Devices on Si for
Optical Interconnects” was a invited review paper so no new data only a review. In Fig.2 below
he showed a 800oC Ge-Epi post anneal can reduce TDD from 109/cm2 to <107/cm2. Fig.4 shows
the Si-cap for n+ doping of the PIN.
Marketing, Sales &
Technology)
65
Ge-channel Formation By Ge-Infusion Doping
ALD-HfSiO
1) EOT reduced from
1.46nm to 1.26nm with insitu bake due to GeO
eliminationat >430C.
2) Leakage reduced from
0.07A/cm2 to 0.04A/cm2
without bake.
3) pMOS good devices
4) nMOS poor devices
nMOS Ge-channel formation using replacement gate process flow
Marketing, Sales &
Technology)
66
Borland et al., JOB/ReVera/SSM/Genus/Epion, Solid State Technology, July 2005
GCIB Ge-Doping/Deposition (Solid Phase Epitaxy)
70nm Ge-DCD on 300mm bulk & SOI wafer
<0.45% uniformity
4E17/cm2=90nm
a-Ge
a-SiGe
c-Si
Marketing, Sales &
Technology)
Borland et al., JOB/Epion, ECS Oct 2004
67
HF-vs-No HF
Cleaning For Ge
Infusion
Marketing, Sales &
Technology)
SSDM-2011: Intel 32nm Node
Channel strain measurements
Munehisa Takei1, Hiroki Hashiguchi1, Takuya Yamaguchi1, Daisuke
Kosemura1, Kohki Nagata1, 2, and Atsushi Ogura1
1School of Science and Technology, Meiji University, 1-1-1
Higashimita, Tama-ku, Kawasaki, 214-8571, Japan
3.75GPa
850MPa
Localized/Selective Ge & SiGe
Formation By Liquid Phase
Epitaxy (LPE) Using Ge+B
Plasma Ion Implantation And
Laser Melt Anealing
IWJT June 6, 2013
JOB Technology, Micron, Innovavent, Excico, KLA-Tencor, CNSE, EAG & UCLA
Ge 3keV at 1E16/cm2 (Ge=20%) & 1E17/cm2 (Ge=55%)
B2H6 500V at 4E15/cm2 & 4E16/cm2
Ge+B Plasma Implanted Wafers Provided by Micron
Laser Melt Annealing Provided by Innovavent & Excico
Marketing, Sales &
Technology)
70
Marketing, Sales &
Technology)
71
ALP Hall Analysis of 308nm
Slot#14:Ge=1E16+B=4E15
Slot#18: Ge=1E17+B=4E16
170
Mobility JA14ED12-1
>4x hole-mobility!
160
Drift
Ge=1E17/cm2 + BH=4E16/cm2
150
140
130
120
Mobility (cm2V-1s-1)
110
100
90
80
70
Ge=1E16/cm2 + BH=4E15/cm2
60
50
40
Ge=0%+BH=4E16/cm2
30
20
10
0
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
Depth
Depth (Å)
(Å)
Borland et al., IWJT-2013
Liquid Phase Epitaxy (LPE)
Formation of Localized High
Quality/Mobility Ge & SiGe by High
Dose Ge-Implantation with Laser Melt
Annealing for 10nm and 7nm Node
Oct 6, 2014 ECS Conference on SiGe & Ge Technology
John Borland1,2, Michiro Sugitani3, Peter Oesterlin4, Walt Johnson5, Temel
Buyuklimanli6, Robert Hengstebeck6, Ethan Kennon7, Kevin Jones7 & Abhijeet Joshi8
1JOB
Technologies, Aiea, Hawaii
2AIP, Honolulu, Hawaii
3SEN, Shinagawa, Tokyo, Japan
4Innovavent, Gottingen, Germany
5KLA-Tencor, Milpitas, California
6EAG, East Windsor, New Jersey
7University of Florida, Gainsville, FL
8Active Layer Parametrics, LA, CA
JOB Sample 3 Si Sb+Ge 3E15 5E16 No Anneal (Sb, Ge)
JOB Sample 5 Si Sb+Ge 3E15 LMA 4J 1200ms (Sb, Ge)
1E+23
1E+03
1E+03
TotalSample
Sb
JOB
4 Si Sb+Ge 3E15 LMA 3.2J (Sb, Ge)
Total Sb
1E+22
1E+02
1E+02
Si->
Si->
Si->
O->
1E+21
Ge->
1E+01
1E+01
Ge=>7%
O->
TotalSb
1E+20
1E+19
1E+00
1E+00
1E-01
1E-01
O->
1E+18
O,Si,Ge CONCENTRATION (atom%)
Sb CONCENTRATION (atoms/cc)
Ge->
Ge->
350nm
1E-02
1E-02
1E+17
0
10
20
30
1E-03
1E-03
40
40
50
50
60
60
70
70
80
80
Fig
Fig#03
#05 Y0DKY928_YR_37
Y0DKY928_YR_38 Sample
Sample35SiSiSb+Ge
Sb+Ge3E15
3E155E16
LMA No
4J 1200ms
Anneal (Sb,
(Sb,Ge)
Ge)
#04
DEPTH
(nm)
DEPTH Fig
(nm)
Marketing, Sales &
Technology)
Y0DKY928_YR_54 Sample 4 Si Sb+Ge 3E15 LMS 3-2J (Sb, Ge)
1/11/2014
1/11/2014
1/13/2014
74
Electron Mobility
500
Ge=100%
450
400
Mobility[cm2/V-s]
350
300
250
4% Ge
Ge+Sb 3E13 4J/cm2 for 600ns
200
Ge=100%
Ge=25%
150
Si=100%
Ge=100%
100
Sb 3E15 4J/cm2 for 600ns
50
0
1E+12
1E+13
1E+14
Sb Concentration
Borland et al., ECS Oct 2014
1E+15
Si=100%
Ge=0%
1E+16
75
B=4E16
Ge-channel Formation by Ge implant, plasma or
GCIB doping (n+Si-cap S/D doping)
nMOS Ge-channel formation using replacement gate process flow
n+ Si-S/D Ge-channel
Bulk Si-wafer
Borland et al., SST July 2005 & US Patent #7,259,036 Aug 22, 2007
nMOS Ge-Fin/channel
nMOS n+ Si-S/D
Borland proposal March 2012
Ge
or
SiGe
Oxide
Oxide
Bulk Si-wafer
Si-SEG
n+ S/D
Ge
or
SiGe
Oxide
76
IEDM-2014 Paper 16.5 by Mitard of IMEC on “First
Demonstration of 15nm WFIN Inversion Mode Relaxed Ge nFinFETs with Si-cap Free RMG and NiSiGe S/D”.
He listed the options for FinFET as follows:
pFinFET
nFinFET
-relaxed Ge
-relaxed Ge
-strained Ge on SiGe SRB
-strain-Si
-strained SiGe on Si
-InGaAs/InP on Si
The process flow is listed in Fig.1 below whereby they first grow a heterogenous Ge-epilayer on Si wafer
followed by Well, ground plane and anti-punch through implant. Next was the Fin defined STI etch and low
temperature fill and oxide recess (see Fig.2 of the Ge-Fin after STI oxide recess). After dummy gate they do
tilted Phos implant for extension and B implant for HALO. Following nitride spacer they grow a 45% SiGe
S/D cap followed by HDD Phos implant then junction anneal at <600C.
Marketing, Sales &
Technology)
77
10000000
10000000
Implant Changing Ge-epi Strain (Tensile & Compressive)
1000000
1000000
JB1-40+76
100000
100000
JB1-40+38
JB1-40+20
JB1-40+00
JB1-40-55
JB1-40-74
10000
Series1
Series1
1000
JOB/LASSE/WaferMasters
100
10
1
60
60.5
Marketing, Sales &
Technology)
61
61.5
62
62.5
63
63
63.5
63.5
78
JOB/CNSE/Nissin/LASSE
Outline
Formation
79
• Summary
IMEC: Selective Epi Fin
IMEC: Si-Fin SiGe-Fin
Ge-Fin
InGaAs-Fin
80
Outline
Formation
81
• Summary
Trumble, Bell Labs, 1959
Stanford Sb-LMA
Excico P-LMA
As-LSA
As-MLD
IBM Sb-RTA
4/27/2015
Advanced Integrated Photonics, Inc. -
82
Boron Activation in Si & Ge
BF2 is self-amorphizing
1000
Si, 5e14/cm2 B
Sheet Resistance, (ohm/sq)
Ge, 5e14/cm2 BF2
Si, 5e14/cm2 BF2
Ge, 5e14/cm2 B
100
Boron Rs is dose limited
Si, 5e15/cm2 B
Room temperature
B-activation (acceptor formation ~1E14/cm2)
Ge-Melt
937C
Si-Melt
1407C
Ge, 5e15/cm2 B
10
0
200
400
600
800
1000
RTP Temperature, C
1200
1400
83
4/27/2015
Borland & Konkola, AIP, IIT-2014
1E+21
Room temperature
B-activation (acceptor formation
11B
~1E19/cm3)
B CONCENTRATION (atoms/cc)
1E+20
1E+19
1E+18
Zaima, Nagoya U., ECS Oct 2014, paper P7-1772
AIP Ge 5e15 B No Anneal
1E+17
1E+16
Carrier Concentration
1E+15
0
0.1
0.2
0.3
0.4
0.5
0.6
DEPTH (µm)
0.7
0.8
0.9
1
1.1
1.2
LD047_ym20 Sample GHC1 (B) all data
Marketing, Sales &
Technology)
85
IEDM-2014 Paper 32.5 by Lee of Univ of Tokyo on “Dramatic
Effects of Hydrogen-induced Out-diffusion of Oxygen from
Ge Surface on Junction Leakage as well as Electron Mobility
in n-channel Ge MOSFETs”
2
To examine the effects of oxygen they implanted O at 1.0 and 10.0E14/cm dose at 100keV
shown in Fig.6 to a depth of 75nm. Fig.7 shows the Ge n+/p junction leakage for Phos implant
50keV/1E15 after annealing 400C to 650C for 30 sec without O-implant and for the 1E13 and
1E14 O-implants. Without Oxygen the lowest n+/p junction leakage is at 600C at 8E-3A/cm2
while with the higher O-implant dose it was 40x lower at 2E-4A/cm2. No data on dopant
activation Rs values in relationship to the junction leakage.
Marketing, Sales &
Technology)
86
IEDM-2014 Paper 16.5 by Mitard of IMEC on “First
Demonstration of 15nm WFIN Inversion Mode Relaxed Ge nFinFETs with Si-cap Free RMG and NiSiGe S/D”.
Results for the Ge n+/p junction leakage is shown in Fig.9 below and Fig.10 shows both p+/n and n+/p
junction leakage in Ge. They also used Ge-PAI to boost the B dopant activation in Ge to ~1E20/cm3 with
500C anneal. Ge n+ junction optimization was required to reduce n+/p Ge junction leakage by 20x from
4A/cm2 to 0.2A/cm2.
Marketing, Sales &
Technology)
87
Summary: Smartphone the technology driver for 3-D
More Moore and More Than Moore in this Decade!
•
•
•
•
Samsung Galaxy S6 using 14nm 3-D FinFET Application Processor, 16M pixel
CMOS image sensor camera, up to 128Gb Flash memory (2-D planar or 3-D 32layers) and thin ePoP (embedded package on package) memory, a single 3-D
memory package consisting of 3GB LPDDR3 DRAM, 32GB eMMC and a controller.
Apple iPhone 6s (Sept 2015) A9 will use 3-D FinFET Application Processor 14nm
from Samsung and 16nm FF+ from TSMC, >8M pixel 3-D stacked backside CMOS
image sensor camera from Sony and 64-128Gb Flash memory.
10nm=2016, 7nm=2018 & 5nm=2020!
High tilt 35-45 degrees bi-mode or quad-mode implantation will continue to be used
for FinFET SDE & S/D doping for 14nm, 10nm and 7nm node.
• Amorphous implantation of the Fin is Good as it leads to highest dopant activation and
stressor formation.
• Dual recess epi for p+ & n+ S/D stressor at 14nmneed direct high mobility channel/Fin by
10nm!
•
Ge, SiGe or GeSn high mobility channel-FinFET at 10nm or 7nm node will require
Ge-epi first approach or amorphous-Ge+LPE.
• Low Ge n+ junction leakage will require <625C activation, no EOR damage, mesa etch
sidewalls or Si(SiGe)-capping layer up to 900C activation.
• Implant damage also creates acceptors so amorphization is preferred. Acceptor EOR
damage acts as heavy HALO doping up to 3E19/cm3!
88
• Laser melt annealing best for localized Ge, shallow n+ USJ and no EOR damage for low
leakage.

PDF of the presentation materials are available here

Transcription

Similar documents

Product datasheet

Samsung S3C2410

15” Technical Specifications Accessories

V th - St.Angel's Rohini

ML-1610

Look. Donʼt touch.

The Samsung Windows 8 tablet that was given away at... either the Samsung Series 7 Slate

Samsung Mono Laser Printer ML-1660 and ML-1665

UD-D SERIES COMMERCIAL LED LCD DISPLAYS

China`s Search for Sporting Success