1 EECS150 - Digital Design Lecture 8
Transcription
1 EECS150 - Digital Design Lecture 8
Outline • Canonical Forms (continued) – They give us a method to go from truth tables (TT) to Boolean Equations • • • • • EECS150 - Digital Design Lecture 8 - Boolean Algebra II Feburary 9, 2003 John Wawrzynek Spring 2005 EECS150 – Lec8-Bool2 Page 1 Algebraic simplification example K-map method of two-level logic simplication Multi-level Logic NAND/NOR networks EXOR revisited Spring 2005 EECS150 – Lec8-Bool2 Relationship Among Representations Canonical Forms * Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT. ? not unique Boolean Expression ? gate representation (schematic) [convenient for manipulation] • Sum of Products (disjunctive normal form, minterm expansion). Example: not unique [close to implementaton] How do we convert from one to the other? Spring 2005 EECS150 – Lec8-Bool2 • Standard form for a Boolean expression - unique algebraic expression directly from a true table (TT) description. • Two Types: * Sum of Products (SOP) * Product of Sums (POS) unique Truth Table Page 2 Page 3 minterms a’b’c’ a’b’c a’bc’ a’bc ab’c’ ab’c abc’ abc Spring 2005 abc 000 001 010 011 100 101 110 111 f f’ 01 01 01 10 10 10 10 10 One product (and) term for each 1 in f: f = a’bc + ab’c’ + ab’c +abc’ +abc f’ = a’b’c’ + a’b’c + a’bc’ EECS150 – Lec8-Bool2 Page 4 1 Sum of Products (cont.) Canonical Forms Canonical Forms are usually not minimal: Our Example: f = a’bc + ab’c’ + ab’c + abc’ +abc (xy’ + xy = x) = a’bc + ab’ + ab = a’bc + a (x’y + x = y + x) = a + bc • Product of Sums (conjunctive normal form, maxterm expansion). Example: maxterms a+b+c a+b+c’ a+b’+c a+b’+c’ a’+b+c a’+b+c’ a’+b’+c a’+b’+c’ f’ = a’b’c’ + a’b’c + a’bc’ = a’b’ + a’bc’ = a’ ( b’ + bc’ ) = a’ ( b’ + c’ ) = a’b’ + a’c’ abc 000 001 010 011 100 101 110 111 f f’ 01 01 01 10 10 10 10 10 One sum (or) term for each 0 in f: f = (a+b+c)(a+b+c’)(a+b’+c) f’ = (a+b’+c’)(a’+b+c)(a’+b+c’) (a’+b’+c)(a+b+c’) Mapping from SOP to POS (or POS to SOP): Derive truth table then proceed. Spring 2005 EECS150 – Lec8-Bool2 Page 5 Spring 2005 Algebraic Simplification Example EECS150 – Lec8-Bool2 Page 6 Algebraic Simplification Ex: full adder (FA) carry out function (in canonical form): Cout = a’bc + ab’c + abc’ + abc Spring 2005 EECS150 – Lec8-Bool2 Page 7 Ex: full adder (FA) carry out function Cout = a’bc + ab’c + abc’ + abc = a’bc + ab’c + abc’ + abc + abc = a’bc + abc + ab’c + abc’ + abc = (a’ + a)bc + ab’c + abc’ + abc = (1)bc + ab’c + abc’ + abc = bc + ab’c + abc’ + abc + abc = bc + ab’c + abc + abc’ + abc = bc + a(b’ +b)c + abc’ +abc = bc + a(1)c + abc’ + abc = bc + ac + ab(c’ + c) = bc + ac + ab(1) = bc + ac + ab Spring 2005 EECS150 – Lec8-Bool2 Page 8 2 General Two-level Logic Simplication Boolean Cubes Visual technique for identifying when the Uniting Theorem can be applied Key tool: The Uniting Theorem 1-cube xy’ + xy = x (y’ + y) = x (1) = x ab 00 01 10 11 f 0 0 1 1 ab 00 01 10 11 g 1 0 1 0 0 3-cube 11 011 111 010 xy 110 y 001 000 x 10 100 101 z • Sub-cubes of on-nodes can be used for simplification. – On-set: filled in nodes, off-set: empty nodes ab 00 01 10 11 g = a’b’+ab’ = (a’+a)b’ =b’ b values stay the same a values changes f 0 0 1 1 g 1 0 1 0 01 11 b f 00 a a asserted & unchanged b varies ab + ab'= a 10 b’ remains, a eliminated Page 9 Spring 2005 EECS150 – Lec8-Bool2 3-variable cube example • K-map is an alternative method of representing the TT and to help visual the adjacencies. ab(c' +c) 011 111 Note: “gray code” labeling. 010 b 000 a 100 a a(b+b' )c 110 001 b 101 c cout = bc + ab + ac What about larger sub-cubes? 011 111 010 110 b 001 000 a 100 101 c Page 10 Karnaugh Map Method (a'+ a)bc FA carry out: Spring 2005 2-cube 00 b values change within the on-set rows a values don’t change b is eliminated, a remains EECS150 – Lec8-Bool2 cout 0 0 0 1 0 1 1 1 1 x f = ab’ + ab = a(b’+b) = a Spring 2005 abc 000 001 010 011 100 101 110 111 01 c ab’c’ + ab’c + abc’ + abc ac’ + ac + ab = a + ab = a 0 1 0 1 ab 00 01 11 10 0 1 ab cd 00 01 11 10 00 01 11 10 5 & 6 variable k-maps possible • Both b & c change, a is asserted & remains constant. EECS150 – Lec8-Bool2 Page 11 Spring 2005 EECS150 – Lec8-Bool2 Page 12 3 Karnaugh Map Method K-map Simplification 1. Draw K-map of the appropriate number of variables (between 2 and 6) 2. Fill in map with function values from truth table. 3. Form groups of 1’s. • Adjacent groups of 1’s represent product terms a b a 0 1 0 0 1 1 0 1 b f=a 0 1 0 1 1 1 0 0 Dimensions of groups must be even powers of two (1x1, 1x2, 1x4, …, 2x2, 2x4, …) Form as large as possible groups and as few groups as possible. Groups can overlap (this helps make larger groups) Remember K-map is periodical in all dimensions (groups can cross over edges of map and continue on other side) g = b' ab c 00 01 11 10 0 0 0 1 0 1 0 1 1 1 c ab 00 01 11 10 0 0 0 1 1 1 0 0 1 1 cout = ab + bc + ac 4. For each group write a product term. the term includes the “constant” variables (use the uncomplemented variable for a constant 1 and complemented variable for constant 0) f=a 5. Form Boolean expression as sum-of-products. Spring 2005 EECS150 – Lec8-Bool2 Page 13 Spring 2005 K-maps (cont.) c EECS150 – Lec8-Bool2 Page 14 Product-of-Sums Version ab 00 01 11 10 0 1 0 0 1 1 0 0 1 1 1. Form groups of 0’s instead of 1’s. 2. For each group write a sum term. the term includes the “constant” variables (use the uncomplemented variable for a constant 0 and complemented variable for constant 1) f = b' c'+ ac 3. Form Boolean expression as product-of-sums. ab cd 00 01 11 10 ab 00 1 0 1 1 01 0 1 1 1 11 0 0 1 1 10 1 0 1 1 cd 00 01 11 10 f = c + a' bd + b' d' (bigger groups are better) 00 1 0 1 1 01 0 1 1 1 11 0 0 1 1 10 1 0 1 1 f = (b'+ c + d)(a'+ c + d' )(b + c + d' ) Spring 2005 EECS150 – Lec8-Bool2 Page 15 Spring 2005 EECS150 – Lec8-Bool2 Page 16 4 BCD incrementer example abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 wxyz 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 - - - - - - - - - - - - - - - - - - - cd ab 00 01 11 10 cd ab 00 01 11 10 w cd 00 00 01 01 11 11 10 11 0 0 0 0 0 0 1 0 - 1 0 - 00 01 11 10 y cd 00 00 01 01 11 11 10 11 0 1 0 1 0 1 0 1 - 0 0 - ab 00 01 11 10 w= BCD Incrementer Example x • Note one map for each output variable. • Function includes “don’t cares” (shown as “-” in the table). 00 00 01 01 11 11 10 11 0 0 1 0 1 1 0 1 - 0 0 - – These correspond to places in the function where we don’t care about its value, because we don’t expect some particular input patterns. – We are free to assign either 0 or 1 to each don’t care in the function, as a means to increase group sizes. z 00 00 01 01 11 11 10 11 1 0 0 1 1 0 0 1 - • In general, you might choose to write product-of-sums or sum-of-products according to which one leads to a simpler expression. 1 0 - x= y= Spring 2005 ab z= EECS150 – Lec8-Bool2 Page 17 Spring 2005 EECS150 – Lec8-Bool2 BCD incrementer example cd ab 00 01 11 10 cd ab 00 01 11 10 Spring 2005 w 00 01 01 11 11 11 10 00 0 0 0 0 0 0 1 0 - cd 1 0 - 00 01 11 10 y 00 00 01 01 11 11 10 11 0 1 0 1 0 1 0 1 - 0 0 - ab cd ab 00 01 11 10 Higher Dimensional K-maps x 00 01 11 11 11 10 00 01 0 0 1 0 1 1 0 1 - 0 0 - z a=1 w= x= a=0 y= de 00 bc 00 01 11 10 ab = 10 10 11 10 00 10 11 10 00 01 11 10 ab = 11 ab = 01 00 00 01 01 11 11 10 11 1 0 0 1 1 0 0 1 - EECS150 – Lec8-Bool2 1 0 - Page 18 z= ab = 00 Page 19 Spring 2005 EECS150 – Lec8-Bool2 ef 00 cd 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 10 11 10 00 10 11 10 00 10 11 10 00 10 11 10 Page 20 5 Multi-level Combinational Logic Example: reduced sum-of-products form x = adf + aef + bdf + bef + cdf + cef + g Implementation in 2-levels with gates: Multi-level Combinational Logic Another Example: F = abc + abd +a’c’d’ + b’c’d’ a let x = ab y = c+d b c f = xy + x’y’ a d f cost: 1 7-input OR, 6 3-input AND => 50 transistors delay: 3-input OR gate delay + 7-input AND gate delay Factored form: x = (a + b +c)(d + e)f + g cost: 1 3-input OR, 2 2-input OR, 1 3-input AND => 20 transistors delay: 3-input OR + 3-input AND + 2-input OR a b c d e f g x Which is faster? In general: Using multiple levels (more than 2) will reduce the cost. Sometimes also delay. Sometime a tradeoff between cost and delay. EECS150 – Lec8-Bool2 Page 21 NAND-NAND & NOR-NOR Networks DeMorgan’s Law: (a + b)’ = a’ b’ a + b = (a’ b’)’ a b x f c d y No convenient hand methods exist for multi-level logic simplification: Footnote: NAND would be used in place of all ANDs and ORs. Spring 2005 a b d a c d b c d = = = Are these optimizations still relevant for LUT implementations? Spring 2005 EECS150 – Lec8-Bool2 Page 22 NAND-NAND & NOR-NOR Networks • Mapping from AND/OR to NAND/NAND (a b)’ = a’ + b’ (a b) = (a’ + b’)’ = a) CAD Tools b) exploit some special structure, example adder a) b) c) d) a b c d push bubbles or introduce in pairs or remove pairs. Spring 2005 EECS150 – Lec8-Bool2 Page 23 Spring 2005 EECS150 – Lec8-Bool2 Page 24 6 NAND-NAND & NOR-NOR Networks • Mapping AND/OR to NOR/NOR a) a b c d Multi-level Networks Mapping OR/AND to NOR/NOR a) b) a b c d Convert to NANDs: F = a(b + cd) + bc’ b) c) c) a b c d • • pair c d b a f b c' OR/AND to NAND/NAND (by symmetry with above) Spring 2005 (note fanout) a' b' c' d' a b c d EECS150 – Lec8-Bool2 Page 25 Spring 2005 EECS150 – Lec8-Bool2 Page 26 EXOR Function Parity, addition mod 2 x' x ⊕ y = x’y + xy’ x y xor xnor 00 0 1 x 01 10 1 1 0 0 y 11 0 1 y x y' Another approach: x y Spring 2005 0 1 if x=0 then y else y' EECS150 – Lec8-Bool2 Page 27 7