UART: Clocking
Transcription
UART: Clocking
UART: Clocking Why Can't We Use One Clock? ● ● ● We have two different clock domains in our design One of these clocks is much slower than the other To solve this problem, we're going to use clock dividers Fixed Clock Divider ● ● Used when we want a clock division by a power of 2 Implemented by chaining flip-flops together, each dividing the last input clock by 2 Arbitrary Clock Divider ● ● ● Used when we want a clock division by a variable amount Implemented by counting clock cycles In our design, the “baud rate” from the bus interface is the number of times to count before inverting the clock output UART Clocking Problem ● Remember, only the baud rate is known between the UARTs ● Phase must be matched between two UARTs ● If the UARTs are out of phase, we'll get unexpected errors Edge Detector Clock Signal 2 Bit Shift Register Not delay <= signal after 3ns; edge <= signal and not delay; AND ● ● Many implementations, these might both be okay What are the drawbacks and advantages of both? Phase Matcher 4x Clk Baud Clock 0 Deg 90 Deg 180 Deg ● Detects the clock edge ● Corrects the clocked output to match the phase 270 Deg Phase Matching Circuit Hints ● ● ● We need to sample the actual Baud clock to determine phase ● Use a shift register to sample the baud clock We need to sample the Baud clock at a faster rate (16x) We need to pick one of the outputs from the shift register as the phase matched clock ● Keep track of which bit in the shift register contains the rising or falling edge of the Baud Clock ● When the RX line drops, (edge detection!) continue to watch a single bit from the shift register Baud Clock Generator ● Questions for Consideration: ● ● ● ● How should you attach the parts to get the Baud Clock? What is the difference between the TX_clk and RX_clk? What is the relation between the Baud_Sel_Code and the actual Baud Clock rate? What is the minimum clock division?