Ultra Low-Power VLSI with Fine Grain Runtime Power Gating

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Ultra Low-Power VLSI with Fine Grain Runtime Power Gating
Ultra Low-Power VLSI
with Fine Grain
Runtime Power Gating
Hiroshi Nakamura
[email protected]
[email protected]
tokyo.ac.jp
([email protected], [email protected])
Th U
The
University
i
it off T
Tokyo
k
IFIP-57th 2010/1/25 (H.Nakamura)
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Outline
„
„
tradeoff between
performance, power and dependability
Outline
… Background
… Introduction
of our Research Project
„
purpose: leakage reduction
„
implementation: fine-grain power-gating processor
IFIP-57th 2010/1/25 (H.Nakamura)
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CO2 Emission from IT Equipments in Japan
Report from METI
((Ministryy of Economy,
y Trade, and Industry)
y)
Power of
IT equipments
-50%
Current trend
5 times
-40%
CO2
(8M cars)
Target
g set by
y
Green IT
5% of
Total Power
2006
2025
2050
IFIP-57th 2010/1/25 (H.Nakamura)
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Relationships of Performance and Power
„
For a transistor,
„
For any complete system
Power
CVDD
t delay v
Switching Delay
(VDD Vth )D
Dynamic Power Pdyn = C VDD2 f ȕ
Leakage
not simple because
„
„
Performance is limited by a bottleneck
Power is summation of the whole system
1/delay
(performance)
Low power and slow operation for unhurried / idle parts
ĺ Low power consumption without performance penalty
„
DVFS (Voltage/Frequency Scaling) for dynamic power
„
What is effective for leakage power ? Æ Power Gating
IFIP-57th 2010/1/25 (H.Nakamura)
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Power-Gating
„
Power-gating (PG) technique
…
…
Inserting sleep transistors between GND and logic blocks
(or between Vdd and logic blocks)
„
Cut power-supply to logic blocks
„
Active/sleep mode controlled by sleep signals
Sleep transistors : High-Vth transistors (slow but non-leaky)
Vdd
×
×
Circuit
Block
sleep
signal
leakage current
VGND
sleep Tr.
GND
IFIP-57th 2010/1/25 (H.Nakamura)
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Introduction of Our Research Project
„
„
Innovative Power Control for Ultra Low-Power and
Hi h P f
High-Performance
S t
System
LSI
LSIs
…
5 years project started from October, 2006
…
Supported by JST (Japan Science and Technology Agency)
CREST (Core Research for Evolutional Science and
Technology)
JST CREST Research Area : (approximately 30)
…
Dependable
p
Operating
p
g Systems
y
for Embedded Systems
y
Aiming
g
at Practical Applications directed by Dr. Mario Tokoro
…
Fundamental Technologies for Dependable VLSI System
…
Technology Innovation and Integration for Information Systems
with Ultra Low Power directed by Prof. Takashi Nanya
„
12 projects: my project is here
IFIP-57th 2010/1/25 (H.Nakamura)
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Geyser: Low Power Processor through
Fine-Grain Run-Time Power-Gating
g
„
Target: Leakage Power
„
Background: Leakage reduction techniques so far,
…
Standby time:
„
…
Runtime:
„
„
power-gating(Coarse Grain)
C h d
Cache-decay,
D
Drowsy-cache,
h (C
(Coarse G
Grain
i iin ttemporal)
l)
Leakage for logic parts (ALU, multiplier, etc.) gets serious
…
F t but
Fast
b t Leaky
L k ttransistors
i t
are used
d
…
Active ratio of those parts are not necessarily high, but active parts
change frequently,
frequently that is,
is cycle by cycle
Objective : Reduce runtime leakage power of logic parts
Challenge: how to realize fine-grain
fine grain power gating
IFIP-57th 2010/1/25 (H.Nakamura)
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Example of Coarse-Grain Power Gating
„
Intel Nehalem
(R.Kumar, paper 3.2. ISSCC09)
Thick On-die (M9)
Interconnect Layer
Thickk metall 9 layer
Thi
l
for
f llow
resistance on-die power routing
IFIP-57th 2010/1/25 (H.Nakamura)
Ultra-low leakage transistor
for high off-resistance
power gates
8
Instruction Pipeline with Power-Gating
„
Geyser: MIPS compatible processor with 5-stage pipeline,
„
Straightforward PG (power-gating)
…
Turn EX-units into active mode only if necessary
…
Ex unit gets active when an affecting instruction enters the IF stage
Ex-unit
…
The activated EX-unit returns to sleep mode after execution
IF
Inst
ID
MEM
EX
ALU
Mult
Shift
Div
SHIFT
Instruction
i
Detects which unit
will be used
S d wake-up
Sends
k
signal
i
l
IFIP-57th 2010/1/25 (H.Nakamura)
WB
Operation
MIPS R3000 pipeline
9
Energy Overhead of Run-Time Power-Gating
Power
Break-even Time
1 + 3 : Energy overhead
1
Normal
Leakage
2 : part of leakage saving
3
2
1 + 3 = 2
4
(
)
Break Even Time(BET)
Time
Sleep
„
4 : Net Energy saving
WakeUp
Sleep period should be longer than BET
…
Otherwise, total energy consumption increases
…
BET tells
t ll the
th smallest
ll t granularity
l it for
f Power
P
Gating
G ti
IFIP-57th 2010/1/25 (H.Nakamura)
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11
Break Even Time of Each Unit
90 nm technology
114
25
65
100
125
Cyclles @2000MHz
92
74
74
44
38
26
12 8
ALU
„
Shift
10
10 8
Mult
14
6 2
Div
12 8
CP0
BET is shortened when the chip temperature climbs up
…
„
16
28
22
Leakage current depends on temperature heavily
We need some novel PG strategies that take BET into account
IFIP-57th 2010/1/25 (H.Nakamura)
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Power Gating Strategy
„
Requirement: Power off Ex-units longer than BET
„
PG Strategies
…
Straightforward EX-units are usually in sleep mode. Turned into
active mode only
y when being
g used
…
Cache-miss: Ex-units are usually in active mode.
Turned into sleep mode only in cache miss situation
Qualitative Comparison:
„
…
Chance of Power-off: Straightforward > Cache-miss
…
Average duration of Power-off:
Straightforward < Cache-miss, for frequently used Ex-units
St t
Strategy
for
f each
h Ex-unit
E
it iis controlled
t ll d b
by OS
„
…
Status registers in Control Processor (CP0), modifid by OS
…
St t
Strategy
is
i under
d control
t l and
d changed
h
d during
d i execution
ti
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Geyser-1:
„
2.1 mm
Geyser-1: Prototype Chip
…
65nm CMOS (Fujitsu e-shuttle)
„ through VDEC
(VLSI Design and Education)
…
without cache
…
successfully in operation (50MHz)
IFIP-57th 2010/1/25 (H.Nakamura)
4 2 mm
4.2
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Preliminary Evaluation & Summary
Ikebuchi et. al. ASSCC ‘‘09
1.4
1.2
1
0.8
0.6
0.4
0.2
0
without PG
with PG
20
„
„
40
50
temperature
[ ] (
60
)
70
Microprocessor with cycle by cycle power gating:
successfully in operation
…
„
30
100%
80%
60%
40%
20%
0%
80
Po
ower Reduction
Ratiio
current ((mA)
c
[[mA]
Real Measurement of Geyser-1 (djkstra)
the first implementation in the world
Power reduction ratio increases for higher temperature
as expected
performance and power : easy to demonstrate
IFIP-57th 2010/1/25 (H.Nakamura)
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