docMT4LSDT864AG-13EF1 64MB PAMIĘĆ SDRAM
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MT4LSDT864AG-13EF1 64MB PAMIĘĆ SDRAM
DATASHEET MICRON MT4LSDT864AG-13EF1 OTHER SYMBOLS: RGB ELEKTRONIKA AGACIAK CIACIEK SPÓŁKA JAWNA Jana Dlugosza 2-6 Street 51-162 Wrocław Poland www.rgbelektronika.pl [email protected] +48 71 325 15 05 www.rgbautomatyka.pl www.rgbautomatyka.pl www.rgbelektronika.pl YOUR PARTNER IN MAINTENANCE Repair this product with RGB ELEKTRONIKA LINEAR ENCODERS ORDER A DIAGNOSIS ∠ PLC SYSTEMS INDUSTRIAL COMPUTERS ENCODERS CNC CONTROLS SERVO AMPLIFIERS MOTORS CNC MACHINES OUR SERVICES SERVO DRIVERS POWER SUPPLIERS OPERATOR PANELS At our premises in Wrocław, we have a fully equipped servicing facility. Here we perform all the repair works and test each later sold unit. Our trained employees, equipped with a wide variety of tools and having several testing stands at their disposal, are a guarantee of the highest quality service. Buy this product at RGB AUTOMATYKA BUY ∠ 4, 8, 16 MEG x 64 SDRAM DIMMs SYNCHRONOUS DRAM MODULE MT4LSDT464A, MT4LSDT864A MT4LSDT1664A For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • PC66-*, PC100- and PC133-compliant • JEDEC-standard, 168-pin, dual in-line memory module (DIMM) • Utilizes 100 MHz*, 125 MHz and 133 MHz SDRAM components • Unbuffered • 32MB (4 Meg x 64), 64MB (8 Meg x 64), 128MB (16 Meg x 64) • Single +3.3V ±0.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths: 1, 2, 4, 8 or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Serial Presence-Detect (SPD) OPTIONS PIN SYMBOL PIN 1 VSS 43 2 DQ0 44 3 DQ1 45 4 DQ2 46 5 DQ3 47 6 VDD 48 7 DQ4 49 8 DQ5 50 9 DQ6 51 10 DQ7 52 11 DQ8 53 12 VSS 54 13 DQ9 55 14 DQ10 56 15 DQ11 57 16 DQ12 58 17 DQ13 59 18 VDD 60 19 DQ14 61 20 DQ15 62 21 NC 63 22 NC 64 23 VSS 65 24 NC 66 25 NC 67 26 VDD 68 27 WE# 69 28 DQMB0 70 29 DQMB1 71 30 S0# 72 31 DNU 73 32 VSS 74 33 A0 75 34 A2 76 35 A4 77 36 A6 78 37 A8 79 38 A10 80 39 BA1 81 40 VDD 82 41 VDD 83 42 CK0 84 **-133/-10E version only MARKING • Package 168-pin DIMM (gold) G • Frequency/CAS Latency 133 MHz/CL = 2 (7.5ns, 133 MHz SDRAM) 133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs) 100 MHz/CL = 2 (8ns, 125 MHz SDRAMs) 66 MHz/CL = 2 (10ns, 100 MHz SDRAMs) -13E -133 -10E -662* *32MB only KEY SDRAM COMPONENT TIMING PARAMETERS MODULE MARKING SPEED GRADE -13E -133 -10E -662 -7E -75 -8E -10 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a CAS ACCESS LATENCY TIME 2 3 2 2 5.4ns 5.4ns 6ns 9ns SETUP TIMES HOLD TIMES 1.5ns 1.5ns 2ns 3ns 0.8ns 0.8ns 1ns 1ns NOTE: 1 SYMBOL VSS DNU S2# DQMB2 DQMB3 DNU VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC (CKE1) VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC NC/WP** SDA SCL VDD PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 SYMBOL VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 NC NC VSS NC NC VDD CAS# DQMB4 DQMB5 NC (S1#) RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 NC (A12) PIN 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 SYMBOL VSS CKE0 NC (S3#) DQMB6 DQMB7 NC (A13) VDD NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs PART NUMBERS PART NUMBER MT4LSDT464AG-13E_ MT4LSDT464AG-133_ MT4LSDT464AG-10E_ MT4LSDT464AG-662_ MT4LSDT864AG-13E_ MT4LSDT864AG-133_ MT4LSDT864AG-10E_ MT4LSDT1664AG-13E_ MT4LSDT1664AG-133_ MT4LSDT1664AG-10E CONFIGURATION SYSTEM BUS SPEED 4 Meg x 64 4 Meg x 64 4 Meg x 64 4 Meg x 64 8 Meg x 64 8 Meg x 64 8 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 133MHz 133 MHz 100 MHz 66 MHz 133 MHz 133 MHz 100 MHz 133 MHz 100 MHz 133 MHz The modules provide for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An atuo precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. These modules are designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to syn-chronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 64Mb, 128Mb, or 256Mb SDRAM data sheets. NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT4LSDT464AG-10EB2. GENERAL DESCRIPTION The MT4LSDT464A, MT4LSDT864A and MT4LSDT1664A are high-speed CMOS, dynamic random-access, 32MB, 64MB and 128MB memories organized in a x64 configuration. These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signals CK0,CK2). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a SERIAL PRESENCE-DETECT OPERATION These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organization and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT4LSDT464A (32MB)/MT4LSDT864A (64MB)/MT4LSDT1664A (128MB) S0# DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DQMB5 DQML CS# DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 S2# DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB2 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 RAS#: SDRAMs U1 U2,U4 U5 CAS# CAS#: SDRAMs U1,U2,U4,U5 CKE0 CKE: SDRAMs U1 U2 U4,U5 WE# WE#: SDRAMs U1,U2,U4 U5 A0-A11: SDRAMs U1,U2,U4,U5 VDD SDRAMs U1,U2,U4,U5 VSS SDRAMs U1,U2,U4,U5 A0 U6 A1 DQML CS# DQ0 DQ1 U5 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CK0 U0 U1 U2 CK0 U3 U1 13.4pF CK2 U2 U3 CK1,CK3 10pF A2 U0 13.6pF CK1,CK2,CK3 SPD SCL WP 47K DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQMB3 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 BA0-1: SDRAMs U1,U2,U4,U5 BA0-1 DQML CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB7 DQML CS# DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMH DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS# A0-A11 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB1 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 10pF SDA 66 MHz VERSION 100 MHz/133 MHz VERSIONS SA0 SA1 SA2 U1,U2,U4,U5 = MT48LC4M16A2TG SDRAMs for 32MB U1,U2,U4,U5 = MT48LC8M16A2TG SDRAMs for 64MB U1,U2,U4,U5 = MT48LC16M16A2TG SDRAMs for 128MB NOTE: All resistor values are 10 ohms. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 115, 111, 27 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE# (along with S0#, S2#) define the command being entered. 42, 125, 79, 163 CK0-CK3 Input Clock: CK0-CK3 are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 128 CKE0 Input Clock Enable: CKE0 activates (HIGH) and deactivates (LOW) the CK0-CK3 signals. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWERDOWN (row ACTIVE in any bank), or CLOCK SUSPEND operation (burst access in progress). CKE0 is synchronous except after the device enters power-down and self refresh modes, where CKE0 becomes asynchronous until after exiting the same mode. The input buffers, including CK0-CK3, are disabled during power-down and self refresh modes, providing low standby power. 30, 45 S0#, S2# Input Chip Select: S0# and S2# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S0# and S2# are registered HIGH. S0# and S2# are considered part of the command code. 28-29, 46-47, 112-113, 130-131 DQMB0-DQMB7 Input Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH during a READ cycle. 122, 39 BA0, BA1 Input Bank Address: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 33, 117, 34, 118, 35, 119, 36, 120, 37, 121, 38, 123, 126 A0-A12 Input Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-A12) and READ/WRITE command (column-address A0-A7/A8 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 81 WP Input Write Protect: Serial presence-detect hardware write protect. Applies to -13E/-133/-10E versions only. 83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE 165-167 SA0-SA2 Input 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 DQ0-DQ63 Input/ Output Data I/Os: Data bus. 82 SDA Input/ Output Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 VDD Supply Power Supply: +3.3V ±0.3V. 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 VSS Supply Ground. 31, 44, 48 DNU – 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a DESCRIPTION Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Do Not Use: These pins are not connected on this module but are assigned pins on the compatible DRAM version. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SCL SCL SDA DATA STABLE DATA CHANGE DATA STABLE SDA Figure 1 Data Validity START BIT STOP BIT Figure 2 Definition of Start and Stop SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge Figure 3 Acknowledge Response From Receiver 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION NUMBER OF BYTES USED BY MICRON TOTAL NUMBER OF SPD MEMORY BYTES MEMORY TYPE NUMBER OF ROW ADDRESSES NUMBER OF COLUMN ADDRESSES NUMBER OF BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, tCK (CAS LATENCY = 3) ENTRY (VERSION) 128 256 SDRAM 12 or 13 8 or 9 1 64 0 LVTTL 7 (-13E) 7.5 (-133) 8 (-10E) 10 (-662) MT4LSDT464A 80 08 04 0C 08 01 40 00 01 70 75 80 A0 MT4LSDT864A 80 08 04 0C 09 01 40 00 01 70 75 80 A0 MT4LSDT1664A 80 08 04 0D 09 01 40 00 01 70 75 80 A0 5.4 (-13E/-133) 6 (-10E) 7.5 (-662) 54 60 75 54 60 75 54 60 75 10 SDRAM ACCESS FROM CLOCK, tAC (CAS LATENCY = 3) 11 12 13 14 15 MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MINIMUM CLOCK DELAY, tCCD UNPARITY 15.6µs/SELF 16 NONE 1 00 80 10 00 01 00 80 10 00 01 00 80 10 00 01 16 17 18 19 20 21 22 23 BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, tCK (CAS LATENCY = 2) 1, 2, 4, 8, PAGE 4 2, 3 0 0 UNBUFFERED 0E 7.5 (-13E) 10 (-133/-10E) 15 (-662) 8F 04 06 01 01 00 0E 75 A0 F0 8F 04 06 01 01 00 0E 75 A0 F0 8F 04 06 01 01 00 0E 75 A0 F0 24 SDRAM ACCESS FROM CK, tAC (CAS LATENCY = 2) 5.4 (-13E) 6 (-133/-10E) 9 (-662) 54 60 90 54 60 90 54 60 90 25 SDRAM CYCLE TIME, tCK (CAS LATENCY = 1) – 00 00 00 26 SDRAM ACCESS FROM CK, tAC (CAS LATENCY = 1) – 00 00 00 27 MINIMUM ROW PRECHARGE TIME, tRP 15 (-13E) 20 (-133/-10E) 30 (-662) 0F 14 1E 0F 14 1E 0F 14 1E MINIMUM ROW ACTIVE TO ROW ACTIVE, 14 (-13E) 15 (-133) 20 (-10E/-662) 0E 0F 14 0E 0F 14 0E 0F 14 15 (-13E) 20 (-133/-10E) 30 (-662) 0F 14 1E 0F 14 1E 0F 14 1E 28 tRRD 29 MINIMUM RAS# TO CAS# DELAY, tRCD NOTE: “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.” 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) BYTE DESCRIPTION 30 MINIMUM RAS# PULSE WIDTH, tRAS 31 32 ENTRY (VERSION) 37 (-13E) 44 (-133) 50 (-10E) 60 (-662) MODULE BANK DENSITY 32MB, 64MB or 128MB COMMAND AND ADDRESS SETUP TIME 1.5 (-13E/-133) 2 (-10E/-662_2) 0 (-662_1) MT4LSDT464A 2D 2C 32 3C 08 15 20 00 MT4LSDT864A 2D 2C 32 3C 10 15 20 00 MT4LSDT1664A 2D 2C 32 3C 20 15 20 00 33 COMMAND AND ADDRESS HOLD TIME 0.8 (-13E/-133) 1 (-10E/-662_2) 0 (-662_1) 08 10 00 08 10 00 08 10 00 34 DATA SIGNAL INPUT SETUP TIME 1.5 (-13E/-133) 2 (-10E/-662_2) 0 (-662_1) 15 20 00 15 20 00 15 20 00 35 DATA SIGNAL INPUT HOLD TIME 0.8 (-13E/-133) 1 (-10E/-662_2) 0 (-662_1) 08 10 00 08 10 00 08 10 00 1.2 (-13E/-133/-10E/-662_2) 1.0 (-662_1) -13E -133 -10E -662_2 -662_1 00 12 01 56 9C E4 B7 46 00 12 01 5F A5 ED C0 4F 00 12 01 70 B6 FE D1 60 2C FF 2C FF 2C FF 01 02 03 04 05 06 07 08 09 01 02 03 04 05 06 07 08 09 01 02 03 04 05 06 07 08 09 36-61 RESERVED 62 SPD REVISION 63 CHECKSUM FOR BYTES 0-62 64 MANUFACTURER’S JEDEC ID CODE 65-71 MANUFACTURER’S JEDEC ID CODE (continued) 72 MANUFACTURING LOCATION 73-90 MODULE PART NUMBER (ASCII) 91 PCB IDENTIFICATION CODE 92 IDENTIFICATION CODE (continued) 93 YEAR OF MANUFACTURE IN BCD 94 WEEK OF MANUFACTURE IN BCD 95-98 MODULE SERIAL NUMBER MICRON x x x 1 2 3 4 5 6 7 8 9 01 02 03 04 05 06 07 08 09 01 02 03 04 05 06 07 08 09 01 02 03 04 05 06 07 08 09 0 00 00 00 x x x x x x x x x NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.” 2. x = Variable Data. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) BYTE DESCRIPTION ENTRY (VERSION) MT4LSDT464A 99-125 MANUFACTURER-SPECIFIC DATA (RSVD) – 126 SYSTEM FREQUENCY 100 MHz (-13E/-133/-10E) 64 66 MHz (-662) 66 127 SDRAM COMPONENT AND CLOCK DETAIL -13E/-133/-10E -662_2 -662_1 AF 8F 06 MT4LSDT864A – 64 66 MT4LSDT1664A – 64 66 AF 8F 06 AF 8F 06 NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.” 2. x = Variable Data. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs COMMANDS Truth Table 1 provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 64Mb,128Mb or 256Mb x4, x8, x16 SDRAM data sheet. TRUTH TABLE 1 – COMMANDS AND DQMB OPERATION (Note: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQMB COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output enable Write Inhibit/Output High-Z NOTE: 1. 2. 3. 4. 5. 6. 7. 8. H L L L L L L L X H L H H H L L X H H L L H H L X H H H L L L H L – – L – – L – – L – – ADDR DQs NOTES X X X X X X X Bank/Row X L/H8 Bank/Col X L/H8 Bank/Col Valid X X Active X Code X X X X X L H Op-Code X – Active – High-Z 3 4 4 5 6, 7 2 8 8 CKE is HIGH for all commands shown except SELF REFRESH. A0-A12 define the op-code written to the Mode Register. A0-A12 provide row address, and BA0, BA1 determine which bank is made active. A0-A7/A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine which bank is being precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.” This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs Table 1 Burst Definition A12 A11 A10 A9 A8 A6 A7 A5 A4 A3 A1 A2 Address Bus A0 Burst Length 12 Unused 11 9 10 8 6 7 Reserved* WB Op Mode 5 4 CAS Latency 3 1 2 BT 0 Mode Register (Mx) Burst Length 2 *Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved 4 8 Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 2 0 1 0 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access Full Page (y) n = A0-A8/A7 (location 0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... …Cn - 1, Cn… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported NOTE: 1. For full-page accesses: y = 512 (64MB/128MB); y = 256 (32MB) 2. For a burst length of two, A1-A7/A8 select the block-of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7/A8 select the block-of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7/A8 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected, and A0-A7/A8 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7/A8 select the unique column to be accessed, and Mode Register bit M3 is ignored. All other states reserved Figure 4 Mode Register Definition 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS .. -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ................................. -1V to +4.6V Operating Temperature, TA (ambient) .. 0°C to +70°C Storage Temperature (plastic) ........... -55°C to +125°C Power Dissipation ................................................... 4W DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VDD 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2 VDD + 0.3 V 3 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.5 0.8 V 3 INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) DQMB0-DQMB7 CK0, CK2, S0#, S2# CKE0, RAS#, CAS#, A0-A2, BA0-BA1, WE# II1 II2 II3 -5 -10 -20 5 10 20 µA µA µA 4 OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDD DQ0-DQ63 IOZ -5 5 µA VOH 2.4 – V VOL – 0.4 V OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) UNITS NOTES NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 4. CK0 = 20µA for 66 MHz versions. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS (Notes: 1-4) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION MAX SYMBOL SIZE OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN); CAS latency = 3 IDD1 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle IDD2 STANDBY CURRENT: Active Mode; S0#, S2# = HIGH; CKE = HIGH; All banks active after tRCD met; No accesses in progress IDD3 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 tRC = tRC (MIN); AUTO REFRESH CURRENT: CKE = HIGH; S0#, S2# = HIGH CL = 3 tRC = 15.625µs; CL = 3 SELF REFRESH CURRENT: CKE ≤ 0.2V -13E -133 -10E -662 UNITS NOTES 500 640 TBD 460 600 TBD 380 560 TBD 360 n/a n/a mA 5, 6, 7, 8 32MB 8 64MB 8 128MB 8 32MB 180 64MB 200 128MB 220 8 8 8 180 200 200 8 8 8 140 160 160 12 n/a n/a 120 n/a n/a mA 8 mA 5, 7, 8, 9 IDD4 32MB 600 64MB 660 128MB TBD 560 600 TBD 480 560 TBD 420 n/a n/a mA 5, 6, 7, 8 IDD5 32MB 920 840 760 64MB 1,320 1,240 1,080 128MB TBD TBD TBD 32MB 12 12 12 64MB 12 12 12 128MB 16 16 16 680 n/a n/a 12 n/a n/a mA 5, 6, 7, 9 mA 8 10 32MB 4 64MB 8 128MB TBD 8 n/a n/a mA 11 IDD6 IDD7 See Note 12 4 8 8 4 8 8 NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. 4. IDD specifications are tested after the device is properly initialized. 5. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. The IDD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 7. Address transitions average one transition every two clocks. 8. tCK = 7.5ns for -13E/-133; tCK = 10ns for -10E; tCK 15ns for -662. 9. Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 10. CKE is HIGH during refresh command period (tRFC[MIN]) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 11. Enables on-chip refresh and address counters. 12. Values represent single module bank operation. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs CAPACITANCE (Note: 1) PARAMETER SYMBOL MIN MAX UNITS NOTES Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, WE#, CKE0 CI1 12 18 pF Input Capacitance: CK0-CK3 CI2 25 29 pF Input Capacitance: S0#, S2# CI3 6 10 pF Input Capacitance: DQMB0#-DQMB7# CI4 4 6 pF Input Capacitance: SCL, SA0-SA2, SDA CI0I – 10 pF Input/Output Capacitance: DQ0-DQ63 CIO2 6 8 pF 2 NOTE: 1. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 2. Values shown include added loading capacitance for 66 MHz, CK0 = 12pF (MIN), 16pF (MAX). 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS (Notes: 1-5) AC CHARACTERISTICS PARAMETER Access time from CK (pos. edge) -13E (PC133) -133 (PC133) -10E (PC100) -662 (PC66) SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES tAC CL = 3 5.4 5.4 6 7.5 ns tAC CL = 2 5.4 6 6 9 ns tAH Address hold time 0.8 0.8 1 1 ns tAS Address setup time 1.5 1.5 2 2 ns tCH CK high-level width 2.5 2.5 3 3 ns tCL CK low-level width 2.5 2.5 3 3 ns tCK Clock cycle time CL = 3 7 7.5 8 10 ns 6 tCK CL = 2 7.5 10 10 15 ns 6 tCKH CKE hold time 0.8 0.8 1 1 ns tCKS CKE setup time 1.5 1.5 2 2 ns t CS#, RAS#, CAS#, WE#, DQM hold time CMH 0.8 0.8 1 1 ns tCMS CS#, RAS#, CAS#, WE#, DQM setup time 1.5 1.5 2 2 ns tDH Data-in hold time 0.8 0.8 1 1 ns tDS Data-in setup time 1.5 1.5 2 2 ns tHZ Data-out high-impedance time CL = 3 5.4 5.4 6 8 ns 7 tHZ CL = 2 5.4 6 7 10 ns 7 tLZ Data-out low-impedance time 1 1 1 2 ns t Data-out hold time (load) OH 2.7 2.7 3 3 ns tOH Data-out hold time (no load) 1.8 1.8 1.8 n/a ns 8 N tRAS ACTIVE to PRECHARGE command 37 120,000 44 120,000 50 120,000 60 120,000 ns tRC ACTIVE to ACTIVE command period 60 66 70 90 ns t ACTIVE to READ or WRITE delay RCD 15 20 20 30 ns tREF Refresh period (4,096 cycles) 64 64 64 64 ms tRFC AUTO REFRESH period 66 66 70 90 ns tRP PRECHARGE command period 15 20 20 30 ns tRRD ACTIVE bank A to ACTIVE bank B command 14 15 20 20 ns tT Transition time 0.3 1.2 0.3 1.2 0.3 1.2 1 1.2 ns 9 t WR CK + 1 CK + 1 CK + 1 CK + – 10 WRITE recovery time 7ns 7.5ns 7ns 7ns Exit SELF REFRESH to ACTIVE command tXSR 14 67 15 75 15 80 15 90 ns ns 11 12 *Specifications for the SDRAM components used on the module. NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ +70°C) is ensured. 2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Outputs measured at 1.5V with equivalent load: Q 50pF 5. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs NOTES: (continued) 6. The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 7. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 8. Parameter guaranteed by design. 9. AC characteristics assume tT = 1ns. 10. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 11. Precharge mode only. 12. CK must be toggled a minimum of two times during this period. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs AC FUNCTIONAL CHARACTERISTICS (Notes: 1-5) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH -133 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 -13E/-10E 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 -662 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 UNITS NOTES tCK 6 tCK 7 tCK 7 tCK 6 tCK 6 tCK 11 tCK 6 tCK 8, 9 tCK 9, 10 tCK 6 tCK 6 tCK 9, 10 tCK 12 tCK 6 tCK 6 NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ +70°C) is ensured. 2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Outputs measured at 1.5V with equivalent load: Q 50pF 5. 6. 7. 8. 9. 10. 11. 12. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. Based on tCK = 133 MHz for -13E/-133, 100 MHz for -10E and 66 MHz for -662. Timing actually specified by tWR. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. JEDEC and PC100 specify three clocks. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX SUPPLY VOLTAGE VDD 3 3.6 INPUT HIGH VOLTAGE: Logic 1; All inputs VIH INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDD x 0.3 OUTPUT LOW VOLTAGE: IOUT = 3mA VDD x 0.7 VDD + 0.5 UNITS NOTES V V V VOL – 0.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI – 10 µA OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO – 10 µA STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% ISB – 30 µA POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz IDD – 2 mA NOTE: 1. All voltages referenced to VSS. SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWRC MIN 0.3 4.7 300 MAX 3.5 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 UNITS µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms NOTES 2 NOTE: 1. All voltages referenced to VSS. 2. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a WRITE sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs SPD EEPROM tF t HIGH tR t LOW SCL t HD:STA t SU:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a MIN 0.3 4.7 300 MAX 3.5 300 0 4 UNITS µs µs ns ns µs µs SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO 19 MIN 4 4.7 MAX 1 250 4.7 4.7 UNITS µs µs µs ns µs µs Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 4, 8, 16 MEG x 64 SDRAM DIMMs 168-PIN DIMM FRONT VIEW .125 (3.18) MAX 5.256 (133.50) 5.244 (133.20) .079 (2.00) R (2X) 1.005 (25.53) .700 (17.78) 0.995 (25.27) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) .039 (1.00)R (2X) 2.625 (66.68) .128 (3.25) (2X) .118 (3.00) .039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) .050 (1.27) TYP .054 (1.37) .046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4, 8 Meg x 64 SDRAM DIMMs ZM16_4.p65 – Rev. 4/00a 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. Micron Memory DRAM Module Reference Guide Density 4MB 4MB 4MB 8MB 8MB 8MB 8MB 8MB 16MB 16MB 16MB 16MB 16MB 32MB 32MB 32MB 32MB 32MB 32MB 32MB 32MB 32MB 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 256MB 256MB Description SS 1 Meg x 32 Gold SIMM/Tin SIMM SS 1 Meg x 32 3.3V Gold SODIMM SS 1 Meg x 32 3.3V Gold DIMM DS 2 Meg x 32 Gold SIMM/Tin SIMM SS 2 Meg x 32 3.3V Gold SODIMM SS 2 Meg x 32 3.3V Gold DIMM SS 1 Meg x 64 3.3V Gold SODIMM DS 1 Meg x 64 3.3V Gold DIMM SS 4 Meg x 32 Gold SIMM/Tin SIMM SS 4 Meg x 36 ECC Gold SIMM/Tin SIMM DS 4 Meg x 32 3.3V Gold SODIMM SS 4 Meg x 32 3.3V Gold SODIMM SS 4 Meg x 32 3.3V Gold DIMM DS 8 Meg x 32 Gold SIMM/Tin SIMM DS 8 Meg x 36 ECC Gold SIMM/Tin SIMM DS 8 Meg x 32 3.3V Gold SODIMM DS 8 Meg x 32 3.3V Gold DIMM DS 4 Meg x 64 3.3V Gold SODIMM SS 4 Meg x 64 3.3V Gold DIMM DS 4 Meg x 64 3.3V Gold DIMM DS 4 Meg x 72 3.3V ECC Gold DIMM SS 4 Meg x 72 3.3V ECC Gold DIMM DS 8 Meg x 64 3.3V Gold SODIMM DS 8 Meg x 64 3.3V Gold DIMM SS 8 Meg x 64 3.3V Gold DIMM DS 8 Meg x 72 3.3V ECC Gold DIMM SS 8 Meg x 72 3.3V ECC Gold DIMM SS 8 Meg x 72 3.3V ECC Gold DIMM DS 16 Meg x 64 3.3V Gold DIMM DS 16 Meg x 72 3.3V ECC Gold DIMM DS 16 Meg x 72 3.3V ECC Gold DIMM DS 32 Meg x 72 3.3V ECC Gold DIMM DS 32 Meg x 72 3.3V ECC Gold DIMM Pins Components on Module 72 (2) 1 Meg x 16 72 (2) 1 Meg x 16 3.3V TSOP 100 (2) 1 Meg x 16 3.3V TSOP 72 (4) 1 Meg x 16 72 (4) 1 Meg x 16 3.3V TSOP 100 (4) 1 Meg x 16 3.3V 144 (4) 1 Meg x 16 3.3V TSOP 168 (4) 1 Meg x 16 3.3V TSOP 72 (8) 4 Meg x 4 72 (9) 4 Meg x 4 72 (8) 4 Meg x 4 3.3V TSOP 72 (2) 4 Meg x 16 3.3V TSOP 100 (2) 4 Meg x 16 3.3V TSOP 72 (16) 4 Meg x 4 72 (18) 4 Meg x 4 72 (4) 4 Meg x 16 3.3V TSOP 100 (4) 4 Meg x 16 3.3V TSOP 144 (4) 4 Meg x 16 3.3V TSOP 168 (4) 4 Meg x 16 3.3V TSOP 168 (16) 4 Meg x 4 3.3V 168 (18) 4 Meg x 4 3.3V 168 (5) 4 Meg x 16 3.3V TSOP 144 (8) 8 Meg x 8 3.3V TSOP 168 (32) 4 Meg x 4 3.3V 168 (8) 8 Meg x 8 3.3V 168 (36) 4 Meg x 4 3.3V 168 (9) 8 Meg x 8 3.3V 168 (9) 8 Meg x 8 3.3V TSOP 168 (16) 16 Meg x 4 3.3V 168 (18) 16 Meg x 4 3.3V 168 (18) 16 Meg x 4 3.3V TSOP 168 (36) 16 Meg x 4 3.3V 168 (36) 16 Meg x 4 3.3V TSOP Part Number MT2D132G/M (X) MT2LDT132HG (X) MT2LD132UG (X) MT4D232DG/M (X) MT4LDT232HG (X) MT4LD232UG (X) MT4LDT164HG (X) MT4LDT164AG (X) MT8D432G/M (X) MT9D436G/M (X) MT8LDT432HG (X) MT2LDT432HG (X) MT2LDT432UG (X) MT16D832G/M (X) MT18D836G/M (X) MT4LDT832HG (X) MT4LDT832UG (X) MT4LDT464HG (X)(S) MT4LDT464AG (X) MT16LD464AG (X) MT18LD472(A)G (X) MT5LDT472(A)G (X) MT8LDT864HG (X)(S) MT32LD864AG (X) MT8LD864AG (X) MT36LD872(A)G (X) MT9LD872(A)G (X) MT9LDT872G (X) MT16LD1664AG (X) MT18LD1672(A)G (X) MT18LDT1672G (X) MT36LD3272G (X) MT36LDT3272G (X) Speed 50,60 60 60 50,60 60 60 60 60 50, 60 50, 60 60 60 60 50, 60 50, 60 60 60 50,60 50,60 60 60 60 60 60 50, 60 60 50, 60 50, 60 50,60 50,60 50,60 50, 60 50, 60 Height .800" 1.000" 1.000" .800" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" 1.000" Unbuff = 1.000", Buff = 1.000" Unbuff = 1.000", Buff = 1.050" 1.050" 1.500" 1.100" Unbuff = 1.500", Buff = 1.500" Unbuff = 1.100", Buff = 1.250" 1.350" 1.250" Unbuff = 1.250", Buff = 1.100" 2.000" 2.000" 2.000" Availability Samples Prod. Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Rev. 7/10/01 SS - Single Sided DS - Double Sided G - Gold Plated M - Tin Plated U - 100-pin DIMM (H) - Small-Outline DIMM (SODIMM) (X) - EDO; no "X" denotes FPM version (A) - 8-CAS; SPD version; unbuffered (no "A" denotes buffered version for x72 DIMMs) Micron Technology, Inc. reserves the right to change products or specifications without notice. (S) - Self Refresh Micron Memory SDRAM Module Reference Guide Density Description 4MB SS 1 Meg x 32 3.3V Gold DIMM Pins 100 Components on Module (2) 1 Meg x 16 3.3V TSOP Base Part Number MT2LSDT132UG 3.3V TSOP 3.3V TSOP 3.3V TSOP MT2LSDT132AGP MT1LSDT132AGP MT4LSDT232UDG SS SS DS 1 Meg x 32 AIMM 1 Meg x 32 AIMM 2 Meg x 32 3.3V Gold DIMM 100 (2) 1 Meg x 16 (1) 2 Meg x 32 (4) 1 Meg x 16 16MB SS 4 Meg x 32 3.3V Gold DIMM 100 (2) 4 Meg x 16 3.3V TSOP MT2LSDT432UG 32MB DS 8 Meg x 32 3.3V Gold DIMM 100 (4) 4 Meg x 16 3.3V TSOP MT4LSDT832UDG 32MB DS 4 Meg x 64 3.3V Gold SODIMM 144* (4) 4 Meg x 16 3.3V TSOP MT4LSDT464HG 8MB 32MB SS 32MB SS 64MB DS 4 Meg x 64 3.3V Gold DIMM 4 Meg x 72 3.3V ECC Gold DIMM 16 Meg x 32 3.3V Gold DIMM 168 168* 100 64MB DS 8 Meg x 64 3.3V Gold SODIMM 144* 64MB DS 8 Meg x 64 3.3V Gold SODIMM 144* 64MB SS 64MB SS DS 64MB SS 64MB SS 8 Meg x 64 3.3V Gold DIMM 8 Meg x 64 3.3V Gold DIMM 8 Meg x 64 3.3V Gold Micro DIMM 8 Meg x 72 3.3V Gold DIMM 8 Meg x 72 3.3V ECC Gold DIMM 168 168 144 168 168 (4) 4 Meg x 16 (5) 4 Meg x 16 3.3V TSOP 3.3V TSOP MT4LSDT464AG MT5LSDT472AG (4) 16 Meg x 8 3.3V TSOP MT4LSDT1632UG (4) 8 Meg x 16 3.3V TSOP MT4LSDT1632UDG (8) 8 Meg x 8 (8) 4 Meg x 16 (4) 8 Meg x 16 3.3V TSOP 3.3V TSOP 3.3V TSOP MT8LSDT864HG (8) 8 Meg x 8 (4) 8 Meg x 16 (4) 8 Meg x 16 (5) 8 Meg x 16 (9) 8 Meg x 8 3.3V TSOP 3.3V TSOP 3.3V TSOP 3.3V TSOP 3.3V TSOP MT4LSDT864HG MT8LSDT864AG MT4LSDT864AG MT4LSDT864WG MT5LSDT872AG MT9LSDT872AG Speed -10E1 -8E1 -6E2 -6E1 -10E1 -8E1 -10C1 -8C1 -10C1 -8C1 -662C1 -662C2 -10EC3 -10EC4 -133C4 -13EC4 -662C6 -10CC6 -10EC6 -133C6 -13EC6 -662C6 -10CC6 -10EC6 -133C6 -13EC6 -10B1 -8B1 -10E1 -8E1 -10B1 -8B1 -10F1 -8F1 -662C3 -10EC5 -662B1 -10EB1 -10EB2 -133B2 -13EB2 -10EF2 -133F2 -13EF2 -662C7 -10CC7 -10EC7 -133C7 -13EC7 -662B1 -10CB1 -10EB1 -133B1 -13EB1 -10EF1 -133F1 -13EF1 -133F1 -10EB1 -133B1 -13EB1 -10EF1 -133F1 -13EF1 -662C7 -10CC7 -10EC7 -133C7 -13EC7 Die Rev. E = Y72G PCB (height) 1 = 6649 (1.000") E = Y72G E = Y84W E = Y72G 2 = 0164B (1.4") 1 = 0178 (1.4") 1 = 6649 (1.000") C = Y84 1 = 6660 (1.000") C = Y84 1 = 6660 (1.000") C = Y84 1 = 6645 (1.150") 2 = 6669 (1.000") 3 = 0118B (1.000") 4 = 0180 (1.000") C = Y84 C = Y84 6 = 0134B (1.000") 6 = 0134B (1.000") B = Y85B E = Y95C 1 = 6692(1.15") B = Y85B F = Y95W 1 = 6660(1.00") C = Y84 B = Y85B F = Y95W 3 = 6678 (1.050") 5 = 0115C (1.250") 1 = 0118B (1.000") 2 = 0180 (1.000") C = Y84 7 = 0104B (1.375") B = Y85B F = Y95W 1 = 0134B (1.00") F = Y95W B = Y85B F = Y95W 1 = 0182 (1.18") 1 = 0134B (1.00") C = Y84 7 = 0104B (1.375") MHz* 100 125 133 133 100 125 100 125 100 125 66 66 100 100 133 133 66 100 100 133 133 66 100 100 133 133 100 125 100 125 100 125 100 125 66 100 66 100 100 133 133 100 133 133 66 100 100 133 133 66 100 100 133 133 100 133 133 133 100 133 133 100 133 133 66 100 100 133 133 Availability Samples Production Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now 4Q01 Now 4Q01 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now 4Q01 Now 4Q01 Now 4Q01 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now 4Q01 Now 4Q01 Now 4Q01 Now 4Q01 Now Now Now Now Now Now Now 4Q01 Now 4Q01 Now 4Q01 Now Now Now Now Now Now Now Now Now Now Notes PC100 PC100 PC133 rev 1.0 PC133 rev 1.0 CL3 CL2 CL3 CL2 PC100 PC100 PC100 PC133 rev 1.0 PC133 rev 1.0 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 Density Description 64MB SS 8 Meg x 72 3.3V ECC Gold DIMM 128MB DS 128MB DS 32 Meg x 32 3.3V Gold DIMM 16 Meg x 64 3.3V Gold SODIMM Pins 168 100 144 Components on Module (9) 8 Meg x 8 3.3V TSOP (8) 16 Meg x 8 3.3V TSOP MT8LSDT3232UG (8) 8 Meg x 16 3.3V TSOP MT8LSDT3232UDG (8) 8 Meg x 16 3.3V TSOP MT8LSDT1664HG 16 Meg x 8 8 Meg x 16 128MB DS 128MB DS 16 Meg x 64 3.3V Gold DIMM 16 Meg x 64 3.3V Gold DIMM 168 168 Base Part Number MT9LSDT872G (16) 8 Meg x 8 (8) 16 Meg x 8 3.3V TSOP 3.3V TSOP 3.3V TSOP MT16LSDT1664AG 3.3V TSOP MT8LSDT1664AG SS 16 Meg x 64 3.3V Gold DIMM 168 (4) 16 Meg x 16 3.3V TSOP MT4LSDT1664AG DS DS 16 Meg x 64 3.3V Gold Micro DIMM 144 144 16 Meg x 64 3.3V Gold SODIMM (4) 16 Meg x 16 3.3V TSOP MT4LSDT1664WG (4) 16 Meg x 16 3.3V TSOP MT4LSDT1664HG 128MB DS 128MB SS SS 16 Meg x 72 3.3V ECC Gold DIMM 16 Meg x 72 3.3V ECC Gold DIMM 16 Meg x 72 3.3V ECC Gold DIMM 168 168 (18) 8 Meg x 8 (9) 16 Meg x 8 3.3V TSOP MT18LSDT1672AG 3.3V TSOP MT9LSDT1672AG 168 (5) 16 Meg x 16 3.3V TSOP MT5LSDT1672AG 168 (9) 16 Meg x 8 3.3V TSOP MT9LSDT1672G Speed -10CC3 -10EC3 -133C3 -13EC3 -10B1 -8B1 -10E1 -8E1 -10B1 -8B1 -10F1 -8F1 -10CB1 -10EB1 -662B2 -10EB3 -133B3 -13EB3 -10EF3 -133F3 -13EF3 -662C7 -10CC7 -10EC7 -133C7 -13EC7 -10CB1 -10EB1 -133B1 -13EB1 -10EE1 -133E1 -13EE1 -10EE3 -133E3 -13EE3 -10EB1 -133B1 -13EB1 -133B1 -10EB1 -133B1 -13EB1 -662C7 -10CC7 -10EC7 -133C7 -13EC7 -10CB1 -10EB1 -133B1 -13EB1 -10EE1 -133E1 -13EE1 -10EE3 -133E3 -13EE3 -10EB1 -133B1 -13EB1 -10CB1 -10EB1 -133B1 -13EB1 Die Rev. C = Y84 PCB (height) 3 = 0144 (1.500") B = Y85B E = Y95C 1 = 6692 (1.15") B = Y85B F = Y95W 1 = TBD (1.15") B = Y85B F = Y95W 1 = 0115C (1.25") 2 = 6678 (1.050") 3 = 0179 (1.25") C = Y84 B = Y85B E = Y95C 7 = 0104B(1.375") 1 = 0104B(1.375") 3 = 0209(1.125") B = Y96 1 = TBD (1.00") B = Y96 B = Y96 1 = 0182 (1.18") 1 = 0180 (1.00") C = Y84 7 = 0104B(1.375") B = Y85B E = Y95C 1 = 0104B(1.375") 3 = 0209(1.125") B = Y96 1 = TBD (1.00") B = Y85B E = Y95C 1 = 0144(1.500") 2 = 0198(1.125") MHz* 100 100 133 133 100 125 100 125 100 125 100 125 100 100 66 100 133 133 100 133 133 66 100 100 133 133 100 100 133 133 100 133 133 100 133 133 100 133 133 133 100 133 133 66 100 100 133 133 100 100 133 133 100 133 133 100 133 133 100 133 133 100 100 133 133 Availability Samples Production Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now TBD TBD TBD TBD TBD TBD TBD TBD Now Now Now Now Now Now Now Now Now Now Now Now Now 4Q01 Now 4Q01 Now 4Q01 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Sept 4Q01 Now Now Now Now Now Now Sept 4Q01 Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Sept 4Q01 Now Now Now Now Now Now Now Now Notes CL3 CL2 PC100 PC100 PC100 PC133 rev 1.0 PC133 rev 1.0 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 Density Description Pins Components on Module Base Part Number DS 128MB DS 256MB DS 16 Meg x 72 3.3V ECC Gold DIMM 32 Meg x 64 3.3V Gold DIMM 168 168 (18) 16 Meg x 4 (16) 16 Meg x 8 3.3V TSOP MT18LSDT1672G 3.3V TSOP MT16LSDT3264AG DS 32 Meg x 64 3.3V Gold SODIMM 144 (8) 16 Meg x 16 3.3V TSOP MT8LSDT3264HG SS 32 Meg x 64 3.3V Gold DIMM 168 (8) 32 Meg x 8 3.3V TSOP MT8LSDT3264AG DS DS 32 Meg x 64 3.3V Gold Micro DIMM 144 144 32 Meg x 64 3.3V Gold SODIMM (8) 32 Meg x 8 (16) 16 Meg x 8 3.3V FBGA MT8LSDF3264WG 3.3V FBGA MT16LSDF3264HG 168 (18) 16 Meg x 8 3.3V TSOP MT18LSDT3272AG 256MB DS 256MB DS DS 32 Meg x 72 3.3V ECC Gold DIMM 32 Meg x 72 3.3V ECC Gold DIMM 32 Meg x 72 3.3V ECC Gold DIMM 168 168 (18) 32 Meg x 4 (18) 16 Meg x 8 3.3V TSOP MT18LSDT3272G 3.3V TSOP MT18LSDT3272DG SS 32 Meg x 72 3.3V ECC Gold DIMM 168 (9) 32 Meg x 8 3.3V TSOP MT9LSDT3272AG SS 32 Meg x 72 3.3V ECC Gold DIMM 168 (9) 32 Meg x 8 3.3V TSOP MT9LSDT3272G DS Speed -10EE1 -133E1 -13EE1 -10EE2 -133E2 -13EE2 -10CC2 -10EC2 -133C2 -13EC2 -10CB1 -10EB1 -133B1 -13EB1 -10EE1 -133E1 -13EE1 -10EE3 -133E3 -13EE3 -10EB1 -133B1 -10EB2 -133B2 -13EB2 -133B1 -10EB2 -133B2 -10EE3 -133E3 -10EE4 -133E4 -13EE4 -10CB1 -10EB1 -133B1 -13EB1 -10EE1 -133E1 -13EE1 -10EE3 -133E3 -13EE3 -10EB1 -133B1 -13EB1 -10EE1 -133E1 -13EE1 -10EB1 -133B1 -13EB1 -10EE1 -133E1 -13EE1 -10EB2 -133B2 -13EB2 -10EB1 -133B1 -13EB1 -10EB2 -133B2 -13EB2 Die Rev. C = Y84 B = Y85B E = Y95C PCB (height) 2 = 0129 (1.700") 1 = 0104B (1.375") 3 = 0209(1.125") B = Y96 1 = 0179 (1.25") B = Y96 2 = 0209 (1.125") B = Y96 B = Y85B E = Y95C 1 = 0189 (1.25") 2 = 0155 (1.25") 3 = 0185A (1.25") 4 = 0185B (1.25") B = Y85B E = Y95C 1 = 0104B (1.375") 3 = 0209 (1.125") B = Y85B E = Y95C B = Y85B E = Y95C 1 = 0129 (1.700") 1 = 0156 (1.7") B = Y96 2 = 0209 (1.125") B = Y96 1 = TBD (1.70") 2 = 0198(1.125") MHz* 100 133 133 100 133 133 100 100 133 133 100 100 133 133 100 133 133 100 133 133 100 133 100 133 133 133 100 133 100 133 100 133 133 100 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 Availability Samples Production Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Sept 4Q01 Now Sept Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Now Sept 4Q01 Now Now Now Now Sept 4Q01 Now Now Now Now Sept 4Q01 Notes CL3 CL2 1U 1U 1U CL3 CL2 CL3 CL2 CL3 CL2 PC100 PC133 rev 1.0 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 CL3 CL2 1U 1U 1U Density Description 512MB DS 64 Meg x 72 3.3V ECC Gold DIMM DS Components on Module Base Part Number (36) 32 Meg x 4 3.3V FBGA MT36LSDF6472G 168 (16) 32 Meg x 8 3.3V TSOP MT16LSDT6464AG DS 64 Meg x 64 3.3V Gold SODIMM 144 (16) 32 Meg x 8 3.3V FBGA MT16LSDF6464HG DS 64 Meg x 72 3.3V ECC Gold DIMM 168 (18) 32 Meg x 8 3.3V TSOP MT18LSDT6472AG DS DS 1GB 64 Meg x 64 3.3V Gold DIMM Pins 168 64 Meg x 72 3.3V ECC Gold DIMM 64 Meg x 72 3.3V ECC Gold DIMM 168 168 (18) 64 Meg x 4 (18) 32 Meg x 8 3.3V TSOP MT18LSDT6472G 3.3V TSOP MT18LSDT6472DG DS 64 Meg x 72 3.3V ECC Gold DIMM 168 (18) 64 Meg x 4 3.3V FBGA MT18LSDF6472G DS 128 Meg x 72 3.3V ECC Gold DIMM 168 (36) 64 Meg x 4 3.3V FBGA MT36LSDF12872G Speed -10EB1 -133B2 -10EB2 -133B2 -13EB2 -10EB2 -133B2 -10EB2 -133B2 -13EB2 -10EB1 -133B1 -13EB1 -10EB1 -133B1 -13EB1 -10EB2 -133B2 -13EB2 -10EB1 -133B1 -13EB1 -10EB1 -133B1 -13EB1 a b Part Number = a + b Example: MT36LSDF12872G-13EB1 Die Rev. B = Y85B B = Y96 PCB (height) 1 = 0123(1.70") 2 = 0142(1.70") 2 = 0209 (1.125") B = Y96 2 = 0185B (1.25") B = Y96 2 =0209 (1.125") B = Y96 B = Y96 1 = 0129 (1.700") 1 =0156 (1.70") 2 =0198 (1.125") B = Y96 1 = 0187 (1.05") B = Y96 1 = 0142 (1.700") MHz* 100 133 100 133 133 100 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 100 133 133 Availability Samples Production Now Now Now Now Now Now Now Now Sept 4Q01 Now Now Now Now Now Now Now Now Sept 4Q01 Now Now Now Now Sept 4Q01 Now Now Now Now Sept 4Q01 Now Now Now Now Sept 4Q01 Now Now Now Now Sept 4Q01 Now Now Now Now Oct 4Q01 Notes 11x13pkg CL3 CL3 CL2 CL3 CL2 CL3 CL2 1U 1U 1U 1U 1U 1U CL3 CL2 Rev. 7/10/01 *For 168-pin DIMMs (66 MHz/100 MHz), adheres to Intel’s 4-Clock SDRAM module specs (66 MHz will use -10 components; 100 MHz will use -8 components). For 100-pin DIMMs, 100 MHz uses -10 components; adheres to JEDEC standard. SS - Single Sided DS - Double Sided G - Gold Plated U - 100-pin DIMM UDG - Double-sided, dual-bank 100-pin DIMM (H) - Small-Outline DIMM (SODIMM) LP - Low Power (A) - 8-CAS; SPD version; unbuffered (no "A" denotes registered version for x72 DIMMs) (W) - Micro DIMM 1U - Reduced height for 1U servers Micron Technology, Inc. reserves the right to change products or specifications without notice. Micron Memory DDR SDRAM Module Reference Guide Density 64MB 128MB Description 8 Meg x 64 2.5V Gold SODIMM SS Pins 200 Components on Module (4) 8 Meg x 16 TSOP Base Part Number MT4VDDT864HG SS 8 Meg x 64 2.5V Gold DIMM 184 (4) 8 Meg x 16 TSOP MT4VDDT864AG DS 8 Meg x 64 2.5V Gold Micro DIMM 172 (4) 8 Meg x 16 TSOP MT4VDDT864WG SS 16 Meg x64 2.5V Gold DIMM 184 (8) 16 Meg x 8 TSOP MT8VDDT1664AG DS 16 Meg x64 2.5V Gold SODIMM 200 (8) 16 Meg x 8 TSOP MT8VDDT1664HG DS 16 Meg x64 2.5V Gold SODIMM 200 (8) 8 Meg x 16 TSOP MT8VDDT1664HDG SS 16 Meg x 64 2.5V Gold SODIMM 200 (4) 16 Meg x 16 TSOP MT4VDDT1664HG SS 16 Meg x 64 2.5V Gold DIMM 184 (4) 16 Meg x 16 TSOP MT4VDDT1664AG DS 16 Meg x 64 2.5V Gold Micro DIMM 172 (4) 16 Meg x 16 TSOP MT4VDDT1664WG SS 16 Meg x72 ECC 2.5V Gold DIMM 184 (9) 16 Meg x 8 TSOP MT9VDDT1672AG SS 16 Meg x72 ECC 2.5V Gold DIMM 184 (5) 16 Meg x 16 TSOP MT5VDDT1672AG SS 16 Meg x72 ECC 2.5V Gold DIMM 184 (9) 16 Meg x 8 MT9VDDT1672G TSOP Speed -202B1 -265B1 -26AB1 -262B1 -202B1 -265B1 -26AB1 -262B1 -202B1 -265B1 -202A1 -265A1 -26AA1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B2 -265B2 -26AB2 -262B2 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -26AA1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202Z1 -265Z1 -26AZ1 -202B1 -265B1 Die Rev. B = T95 B = T95 B = T95 A = T85 B = T95 A = T85 B = T95 A = T96A B = T96B A = T96A B = T96B A = T96A B = T96B A = T85 B = T95 A = T96A B = T96B Z = T85 B = T95 MHz PCB (height) (Data rate) 1 = 0175 (1.25") 200 266 266 266 1 = 0203 (1.25") 200 266 266 266 1 = 0207 (1.25") 200 266 1 = 0161 (1.25") 200 266 266 200 266 266 266 1 = 0168(1.25") 200 266 200 2 = 0174 (1.25") 266 266 266 1 = 0175 (1.25") 200 266 200 266 266 266 1 = 0203 (1.25") 200 266 200 266 266 266 1 = 0207 (1.25") 200 266 200 266 266 266 1 = 0161 (1.25") 200 266 266 200 266 266 266 1 = 0151 (1.25") 200 266 200 266 266 266 1 = 0162 (1.70") 200 2 = TBD (1.2") 266 266 200 266 Availability Samples Production 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 3Q01 4Q01 3Q01 4Q01 Now Now Now Now 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 Contact Mktg Contact Mktg Contact Mktg Contact Mktg 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 Now Now Now Now 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 Now Now Now Now 3Q01 4Q01 3Q01 3Q01 3Q01 3Q01 Notes Density Description Pins Components on Module Base Part Number DS 256MB 256MB DS 32 Meg x64 2.5V Gold DIMM 184 (16) 16 Meg x 8 TSOP MT16VDDT3264AG DS 32 Meg x64 2.5V Gold SODIMM 200 (8) 16 Meg x 16 TSOP MT8VDDT3264HDG SS 32 Meg x64 2.5V Gold DIMM 184 (8) 32 Meg x 8 TSOP MT8VDDT3264AG DS 32 Meg 72 ECC 2.5V Gold DIMM 184 (18) 16 Meg x 8 TSOP MT18VDDT3272AG DS 32 Meg 72 ECC 2.5V Gold DIMM 184 (18) 32 Meg x 4 TSOP MT18VDDT3272G DS 32 Meg 72 ECC 2.5V Gold DIMM 184 (18) 16 Meg x 8 TSOP MT18VDDT3272DG SS 32 Meg 72 ECC 2.5V Gold DIMM 184 (9) 32 Meg x 8 TSOP MT9VDDT3272AG DS 32 Meg 72 ECC 2.5V Gold DIMM 184 (9) 32 Meg x 8 TSOP MT9VDDT3272G Speed -26AB1 -262B1 -202Z2 -265Z2 -26AZ2 -202B2 -265B2 -26AB2 -262B2 -202A1 -265A1 -26AA1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -26AA1 -202B1 -265B1 -26AB1 -262B1 -202Z1 -265Z1 -26AZ1 -202B1 -265B1 -26AB1 -262B1 -202Z1 -265Z1 -26AZ1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 Die Rev. A = T85 B = T95 A = T96A B = T96B A = T96A B = T96B A = T85 B = T95 Z = T85 B = T95 Z = T85 B = T95 A = T96A B = T96B A = T96A B = T96B MHz (Data rate) 266 266 200 266 266 200 266 266 266 1 = 0116B (1.25") 200 266 266 200 266 266 266 200 1 = 0174 (1.25") 266 200 266 266 266 200 1 = 0161 (1.25") 266 200 266 266 266 1 = 0116B (1.25") 200 266 266 200 266 266 266 1 = 0163 (1.70") 200 266 266 200 266 266 266 1 = 0162 (1.70") 200 266 266 200 266 266 266 1 = 0161 (1.25") 200 266 200 266 266 200 1 = TBD (1.2") 200 266 200 266 266 200 PCB (height) Availability Samples Production 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 Now Now Now Now 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 Now Now Now Now 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 Now Now Now Now 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 Now Now Now Now 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 Notes 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U Density 512MB Description DS 64 Meg 64 2.5V Gold DIMM Pins 184 Components on Module (16) 32 Meg x 8 TSOP Base Part Number MT16VDDT6464AG DS 64 Meg 72 ECC 2.5V Gold DIMM 184 (18) 32 Meg x 8 TSOP MT18VDDT6472AG DS 64 Meg 72 ECC 2.5V Gold DIMM 184 (18) 32 Meg x 8 TSOP MT18VDDT6472DG DS 64 Meg 72 ECC 2.5V Gold DIMM DS 1GB DS 128 Meg 72 ECC 2.5V Gold DIMM 184 (18) 64 Meg x 4 TSOP MT18VDDT6472G 184 (18) 64 Meg x 4 FBGA MT18VDDF6472G 184 (36) 64 Meg x 4 FBGA MT36VDDF12872G Speed -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202A2 -265A2 -202B1 -265B1 -26AB1 -262B1 -202B2 -265B2 -26AB2 -262B2 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 -202A1 -265A1 -202B1 -265B1 -26AB1 -262B1 a b Part Number = a + b Example MT36VDDF12872G-262A1 SS - Single Sided DS - Double Sided G - Gold Plated (H) - Small-Outline DIMM (SODIMM) (A) - 8-CAS; SPD version; unbuffered (no "A" denotes registered version for x72 DIMMs) Speeds: -202xx = PC1600 CL2 SPD (2-2-2) -265xx = PC2100 CL2.5 SPD (2.5-3-3) -26Axx = PC2100 CL2 SPD (2-3-3) -262xx = PC2100 CL2 SPD (2-2-2) Micron Technology, Inc. reserves the right to change products or specifications without notice. (W) - Micro DIMM 1U - Reduced height for 1U servers Die Rev. A = T96A B = T96B A = T96A B = T96B A = T96A B = T96B A = T96A B = T96B A = T96A B = T96B A = T96A B = T96B MHz PCB (height) (Data rate) 1 = 0116B (1.25") 200 266 200 266 266 266 1 = 0116B (1.25") 200 266 200 266 266 266 1 = 0162 (1.70") 200 2 = TBD (1.2") 266 200 266 200 266 266 266 200 266 266 266 1 = 0163 (1.70") 200 266 200 266 266 266 1 = TBD (1.125") 200 266 200 266 266 266 1 = 0173 (1.70") 200 266 200 266 266 266 Availability Samples Production 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 3Q01 4Q01 3Q01 4Q01 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 4Q01 1Q02 Notes 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U 1U Rev. 7/10/01 Micron Memory Rambus® RIMM™ Module Reference Guide Density 128MB Description SS 64 Meg x 16 non-ECC Pins 184 Components on Module (4) 16 Meg x 16 Base Part Number MT4VR6416AG 128MB SS 32 Meg x 18 ECC 184 (4) 16 Meg x 18 MT4VR6418AG 256MB SS 64 Meg x 16 non-ECC 184 (8) 16 Meg x 16 MT8VR12816AG 256MB SS 64 Meg x 18 ECC 184 (8) 16 Meg x 18 MT8VR12818AG 512MB DS 128 Meg x 16 non-ECC 184 (16) 16 Meg x 16 MT16VR25616AG 512MB DS 128 Meg x 18 ECC 184 (16) 16 Meg x 18 MT16VR25618AG Speed -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 -653A1 -750A1 -745A1 -845A1 -840A1 a b Part Number = a + b Example MT16VR25618AG-840A1 Micron Technology, Inc. reserves the right to change products or specifications without notice. Die Rev. A = R96A PCB (height) 1 = TBD (1.25") A = R96A 1 = TBD (1.25") A = R96A 1 = TBD (1.25") A = R96A 1 =TBD (1.25") A = R96A 1 = TBD (1.25") A = R96A 1 = TBD (1.25") MHz 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 600 700 700 800 800 Availability Samples Production TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Rev. 7/10/01
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