Jetson TK1 Schematics

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D
C
B
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: TITLE
1:
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COVER PAGE
SYSTEM POWER TREE
I2C ADDRESS MAP
TK1: CH0 MEMORY I/F
TK1: CH1 MEMORY I/F
DDR3 X16 PAGE 1
DDR3 X16 PAGE 2
TK1: SDMMC/ULPI/JTAG/KB
TK1: CSI/DSI/HDMI/USB
TK1: UART/GMI/DAP/SPI
TK1: POWER
TK1: GND
HDMI TYPE A CONN
TK1: SATA, PEX, USB 3.0
MINI HALF PCIE
PEX OPTIONS AND SATA
USB PORTS
TEMP SENSOR, SERIAL, ID
PEX GIGE LAN/PHY
AUDIO CODEC
AUDIO CONNECTORS
JTAG CONN; I2C TRANSLATER
EMMC,SPI ROM
SWITCHES & STRAPS
SD CONN & FRONT PANEL HDR
EXP:TOUCH/DISP & GENERAL
DC IN
+3.3V VR
+5V VR
LOAD SWITCHES
PMIC: LOGIC AND GPIOS
PMIC: CNTL, INT SW, LDOS
PMIC: DCDC
PMIC: TK1 GPU AND CORE
VDD_CPU VR
REVISION HISTORY
BASENET REPORT
BASENET REPORT
BASENET REPORT
BASENET REPORT
BASENET REPORT
BASENET REPORT
CREF PART REPORT
CREF PART REPORT
CREF PART REPORT
CREF PART REPORT
CREF PART REPORT
CREF PART REPORT
CREF PART REPORT
D
C
TK1 Compact Development Module
602-7R375-0000-D00
SCH REV 4.02
5/7/2014
FAB REV D
BOM REV E
B
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050
NVIDIA
CONFIDENTIAL
ALL NVIDIA DESIGN SPECIFICATION, REFERENCE
BOARDS, FILTERS, DRAWINGS, DIAGNOSTICS, LISTS
AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY,
MATERIALS) ARE BEING PROVIDED AS IS. NVIDIA
MAKES NO WARRANTIES, EXPRESSED, IMPLIED,
STATUTORY OR OTHERWISE WITH RESPECT TO THE
MATERIALS, AND EXPRESSLY DISCLAIMS ALL IMPLIED
WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY
AND FITNESS FOR A PARTICULAR PURPOSE.
A
TITLE
A
COVER PAGE
TK1 Compact Development Module
DATE
Mon Apr 07 09:02:33 2014
DOC NUMBER
602-7R375-0000-D00
8
7
6
5
4
3
2
PAGE 1 OF 49
1
8
7
6
5
4
3
2
1
DDR3L
4X16
F
F
+VDD_MUX
DCDC0
MAIN PMU
DC CONN
AS3722
TK1 MID
X2
+VDD_MUX
DCDC6
PROCESSOR
AS3728
DCDC2
1.35V
VDD_GPU
AS3728
+VDDIO_DDR @6A
DCDC3
VDDIO_DDR,VDDIO_DDR_MCLK
1.35V
+VDD_MUX
+1.8V_VDDIO
VDDIO_SYS,AVDD_OSC,VDDIO_BB,VDDIO_SDMMC1,
VDDIO_SDMMC4,VDDIO_UART,
VDDIO_SYS2, VDDIO_AUDIO,VDDIO_GMI
DCDC5 (1.5A) 1.8V
+VDD_MUX
DCDC1
VDD_CORE
X1
AS3728
TPS51220
+5V_SYS
E
VDD_CPU
X2
DCIN_12V
DCDC
+1.05V_RUN
5V
AVDD_PEX_PLL, DVDDIO_PEX, AVDDIO_PEX,
AVDD_SATA_PLL, VDDIO_SATA
DCDC4 (1.5A) 1.05V
+3.3V_SYS
DCDC
LS
3.3V
+5V_STBY
LDO
+VDDIO_DDR
AVDD_HDMI_PLL
+1.05V_RUN_AVDD
5V
AVDD_PLL_EREFE, AVDD_PLL_X, AVDD_PLL_CG
AVDD_PLL_APC2C3,AVDD_PLL_M,AVDD_PLL_M
VDDIO_DDR_HS, AVDD_PLL_UD2DPD
AVDD_LVDS0_IO, AVDD_PLL_C4
LDO0 (300MA) 1.05V
+3.3V_LP0
+1.8V_VDDIO
VDDIO_HV, HVDD_PEX_PLL_E, HVDD_PEX
VDDIO_PEX_CTL, HVDD_SATA
+1.2V_GEN_AVDD
VDDIO_HSIC,AVDD_DSI_CSI
LDO2 (300MA) 1.2V
+3.3V_RUN
+1.05V_RUN
D
+3.3V_SYS
+2.8V_RUN_CAM
BD
AVDD_HDMI
LS
AVDD_HDMI_PLL
+3.3V_RUN
LDO4 (150MA) 2.8V
+1.8V_VDDIO_LP0_OFF
VDD_CORE
LDO3 SW
1.0V
LDO3 TRACK
1.0V
LDO3 SLEEP
1.0V
+3.3V_SYS
E
+VDD_RTC_AON
D
AVDD_LVDS0_PLL
AVDD_PLL_UTMIP
VDD_RTC
+VDDIO_DDR
C
+3.3V_RUN
C
+VDDIO_SDMMC3
LDO6
+1.8V_VDDIO
VDDIO_SDMMC3
3.3V/1.8V
SPI ROM 4MB
+1.8V_RUN_VPP_FUSE
VPP_FUSE
LDO11 (300MA) 1.8V
+1.8V_VDDIO
+2.85V_EMMC
EMMC
16GB
+1.8V_RUN_CAM
VDDIO_CAM
LDO1 (? MA) 1.8V
+3.3V_LP0
VDDIO_HV
+2.5V_AON_RTC
LDOVRTC_OUT
+VDDIO_DDR
USB90_VBUS
DDR3L-1600X4PCS
2G BYTE
VBACKUP
B
B
+3.3V_SYS
LOAD SW
TPS22908
+3.3V_SD_CARD
SD SOCKET
+5V_SYS
+3.3V_SYS
+1.8V_VDDIO
LS
EN1
AUDIO CODEC
ALC5639
LS
EN3
LOAD SW
TPS2065
USB 3.0
LOAD SW
TPS2051
USB 2.0
CONN
+3.3V_LP0
U AB CONN
+3.3V_RUN
+5V_SYS
+1.8V_VDDIO
A
+3.3V_RUN
8
7
TEMP SENSOR
TMP451
6
LS
EN3
+1.8V_VDDIO_LP0_OFF
TITLE
A
SYSTEM POWER TREE
+5V_SYS
5
LOAD SW
RT9728
4
DATE
HDMI CONN
Wed May 07 10:36:25 2014
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
REV
602-7R375-0000-D00
2
4.02
1
PAGE
2
8
7
6
5
4
3
2
1
POWER SEQUENCING
D
PMIC
NET NAME
0
1
2
3
4
5
6
7
8
9 10
11
12
20
21
D
VDD_MUX
C
V2_5
+2.5V_AON_RTC
ONKEY
ONKEY_L
VSUP_EN/EN5V
AS2730_5V_VR_EN
(+5V_SYS / +3.3_SYS)
LDO3
+1.05V_LP0_VDD_RTC
SD1
+VDD_CORE
SD5
+1.8V_VDDIO
GPIO2
PMU_REGEN1
(+3.3V_LP0)
SD2 & SD3
+1.35V_LP0
CLK32K
CLK_32KHZ_PMU
LDO0
+1.05V_RUN_AVDD
GPIO1
PMU_REGEN3
(+1.8V_VDDIO_LP0_OFF &
+3.3V_RUN)
GPIO4
EN_AVDD_LCD
C
VALID / RUNNING
RESET_OUT
SD4
+1.05V_RUN
S/W CONTROLLED
I2C ADDRESS MAP
B
BUS
DEVICE
GEN1_I2C - 1.8V
A
B
ADDRESS
AUDIO CODEC
7'H1C, 8'H38
TEMPERATURE SENSOR
7'H4C, 8'H98
BOARD ID
7'H56, 8'HAC
EXPANSION
UNKNOWN
GEN1_I2C - 3.3V
HALF MINI PCIE
UNKNOWN
GEN2_I2C - 3.3V
EXPANSION
UNKNOWN
PWR_I2C - 1.8V
PMIC AS3722
7'H40, 8'H80
EXPANSION
UNKNOWN
EXPANSION
UNKNOWN
CAM_I2C - 3.3V
A
TITLE
I2C ADDRESS MAP
Fri Apr 11 09:12:47 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
3
8
7
6
5
4
3
2
1
D
D
U3C1
BGA
PLACE <100 MILS FROM TEGRA
1
2
7D1<>
6D4<>
6D1<>
5C7<>
7D5<>
DDR_DQ<63..0>
BI
C
B
1
SEC 5 OF 8
16
17
18
19
20
21
22
23
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3B12
T3B2
T3B8
T3B3
T3B7
T3B5
T3B6
T3B4
B5
B2
A5
C2
B3
C3
A4
A3
DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
0
1
2
3
4
5
6
7
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3B34
T3B27
T3B24
T3B31
T3B25
T3B28
T3B23
T3B36
E9
A9
G8
C9
E8
F9
F8
D9
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
24
25
26
27
28
29
30
31
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3B22
T3B15
T3B21
T3B10
T3B17
T3B18
T3B16
T3B11
B8
C6
A8
A6
F6
D6
A7
E6
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
8
9
10
11
12
13
14
15
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3B38
T3B35
T3B37
T3B41
T3B32
T3B44
T3B26
T3B43
D11
A11
E11
B11
F11
G12
A10
H12
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
2.2PF
G14
H14
DDR_CLK
DDR_CLK_N
BYTE 2
BYTE 3
BYTE 1
TEE 1
TEE 1
1
T4B24
T4B18
H18
G18
DDR_CLKB
DDR_CLKB_N
TEE 1
TEE 1
T4C43
T4C31
1
2.2PF
0201_R
C0G
50V
+/-0.25PF
DDR_A<15..0>
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
C14
D12
E14
G15
E12
D14
B12
F14
C12
F12
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T4C5
T4C1
T4C6
T4B32
6
7
8
9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14
DDR_A15
H15
D20
F18
D18
C20
A16
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T4C10
T4C13
T4C18
T4C7
T4C14
T4C12
10
11
12
13
14
15
DDR_A_B3
DDR_A_B4
DDR_A_B5
G17
E20
H17
DDR_BA0
DDR_BA1
DDR_BA2
E17
E18
F17
TEE 1
TEE 1
TEE 1
T4C9
T4C16
T4C15
DDR_CAS_N
DDR_RAS_N
DDR_WE_N
C15
D15
E15
TEE 1
TEE 1
TEE 1
T4C4
T4C17
T4C3
0
1
2
T4C8
T4C2
T4B33
3
4
5
7B4<
6B4<
6D4<
7D4<
7B8<
6B8<
6D8<
7D8<
2
OUT
6D4<
1
R8B21
45.3
2
1%
0201_R
1
R8B19
45.3
1 C8B17
.01UF
6D8<
0201_R
X5R
10V
DDR_A1<5..3>
OUT
7D4<
7D8<
DDR_BA<2..0>
OUT
6C4<
6C8<
7C4<
7C8<
DDR_CAS_L
DDR_RAS_L
DDR_WE_L
OUT
OUT
OUT
6C4<
6C4<
6C4<
6C8<
6C8<
6C8<
7C4<
7C4<
7C4<
7C8<
7C8<
7C8<
OUT
6B4<
6B8<
7B4<
7B8<
6C8<
6C8<
6C8<
BI
BI
OUT
DDR_DQS2P
DDR_DQS2N
DDR_DM2
TEE 1
TEE 1
TEE 1
T3B13
T3B14
T3B1
C5
D5
C1
DDR_DQS0P
DDR_DQS0N
DDR_DM0
DDR_RESET_N
F15
DDR_RESET_L
DDR_CS0_N
DDR_CS1_N
A12
B14
DDR0_CS0_L
DDR0_CS1_L
OUT
OUT
6B4<
6B4<
6B8<
6B8<
6C8<
6C8<
6C8<
BI
BI
OUT
DDR_DQS0P
DDR_DQS0N
DDR_DM0
TEE 1
TEE 1
TEE 1
T3B30
T3B29
T3B33
G9
H9
B9
DDR_DQS1P
DDR_DQS1N
DDR_DM1
DDR_CS_B0_N
DDR_CS_B1_N
A19
A18
DDR1_CS0_L
DDR1_CS1_L
OUT
OUT
7B4<
7B4<
7B8<
7B8<
6C4<
6C4<
6C4<
BI
BI
OUT
DDR_DQS3P
DDR_DQS3N
DDR_DM3
TEE 1
TEE 1
TEE 1
T3B20
T3B19
T3B9
C8
D8
B6
DDR_DQS2P
DDR_DQS2N
DDR_DM2
DDR_CKE0
DDR_CKE1
A13
A14
DDR0_CKE0
DDR0_CKE1
OUT
OUT
6C4<
6C4<
6C8<
6C8<
DDR_CKE_B0
DDR_CKE_B1
A20
B20
DDR1_CKE0
DDR1_CKE1
OUT
OUT
7C4<
7C4<
7C8<
7C8<
6C4<
6C4<
6C4<
BI
BI
OUT
DDR_DQS1P
DDR_DQS1N
DDR_DM1
TEE 1
TEE 1
TEE 1
T3B42
T3B40
T3B39
H11
G11
C11
DDR_DQS3P
DDR_DQS3N
DDR_DM3
DDR_ODT0
DDR_ODT1
A15
B15
DDR0_ODT0
DDR0_ODT1
OUT
OUT
6B4<
6B4<
6B8<
6B8<
DDR_ODT_B0
DDR_ODT_B1
C18
B18
DDR1_ODT0
DDR1_ODT1
OUT
OUT
7B4<
7B4<
7B8<
7B8<
2
1%
0201_R
1
DDR0_CLK_TERM
2 10%
0
1
2
T4C11
OUT
1
DDR_A0<5..3>
3
4
5
TEE 1
PLACE AT "T" BRANCH
1
0201_R
C0G
50V
+/-0.25PF
C8C16
2
DDR3L4X16
BYTE 0
C8C1
1
R8C1
45.3
2
1%
0201_R
1
DDR0_CLKP
DDR0_CLKN
OUT
OUT
6C4<
6C4<
6C8<
6C8<
DDR1_CLKP
DDR1_CLKN
OUT
OUT
7C4<
7C4<
7C8<
7C8<
1
R8C2
45.3
1%
0201_R
1
DDR1_CLK_TERM
1 C8C12
.01UF
C
0201_R
X5R
10V
2 10%
B
I488
A
A
TITLE
TK1: CH0 MEMORY I/F
Mon Apr 07 08:50:46 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
4
8
7
6
5
4
3
2
+1.05V_RUN_AVDD
1 C8C10
0.1UF
D
0201_R
X5R
16V
U3C1
BGA
7D5<>
7D1<>
6D4<>
6D1<>
4D8<>
BI
B
9C4<
14C1<
14C7<
32D5>
0402_R
X5R
6.3V
D
2 20%
1 C8C8
0.1UF
1 C8C7
2.2UF
0402_R
X5R
6.3V
2 10%
2 20%
1 C8C18
0.1UF
1 C8C20
2.2UF
1
SEC 6 OF 8
DDR_DQ<63..0>
C
9C2<
1 C8C11
2.2UF
2 10%
0201_R
X5R
16V
IN
1
48
49
50
51
52
53
54
55
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3C11
T3C8
T3C7
T3C9
T3C2
T3C13
T3C1
T3C12
E21
B21
G21
A21
G20
D21
F20
C21
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
32
33
34
35
36
37
38
39
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3C35
T3C25
T3C36
T3C22
T3C29
T3C26
T3C31
T3C28
B26
C24
A26
A24
E26
D24
E27
A25
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
56
57
58
59
60
61
62
63
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3C20
T3C6
T3C19
T3C3
T3C17
T3C23
T3C14
T3C21
B23
G23
A23
H23
C23
F24
A22
E24
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
40
41
42
43
44
45
46
47
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
T3C44
T3C34
T3C43
T3C37
T3C38
T3C33
T3C41
T3C39
C31
C27
C30
A27
C29
D27
A29
A28
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
(1.05V)
AVDD_PLL_M
AVDD_PLL_APC2C3
K16
B17
VDDIO_DDR_HS
A17
0201_R
X5R
16V
2 10%
0402_R
X5R
6.3V
C
2 20%
DDR3L4X16
EMPTY
(1.2 - 1.5V)
VDDIO_DDR 1
VDDIO_DDR 2
VDDIO_DDR 3
VDDIO_DDR 4
VDDIO_DDR 5
VDDIO_DDR 6
VDDIO_DDR 7
VDDIO_DDR 8
VDDIO_DDR 9
VDDIO_DDR 10
J9
J12
J14
J11
J17
J18
J20
J21
K10
K11
VDDIO_DDR_MCLK
J15
EMPTY
EMPTY
1 C8B19
0.1UF
1 C8C31
0.1UF
1 C8C28
1 C8C38
1 C8B16
1 C8C36
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
2
2
4.7UF
2
4.7UF
2
4.7UF
2
4.7UF
2
1 C8B31 1 C8B14
2
4.7UF
4.7UF
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
2
1 C8B21
4.7UF
2
0402_R
X5R
6.3V
20%
1 C8B28
4.7UF
0402_R
X5R
6.3V
2 20%
ROUTE VDDIO_DDR_MCLK AS 10MIL TRACE W/5X SPACING FROM VREG
+1.35V_LP0_VDDIO_DDR_MCLK_AP
1 C8B30
0.1UF
B
1
ISO8C1
10MIL
0201_R
X5R
16V
2 10%
2
32D8<
6A8< 5A8<
32B8<
7A8<
33B2>
IN
+1.35V_LP0
PLACE CLOSE TO PIN
7C8<
7C8<
7C8<
BI
BI
OUT
DDR_DQS6P
DDR_DQS6N
DDR_DM6
TEE 1
TEE 1
TEE 1
T3C5
T3C4
T3C15
H21
H20
F21
DDR_DQS4P
DDR_DQS4N
DDR_DM4
7C8<
7C8<
7C8<
BI
BI
OUT
DDR_DQS4P
DDR_DQS4N
DDR_DM4
TEE 1
TEE 1
TEE 1
T3C30
T3C27
T3C24
C26
D26
B24
DDR_DQS5P
DDR_DQS5N
DDR_DM5
7C4<
7C4<
7C4<
BI
BI
OUT
DDR_DQS7P
DDR_DQS7N
DDR_DM7
TEE 1
TEE 1
TEE 1
T3C16
T3C18
T3C10
E23
D23
F23
DDR_DQS6P
DDR_DQS6N
DDR_DM6
7C4<
7C4<
7C4<
BI
BI
OUT
DDR_DQS5P
DDR_DQS5N
DDR_DM5
TEE 1
TEE 1
TEE 1
T3C42
T3C40
T3C32
B30
B29
B27
DDR_DQS7P
DDR_DQS7N
DDR_DM7
C17
D17
DDR_COMP_PU
DDR_COMP_PD
A
A
32D8<
32B8<
7A8<
6A8< 5B3<
33B2>
IN
+1.35V_LP0
2
R3C2
1%
DDR_COMP_PU
DDR_COMP_PD
1
0201_R
34
R3C1
34
TITLE
I665
2
TK1: CH1 MEMORY I/F
1%
0201_R
1
Mon Apr 07 08:50:48 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
5
8
7D8<
6B4<
7B4<
6B8<
7B8<
7D4<
4C3>
6D4<
7
D
7C4<
4C3>
6C4<
7C8<
7C8<
7C8<
IN
7C4<
7C4<
7C4<
6C4<
6C4<
6C4<
6B5>
7D8<
6B4<
7B4<
1
TEE
1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
A5
DDP
A6
FOOTPRINT
A7
A8
A9
A10/AP
A11
A12/BC_L
A13
A14/NC
TEE 1
TEE 1
TEE 1
T4C30
T4C36
T4B25
M2
N8
M3
BA0
BA1
BA2
TEE 1
TEE 1
TEE 1
T4C34
T4C44
T4B8
J3
K3
L3
RAS_L
CAS_L
WE_L
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
4D1>
4D1>
IN
IN
DDR0_CLKP
DDR0_CLKN
J7
K7
CK
CK_L
4B7<>
4B7<>
4B7<>
4B7<>
IN
IN
IN
IN
DDR_DQS2P
DDR_DQS2N
DDR_DQS0P
DDR_DQS0N
F3
G3
C7
B7
LDQS
LDQS_L
UDQS
UDQS_L
4B7>
4B7>
IN
IN
DDR_DM2
DDR_DM0
E7
D3
LDM
UDM
6C4<
6C4<
4B4>
4B4>
IN
IN
DDR0_CKE0
DDR0_CKE1
TEE 1
TEE 1
T4B20
T4B23
K9
J9
CKE0
CKE1
6B4<
6B4<
4B4>
4B4>
IN
IN
DDR0_CS0_L
DDR0_CS1_L
TEE 1
TEE 1
T4B30
T4B31
L2
L1
CS0_L
CS1_L
6B4<
6B4<
6B4<
4A4>
4A4>
4B3>
IN
IN
IN
DDR0_ODT0
DDR0_ODT1
DDR_RESET_L
TEE 1
TEE 1
TEE 1
T4B28
T4B14
T4C24
K1
J1
T2
ODT0
ODT1
RESET_L
M8
H1
VREFCA
VREFDQ
VREF_DDR0
1 C7B8
0.1UF
1 C7B13
0.1UF
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
2
6D4<
7B8<
1
TEE
T4B13
T4B6
T4B22
T4B21
T4B19
T4B2
T4B10
T4B7
T4C41
T4C25
T4C38
T4B1
T4B26
T4B12
T4B4
IN
IN
IN
4B3>
4B3>
4B3>
IN
B
TEE
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
0
1
2
C
7B4<
6
7
8
9
10
11
12
13
14
DDR_BA<2..0>
4B3>
7C8<
6C4<
6C4<
7B8<
3
4
5
DDR_A0<5..3>
IN
TEE 1
TEE 1
TEE 1
7D4<
4C3>
6D8<
2
IN
1
R7B2
R7B1
0201_R
2
1
0.5%
240
DDR_ZQ0_U27U1
2 DDR_ZQ1_U27U1
0201_R
L8
L9
15
TEE 1
T4B17
SNN_U27U1_Z3
SNN_U27U1_Z4
SNN_U27U1_Z1
SNN_U27U1_Z2
NC4/A15
NC5
NC6
NC7
NC8
A9
B3
E1
G8
J2
DDR_A<15..0>
CHANNEL 0
RANK 0
7D4<
DDR_DQ<63..0>
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E3
F7
F2
F8
H3
H8
G2
H7
16
17
21
23
19
22
20
18
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D7
C3
C8
C2
A7
A2
B8
A3
7
4
0
5
3
6
1
2
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
B2
D9
G7
K2
K8
N1
N9
R1
R9
BI
7B8<
7B4<
4D8<>
6B4<
6D8<
5C7<>
4C3>
6B8<
6D1<>
6D8<
4C3>
7C8<
7C4<
7C8<
7C8<
7C8<
2
0
1
2
7D5<>
IN
6C8<
7C4<
7C4<
7C4<
4B3>
R4B3
1K
1%
0402_R
1
7B8<
7B4<
6
7
8
9
10
11
12
13
14
0
1
2
M2
N8
M3
BA0
BA1
BA2
3
4
5
DDR_BA<2..0>
IN
VSS0
VSS1
VSS2
VSS3
VSS4
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
J8
M1
M9
P1
P9
T1
T9
6B8<
2
OUT
1 C7B4
0.1UF
R4B4
1K
1%
0402_R
2
0201_R
X5R
16V
10%
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
J3
K3
L3
RAS_L
CAS_L
WE_L
4D1>
4D1>
IN
IN
DDR0_CLKP
DDR0_CLKN
J7
K7
CK
CK_L
4B7<>
4B7<>
4A7<>
4A7<>
IN
IN
IN
IN
DDR_DQS3P
DDR_DQS3N
DDR_DQS1P
DDR_DQS1N
F3
G3
C7
B7
LDQS
LDQS_L
UDQS
UDQS_L
4A7>
4A7>
IN
IN
DDR_DM3
DDR_DM1
E7
D3
LDM
UDM
6C8<
6C8<
4B4>
4B4>
IN
IN
DDR0_CKE0
DDR0_CKE1
K9
J9
CKE0
CKE1
6B8<
6B8<
4B4>
4B4>
IN
IN
DDR0_CS0_L
DDR0_CS1_L
L2
L1
CS0_L
CS1_L
6B8<
6B8<
6B8<
4A4>
4A4>
4B3>
IN
IN
IN
DDR0_ODT0
DDR0_ODT1
DDR_RESET_L
K1
J1
T2
ODT0
ODT1
RESET_L
M8
H1
VREFCA
VREFDQ
L8
L9
ZQ0
ZQ1
M7
Z3
Z4
Z1
Z2
NC4/A15
NC5
NC6
NC7
NC8
A9
B3
E1
G8
J2
VSS0
VSS1
VSS2
VSS3
VSS4
4B3>
4B3>
4B3>
1
R4B2
0.5%
240
0201_R
X5R
16V
10%
R4B1
2
0201_R
7B4<
6D8<
6D4<
6B8<
7D8<
4C3>
7D4<
DDR_ZQ0_U27U2
DDR_ZQ1_U27U2
1
2
0201_R
0.5%
240
15
SNN_U27U2_Z3
SNN_U27U2_Z4
SNN_U27U2_Z1
SNN_U27U2_Z2
1
7B8<
IN
DDR_A<15..0>
A15 USED FOR FUTURE DUAL DIE CONFIG...
A
MEM_0A VDDQ
+1.35V_LP0
IN
1 C7B7
4.7UF
2
0402_R
X5R
6.3V
20%
1 C7B5
2
1 C7B6
0.1UF
0.1UF
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0402_R
X5R
2 6.3V
20%
1 C3B1
0.1UF
0201_R
X5R
2 16V
10%
2
1 C8B4
4.7UF
2
0402_R
X5R
6.3V
20%
1 C8B6
2
1 C7B11
1 C7B9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E3
F7
F2
F8
H3
H8
G2
H7
24
28
26
31
29
27
30
25
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D7
C3
C8
C2
A7
A2
B8
A3
8
15
12
13
10
11
14
9
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
J8
M1
M9
P1
P9
T1
T9
BI
7D5<>
6D4<>
4D8<>
5C7<>
7D1<>
D
BYTE 3
BYTE 1
C
B
1 C8B5
0.1UF
0.1UF
0.1UF
0.1UF
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
2
2
2
A
MEM_0B VDD
1 C4B1
1 C7C5
4.7UF
0.1UF
0402_R
X5R
0201_R
X5R
2 6.3V
20%
2 16V
10%
1 C7C3
0.1UF
0201_R
X5R
2 16V
10%
1 C7C6
1 C4B2
0.1UF
0201_R
X5R
0.1UF
0201_R
X5R
2 16V
10%
2 16V
10%
TITLE
1 C7B12
0.1UF
DDR3 X16 PAGE 1
0201_R
X5R
2 16V
10%
Wed Mar 26 14:39:56 2014
8
DDR_DQ<63..0>
MEM_0A VDD
MEM_0B VDDQ
1 C4B3
4.7UF
1
I259
I366
32D8<
7A8<
5A8<
5B3<
32B8<
33B2>
A5
DDP
A6
FOOTPRINT
A7
A8
A9
A10/AP
A11
A12/BC_L
A13
A14/NC
IN
IN
IN
6C8<
6C8<
6C8<
1 C7B10
0.1UF
2
TOP
U4B1
BGA100_2
DDR3_X16
1.35V
A0
1866
A1
256MBIT
A2
HYNIX
A3
2
A4
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
DDR_A0<5..3>
BYTE 2
BYTE 0
2
DDR_A<15..0>
IN
7D1<>
6C8<
6C8<
A1
A8
C1
C9
D2
E9
F1
H2
H9
3
VREF_DDR0
ZQ0
ZQ1
M7
Z3
Z4
Z1
Z2
4
7D8<
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
0.5%
240
5
BOTTOM
U7B1
BGA100_2
DDR3_X16
1.35V
A0
1866
A1
256MBIT
A2
HYNIX
A3
1
A4
DDR_A<15..0>
IN
0
1
2
6D4<
6
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
6
8
7B4<
6B4<
6D4<
7D4<
6D8<
4C3>
6B8<
7B8<
7
DDR_A<15..0>
IN
0
1
2
D
7D4<
6C4<
7C4<
7C4<
7C4<
7C4<
4C3>
4B3>
6C8<
6C8<
6C8<
6C8<
7B4>
1
TEE
1
A5
DDP
A6
FOOTPRINT
A7
A8
A9
A10/AP
A11
A12/BC_L
A13
A14/NC
TEE 1
TEE 1
TEE 1
T4B16
T4B5
T4C42
M2
N8
M3
BA0
BA1
BA2
TEE 1
TEE 1
TEE 1
T4B11
T4B27
T4C29
J3
K3
L3
RAS_L
CAS_L
WE_L
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
4C1>
4C1>
IN
IN
DDR1_CLKP
DDR1_CLKN
J7
K7
CK
CK_L
5A7<>
5A7<>
5B7<>
5B7<>
IN
IN
IN
IN
DDR_DQS4P
DDR_DQS4N
DDR_DQS6P
DDR_DQS6N
F3
G3
C7
B7
LDQS
LDQS_L
UDQS
UDQS_L
5A7>
5A7>
IN
IN
DDR_DM4
DDR_DM6
E7
D3
LDM
UDM
7C4<
7C4<
4A4>
4A4>
IN
IN
DDR1_CKE0
DDR1_CKE1
TEE 1
TEE 1
T4C35
T4C26
K9
J9
CKE0
CKE1
7B4<
7B4<
4B4>
4B4>
IN
IN
DDR1_CS0_L
DDR1_CS1_L
TEE 1
TEE 1
T4C47
T4C49
L2
L1
CS0_L
CS1_L
7B4<
7B4<
6B4<
4A4>
4A4>
4B3>
IN
IN
IN
DDR1_ODT0
DDR1_ODT1
DDR_RESET_L
TEE 1
TEE 1
TEE 1
T4C46
T4C37
T4B9
K1
J1
T2
ODT0
ODT1
RESET_L
M8
H1
VREFCA
VREFDQ
4B3>
4B3>
4B3>
VREF_DDR1
IN
1 C7C2
0.1UF
1 C7C4
0.1UF
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
2
6D8<
4C3>
6B8<
7D4<
1
TEE
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
T4C27
T4C23
T4C45
T4C48
T4C32
T4C40
T4C21
T4C19
T4B3
T4B29
T4B15
T4C22
T4C28
T4C39
T4C20
U4C1
BGA100_2
DDR3_X16
1.35V
A0
1866
A1
256MBIT
A2
HYNIX
A3
3
A4
IN
IN
IN
6C4<
6C4<
6C4<
B
7B4<
6B4<
6D4<
7D8<
TEE
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
TEE 1
0
1
2
C
6B8<
6
7
8
9
10
11
12
13
14
DDR_BA<2..0>
IN
TEE 1
TEE 1
TEE 1
3
4
5
DDR_A1<5..3>
IN
7C4<
7C4<
7B4<
6
2
1
R7C2
0201_R
2
0.5%
240
R7C1
DDR_ZQ0_U28U1
1
2 DDR_ZQ1_U28U1
0201_R
0.5% T4C33
15 240
1
TEE
L8
L9
M7
Z3
Z4
Z1
Z2
SNN_U28U1_Z3
SNN_U28U1_Z4
SNN_U28U1_Z1
SNN_U28U1_Z2
A9
B3
E1
G8
J2
DDR_A<15..0>
IN
5
7D8<
7B8<
7B4<
6D8<
4
6D4<
DDR_DQ<63..0>
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E3
F7
F2
F8
H3
H8
G2
H7
34
33
32
35
36
37
38
39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D7
C3
C8
C2
A7
A2
B8
A3
50
49
48
51
52
53
54
55
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
J8
M1
M9
P1
P9
T1
T9
6B8<
6B4<
4C3>
4D8<>
BI
7D8<
BYTE 4
4C3>
6D4<>
7D1<>
7C8<
6C8<
7C8<
7C8<
7C8<
6C4<
4B3>
6C8<
6C8<
6C8<
1%
0402_R
1
7B8<
6B8<
DDR_BA<2..0>
IN
0
1
2
M2
N8
M3
BA0
BA1
BA2
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
J3
K3
L3
RAS_L
CAS_L
WE_L
4C1>
4C1>
IN
IN
DDR1_CLKP
DDR1_CLKN
J7
K7
CK
CK_L
5A7<>
5A7<>
5A7<>
5A7<>
IN
IN
IN
IN
DDR_DQS5P
DDR_DQS5N
DDR_DQS7P
DDR_DQS7N
F3
G3
C7
B7
LDQS
LDQS_L
UDQS
UDQS_L
5A7>
5A7>
IN
IN
DDR_DM5
DDR_DM7
E7
D3
LDM
UDM
7C8<
7C8<
4A4>
4A4>
IN
IN
DDR1_CKE0
DDR1_CKE1
K9
J9
CKE0
CKE1
7B8<
7B8<
4B4>
4B4>
IN
IN
DDR1_CS0_L
DDR1_CS1_L
L2
L1
CS0_L
CS1_L
7B8<
7B8<
6B4<
4A4>
4A4>
4B3>
IN
IN
IN
DDR1_ODT0
DDR1_ODT1
DDR_RESET_L
K1
J1
T2
ODT0
ODT1
RESET_L
M8
H1
VREFCA
VREFDQ
L8
L9
ZQ0
ZQ1
M7
Z3
Z4
Z1
Z2
NC4/A15
NC5
NC6
NC7
NC8
A9
B3
E1
G8
J2
VSS0
VSS1
VSS2
VSS3
VSS4
4B3>
4B3>
4B3>
VREF_DDR1
ZQ0
ZQ1
NC4/A15
NC5
NC6
NC7
NC8
VSS0
VSS1
VSS2
VSS3
VSS4
2
OUT
R4C1
1K
7B8<
1 C4C5
0.1UF
2
1%
0402_R
0201_R
X5R
16V
10%
1 C4C2
0.1UF
2
1
6D8<
6D4<
6B8<
6B4<
7D8<
4C3>
7D4<
R7C3
0201_R
0201_R
X5R
16V
10%
1
7B8<
0.5%
240
R7C4
2
DDR_ZQ0_U28U2
1
2
0201_R
0.5%
DDR_ZQ1_U28U2
15 240
SNN_U28U2_Z3
SNN_U28U2_Z4
SNN_U28U2_Z1
SNN_U28U2_Z2
DDR_A<15..0>
IN
MEM_1A VDDQ
+1.35V_LP0
IN
A
1 C3C1
0.1UF
1 C3C2
0.1UF
1 C4C1
4.7UF
1 C4C3
0.1UF
1 C4C4
0.1UF
1 C4C8
0.1UF
1 C4C7
0.1UF
0402_R
X5R
6.3V
20%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0402_R
X5R
6.3V
20%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
2
2
2
MEM_1B VDDQ
2
2
2
2
1 C7C11
0.1UF
1 C7C10
0.1UF
1 C7C12
4.7UF
1 C8C46
0.1UF
1 C7C1
0.1UF
1 C7C9
0.1UF
1 C7C8
0.1UF
0402_R
X5R
6.3V
20%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0402_R
X5R
6.3V
20%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
2
E3
F7
F2
F8
H3
H8
G2
H7
43
45
41
47
40
44
42
46
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D7
C3
C8
C2
A7
A2
B8
A3
58
62
61
60
56
59
63
57
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
J8
M1
M9
P1
P9
T1
T9
7D5<>
6D1<>
4D8<>
5C7<>
6D4<>
BYTE 5
D
BYTE 7
C
B
A
2
2
2
2
2
2
TITLE
DDR3 X16 PAGE 2
Wed Mar 26 14:39:57 2014
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BI
MEM_1B VDD
1 C7C7
4.7UF
2
DDR_DQ<63..0>
MEM_1A VDD
1 C4C6
4.7UF
2
1
I58
I164
32D8<
5B3< 5A8<
32B8<
6A8<
33B2>
A5
DDP
A6
FOOTPRINT
A7
A8
A9
A10/AP
A11
A12/BC_L
A13
A14/NC
IN
IN
IN
6C4<
6C4<
6C4<
R7C5
1K
6
7
8
9
10
11
12
13
14
3
4
5
RANK 0
U7C1
BGA100_2
DDR3_X16
1.35V
A0
1866
A1
256MBIT
A2
HYNIX
A3
4
A4
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
DDR_A1<5..3>
IN
7C8<
7C8<
2
6D1<>
0
1
2
CHANNEL 1
BYTE 6
2
DDR_A<15..0>
IN
5C7<>
3
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
7
8
7
6
5
1 C9C6
4.7UF
0402_R
X5R
6.3V
(1.8V-3.3V)
AC14
R9B12
0402_R
1
PEX_MINI_PRSNT_L
TP_ULPI_DATA1
TP_ULPI_DATA2
PEX_GIGE_PRSNT_L
SNN_ULPI_DATA4
SNN_ULPI_DATA5
SNN_ULPI_DATA6
SNN_ULPI_DATA7
2
5%
0
R9C1
2
0402_R
5%
0
26D3>
26D3<
26D6>
26D6>
26D3<
+1.8V_VDDIO
C
1
R2C1
1
1%
10K
OUT
ULPI_CLK
ULPI_DIR
ULPI_NXT
ULPI_STP
SNN_DGPU_VDD_EN
SNN_DAP3_SCLK
AF17
AE17
AE15
AJ17
DAP3_DIN
DAP3_DOUT
DAP3_FS
DAP3_SCLK
GPIO_PV0
GPIO_PV1
AG17
AD15
GPIO_PV0
GPIO_PV1
P9
VDDIO_SDMMC1
L2
L3
L1
J8
L7
L8
L5
SDMMC1_DAT0
SDMMC1_DAT1
SDMMC1_DAT2
SDMMC1_DAT3
SDMMC1_CLK
SDMMC1_CMD
SDMMC1_WP_N
(1.8V-3.3V)
1%
C8B15
2
1
2
0402_R
X5R
6.3V
20%
4.7UF
C8B25
0.1UF
1
0201_R
X5R
16V
10%
0
1
2
3
SNN_SDMMC1_DAT<3..0>
SNN_SDMMC1_CLK
SNN_SDMMC1_CMD
SNN_CAMERA_SHUTTER
+1.8V_VDDIO
EMPTY
1
R8B22
0201_R
R8B18
2
1
1%
33.2
SDMMC1_COMP_PU
SDMMC1_COMP_PD
2
0201_R
J7
L6
SDMMC1_COMP_PU
SDMMC1_COMP_PD
K1
L4
CLK2_OUT
CLK2_REQ
E1
VDDIO_SDMMC3
V23
L10
KB_COL0
KB_COL1
KB_COL2
KB_COL3
KB_COL4
KB_COL5
KB_COL6
KB_COL7
AD30
AC28
AD28
AD31
AF28
AA27
AD29
AA25
KB_ROW0
KB_ROW1
KB_ROW2
KB_ROW3
KB_ROW4
KB_ROW5
KB_ROW6
KB_ROW7
KB_ROW8
KB_ROW9
KB_ROW10
KB_ROW11
KB_ROW12
KB_ROW13
KB_ROW14
KB_ROW15
KB_ROW16
KB_ROW17
W31
Y26
AF30
AC31
Y29
Y31
AB31
Y30
AA29
AA28
AA31
V28
Y27
AF29
AC30
Y25
AA26
AC29
IN
SNN_WF_RST_L
C8B8
4.7UF
25B7<>
25B7<
25B7<>
25A7>
BI
OUT
OUT
IN
1
SDMMC3_DAT<3..0>
SDMMC3_CLK
SDMMC3_CMD
SDMMC3_CD_L
1
32C5>
8B8<
IN
C8B7
2
0402_R
X5R
6.3V
20%
ISO3A1
4MIL
2
2
C8C45
4.7UF
23C7<>
BI
2
1%
33.2
2
A
SDMMC3_CLK_LB_OUT
SDMMC3_CLK_LB_IN
R8B15
SDMMC3_COMP_PU
1
0201_R
+1.8V_VDDIO
H2
H1
F1
G1
F5
F2
V24
F4
F3
E2
E5
0
1
2
3
R8B13
+VDDIO_SDMMC3
1
0201_R
SDMMC3_COMP_PD
33.2
1
2
0402_R
X5R
6.3V
20%
C8C44
0.1UF
+1.8V_VDDIO
2
OUT
OUT
J4
J3
CORE_PWR_REQ
CPU_PWR_REQ
Y28
V25
CLK_32K_IN
H3
SDMMC3_DAT0
SDMMC3_DAT1
SDMMC3_DAT2
SDMMC3_DAT3
SDMMC3_CLK
SDMMC3_CMD
SDMMC3_CD_N
SDMMC3_CLK_LB_OUT
SDMMC3_CLK_LB_IN
SDMMC3_COMP_PU
SDMMC3_COMP_PD
CLK_32K_OUT
J6
PWR_INT_N
V30
SYS_RESET_N
AA30
49.9
1%
2
1
0201_R
LCD_TE
HEAD_DET_T124_L
SNN_KB_ROW8
BR_UART1_TXD
BR_UART1_RXD
SNN_KB_ROW11
SNN_KB_ROW12
18D2<
26A2<
10D2<
25B7<
IN
+1.8V_VDDIO
D
IN
24A5>
IN
IN
IN
24A3>
25A7>
21C7>
OUT
30B4<
OUT
20B7<
OUT
IN
26C3<
21B7>
OUT
IN
22C7<>
22C7<>
IN
OUT
IN
31C2>
27C4<
24A3>
R3C3
100K
1%
0201_R
1
26B4<
26B7>
C
SNN_DGPU_PWRGD
SNN_NFC_PROG
IGPU_PWRGD
FAN_PWM
BD_ID_STRAP1
+1.05V_LP0_VDD_RTC
2
+1.8V_VDDIO
0.1UF
32B5>
IN
1
2
R3B7
1K
1%
0201_R
1
PWR_I2C_SCL
PWR_I2C_SDA
2
R3B6
1K
1%
0201_R
0201_R
X5R
16V
10%
EMPTY
R3C5
100K
1%
0201_R
1
1
CORE_PWR_REQ
CPU_PWR_REQ
CLK_32KHZ_PMU
2
31B1>
IN
VDDIO_SDMMC4
F29
F30
E28
H31
D31
E30
E29
F28
G31
E31
SDMMC4_DAT0
SDMMC4_DAT1
SDMMC4_DAT2
SDMMC4_DAT3
SDMMC4_DAT4
SDMMC4_DAT5
SDMMC4_DAT6
SDMMC4_DAT7
SDMMC4_CLK
SDMMC4_CMD
IN
31B7>
PMU_INT_L
IN
31B5>
IN
22A5<
IN
IN
18A7<
18A7>
IN
32A4>
SYS_RESET_L
OUT
BI
26A7<
31C6<
26A3<>
31C6<>
OUT
OUT
33C7<
33C7<
R8C3
100K
OWR
AA7
THERM_DP
THERM_DN
U28
U29
VPP_FUSE
R10 +1.8V_RUN_VPP_FUSE
THERMD_P
THERMD_N
C8B27
1
0201_R
X5R
16V
10%
JTAG_RTCK
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
J2
H6
H5
J1
J5
H4
JTAG_RTCK
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_L
TEST_MODE_EN
H7
TEST_MODE_EN
1
31B2>
2
1%
1
R8B20
IN
IN
IN
OUT
IN
IN
2
2
5%
0
XTAL_OUT
XTAL_IN
2
0402_R
X5R
6.3V
20%
1
R8B8
1
2
1 C8B2
12PF
22C7>
22C7>
22C7>
22C7<
22C7>
1%
0201_R
1
EMPTY
2
+1.8V_VDDIO
2M
L8B1
2
FB
4
30
0402_R
1
1700MA
1 C8B3
12PF
2 5%
NVIDIA
CONFIDENTIAL
4
TITLE
TK1: SDMMC/ULPI/JTAG/KB
0402_R
C0G
50V
2 5%
A
R8B14
10K
1
- GND -
12.000MHZ
10PF
50PPM
SMD4P_R
0402_R
C0G
50V
2
22A4<
22A4>
22A4>
22A4<
22A4>
22C7<
5%
Y8B1
3
R8B1
10K
1%
0201_R
+1.8V_LP0_AVDD_OSC_AP_F
D1
E3
E4
1 C8B9
4.7UF
5
23D7<
10K
0201_R
I246
R8B23
0201_R
0201_R
(1.8V - 3.3V)
SDMMC4_COMP_PU
SDMMC4_COMP_PD
B
SNN_OWR
0.1UF
AVDD_OSC
XTAL_IN
XTAL_OUT
EMPTY
TP_RESET_OUT_L
Y24
1%
6
1
CPU_OC_INT
Mon Apr 07 08:50:50 2014
7
20D2<
32D4<
SNN_GPU_PWR_REQ
2
(1.2V-1.8V)
F31
H30
H29
SDMMC4_COMP_PU
SDMMC4_COMP_PD
49.9
8
21D2<
33A2>
LID_CLOSED_L
RESET_OUT_N
(1.8V)
1
0201_R
X5R
16V
10%
SDMMC4_CLK
SDMMC4_CMD
R8C4
1
0201_R
SNN_SYS_CLK_REQ
22B6<
1
2
EN_VDD_SD
TP_AP_WP_L
AUDIO_LDO_EN
1%
0
1
2
3
4
5
6
7
R8C6
JD_MIC_T124_L
SNN_KB_COL6
SNN_KB_COL7
22C7<
0402_R
X5R
6.3V
20%
4.7UF
SDMMC3_WP_L
AB12
PWR_I2C_SCL
PWR_I2C_SDA
SDMMC4_DAT<7..0>
23D7<
23D7<>
C8C47
2
KB_COL0_AP
SNN_KB_COL1
SNN_KB_COL2
BD_ID_STRAP0
C9B19
1
0201_R
X5R
16V
10%
0.1UF
1
0201_R
X5R
16V
10%
22D2<
0402_R
X5R
6.3V
20%
4.7UF
2
VDD_RTC
(1.8V-3.3V)
+VDDIO_SDMMC3
2
0.1UF
(0.9-1.1V)
LAYOUT: MATCH SDMMC3_CLK
8A8<
C8C33
23A2<
1
1%
0201_R
EMPTY
TS_CLK
B
32C5>
2
C8B20
2
0201_R
X5R
16V
10%
0.1UF
VDDIO_SYS
VDDIO_SYS_2
1
1%
33.2
OUT
ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7
AK17
AL18
AG15
AL16
10K
26D6<
VDDIO_BB
TS_SPI_MOSI
TS_SPI_MISO
TS_SPI_SCK
TS_SPI_CS_L
SNN_DGPU_3P3_EN
2
0402_R
AF15
AH15
AD17
AJ15
AJ18
AH17
AK18
AL17
EN_VDD_BL
R2B9
2
0402_R
OUT
IN
OUT
OUT
C8B24
(1.8V-3.3V)
0201_R
X5R
16V
1
+1.8V_VDDIO
24A2<
1
SEC 1 OF 8
2 10%
2
+1.8V_VDDIO
2
1 C9C3
0.1UF
2 20%
1
3
U3C1
BGA
+1.8V_VDDIO
D
4
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
8
8
7
6
5
4
3
2
Q9A2
SI2305CDS
S23_R
P-MOSFET TO PREVENT BACKDRIVE ON AVDD_HDMI
2
U3C1
BGA
+3.3V_AVDD_HDMI_AP_GATED
2
D
32C4>
14D1<
26B4<
9C1<
C9B17
+1.2V_GEN_AVDD
IN
2
26B7>
26B7>
26B7>
26B7>
26B7<
26B7<
26A7>
26B7>
26B7>
26B7>
26B4<
26B4<
26B4>
26B7>
1
4.7UF
20%
C9B21
2
0402_R
X5R
6.3V
IN
IN
IN
IN
CSI_B_D0_N
CSI_B_D0_P
CSI_B_D1_N
CSI_B_D1_P
OUT
OUT
IN
IN
CSI_E_CLK_N
CSI_E_CLK_P
CSI_E_D0_N
CSI_E_D0_P
R9B11
B
2
R9B13
2
1
1%
1%
2
2
1%
0201_R
R9B9
1K
1%
0201_R
1
1
26A7<>
26B3<>
26B4<
26B4<
26A7<
26A7<
26B7<
26A7<
SNN_DSI_B_D0_N
SNN_DSI_B_D0_P
SNN_DSI_B_D1_N
SNN_DSI_B_D1_P
SNN_DSI_B_D2_N
SNN_DSI_B_D2_P
SNN_DSI_B_D3_N
SNN_DSI_B_D3_P
SNN_DSI_B_CLK_N
SNN_DSI_B_CLK_P
AH12
AJ12
AE12
AD12
AL12
AK12
AF12
AG12
AJ11
AH11
HSIC1_DATA
OUT
1
R9C2
HSIC1_STROBE
1
1
0201_R
X5R
16V
10%
CSI_E_CLK_N
CSI_E_CLK_P
CSI_E_D0_N
CSI_E_D0_P
DSI_A_D0_N
DSI_A_D0_P
DSI_A_D1_N
DSI_A_D1_P
DSI_A_D2_N
DSI_A_D2_P
DSI_A_D3_N
DSI_A_D3_P
DSI_A_CLK_N
DSI_A_CLK_P
DSI_B_D0_N
DSI_B_D0_P
DSI_B_D1_N
DSI_B_D1_P
DSI_B_D2_N
DSI_B_D2_P
DSI_B_D3_N
DSI_B_D3_P
DSI_B_CLK_N
DSI_B_CLK_P
CSI_DSI_TEST_OUT
CSI_DSI_RUP
CSI_DSI_RDN
C9B15
C9C5
1
0402_R
X5R
6.3V
20%
2
2
5%
0201_R
0
R9C5
(1.2V)
AC15
1
0.1UF
AF18
AE18
AH18
HSIC1_DATA
HSIC_STROBE
HSIC_REXT
AG18
AD18
HSIC2_DATA
HSIC2_STROBE
1%
1K
SNN_HSIC2_DATA
SNN_HSIC2_STROBE
USB 2.0 PORTS
PORT
AVDD_HDMI
AVDD_HDMI
AVDD_HDMI_PLL
2
AH1
0
AD5
0
AD6
1
AD4
1
AD3
2
AD2
2
AD1
AF5 HDMI_TXC_N
AF6 HDMI_TXC_P
HDMI_CEC
HDMI_INT
HDMI_RSET
HDMI_PROBE
AD7 HDMI_CEC
AC3 HDMI_INT
AF2 HDMI_RSET
AE1 SNN_HDMI_PROBE
DDC_SCL
DDC_SDA
C9B2
0.1UF
HDMI_TXD0N
HDMI_TXD0P
HDMI_TXD1N
HDMI_TXD1P
HDMI_TXD2N
HDMI_TXD2P
HDMI_TXCN
HDMI_TXCP
1
EXTERNAL DEBUG PORT MICRO AB
MINI PCIE
EXTERNAL TYPE A, SUPER SPEED PAIRED
8
7
0.1UF
DP_AUX_CH0_P
DP_AUX_CH0_N
AC6
AC5
14D2<
33A2>
5%
19B8<
1
+1.05V_RUN_AVDD_HDMI_PLL_AP
EMPTY
R2A7
0402_R
2
+1.2V_GEN_AVDD
2
IN
9D8<
14D1<
26B4<
32C4>
5%
0
R2A5
1M
1
G
S2
1
EMPTY
Q9A3
DMN2005K
EN_AVDD_HDMI_PLL
1
R2A11
0402_R
S23_R
R2A12
0402_R
2
GPIO_PH7
IN
10C3<>
EN_VDD_HDMI
IN
9D1<
5%
0
2
10A7<>
13A8<
5%
0
C
VGTH(MAX)=0.9V
1%
1K
5D2< 9C2< 14C1<
14C7<
32D5>
IN
C9B5
4.7UF
1
0.1UF
1
2
0201_R
X5R
16V
10%
1
0201_R
14C1<
14C7<
32D5>
1
0402_R
X5R
6.3V
20%
4.7UF
30
3.3V FOR DP MODE
L9B1
2
0402_R
FB
LVDS_TXD0_N
LVDS_TXD0_P
LVDS_TXD1_N
LVDS_TXD1_P
LVDS_TXD2_N
LVDS_TXD2_P
LVDS_TXD3_N
LVDS_TXD3_P
LVDS_TXD4_N
LVDS_TXD4_P
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
26C3<
26D3<
26C6<
26C6<
26C6<
26C6<
26C3<
26C3<
26C3<
26C3<
B
EDP_HPD
SNN_LVDS0_PROBE
9C4<
1
0402_R
X5R
6.3V
20%
4.7UF
LVDS_RSET
5D2<
IN
C9B9
+3.3V_RUN
1
C9B6
2
0201_R
X5R
16V
10%
C9B1
0.1UF
+AVDD_LVDS0_PLL_AP_F
C9B4
2
1
0402_R
X5R
6.3V
20%
1700MA
AC2
AK3
AL3
IN
5%
0
13B7<
13B7<>
OUT
BI
0201_R
X5R
16V
10%
AF1
2
IN
2
1K
26C6>
C2B1 1
.01UF
1%
R9B7
DP_AUX_P
DP_AUX_N
26D6<>
26D6<>
BI
BI
0201_R
X5R
10V
10%
2
+1.8V_VDDIO_LP0_OFF
(1.8V)
AVDD_PLL_UTMIP
AB15
+1.8V_RUN_AVDD_PLL_UTMIP_AP_F
1
30
1700MA
2
C9C1
1
0.1UF
2
0201_R
X5R
16V
10%
C9B18
4.7UF
L9B2
2
0402_R
FB
1
0402_R
X5R
6.3V
20%
+3.3V_RUN
+3.3V_LP0
32D3<
(3.3V)
AVDD_USB
USB0_DN
USB0_DP
USB1_DN
USB1_DP
USB2_DN
USB2_DP
AH20
AJ20
AF20
AG20
AE20
AD20
USB_VBUS_EN0
USB_VBUS_EN1
AB1
AC1
USB0D_N
USB0D_P
USB1D_N
USB1D_P
USB2D_N
USB2D_P
C9B20
0.1UF
1
2
0201_R
X5R
16V
10%
USB_VBUS_EN0
USB_VBUS_EN1
AL20
USB0_ID
AK20
AL19 USB_REXT
1
C9B23
BI
BI
BI
BI
BI
BI
4.7UF
17C5<
17C5<
15C3<>
15C3<>
17B7<>
17B7<>
BI
BI
17C8<
17B8<
1
0402_R
X5R
6.3V
20%
30C5>
26D6<
23A2<
22D8<
18D2<
2
IN
2
IN
+3.3V_RUN
+3.3V_LP0
R9C6
0
22D2<
5%
0402_R
19D2<
18D2<
17D2<
15D1<
14D1<
13D1<
10D2<
30A3>
IN
A
+3.3V_LP0
1
+1.8V_VDDIO_LP0_OFF
30A6>
IN
+1.8V_VDDIO_LP0_OFF
EMPTY
USB0_VBUS
R9C4
17B1>
2
C2C1
1UF
TITLE
1
0402_R
X5R
16V
10%
TK1: CSI/DSI/HDMI/USB
1%
1K
Wed May 07 10:30:23 2014
5
30D1<
AC12
2
I262
6
EMPTY
0201_R
1
(1.8V)
DP_HPD
LVDS0_RSET
LVDS0_PROBE
D3
13C7<>
13D5>
R9B8
1
2
BI
IN
0201_R
0
1
2
13C8<
13C8<
OUT
OUT
2
C9B7
+1.05V_RUN
2
0402_R
D
0
+1.05V_RUN_AVDD
2
AJ2
AJ3
AG3
AG4
AG5
AG6
AG1
AG2
AF3
AF4
D
S
3
2
G 1
13D8<
13D8<
R2A9
5%
0402_R
+1.05V_RUN_AVDD
AL4
LVDS0_TXD0N
LVDS0_TXD0P
LVDS0_TXD1N
LVDS0_TXD1P
LVDS0_TXD2N
LVDS0_TXD2P
LVDS0_TXD3N
LVDS0_TXD3P
LVDS0_TXD4N
LVDS0_TXD4P
1
13A8<
9C1<
10A7<>
33A2>
19B8<
14C8<
9D2<
14C1<
14D2<
IN
P-MOSFET TO POWER GATE AVDD_HDMI_PLL
R2A6
2+1.05V_RUN
IN 9D1< 14C1< 14C8<
0402_R
Q9A1
SI2329DS
S23_R
OUT
OUT
1
1
1.05V_RUN_AVDD_HDMI_PLL_AP_EN_L
(1.05V)
AVDD_LVDS0_PLL
1
EN_VDD_HDMI
2
5%
0
EN_AVDD_HDMI
VGTH(MAX)=0.9V
5%
R2A10
0402_R
S23_R
0
0402_R
X5R
6.3V
20%
2.2UF
1
Q9A4
DMN2005K
2
0402_R
HDMI_TXD_N<2..0>
HDMI_TXD_P<2..0>
AC7 HDMI_DDC_SCL
AC8 HDMI_DDC_SDA
AJ1
R2A4
EMPTY
3.3V_RUN_AVDD_HDMI_AP_EN_L
D3
1
C9B3
2
0201_R
X5R
16V
10%
(1.05V)
AVDD_LVDS0_IO
USB0_VBUS
USB0_ID
USB_REXT
USAGE
1
EMPTY
+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE
(1.05V.. 1.2V?)
VDDIO_HSIC
0201_R
X5R
16V
10%
5%
0402_R
1
0402_R
X5R
6.3V
20%
4.7UF
R2A8
1M
S2
AA9
AA10
CAM_I2C_SCL
CAM_I2C_SDA
CAM_MCLK
C8B22
(3.3V)
VDDIO_CAM
GPIO_PCC1
GPIO_PCC2
GPIO_PBB0
GPIO_PBB3
GPIO_PBB4
GPIO_PBB5
GPIO_PBB6
GPIO_PBB7
2
+3.3V_RUN
S
D
2
3
G 1
1
G
AVDD_PLL_UD2DPD
AL5
HSIC1_DATA_R
HSIC1_STROBE_R
HSIC_REXT
1
2
0
0201_R
AJ6
AL7
AK5
AK6
AH6
AH5
AL6
AJ5
AF8
AG8
2
5%
R9C3
CSI_B_D0_N
CSI_B_D0_P
CSI_B_D1_N
CSI_B_D1_P
+1.2V_GEN_AVDD
2
0201_R
OUT
AC11
CAM1_MCLK
OUT
CSI_A_D0_N
CSI_A_D0_P
CSI_A_D1_N
CSI_A_D1_P
CSI_A_CLK_N
CSI_A_CLK_P
(1.8V - 3.3V)
C9B13
CAM_I2C_SCL
CAM_I2C_SDA
OUT
BI
(1.2V)
1
0201_R
X5R
16V
10%
0.1UF
1
SEC 2 OF 8
AVDD_DSI_CSI 1
AVDD_DSI_CSI 2
AVDD_DSI_CSI 3
1
0402_R
X5R
6.3V
20%
4.7UF
26B4<
AK11
AL11
AD14
AE14
AL15
AK15
AG14
AF14
AJ14
AH14
CAM1_GPIO
CAM2_GPIO
CAM2_MCLK
CAM_RST_L
CAM_FLASH
CAM1_PWDN
CAM2_PWDN
CAM1_AF_PWDN
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
26A7<
26B3<>
SNN_DSI_A_D0_N
SNN_DSI_A_D0_P
SNN_DSI_A_D1_N
SNN_DSI_A_D1_P
SNN_DSI_A_D2_N
SNN_DSI_A_D2_P
SNN_DSI_A_D3_N
SNN_DSI_A_D3_P
SNN_DSI_A_CLK_N
SNN_DSI_A_CLK_P
0.1UF
CAD NOTE:
PLACE NEAR TEGRA
A
AJ8
AH8
AF9
AG9
2
R9B10
1K
26B4<
26B7<>
C9B14
4.7UF
+1.8V_RUN_CAM
IN
0201_R
2
AK9
AL9
AE9
AD9
AE11
AD11
TP_CSI_DSI_TEST_OUT AL10
DSI_CSI_RUP
AF11
DSI_CSI_RDN
AG11
1
453
0201_R
49.9
0201_R
X5R
16V
10%
AK8
AL8
AJ9
AH9
C
26B4<
32C5>
1
0.1UF
CSI_A_D0_N
CSI_A_D0_P
CSI_A_D1_N
CSI_A_D1_P
CSI_A_CLK_N
CSI_A_CLK_P
IN
IN
IN
IN
OUT
OUT
AK14
AL13
AL14
C8B26
1
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
9
8
7
6
5
4
3
2
1
+3.3V_LP0
U3C1
BGA
D
0.1UF
(1.8V-3.3V)
U10
C8B23
4.7UF
26A4>
26A7<
26A4>
26A7<
C
1
0402_R
X5R
6.3V
20%
0.1UF
R8B10
1K
2
R8B11
1K
1%
0201_R
1%
0201_R
1
26A7<
22C4<>
22C4<
20B7<
20B7<>
18D3<
18D3<>
26D3<>
18A6<
26D3<
SNN_UART3_RXD
SNN_UART3_TXD
SNN_UART3_CTS_L
SNN_UART3_RTS_L
M3
M2
R8
R9
UART3_RXD
UART3_TXD
UART3_CTS_N
UART3_RTS_N
TP_DAP4_DIN
TP_DAP4_DOUT
TP_DAP4_FS
TP_DAP4_SCLK
P3
P5
P1
N1
DAP4_DIN
DAP4_DOUT
DAP4_FS
DAP4_SCLK
18A6<>
26A3<>
1
1
R8B12
0201_R
2
CLK3_OUT_R
5%
C8C43
2
4.7UF
25D7<
OUT
20C8<>
OUT
BI
BI
BI
BI
BI
BI
BI
P7
M7
CLK3_OUT
CLK3_REQ
R7
P2
M10
P8
M9
M4
M5
GPIO_PU0
GPIO_PU1
GPIO_PU2
GPIO_PU3
GPIO_PU4
GPIO_PU5
GPIO_PU6
P6
M6
+1.8V_VDDIO
BI
B
20B7<
GPIO_PU0
GPIO_PU1
GPIO_PU2
GPIO_PU3
GPIO_PU4
GPIO_PU5
GPIO_PU6
GEN1_I2C_SCL
GEN1_I2C_SDA
OUT
OUT
TP_DAP1_DIN
SATA_LED
TP_DAP1_FS
TP_DAP1_SCLK
DAP_MCLK1
2
SATA_PWR_EN_T124
OUT
0201_R
X5R
16V
10%
DAP_MCLK1_R
2
5%
22
20C8>
20C8<
20C8<>
DAP2_SCLK
R3C6
0201_R
K31
1
0.1UF
IN
OUT
OUT
DAP2_DIN
DAP2_DOUT
DAP2_FS
R3C4
1
DAP2_SCLK_R
2
0201_R
GEN1_I2C_SCL
GEN1_I2C_SDA
(1.8V-3.3V)
C8C41
1
0402_R
X5R
6.3V
20%
1
16A5<
VDDIO_AUDIO
H28
L28
J28
P31
DAP1_DIN
DAP1_DOUT
DAP1_FS
DAP1_SCLK
L29
M31
DAP_MCLK1
DAP_MCLK1_REQ
L30
J29
R30
M29
DAP2_DIN
DAP2_DOUT
DAP2_FS
DAP2_SCLK
AA8
AC4
SPDIF_IN
SPDIF_OUT
5%
22
13A8<
9D1<
9C1<
BI
C9B24
1
0402_R
X5R
6.3V
20%
4.7UF
EN_VDD_HDMI
SNN_EN_BAT_SMB
A
+3.3V_LP0
17D2<
15D1<
30A3>
14D1<
22D2<
13D1<
19D2<
9A2<
D
+3.3V_LP0
IN
+1.8V_VDDIO
+1.8V_VDDIO
(2.8V-3.3V)
Y10
VDDIO_HV
C8B10
2
(1.8V-3.3V)
UART2_RXD
UART2_TXD
UART2_CTS_N
UART2_RTS_N
26B3<>
26B3<>
26B3<>
26A3<>
26A3<>
26A3<>
26A3<>
2
VDDIO_UART
0201_R
X5R
16V
10%
0
+1.8V_VDDIO
2
18D2<
1
L9
M8
M1
P4
OUT CLK3_OUT
SNN_CLK3_REQ
26A4<
C8B18
2
UART2_RXD
UART2_TXD
UART2_CTS_L
UART2_RTS_L
IN
OUT
IN
OUT
1
0201_R
X5R
16V
10%
1
SEC 3 OF 8
+1.8V_VDDIO
2
C9B22
2
VDDIO_GMI 1
VDDIO_GMI 2
U9
V10
GPIO_PB0
GPIO_PB1
GPIO_PC7
GPIO_PG0
GPIO_PG1
GPIO_PG2
GPIO_PG3
GPIO_PG4
GPIO_PG5
GPIO_PG6
GPIO_PG7
GPIO_PH0
GPIO_PH1
GPIO_PH2
GPIO_PH3
GPIO_PH4
GPIO_PH5
GPIO_PH6
GPIO_PH7
GPIO_PI0
GPIO_PI1
GPIO_PI2
GPIO_PI3
GPIO_PI4
GPIO_PI5
GPIO_PI6
GPIO_PI7
GPIO_PJ0
GPIO_PJ2
GPIO_PJ7
GPIO_PK0
GPIO_PK1
GPIO_PK2
GPIO_PK3
GPIO_PK4
GPIO_PK7
U4
V9
U1
V2
V6
Y7
AA5
Y3
AA3
Y8
V3
Y6
U3
AA4
V8
R5
R4
U8
U2
Y5
AA6
V1
V7
Y9
U7
R1
Y4
U6
W1
V4
AA1
R3
Y1
R2
T1
V5
GEN2_I2C_SCL
GEN2_I2C_SDA
Y2
AA2
0.1UF
1
2
0201_R
X5R
16V
10%
UART4_RXD
UART4_CTS_L
TP_KBC_IRQ_L
LCD_LR
LCD_UD
MODEM_SAR0
GPIO_PG3
SPI4_CS3_L
SPI4_SCK
SPI4_MOSI
SPI4_MISO
TP_KBL_PWM
LCD_BL_PWM
LCD_BL_EN
CODEC_IRQ_L
TP_GPIO_PH5
TP_GPIO_PH6
GPIO_PH7
GPIO_PI0
AP_FORCE_RECOVERY_L
TP_GPIO_PI2
SPI4_CS0_L
SNN_GPIO_PI4
SNN_GPIO_PI5
SDMMC2_COMP_PU
SDMMC2_COMP_PD
18B8>
18B8>
24D1>
24D1>
24D1>
24D1>
24B2>
23A4<
24B2>
23A4<
24B2>
23A7>
24B2>
OUT
OUT
26C6<
26C6<
IN
20B7>
BI
OUT
IN
9C1<
24C5>
24D5>
OUT
23B7<
IN
18A3>
1
SNN_PG_OC_L
EMPTY
GPIO_X1_AUD
GPIO_X3_AUD
GPIO_X4_AUD
GPIO_X5_AUD
GPIO_X6_AUD
GPIO_X7_AUD
GPIO_W2_AUD
GPIO_W3_AUD
P29
M30
R28
R31
N31
P28
M28
J30
BD_ID_STRAP2
TP_ALS_IRQ_L
BD_ID_STRAP3
DVFS_PWM
DVFS_CLK
P30
R29
DVFS_PWM
DVFS_CLK
SNN_GPS_IRQ_L
SNN_COMPASS_DRDY
WF_EN
SNN_NFC_IRQ_L
33A2>
18D2<
22D2<
8D1<
+1.8V_VDDIO
IN
C
R3B3
2
OUT
18C7<
22D7>
OUT
OUT
26D3<
26D3<
OUT
OUT
26D3<
18C7<
24D5>
1%
10K
+3.3V_LP0
+1.8V_VDDIO
24C5>
2
R2B6
1K
2
1%
0201_R
22D7>
1
GEN2_I2C_SCL_3.3V
GEN2_I2C_SDA_3.3V
SDMMC2_COMP_PU
SDMMC2_COMP_PD
20D2<
23A2<
STRAPS
0402_R
UART4_TXD
TP_GPIO_PK0
TS_SHDN_L
GPIO_PK2
TP_GPIO_PK3
TS_RESET_L
UART4_RTS_L
21D2<
24A2<
22D7<
22D7<
OUT
OUT
BI
BI
OUT
OUT
OUT
IN
TEMP_ALERT_L
SNN_GPIO_PI7
AC_OK_AP_L
22B6<
25B7<
1
IN
IN
SNN_GPIO_PH3
22C7<
26A2<
0402_R
X5R
6.3V
20%
4.7UF
R2B8
1K
2
1%
0201_R
1
R9B4
1K
2
1%
0201_R
1
B
R9B6
1K
1%
0201_R
1
OUT
BI
+1.8V_VDDIO
EMPTY
U5
R6
32D4<
C8B12
R8B17
1
1
2
0201_R
R8B16
0201_R
EMPTY
26D6<
26D6<>
EMPTY
2
1%
49.9
1%
49.9
IN
24A3>
IN
24A3>
OUT
15C1<
BI
OUT
33C7<
33C7<
TP_TOUCH_IRQ_L
A
I204
SET E_OD PAD = 1 WHEN PU VALUE DIFFERS FROM VDD SOURCE FOR GEN2 I2C
TITLE
TK1: UART/GMI/DAP/SPI
Mon Apr 07 08:50:54 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
10
8
D
34A2>
11A1<
32B8<
7
6
1 C9B10
0.1UF
1 C8C9
0.1UF
1 C9C4
0.1UF
1 C9C2
0.1UF
1 C8C2
4.7UF
1 C8B29
4.7UF
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
2
2
1 C8C19
4.7UF
0402_R
X5R
6.3V
2
1 C9B11
4.7UF
2
1 C8C24
4.7UF
0402_R
X5R
6.3V
2 20%
0402_R
X5R
6.3V
2 20%
2
1 C9B12
4.7UF
1 C9B8
4.7UF
0402_R
X5R
6.3V
2 20%
0402_R
X5R
6.3V
2 20%
2 20%
2
1 C9B16
4.7UF
0402_R
X5R
6.3V
2 20%
C
35C2>
11B1<
+VDD_CPU_AP
IN
C8C25 1
0.1UF
C8C32 1
0.1UF
C8C26 1
0.1UF
C8C39 1
0.1UF
C8C29 1
0.1UF
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
2
B
2
2
2
C8C37 1
0.1UF
C8C40 1
0.1UF
C8C23 1
0.1UF
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
0201_R
X5R
16V
10%
2
EMPTY
2
EMPTY
2
C8C34
1
0.1UF
0201_R
X5R
16V
10%
2
EMPTY
2
EMPTY
C8C13 1
4.7UF
C8B33 1
4.7UF
C8B32 1
4.7UF
C8C35 1
0.1UF
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
0201_R
X5R
16V
10%
2
2
2
2
EMPTY
1 C8C50
22UF
1 C8C14
4.7UF
0805_R
X5R
0402_R
X5R
6.3V
6.3V
EMPTY2 20%
2 20%
1 C8C21
4.7UF
0402_R
X5R
6.3V
2 20%
4
3
1 C8C6
4.7UF
0402_R
X5R
6.3V
2 20%
1 C8C5
4.7UF
0402_R
X5R
6.3V
1 C8C42
4.7UF
0402_R
X5R
6.3V
2 20%
2 20%
A
1
SEC 7 OF 8
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA22
K12
K14
K15
K17
K18
K20
K21
M12
N12
P12
R12
T12
U12
V12
W12
Y12
Y22
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
R23
L23
L24
M13
M14
M15
M16
M17
M18
M19
M20
M22
M23
M24
M25
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N25
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R17
R18
R19
R20
R21
R22
L25
L26
M26
L27
M27
P23
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
D
VDD_GPU 1
VDD_GPU 2
VDD_GPU 3
VDD_GPU 4
VDD_GPU 5
VDD_GPU 6
VDD_GPU 7
VDD_GPU 8
VDD_GPU 9
VDD_GPU 10
VDD_GPU 11
VDD_GPU 12
VDD_GPU 13
VDD_GPU 14
VDD_GPU 15
VDD_GPU 16
VDD_GPU 17
VDD_GPU 18
VDD_GPU 19
VDD_GPU 20
VDD_GPU 21
VDD_GPU 22
VDD_GPU 23
VDD_GPU 24
VDD_GPU 25
VDD_GPU 26
VDD_GPU 27
+VDD_GPU_AP
AA23
U17
U18
U19
U20
V13
V14
V15
V16
V17
V18
V19
V20
W13
W14
W15
W16
W17
W18
W19
W20
W21
Y19
Y20
Y23
U21
V21
1 C8C30
0.1UF
0201_R
X5R
16V
1 C9C9
0.1UF
0201_R
X5R
16V
IN
1 C8C27
0.1UF
11B1<
1 C8C3
4.7UF
0201_R
X5R
16V
0402_R
X5R
6.3V
34D2>
1 C8C4
4.7UF
0402_R
X5R
6.3V
2 10%
2 10%
2 10%
2 20%
2 20%
1 C8C22
4.7UF
1 C8B34
4.7UF
1 C8B35
4.7UF
1 C8C17
4.7UF
1 C8C15
4.7UF
0402_R
X5R
6.3V
2 20%
0402_R
X5R
6.3V
2 20%
0402_R
X5R
6.3V
0402_R
X5R
6.3V
2 20%
2 20%
EMPTY
0402_R
X5R
6.3V
2 20%
C
EMPTY
1
+VDD_GPU_AP
2
IN
11D4<
34D2>
1%
1K
VDD_GPU_SENSE
VVDD_GPU_PROBE
GND_GPU_SENSE
U26
U25
U27
VDD_GPU_SENSE_P
VVDD_GPU_PROBE
OUT
33C3<
1
2
R8C5
0
B
+0.05R
0201_R
EMPTY
1
VDD_GPU_SENSE_N
1
R5E6
0402_R
VDD_CPU_SENSE
VVDD_CPU_PROBE
GND_CPU_SENSE
R26
R25
R27
OUT
1
EMPTY
VDD_CPU_SENSE_P
VVDD_CPU_PROBE
33C3<
EMPTY
2
1%
1K
R5E8
0402_R
+VDD_CPU_AP IN
2
11C8<
35C2>
11D8<
32B8<
1%
1K
OUT
33C3<
OUT
33C3<
1
2
R8C8
0
+0.05R
0201_R
EMPTY
1
VDD_CPU_SENSE_N
1
R5E9
0402_R
VDD_CORE_SENSE
VVDD_CORE_PROBE
GND_CORE_SENSE
P25
P27
P26
EMPTY R6E3
2
1%
1K
VVDD_CORE_PROBE
1
EMPTY
VDD_CORE_SENSE_P
0402_R
+VDD_CORE
2
IN
34A2>
1%
1K
OUT
33B3<
OUT
33B3<
A
1
2
R8C7
0
+0.05R
0201_R
EMPTY
1
VDD_CORE_SENSE_N
1
R6E2
0402_R
Mon Apr 07 08:50:56 2014
6
5
4
TITLE
2
1%
1K
7
R5E7
0402_R
I121
8
2
U3C1
BGA
+VDD_CORE
IN
5
EMPTY
TK1: POWER
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
11
8
7
6
5
4
3
2
1
U3C1
BGA
A2
AB21
L16
L17
L18
L19
N2
N4
N7
N10
N11
N28
AB25
N30
P11
R11
R13
R14
R15
R16
T2
T4
T7
AB28
T10
T11
T13
T14
T15
T16
T17
T18
T19
T20
AB30
T21
T22
T25
T28
T30
U11
U13
U14
U15
U16
AC9
U22
V11
V22
W2
W4
W7
W10
W11
W22
W25
AD8
W28
W30
Y13
Y14
Y15
Y16
Y17
Y18
AK2
AE8
AB11
AB14
P24
R24
T31
V27
AE23
L22
AE2
AE4
AE7
AE10
A30
AE13
K30
L13
L14
L15
D
HS3C1
HEATSINK
50MMX67MM_ELLIPTIC_12V
FANSINK
C
MECH
I344
M1A1
BRD_MOUNT
BRDMNT2
B
1
2
3
4
1
2
3
4
1
5
2
6
3
7
4
8
5
6
7
8
M5E1
BRD_MOUNT
BRDMNT2
1
2
3
4
1
5
2
6
3
7
4
8
5
6
7
8
I346
I345
M1E1
BRD_MOUNT
BRDMNT2
M5A1
BRD_MOUNT
BRDMNT2
1
5
2
6
3
7
4
8
5
6
7
8
1
2
3
4
I355
1
5
2
6
3
7
4
8
5
6
7
8
I350
A
1
SEC 8 OF 8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
10
100
101
102
103
104
105
106
107
108
109
11
110
111
112
113
114
115
116
117
118
119
12
120
121
122
123
124
125
126
127
128
129
13
130
131
132
133
134
135
136
137
138
139
14
140
141
142
143
144
145
146
147
148
149
15
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
16
17
18
19
2
20
96
97
98
99
AE16
AE19
AE22
AE28
AE30
AH2
AH4
AH7
AH10
AB2
AH13
AH16
AH19
AH22
AH25
AH28
AH30
AK1
AK4
AK7
AB4
AK10
AK13
AK16
AK19
AK22
AK25
AK28
AK31
AL2
AL30
AB7
B1
B4
B7
B10
B13
B16
B19
B22
B25
B28
AB10
B31
D2
D4
D7
D10
D13
D16
D19
D22
D25
AB13
D28
D30
G2
G4
G7
G10
G13
G16
G19
G22
AB16
G24
G25
G28
G30
H8
H24
J23
K2
K4
K7
AB19
K13
AE24
K19
K22
AE25
K28
GND 21
GND 22
GND 23
GND 24
GND 25
GND 26
GND 27
GND 28
GND 29
GND 3
GND 30
GND 31
GND 32
GND 33
GND 34
GND 35
GND 36
GND 37
GND 38
GND 39
GND 4
GND 40
GND 41
GND 42
GND 43
GND 44
GND 45
GND 46
GND 47
GND 48
GND 49
GND 5
GND 50
GND 51
GND 52
GND 53
GND 54
GND 55
GND 56
GND 57
GND 58
GND 59
GND 6
GND 60
GND 61
GND 62
GND 63
GND 64
GND 65
GND 66
GND 67
GND 68
GND 69
GND 7
GND 70
GND 71
GND 72
GND 73
GND 74
GND 75
GND 76
GND 77
GND 78
GND 79
GND 8
GND 80
GND 81
GND 82
GND 83
GND 84
GND 85
GND 86
GND 87
GND 88
GND 89
GND 9
GND 90
GND 91
GND 92
GND 93
GND 94
GND 95
8
7
6
5
4
C
B
A
TITLE
TK1: GND
I357
Mon Apr 07 08:50:57 2014
D
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
12
8
7
6
5
9C4<
4
HDMI_INT
OUT
1
R10B2
0402_R
3
+3.3V_LP0
HDMI_HPD
1%
R1C1
22K
1
EMPTY
9C3>
9C3>
IN
IN
30A3>
2
32D4<
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
2
1
0
0
IN
IN
HDMI_TXC_N
CR1C1
RCLAMP_0524P
SLP2510P8_R
10
1
CR1C1
RCLAMP_0524P
SLP2510P8_R
2
9
7
4
3
CR1B1
RCLAMP_0524P
SLP2510P8_R
5
6
EMPTY
C
7
4
3
+3.3V_LP0
15D1<
14D1<
10D2<
9A2<
IN
+3.3V_LP0
26A2<
31D5<
20D2<
30D1<
17D2<
29D2<
34D2<
16D2<
29C1>
33B7<
15B7<
27A2<
IN
+5V_SYS
D
3
+3.3V_LP0
1
2
S
Q10B1
G 1 FDV301N
S23_R
3 HDMI_CEC_L
D
D1D0+
GND
D0CK+
GND
CKCEC
RSVD
SCL
SDA
GND
+5V
HPD
C
I198
L10B3
1
1200MA
2
0402_R
FB
120
1 C10B7
10PF
S323_R
I80
1%
0402_R
D1+
GND
GND
CR10C1
BAS70W
3
2
GND
D2-
20
21
22
23
+3.3V_LP0
HDMI_CEC
R10C1
32.4K
3
I189
R10B3
162K
1%
0402_R
2
2
9
D2+
EMPTY
I187
1
BI
10
1
EMPTY
I184
HDMI_CEC_CON
CR1B1
RCLAMP_0524P
SLP2510P8_R
5
6
EMPTY
I183
2
9C4<>
17D2<
+5V_SYS
CON_HDMI_A
SMT_G_R
1
9C4>
18D2<
TYPE A
HDMI_TXD_P<2..0>
HDMI_TXD_N<2..0>
HDMI_TXC_P
19D2<
J1C1
0402_R
C0G
50V
5%
2
9C4>
22D2<
1 C10B6
330PF
5%
0402_R
D
1
2
1K
2
2
0402_R
C0G
50V
2 5%
1
R1B9
1.8K
2
HDMI_CEC_A_PU
5%
0402_R
9C4>
1
HDMI_DDC_SCL
IN
120
1
1200MA
L10B2
2
0402_R
HDMI_DDC_SCL_CON
FB
B
B
EMPTY
1 C1B3
4.7PF
0402_R
C0G
50V
2
2 +/-0.25PF
R1B8
1.8K
5%
0402_R
9C4<>
BI
1
HDMI_DDC_SDA
120
1
1200MA
L10B1
2
0402_R
HDMI_DDC_SDA_CON
FB
EMPTY
1 C1B2
4.7PF
+5V_SYS
0402_R
C0G
50V
2 +/-0.25PF
1 C10B5
10UF
U1B4
0603_R
X5R
6.3V
2 20%
6
A
10A7<>
9D1<
9C1<
IN
EN_VDD_HDMI
1
R1B7
2
0402_R
SON7_R
RT9728AHGQW
VOUT
1
FAULT#
3
VIN
4
EN
5
7
GND
GNDPAD
120
+5V_HDMI
1
1200MA
L1B1
2
0402_R
+5V_HDMI_CON
FB
100
ILIM
A
1 C1B1
.1UF
HDMI_FAULT_L
5%
0402_R
X7R
16V
2 HDMI_ILIM
2 10%
2
I97
R10B1
60.4K
1%
0402_R
1
EN
VIH MIN 1.1V
VIL MAX 0.66V
TITLE
MINIMUM 400MA
FOR HDMI TO VGA DONGLE
HDMI TYPE A CONN
Wed Mar 26 14:40:02 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
13
8
7
6
5
4
3
2
1
U3C1
BGA
D
+3.3V_LP0
+3.3V_LP0
1
SEC 4 OF 8
2
C9C17
4.7UF
(3.3V)
C9C18
2
1
0402_R
X5R
6.3V
20%
2
0201_R
0.1UF X5R
16V
C9C1510%
14C1<
33A2>
9D2< 9D1<
19B8<
+1.05V_RUN
IN
2
FB
L9C3
0402_R
0402_R
X5R
16V
10%
C9C19
1
R9C9
100
C
2
1
1
0.1UF
1%
2.49K
9C4<
9C2<
5D2<
IN
C8B11
4.7UF
(1.05V)
AVDDIO_PEX
AVDDIO_PEX
AVDDIO_PEX
AB17
AC17
AC18
DVDDIO_PEX
DVDDIO_PEX
DVDDIO_PEX
AB20
AC20
AB18
(1.05V)
(3.3V)
AL28
(3.3V)
AL29
HVDD_PEX
SATA_L0_TXP
SATA_L0_TXN
SATA_L0_RXP
SATA_L0_RXN
AG27
AF27
AL25
SATA_TESTCLKP
SATA_TESTCLKN
SATA_TERMP
1
C9C13
(1.05V)
1
2
0402_R
X5R
6.3V
20%
C8B13
0.1UF
U24
U23
U31
V31
V26
V29
DIRECTDC_CLK
DIRECTDC_IN
DIRECTDC_OUT0
DIRECTDC_OUT1
DIRECTDC_OUT2
DIRECTDC_OUT3
J25
H27
F26
AD27
F27
AD25
AB22
J27
AD24
J24
U30
H25
H26
J26
K25
AD23
AD26
AC23
AC24
AC25
AA24
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
0201_R
X5R
16V
10%
SNN_DIRECTDC_CLK
SNN_DIRECTDC_IN
SNN_DIRECTDC_OUT0
SNN_DIRECTDC_OUT1
SNN_DIRECTDC_OUT2
SNN_DIRECTDC_OUT3
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
18D2<
17D2<
C9C8
15D1<
0402_R
X5R
6.3V
20%
(1.05V)
AG31
AVDD_PLL_EREFE
C9C10
1
2
2
(1.05V)
L31
J31
AVDD_PLL_X
AVDD_PLL_CG
2
C9C20
2
1
1
FB
1
C9C11
1
2
C9C21
USB3_TX0N
USB3_TX0P
USB3_RX0N
USB3_RX0P
PEX_USB3_TX1N
PEX_USB3_TX1P
PEX_USB3_RX1N
PEX_USB3_RX1P
PEX_TX2N
PEX_TX2P
PEX_RX2N
PEX_RX2P
AJ21
AH21
AL21
AK21
AG21
AF21
AL23
AK23
AJ23
AH23
AE21
AD21
PEX_TX2_C_N
PEX_TX2_C_P
PEX_RX2_N
PEX_RX2_P
PEX_TX3N
PEX_TX3P
PEX_RX3N
PEX_RX3P
AG23
AF23
AK24
AL24
SNN_PEX_TX3_N
SNN_PEX_TX3_P
SNN_PEX_RX3_N
SNN_PEX_RX3_P
PEX_TX4N
PEX_TX4P
PEX_RX4N
PEX_RX4P
AH26
AJ26
AL26
AK26
PEX_TX4_N
PEX_TX4_P
PEX_RX4_N
PEX_RX4_P
OUT
OUT
IN
IN
15C7<
15C7<
15C7>
15C7>
PEX_CLK1P
PEX_CLK1N
AF26
AG26
PEX_CLK1_P
PEX_CLK1_N
OUT
OUT
15D7<
15D7<
PEX_CLK2P
PEX_CLK2N
AC26
AC27
PEX_CLK2_P
PEX_CLK2_N
OUT
OUT
19C7<
19C7<
PEX_REFCLKP
PEX_REFCLKN
AH24
AJ24
PEX_TESTCLKN
PEX_TESTCLKP
PEX_TERMP
AF24
AG24
AL22
OUT
OUT
IN
IN
16C8<
16C8<
16B8>
16B8>
OUT
OUT
IN
IN
16B8<
16B8<
16A8>
16A8>
L9C1
2
30
0402_R
30
0402_R
1
+1.05V_RUN
1700MA
IN
TP_PEX_TESTCLK_N
TP_PEX_TESTCLK_P
PEX_TERMP
6
9C2<
9C4<
14C7<
32D5>
1
R9C7
1
+3.3V_LP0
0201_R
2
C9C16
PEX_L0_RST_L
PEX_L1_RST_L
PEX_L0_CLKREQ_L
PEX_L1_CLKREQ_L
OUT
OUT
R2C4
SNN_GPIO_PFF2
A
15C3<
19C7<
IN
IN
1
1
0402_R
X5R
6.3V
20%
15D7>
19C7>
2
1%
100K
TP_USB_VBUS_EN2
IN
15D7>
19B7>
TITLE
TK1: SATA, PEX, USB 3.0
Mon Apr 07 08:50:59 2014
7
5D2<
0402_R
X5R
6.3V
20%
I445
8
9D1< 9D2< 14C8<
14D2<
19B8<
33A2>
MPCIE SLOT
PEX CONTROLLER 0
2
0402_R
AG30
AG29
IN
26B4<
9C1<
9D8<
32C4>
SNN_PEX_REFCLKP
SNN_PEX_REFCLKN
AG28 PEX_WAKE_L
GPIO_PFF2
USB_VBUS_EN2
IN
C
4.7UF
PEX_WAKE_N
33A2>
0402_R
X5R
6.3V
20%
AE31
AJ29
AJ31
AK29
AJ30
19B8<
+1.2V_GEN_AVDD
1
+1.05V_RUN_AVDD
2.49K
PEX_L0_RST_N
PEX_L1_RST_N
PEX_L0_CLKREQ_N
PEX_L1_CLKREQ_N
14C8<
1700MA
(1.8V - 3.3V)
VDDIO_PEX_CTL
14C1<
B
1%
A
9D2<
2
C8C49
4.7UF
9D1<
D
+3.3V_LP0
IN
1
0402_R
X5R
6.3V
20%
4.7UF
0201_R
X5R
16V
10%
9A2<
EMPTY
0402_R
X5R
6.3V
20%
4.7UF
0201_R
X5R
16V
10%
C8C48
USBSS_TX0_N
USBSS_TX0_P
USBSS_RX0_N
USBSS_RX0_P
SNN_PEX_TX1_N
SNN_PEX_TX1_P
SNN_PEX_RX1_N
SNN_PEX_RX1_P
1
IN
L9C2
2
C9C12
4.7UF
0201_R
X5R
16V
10%
0.1UF
AC21
(1.05V)
10D2<
+3.3V_LP0
FB
AVDD_PEX_PLL
13D1<
1
+1.05V_RUN_AVDD_PEX_PLL_AP_F
0.1UF
AVDD_PLL_C4
19D2<
4.7UF
0201_R
X5R
16V
10%
0.1UF
P10
2
0201_R
X5R
16V
10%
0.1UF
2
AL27
AK27
AJ27
AH27
C9C7
0.1UF
2
HVDD_PEX_PLL_E
22D2<
+1.05V_RUN
2
R9C8
+1.05V_RUN_AVDD
2
AVDD_SATA_PLL
1
0201_R
X5R
16V
10%
SATA_TERMP
2
0201_R
14C1<
C9C14
SATA_L0_TX_P
SATA_L0_TX_N
SATA_L0_RX_P
SATA_L0_RX_N
SATA_TESTCLKP
SATA_TESTCLKN
5%
0201_R
32D5>
2
0402_R
X5R
6.3V
20%
4.7UF
EMPTY
AH31
+1.05V_RUN_AVDD_SATA_PLL_F
1700MA
OUT
OUT
IN
IN
VDDIO_SATA
(1.05V)
30
1
2
16D3<
16D3<
16C3<
16D3<
HVDD_SATA
(1.05V)
AK30
1
1UF
14D2<
AF31
1
30A3>
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
14
8
7
6
5
4
M2E1
PEM
2-56
0.062
SMT_R
J2D2
SMT_HALF_STND_R
MINI_PCIE_HALF
D
3
2
1
W_DISABLE# PULLUP REQUIRED ON CARD PER SPEC
1
D
53 GND
MECH
19B7>
14A3<
14A2<
14B3>
14B3>
OUT
PEX_WAKE_L
OUT
PEX_L0_CLKREQ_L
IN
IN
PEX_CLK1_N
PEX_CLK1_P
1
3
5
7
9
11
13
15
SNN_MPCIE_3
SNN_MPCIE_5
WAKE*
3.3VAUX
GND
1.5V
COEX1
COEX2
CLKREQ*
GND
REFCLKn
REFCLKp
GND
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
I22
2
4
6
8
10
12
14
16
+3.3V_LP0
SNN_MPCIE_8
SNN_MPCIE_10
SNN_MPCIE_12
SNN_MPCIE_14
SNN_MPCIE_16
1 C9E4
22UF
1 C9E1
10UF
0805_R
X5R
6.3V
20%
0603_R
X5R
6.3V
20%
2
2
2
IN
19D2<
22D2<
30A3>
9A2< 10D2<
13D1<
14D1<
17D2<
18D2<
R9D9
8.87K
1%
0402_R
1
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
SNN_MPCIE_17
SNN_MPCIE_19
14B3<
14B3<
14B3>
14B3>
OUT
OUT
PEX_RX4_N
PEX_RX4_P
IN
IN
PEX_TX4_N
PEX_TX4_P
2
C2D13
.1UF
C
C2D12
1
0402_R
X7R
16V
10%
2
1
.1UF
PE_TX4_C_N
PE_TX4_C_P
0402_R
X7R
16V
10%
SNN_MPCIE_45
SNN_MPCIE_47
SNN_MPCIE_49
SNN_MPCIE_51
RESERVED/UIM_C8
GND
RESERVED/UIM_C4
W_DISABLE*
GND
PERn0
PERp0
GND
GND
PETN0
PETP0
GND
GND
3.3VAUX
3.3VAUX
GND
PERST*
3.3VAUX
GND
1.5V
SMB_CLK
SMB_DATA
GND
USB_Dn
USB_Dp
GND
RESERVED
LED_WPAN*
RESERVED
1.5V
GND
3.3VAUX
LED_WWAN*
LED_WLAN*
RESERVED
RESERVED
54
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
W_DISABLE_R_L
30D1<
29D2<
29C1>
27A2<
26A2<
20D2<
17D2<
34D2<
16D2<
33B7<
13D1<
32D4<
IN
+5V_SYS
4
C9E5 1
1UF
B
0402_R
X5R
16V
10%
1
R9E4
0402_R
2
1P5V_EN
GEN1_I2C_SCL_3.3V
GEN1_I2C_SDA_3.3V
2
EN
3
VIN
5%
0
1 C9E3
10UF
2
WWAN_L
WLAN_L
WPAN_L
0603_R
X5R
6.3V
1%
0402_R
2 20%
1
EMPTY
9
8
GNDPAD
GND
1
R9D11
22C1>
22C1<>
BI
BI
9A4<>
9A4<>
0402_R
5%
330
PEM
2-56
0.062
SMT_R
1
2
G
AN
1
1
S1
SC70S_R
CR1E2
GRN
WLAN_LED
2
0603_R
2.2V
25MA
D3
Q9D2
RJU003N03
WF_EN
2
G
S1
CAT
IN
10A3>
SC70S_R
C
2
2
0402_R
M3E1 R9D12
5%
330
1
2
0402_R
5%
330
R9D13
MECH
POK
1
SNN_1P5V_POK
VOUT
NC
6
5
+VDD_1V5_MPCIE
2
FB
7
1
FB_1PV5
2
I56
B
R9E2 1 C9E2
8.87K 10UF
1%
0402_R
R9E1
10K
WF_DISABLE
Q9D3
RJU003N03
I23
U9E1
SOP8P_R
APL5910
VCNTL
W_DISABLE_L
2
5%
0
IN
BI
USB1D_N
USB1D_P
GND
2
14A3>
IN
R9D10
0402_R
D3
I43
31D5<
1
PEX_L0_RST_L
0603_R
X5R
6.3V
2 20%
R9E3
10K
1%
0402_R
1
WIRELESS CARDS CAN WAKE FROM LP0 BUT NOT OFF
A
A
TITLE
MINI HALF PCIE
Wed Mar 26 14:40:03 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
15
8
7
6
5
4
3
2
1
+5V_SYS
31D5<
30D1<
29D2<
29C1>
27A2<
26A2<
20D2<
17D2<
34D2<
15B7<
33B7<
13D1<
32D4<
IN
+5V_SYS
D
D
J2D1
THR_SHRD_R
BLACK
14C7>
14C7>
IN
IN
SATA_L0_TX_P
SATA_L0_TX_N
2
14C7<
14C7<
IN
IN
SATA_L0_RX_N
SATA_L0_RX_P
2
C9D5
.01UF
2
0402_R
X7R
16V
10%
.01UF
C9D7
1
0402_R
X7R
16V C9D6
10%
.01UF
1
2
1
2
3
4
5
6
7
SATA_TX_P
SATA_TX_N
C9D4
1
0402_R
X7R
16V
10%
SATA_RX_N
SATA_RX_P
1
0402_R
X7R
16V
10%
.01UF
1
I85
SATA
C
1 C3E9
10UF
PLACE NEAR USB CONN
2
VERT
J4E2
THR_R
SKT_PWR_IDE
7
U3E1
SLG5NV1430V
TDFN-6_R
+5V_SYS
D
D
S
+5V_SATA
S
C2C4
14C3>
14C3>
USBSS_TX0_P
USBSS_TX0_N
IN
IN
2
USBSS_TX0C_P
USBSS_TX0C_N
C2C5
1
16V
10%
0402_R
X7R
2
.1UF
1
16V
10%
0402_R
X7R
.1UF
16V
10%
0402_R
X7R
.1UF
B
IN
IN
14C3<
14C3<
OUT
OUT
2
1
16V
10%
R9D6
1
2
+0.05R
EMPTY
2
1
+0.05R
EMPTY
0201_R
R2C5
1
2
5%
1
0402_R
X7R
16V
10%
1
0
2
PEX_TX2_P
PEX_TX2_N
OUT
OUT
19C7<
19C7<
IN
IN
17A7>
17A7>
USBSS_RX0R_P
USBSS_RX0R_N
1
5%
EMPTY
2
16V
10%
.1UF
1%
C9C23
2
16V
10%
1
PEX_RX20_P
PEX_RX20_N
R9D4
1
2
+0.05R
35D8<
2
34D8<
29C4<
28C4<
27D2>
27C7<
26D3<
EMPTY
C2D8
C2D7
.1UF
1
0402_R
X7R
16V
10%
I23
1
0402_R
X7R
16V
10%
1 C3E6
1UF
2
1
.1UF
0603_R
X7R
16V
10%
2
PEX_RX2_C_P
PEX_RX2_C_N
IN
IN
0402_R
X7R
16V
10%
1
0402_R
Q3E2
MDV3605URH
DFN3X3_R
S
D
S
D
+VDD_MUX
IN
0201_R
EMPTY
2
+12V_SATA
100K
1
+0.05R
R3E5
2
1%
0
PEX_RX2_P
PEX_RX2_N
OUT
OUT
LV_SATA_EN
1
0402_R
R9D2
0201_R
0
0402_R
X7R
GND
1 C3E8
.1UF
+12V
10K
.1UF
14B3<
14B3<
R3E6
2
0201_R
EMPTY
1
0402_R
X7R
1
8
B
0
C9C22
VDD
GND
0402_R
X7R
50V
10%
2
.1UF
R2C6
0201_R
GND
C2D10
2
0402_R
X7R
.1UF 16V
10%
USBSS_RX0_P
USBSS_RX0_N
0402_R
X5R
16V
2 10%
EMPTY
C2D9
2
ON
CAP
I106
1 C3E11
2200PF
0
PEX_TX2_C_P
PEX_TX2_C_N
2
7
CAP_SLG_5V_SAT
2
0201_R
0
0402_R
X7R
+5V
3
2
R9D5
.1UF
EMPTY
14B3>
14B3>
PEX_TX20_C_P
PEX_TX20_C_N
C9C25
1
+5V_SYS
17A7<
17A7<
PLACE NEAR RTL8111
C9C24
2
OUT
OUT
4
1 C3E10
1UF
0805_R
X5R
16V
10%
C
19C7>
19C7>
2
R3E2
100K
1 C3E7
1UF
GG
1%
0402_R
1
0402_R
X5R
16V
2 10%
EN_VDD_12V_GATE
2
R3E1
75K
5%
0402_R
1
A
EN_VDD_12V_DRAIN
A
10B7>
IN
SATA_PWR_EN_T124
3D
R3E3
1
2
0402_R
5%
0
SATA_PWR_EN
2
2
G
VTH 1.5V MAX
ID 300MA
R3E4
10K
1%
0402_R
1S
Q3E1
RJU003N03
SC70S_R
1
TITLE
PEX OPTIONS AND SATA
Wed Mar 26 14:40:04 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
16
8
7
D
6
5
4
3
2
1
+5V_SYS
D
+5V_SYS
2
2
+3.3V_LP0
2
.1UF
U2D3
R9D7
100K
5
1%
0402_R
1
9A4<>
IN
C9D8
USB_VBUS_EN0
4
2
CR2D1
BAV70
USB0_ID_PWR
3
1
2
1
IN
OC*
18D2<
15D1<
1 C1E6
100UF
1 C1E7
4.7UF
1 C2D11
.1UF
1206_R
X5R
6.3V
20%
0805_R
X5R
10V
10%
0402_R
X7R
16V
10%
2
3
2
2
.2A
2012_R
USB0DL_N
USB0DL_P
CM_CHOKE
L1E3
I220
EMPTY
2
1
2
3
R9D8
100K
1%
0402_R
D3
CR1E1
EMPTY
XSOP7_R
28.0V
TVS_USB
D#
D
ID
1
VBUS
3
2
D_P
D_N
4
ID
5
GND
6
7
V
GND
SC70S_R
1 C1E12
100PF
+5V_SYS
0402_R
C0G
50V
1 C10C1
.1UF
0603_R
X5R
6.3V
10%
0402_R
X7R
16V
10%
2
2
U1C1
SON8_R
TPS2065DGNRG4
+3.3V_LP0
2
2 5%
2
3
OUT
OUT
OUT
IN
IN
R1C2
100K
1 C10C3
.1UF
1%
0402_R
1
B
9A4<>
IN
USB_VBUS_EN1
5
OC*
4
EN
GND
TP
1
9
1 C2C3
22UF
9A4<>
BI
BI
0402_R
X7R
16V
10%
2
2
0805_R
X5R
6.3V
20%
1 C10C4
.1UF
1 C10C5
470PF
B2_R
POSCAP
6.3V
20%
0402_R
X7R
16V
10%
0402_R
X7R
16V
10%
2
2
2
USB2D_P
2
.2A
USB2D_N
1
.2A
2012_R
IN
IN
OUT
OUT
TYPE
ID PIN
POWER PROVIDER
A
B
EMPTY
FALSE
TRUE
TRUE
YES
NO
NO
CM_CHOKE
1%
0402_R
USB2DL_N
D0+
TX+ TX- GND RX+ RX-
D0TX+
TXRX+
2
9
VCC D0- D0+ GND
RX-
Q9E2
BSS138LT1
3
3D
S23_R
EMPTY
3
USB0_ID_AP_R
S23_R
1
2
3
I176
USB0_ID OUT
2
9A4<
1%
1K
2S
2
R9E7
1M
5%
0402_R
Q9E3
BSS138LT1
3D
EMPTY
1
1
G
S23_R
CR2C1
XSOP7_R
28.0V
TVS_USB
D#
V
D
GND
ID
R9E8
0402_R
EMPTY
5
6
1
2S
CR2C2
RCLAMP_0524P
SLP2510P8_R
I178
EMPTY
3D
1
G
1
7
4
B
1
G
I273
A
EMPTY
Q9E1
BSS138LT1
USB0_ID_GATE_L
1
13
12
11
10
7
4
1
10
1
R9E6
1M
R9E5
100K
1
VCC
3
2
9
8
6
5
CM_CHOKE
USBSS_TX0C_P
USBSS_TX0C_N
USBSS_RX0R_P
1 USBSS_RX0R_N
CR2C2
RCLAMP_0524P
SLP2510P8_R
33D7<
OUT
5%
0402_R
USB2DL_P
90OHM
4
2012_R
6
7
8
9
10
11
C
+5V_SYS
J1C2
RA_FLAG_TH_R
USBX1_V3
3
+3.3V_LP0
IN
SH1
SH2
SH3
SH4
MT1
MT2
2
2
L9C4
90OHM
9A2<
1
L9C4
16C4>
16C4>
16B4<
16B4<
10D2<
19D2<
USB0_ID_PMU
1 C1C1
220UF
I59
9A4<>
13D1<
22D2<
+5V_USB_HS
6
7
8
GROUND
1 C10C2
4.7UF
+5V_SYS
IN
I189
SNN_TVS_USB_VBUS0
I194
USB0_ID_C
1
Q2D3
RHU002N06
2
G
S1
34D2<
13D1<
29C1>
15B7<
29D2<
J1E1
TH_UAB_11P
CON_USB_MICRO_AB
PORT 0 IS OTG NORMALLY
DEVICE NEEDED FOR RECOVERY MODE
90OHM L1E3
USB0D_N
1
4
9A4<>
IN
.2A 2012_R CM_CHOKE
USB0D_P
2
3
9A4<>
IN
90OHM
C
16D2<
30D1<
14D1<
30A3>
+USB0_VBUS_SW
1
EN
GND
20D2<
31D5<
+3.3V_LP0
1
EMPTY
OUT
26A2<
32D4<
1%
0402_R
0402_R
X7R
16V
10%
SOT23_5B_R
TPS2051B
27A2<
33B7<
R1E4
100K
S23_R
I202
R10E1
0402_R
2S
2
1%
1K
A
6
7
I120
Wed Mar 26 14:40:04 2014
EMPTY
TITLE
USB PORTS
NVIDIA
CONFIDENTIAL
8
7
6
5
4
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
17
8
7
6
5
4
3
BOARD ID ROM
2
1
+1.8V_VDDIO
I2C ADDR 7H'56
2
D
R2A1
10K
2
1%
0402_R
1
R2A2
10K
U2A1
DFN08_R
CAT24C02HU4
1%
0402_R
EEPROM_2WIRE_8PIN
+1.8V_VDDIO
1 C9A2
.1UF
2
BOARD_ID_WP
7 WP
VCC 8
BOARD_ID_A0
1 A0
2 A1
3 A2
SCL 6
SDA 5
BOARD_ID_A2
2
R9A1
10K
2
32D3<
GEN1_I2C_SCL
GEN1_I2C_SDA
0402_R
X7R
16V
10%
8
IN
UART4_RTS_L
7
B1
IN
UART4_TXD
6
B2
.1UF
VCCB
C
24D5>
22D7>
10B3>
24C5>
22D7>
10B3>
2
.1UF
22D7<
10C3<
OUT
UART4_CTS_L
22D7<
10C3<
OUT
UART4_RXD
R1B11
1
0402_R
1
2
A2
3
0402_R
X7R
16V
10%
1
VCCA
2
A1
3
A2
VCCB
5%
UART4_RXD_R
0 2
0402_R
5%
5
0
R1B10
1
0402_R
X7R
16V
10%
C10B2
2
C1A2
.1UF
C1A1
2
DIR
0| B->A(rx)
1| A->B(tx)
I254
B
C1P 1
C1N 3
1
.1UF
1
0402_R
X7R
16V
10%
C10B1
C2P 4
C2N 5
0402_R
X7R
16V
10%
UART4_CTS_3V3_L
B2
6
UART4_RXD_3V3
GND
4
C1+
C1-
V+
V-
2
6
VP
VN
2
C1A4
.1UF
22D2<
8D1<
30D1<
30C5>
26D6<
23A2<
22D8<
9A2<
+1.8V_VDDIO
IN
D
+3.3V_RUN
IN
26D3<>
19D2<
17D2<
15D1<
14D1<
13D1<
10D2<
9A2<
+3.3V_LP0
IN
12
9
R1OUT
R2OUT
BLACK
J1A2
DSUB9_R
C1A3
1
0402_R
X7R
16V
10%
2
T1OUT
T2OUT
14
7
RS232_RTS
RS232_TXD_L
R1IN
R2IN
13
8
RS232_CTS
RS232_RXD_L
10
1
.1UF
C2+
C2T1IN
T2IN
.1UF
7
SERIAL_RS232_3V3
11
10
2
B1
DIR
1
0402_R
X7R
16V
10%
UART4_RTS_3V3_L
UART4_TXD_3V3
8
10D2<
25B7<
U1B1
TSSOP16_R
TRS3232E
2
.1UF
GND
1
20D2<
26A2<
SERIAL PORT
5
DIR
0| B->A(rx)
1| A->B(tx)
I253
U1B3
LEVEL_SHIFTER_2BIT
SN74AVC2T45
SSOP8_R
UART4_CTS_R_L
2
A1
DIR
4
C10B4
VCCA
1
21D2<
32D4<
I247
1
+3.3V_LP0
U1B2
22B6<
33A2>
+3.3V_LP0
30A3>
+1.8V_VDDIO
LEVEL_SHIFTER_2BIT
SN74AVC2T45
SSOP8_R
22C7<
10B8>
18A6<
20B7<
22C4<
26A7<
26D3<
10B8<>
18A6<>
20B7<>
22C4<>
26A3<>
IN
BI
SERIAL EEPROM
1%
0402_R
1
1
22D2<
+3.3V_RUN
GND 4
THERMPAD 9
R2A3
10K
1%
0402_R
C10B3
23A2<
2-WIRE
1
BOARD_ID_A1
2
24A2<
0402_R
X7R
16V
10%
0402_R
X7R
16V
10%
EMPTY
R1A8
1
SNN_DCD
DSR
2
0402_R
5%
0
DTR
SNN_RI
GND
VCC
16
DSR
6
1
RXD
RTS
TXD
CTS
DTR
RI
9
GND
5
11 GND
I223
SERIAL_DSUB
1 C10A1
.1UF
I232
10 GND
DCD
1
6
2
7
3
8
4
9
5
11
15
C
0402_R
X7R
16V
2 10%
B
+3.3V_RUN
R2D2
100K
2
EMPTY
R2D3
100K
1%
0402_R
+1.8V_VDDIO
TEMP SENSOR
1
2
0402_R
5%
100
8B3<
8B3<
A
IN
OUT
1 C2C7
1000PF
THERMD_P
THERMD_N
100
R9C11
2
1
8
7
5%
26D3<
26A7<
22C4<
20B7<
18D3<
10B8>
26A3<>
22C4<>
20B7<>
18D3<>
10B8<>
2
3
IN
BI
GEN1_I2C_SCL
GEN1_I2C_SDA
D+
D-
2
0402_R
X7R
16V
10%
Q2D1
RJU003N03
AP_OVRHT_G
2
3D
EMPTY
G
SC70S_R
3D
1S
2
G
R9D1
10K
SC70S_R
1%
0402_R
1S
EMPTY
1
TEMP_SENSOR
THERMD_R_P
THERMD_R_N
2
0402_R
26D3<>
0402_R
X7R
50V
10%
2
1
Q2D2
RJU003N03
1 C2C6
.1UF
U2C2
DFN08
R9C10
1%
0402_R
1
EMPTY
2
VCC 1
THERM*
ALERT*/THERM2*
4
6
AP_OVERHEAT_R_L
AP_OVERHEAT_L
2
OUT
A
31C8<
5%
0
GND 5
SCLK
SDATA
R2D1
1
0402_R
TEMP_ALERT_L
OUT
10B3<
TMP451
I222
TITLE
I2C ADDR 7'H4C
TEMP SENSOR, SERIAL, ID
Wed Mar 26 14:40:05 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
18
8
7
6
5
4
3
2
1
+3.3V_LP0
D
D
RISE TIME ON 3.3V RAIL MUST BE > 0.5MS
30A3>
22D2<
18D2<
17D2<
15D1<
14D1<
13D1<
10D2<
9A2<
+3.3V_LP0
IN
+3.3V_LP0
EMPTY
2
R9D3
10K
1%
0402_R
14B3>
14A3>
IN
IN
PEX_CLK2_P
PEX_CLK2_N
14A2<
OUT
PEX_L1_CLKREQ_L
12
CLKREQB
16B4>
16B4>
IN
IN
PEX_TX2_P
PEX_TX2_N
13
14
HSIP
HSIN
16A4<
16A4<
OUT
OUT
PEX_RX2_C_P
PEX_RX2_C_N
17
18
HSOP
HSON
14A3>
IN
PEX_L1_RST_L
19
PERSTB
15
16
REFCLK_P
REFCLK_N
AVDD33
AVDD33
11
32
0402_R
X7R
16V
VDDREG
1 C9D3
.1UF
EMPTY
R2D9
100K
R2D10
100K
IN
+1.05V_RUN
1%
0402_R
1%
0402_R
Q9D1
MMBT3904
LAN_ISOLATE_L
20
ISOLATEB
3
2
LAN_ISO_BASE
6
REGOUT
24
AVDD10
AVDD10
AVDD10
3
8
30
1 C10D2
.1UF
1 C10D3
.1UF
SMD
0402_R
X7R
16V
0402_R
X7R
16V
1 C10D1
.1UF
2 10%
1 C2D1
4.7UF
0603_R
X5R
6.3V
2 10%
0402_R
X7R
16V
2 10%
2 10%
2 10%
21
1
EMPTY
1 C2D4
.1UF
1 C2D6
1UF
1 C2D5
.1UF
LANWAKEB
DVDD10
+1.05V_LAN_REGOUT
22
0402_R
X7R
16V
PEX_WAKE_L
1
R2D8
2
0402_R
0402_R
X5R
16V
2 10%
MDIP0
MDIN0
XTAL_LAN_P
2
1
HC49_R
I359
XTAL_LAN_N
30_30PPM
18PF
28
29
CKXTAL1
CKXTAL2
Y2C1
1 C1D1
25.000MHZ
20PF
1 C2D3
20PF
0402_R
C0G
50V
1
2
0402_R
X7R
16V
2 10%
LAN_MDI0_P
LAN_MDI0_N
9
10
MDIP1
MDIN1
7
8
MX1+
MDIP2
MDIN2
6
7
LAN_MDI2_P
LAN_MDI2_N
5
6
MX2+
MDIP3
MDIN3
9
10
3
4
MX3+
31
1
R1D1
LED0
LED1/GPO
LED2
27
26
25
LAN_LED0
LAN_LED1
LAN_LED2
C1C2
GND
ORNG
GRN
MX3-
2
.01UF
R1D2
1
2
5%
0
11
12
YLW
+3.3V_LP0
1
1%
240
1
14
15 13
LAN_LED_100
2
1%
R2D6
0402_R
X7R
16V
LAN_LED0_ACT_L
2
0402_R
1 C1D7
.1UF
LAN_LED_1000
240
2
16
A
R2D4
0402_R
R2D5
0402_R
I404
1
0402_R
X7R
16V
10%
0402_R
MX2-
I382
1%
1
LAN_TRCT1
2
1
LAN_CH_GND
2
2.49K
2 5%
MX1-
GND
LAN_MDI3_P
LAN_MDI3_N
LAN_RSET
VCC
CH_GND
0402_R
GND
MX0-
LAN_MDI1_P
LAN_MDI1_N
RSET
33
MX0+
4
5
0402_R
C0G
50V
2 5%
B
LINK 10
= OFF
LINK 100 = SOLID ORANGE
LINK 1000 = SOLID GREEN
LINK ACT = BLINK YELLOW
J1D1
RJ45_2_R
RJ45_1X1GBIT_MAG_LED
PEX0_WAKE_R_L
5%
0
A
SMD_R
2
S363_R
OUT
EMPTY
SMD
1 C2D2
.1UF
2 10%
14A3<
L2D1
2
2016_R
4.7UH
L2D2
1
2
+1.05V_LAN_REGOUT_L
0402_R
X7R
16V
4
EMPTY
15D7>
4.7UH
1
0.7A
EMPTY
S363_R
1%
10K
B
1
LAN_ISOLATE
Q9D1
MMBT3904
0402_R
2
TWO INDUCTOR FOOTPRINTS
FOR AVAILABILITY REASONS
0603_R
X5R
6.3V
10%
2
5
R2D11
1
1 C9D2
4.7UF
(1)TD0+
14C1<
14D2<
33A2>
9D2< 9D1<
14C8<
0402_R
X7R
16V
10%
(2)TD0-
1%
10K
C
(3)TD1+
2
0402_R
2 10%
(4)TD2+
PMU_REGEN3
0603_R
X5R
6.3V
2 10%
(5)TD2-
IN
0603_R
X5R
6.3V
2 10%
(6)TD1-
27C4<
31C2>
0402_R
X7R
16V
1 C1D3
4.7UF
(7)TD3+
30A8<
1 C1D5
4.7UF
550MA
1
30C8<
1 C1D2
.1UF
23
2
2
R9D14
1
1 C1D4
.1UF
2 10%
BIOS PULL HIGH/LOW ON PIN
TO ISOLATE LEAVE/ENTER DSM
EMPTY
EMPTY EMPTY
(8)TD3-
C
1
U2D2
QFN-33_R
RTL8111GS
2 10%
EMPTY
5%
510
TITLE
PEX GIGE LAN/PHY
Wed Mar 26 14:40:05 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
19
8
7
6
5
4
3
2
1
+1.8V_VDDIO
25B7<
24A2<
23A2<
22D2<
22C7<
22B6<
21D2<
33A2>
18D2<
32D4<
10D2<
26A2<
8D1<
+1.8V_VDDIO
IN
+5V_SYS
D
D
31D5<
30D1<
29D2<
29C1>
27A2<
26A2<
17D2<
R10E4
HEADSET1R_R
1
0402_R
1
0402_R
I2C ADDR 7'H38
10B7>
10B7<
IN
OUT
DAP2_DOUT
DAP2_DIN
BI
BI
DAP2_SCLK
DAP2_FS
0402_R
10A8>
10A7>
33
34
DAP2_DIN_R
2
DAC1DAT1
ADCDAT1
5%
0
36
35
BCLK1
LRCK1
31
32
DACDAT2
ADCDAT2
HPO_R
HPO_L
HPOFB
DACDAT2
SNN_ADCDAT2
2
2
R10E2
10K
1%
0402_R
1
26A3<>
22C4<>
18D3<>
18A6<>
10B8<>
26D3<
26A7<
22C4<
18D3<
18A6<
10B8>
B
2
1%
0402_R
1
26D3<>
R1E8
10K
R10E3
10K
30
29
BCLK2
1%
0402_R
LRCK2
BCLK2
LRCK2
1
BI
IN
GEN1_I2C_SDA
GEN1_I2C_SCL
39
38
IN
DAP_MCLK1
37
10C3<
OUT
CODEC_IRQ_L
TP_DMIC_CLK
40
41
GPIO1_IRQ
GPIO2_DMIC_SCL
IN
AUDIO_LDO_EN
44
LDO1_EN
8C3>
17
16
SNN_LOUTR
SNN_LOUTL
21C8>
21B7>
21C7>
IN
IN
IN
HEADSET_MIC_C
HEAD_DET_L
7
8
TP_DMIC_DATA
JD_MIC_L
L10E1
1
1700MA
0402_R
5
6
22
9
49
2
MCLK
LOUTR
LOUTL
NEXT FAB ADD 0 OHM PD
ON HP1_SENSE AT CODEC
26
28
25
HP1_SENSE
SPO_LP
SPO_LN
1
48
SNN_SPKL_P
SNN_SPKL_N
SPO_RP
SPO_RN
45
47
SNN_SPKR_P
SNN_SPKR_N
IN3P
IN3N
13
14
MICBIAS1
4
VREF1
VREF2
11
12
AUD1_VREF1
AUD1_VREF2
CPN1
CPP1
CPN2
CPP2
21
20
18
19
CHGPUMP_N1
CHGPUMP_P1
CHGPUMP_N2
CHGPUMP_P2
MICVDD
AVDD
3
15
+VDD_MIC
AUDIO_AVDD
SDA
SCL
10B8>
DACREF
30
IN
2
2
2
R1E9
22
5%
21A7>
OUT
21A7<
2
HP1_LT
OUT
21A7<
5%
0402_R
C
R10E5
22
0402_R
1
R1E6
2
SNN_IN3P
0402_R
X7R
16V
10%
5%
0402_R
1
SNN_IN3N
MIC1_BIAS
1
OUT
21C5<
5%
0
MIC1_BIAS_R
1 C1E16
2.2UF
1 C1E15
2.2UF
0402_R
X5R
6.3V
1 C1E11
4.7UF
0402_R
X5R
6.3V
2 20%
0603_R
X5R
6.3V
2 20%
2 10%
1 C10E3
4.7UF
1 C1E5
4.7UF
0603_R
X5R
6.3V
1 C10E1
.1UF
0603_R
X5R
6.3V
2 10%
0402_R
X7R
16V
2 10%
2 10%
1 C10E2
2.2UF
0402_R
X5R
6.3V
2 20%
10
L1E4
1
0402_R
2
FB
120
AUDIO_DACREF
2
R1E5
1
0402_R
IN2P
IN2N_JD2
CPVDD
CPVEE
CPVPP
23
27
24
CPVDD
CPVEE
CPVPP
DCVDD
42
AUD_DCVDD
IN1P_DMIC1_DAT
IN1N_DMIC2_DAT_JD1
+1.8V_VDDIO
1200MA
CPGND
AGND
GNDPAD
43
SPKVDDL
SPKVDDR
2
46
0402_R
5%
47
1 C1E14
.1UF
0402_R
X7R
16V
L1E5
1
+1.8V_VDDIO
DBVDD
B
+1.8V_VDDIO
1200MA
2 10%
1 C1E13
10UF
0603_R
X5R
6.3V
2 20%
1 C1E9
.1UF
0402_R
X7R
16V
2 10%
1 C1E8
10UF
0603_R
X5R
6.3V
2 20%
2
FB
120
1 C10E7
.1UF
0402_R
X7R
16V
2 10%
I204
FB
HP1_RT
1 C1E21
.1UF
0402_R
X7R
16V
10%
2
ALC5639
2
+5V_SYS
IN
HEADSET1RC_L
R1E7
1
1 C1E19
.1UF
HEADSET1RC_R
C
13D1<
32D4<
33
U1E1
QFN48
NEXT FAB ADD 0 OHM OPTION
ON DAP2_DOUT & DAP2_FS
15B7<
33B7<
5%
33
R1E10
HEADSET1R_L
16D2<
34D2<
1 C10E6
2.2UF
1 C10E9
.1UF
0402_R
X5R
6.3V
0402_R
X7R
16V
2 20%
2 10%
1 C10E8
2.2UF
0402_R
X5R
6.3V
2 20%
1 C10E10
2.2UF
0402_R
X5R
6.3V
2 20%
1 C1E20
2.2UF
1 C1E17
.1UF
0402_R
X5R
6.3V
0402_R
X7R
16V
2 20%
2 10%
1 C1E18
10UF
0603_R
X5R
6.3V
2 20%
A
A
+5V_SYS
1 C10E5
.1UF
0402_R
X7R
16V
2 10%
1 C1E10
10UF
0603_R
X5R
6.3V
2 20%
1 C10E4
10UF
0603_R
X5R
6.3V
2 20%
TITLE
AUDIO CODEC
Mon Mar 31 17:28:55 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
20
8
7
6
5
4
3
2
1
+1.8V_VDDIO
25B7<
24A2<
23A2<
22D2<
22C7<
22B6<
20D2<
33A2>
18D2<
32D4<
10D2<
26A2<
8D1<
IN
+1.8V_VDDIO
D
D
+1.8V_VDDIO
2
20B2>
1%
0402_R
MIC1_BIAS
IN
2
R1D9
100K
1
AUDIO_JACK_2PORT_LIMEPINK
J1D2
THR_R
R1D8
2.2K
5%
0402_R
C
20B7<
OUT
HEADSET_MIC_C
2
C1E1
1UF
1
HP1_MIC_L
1
C
MIC IN (PINK)
22
23
24
JD_MIC_R_L
0402_R
X5R
16V
10%
LT
TIP
JDET
JDET2
INSULATOR
20A7<
OUT
JD_MIC_L
2
R1D7
HP1_MIC_R
5%
1
2
0402_R
0
8D3<
OUT
30
JD_MIC_T124_L
L1D2
2
1
1700MA
0402_R
25
1
RT
RING
SLEEVE
R1D6
2.2K
5%
0402_R
FB
I203
1
+1.8V_VDDIO
2
R1E3
100K
+1.8V_VDDIO
1%
0402_R
1
R1E2
2
B
20B7<
OUT
8C3<
OUT
HEAD_DET_L
5%
2
1
HEAD_DET_T124_L
1
1700MA
L1E1
2
0402_R
D3
1
Q1E1
RJU003N03
FB
B
1%
0402_R
0402_R
0
30
EMPTY
R1E1
100K
HEAD_DET_JACK_L
2
G
S1
SC70S_R
1 C1E2
10PF
EMPTY
2
0402_R
C0G
50V
5%
AUDIO_JACK_2PORT_LIMEPINK
J1D2
THR_R
20C2>
IN
30
HP1_LT
1
1700MA
L1E2
2
0402_R
FNT OUT (GREEN)
HP1_LT_L
2
3
4
FB
LT
10
TIP
JDET
11
JDET2
3/4 SHORTED W JACK
3/4 OPEN W/O JACK
INSULATOR
20C2>
20C4<
IN
OUT
30
HP1_RT
1
1700MA
L1D1
2
0402_R
HP1_RT_L
FB
HP1_SENSE
1
1 C1D9
10PF
A
2
2
C9D1A
.1UF
2
C1E4
.1UF
5
1
4MIL
0402_R
C0G
50V
5%
1 C1E3
10PF
2
RT
RING
12
SLEEVE
13
2
I202
ISO10D1
A
0402_R
C0G
50V
5%
1
0402_R
X7R
16V
10%
1
0402_R
X7R
16V
10%
TITLE
AUDIO CONNECTORS
Wed Mar 26 14:40:07 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
21
8
7
6
5
4
3
2
1
+3.3V_SYS
30C5>
26D6<
23A2<
32D3<
18D2<
30D1<
9A2<
IN
+3.3V_RUN
2
EMPTY
2
R8B6
0
5%
0402_R
1
D
+1.8V_VDDIO
5%
0402_R
+3.3V_342
1
1 C8B1
.1UF
2
24C5>
24D5>
22A4>
22A4>
22A4>
22A4<
22A4<
R8B4
0
5%
0402_R
1
31B2<
25C5>
24B6>
26A3<>
26B4<
8C3>
26B7>
8C3<
26A3<>
24D5<>
21D2<
25B7<
8A3<
8A3<
8A3<
8A3<
8A3>
8A3<
IN
C
22B6<
26A2<
10B3>
10C3<
10C3<
10B3>
20D2<
24A2<
33A2>
18D2<
23A2<
32D4<
10D2<
22D2<
8D1<
BI
BI
IN
IN
OUT
IN
IN
OUT
25B7<
1
J7B1 EMPTY
SMT2_R
HDR_24_FPC_RA
UART4_TXD
UART4_RXD
UART4_CTS_L
UART4_RTS_L
DEBUGGER_RESET_L
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_RTCK
JTAG_TDO
JTAG_TRST_L
PMU_RESET_IN_L
SNN_PM_I2C_SCL_3.3V
SNN_PM_I2C_SDA_3.3V
BR_UART1_TXD
BR_UART1_RXD
FORCE_RECOVERY_L
OUT
OUT
OUT
OUT
IN
IN
+1.8V_VDDIO
1 C7B3
.1UF
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
22C7<
22B6<
21D2<
20D2<
33A2>
32B8<
18D2<
32D4<
10D2<
26A2<
8D1<
30D1<
28D2<
28C1>
26D6<
IN
+3.3V_SYS
I2C LEVEL TRANSLATOR
+3.3V_LP0
EMPTY
26D3<
26A7<
20B7<
18D3<
18A6<
10B8>
26A3<>
20B7<>
18D3<>
18A6<>
10B8<>
26D3<>
IN
BI
2
3
4
1
GEN1_I2C_SCL
GEN1_I2C_SDA
VREF1
SCL1
SDA1
GND
I201
VREF2
SCL2
SDA2
EN
2
26
R1D3
205K
R1D4
2.7K
IN
2
5%
0402_R
1
7
6
5
8
1
9A2< 10D2<
13D1<
14D1<
15D1<
17D2<
18D2<
19D2<
30A3>
R1D5
2.7K
5%
0402_R
1
GEN1_I2C_SCL_3.3V
GEN1_I2C_SDA_3.3V
1 C1D8
.1UF
EMPTY
C1D6 1
.1UF
0402_R
X7R
16V
10%
2
1%
0402_R
U1D1
QFN8_R
PCA9306
+1.8V_VDDIO
26
IN
D
25
25
23A2<
+1.8V_VDDIO
+3.3V_SYS
0402_R
X7R
16V
10%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
24A2<
STUFF THIS DEBUG CONN
OR JTAG & DSUB, NOT BOTH
PCA9306_VREF21
2
18C7<
18B8>
18B8>
18C7<
NVPN
080-0665-000
R8B5
0
OUT
BI
15C3<
15C3<>
EMPTY
C
0402_R
X7R
16V
2 10%
2
EMPTY
I217
0402_R
X7R
16V
10%
RESET SUPERVISOR ALLOWS EXTERNAL ARM JTAG DEBUGGER TO DETECT POWER CYCLE
DEPOPULATE SUPERVISOR FOR PRODUCTION VERSIONS?
25B7<
24A2<
23A2<
22D2<
22C7<
21D2<
20D2<
33A2>
18D2<
32D4<
10D2<
26A2<
8D1<
+1.8V_VDDIO
IN
U4A3
EMPTY
SOT23_3_R
RT9818B15GV
B
3
2
C4A2
.1UF
RST_MON
VCC
RST*
1
GND
2
B
2
I254
U4A1
SOT23_6PIN_R
TPS3103
1
0402_R
X7R
16V
10%
6
3
4
RST_MON
VDD
RST*
2
1%
0402_R
1
1
Y_JTAG_TRST_L
PFO*
5
GND
2
22C7>
22C7>
22C7>
22C7>
22C7<
8A3<
8A3<
8A3<
8A3<
8A3>
1
OUT
OUT
OUT
IN
IN
1 C5A1
.1UF
2
23D7<
8B3<
SYS_RESET_L
IN
R4A2
10K
2
1%
0402_R
1
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_RTCK
JTAG_TDO
I188
PFO_JTAG_TRST_L
31B2>
2
1%
0402_R
2
A
R4A1
10K
R4A3
10K
1%
0402_R
1
J4A1
THR_RA_SHR2
2.54MM
MR*
PFI
R5A4
10K
1
R2C3
R4A4
10K
10K
1%
0402_R
1
1%
0402_R
2
1
R5A2
10K
1%
0402_R
4
1
I176
2
R5A1
10K
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2
C4A1
.1UF
1
0402_R
X7R
16V
10%
I164
HDR2X10
A
1%
0402_R
1
3
JTAG
JTAG_SRST_L
2
0402_R
0402_R
X7R
16V
10%
5
2
U5A1
74LVC1G07
SC70_R
2
JTAG_SRST_B_L
JTAG_PD0
JTAG_PD1
R4A13
1
5%
0
TITLE
JTAG CONN; I2C TRANSLATER
Wed May 07 10:39:43 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
22
8
7
6
5
4
3
2
1
EMMC 4.51
+3.3V_RUN
+1.8V_VDDIO
174-0136-000
D
2
U7D1
BGA169_1
SDIN8DE4-16G
EMMC
R4D1
4.7K
5%
0201_R
1 C4D4
.1UF
1
8A7>
8A7>
31B2>
22A5<
8B3<
8A8<>
2
IN
SDMMC4_CLK
W6
CLK
BI
SDMMC4_CMD
W5
CMD
IN
SYS_RESET_L
U5
RST*
BI
SDMMC4_DAT<7..0>
C
VCC
VCC
VCC
VCC
M6
N5
T10
U9
K6
W4
Y4
AA3
AA5
0
H3
DAT0
1
H4
DAT1
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
2
H5
DAT2
VDDI
3
J2
DAT3
4
J3
DAT4
5
J4
DAT5
6
J5
DAT6
7
J6
DAT7
K4
Y2
Y5
AA4
AA6
VSS
VSS
VSS
VSS
P5
M7
R10
U8
2
D
0402_R
X5R
6.3V
20%
+1.8V_VDDIO
1 C4D2
.1UF
0402_R
X7R
16V
K2 +EMMC_VDDI
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
0402_R
X7R
16V
10%
1 C4D3
4.7UF
2 10%
1 C4D5
4.7UF
0402_R
X5R
6.3V
2 20%
1 C4D1
.1UF
0402_R
X7R
16V
C
2 10%
I123
SPI BOOT ROM
+1.8V_VDDIO
B
B
1 C3A1
.1UF
R3A1
10K
2
U3A1
W25Q32DW
SOIC_R
1%
0402_R
1
24B2>
10B3>
10C3<
IN
OUT
2
0402_R
X7R
16V
10%
2
R3A2
100K
1%
0402_R
1
SPI
SPI4_CS0_L
SPI4_MISO
SPI_ROM_WP_L
1
2
3
4
CS*
DO
WP*
GND
VCC
HOLD*
SK
DI
8
7
6
5
SPI_HOLD_L
SPI4_SCK
SPI4_MOSI
IN
IN
10C3>
10C3>
24B2>
24B2>
+3.3V_RUN
SERIAL EEPROM
32MBIT
I58
32D3<
30D1<
30C5>
26D6<
22D8<
18D2<
9A2<
IN
+3.3V_RUN
+1.8V_VDDIO
A
A
25B7<
24A2<
22D2<
22C7<
22B6<
21D2<
20D2<
33A2>
18D2<
32D4<
10D2<
26A2<
8D1<
IN
+1.8V_VDDIO
TITLE
EMMC,SPI ROM
Wed Mar 26 14:40:08 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
23
8
7
6
5
4
3
2
1
+1.8V_VDDIO
ISOLATE FOR
EMMC BOOT = DEFAULT
REWORK EASE
2
+1.8V_VDDIO
2
R8B7
100K
1%
0402_R
D
2
2
R5E11
100K
EMPTY
1%
0201_R
FORCE RECOVERY
BUTTON
R1B1
100K
2
1%
0201_R
1
EMPTY
R1B4
100K
2
1%
0201_R
1
1
R1B5
100K
2
6
3
2
4
GND
2
R1B3
100K
1%
0201_R
5
R1B2
100K
2
1%
0201_R
1
OUT
10C3<
5%
2.2K
1
GPIO_PI1
FORCE_RECOVERY_L
GPIO_PK7
UART4_RTS_L
GPIO_PJ7
GPIO_PI0
22C7<
10B3>
22D7>
18C7<
UART4_TXD
OUT
10B3>
22D7>
18C7<
GPIO_PI0
OUT
10C3>
2
R9B5
100K
1%
0201_R
1
R9B3
100K
1%
0201_R
1
1
LCD_LR
OUT
10C3>
GPIO_PG1
BOOT_SEL1
LCD_UD
OUT
10C3>
GPIO_PG2
BOOT_SEL2
MODEM_SAR0
OUT
10C3<>
BOOT_SEL3
GPIO_PG3
OUT
10C3<>
EMPTY
26A3<>
OUT
EMPTY
BOOT_SEL0
GPIO_PG3
BI
1%
0402_R
1
GPIO_PG0
AP_FORCE_RECOVERY_L
1
J LEAD
GND
2
0201_R
1%
0201_R
SW5E2
THICK_UNIV
BUTTON_6P
1
R7A1
1
2
R8B9
100K
2
EMPTY
2
R3B4
100K
2
R3B5
100K
1%
0201_R
1%
0201_R
1
2
R2B7
100K
1%
0201_R
1
D
R2B5
100K
1%
0201_R
1
1
NOTE:
EMPTY 1011: EMMC BOOT X8 - BOOT MODE OFF
1000: SPI BOOT
R1B6
100K
1%
0201_R
1
EMPTY
I83
1
C
PHIDGET
EMPTY
NOTE:
CR5E2
AOZ8231A
SOD882_R
I249
J5E1
THR
1
2
I85
C
RAM CODE
NOR_BOOT:
1 = IROM --> UART
0 = NOR
ARM_JTAG[1:0]
2'B00 = SERIAL JTAG CHAIN CPU AND COP
2'B01 = CPU
2'B10 = COP
2'B11 = SERIAL_ALT
+1.8V_VDDIO
2
2
R8B3
100K
1%
0201_R
31C6<
31B7>
24A8<
31C8<
+2.5V_AON_RTC
IN
GPIO_PG4
SW5E1
THICK_UNIV
BUTTON_6P
B
2
J LEAD
RESET
BUTTON
GND
2
1
RAM_CODE0
SPI4_CS3_L
OUT
10C3>
SPI4_SCK
OUT
10C3>
23A4<
OUT
10C3>
23A4<
OUT
10C3<
23A7>
GPIO_PG6
SPI4_MOSI
GPIO_PG7
RAM_CODE3
SPI4_MISO
2
1 C5E1
1000PF
PHIDGET
EMPTY
1%
0201_R
1
1%
0402_R
OUT
22C8<
25C5>
26A3<>
1
CR5E3
AOZ8231A
SOD882_R
I248
0402_R
X7R
50V
10%
R3B1
100K
EMPTY
2
R2B1
100K
R2B2
100K
1%
0201_R
1
EMPTY
2
1%
0201_R
B
R3B2
100K
1%
0201_R
1
1
NOTE:
RAM_CODE[1:0]:SELECTS SDRAM CONFIGURATION FROM BCT
RAM_CODE[3:2]:SELECTS SECONDARY BOOT DEVICE FROM BCT
2
J5E2
THR
2
1%
0201_R
31B2<
1
I105
R8B2
100K
R4E5
100K
3
5
1
1%
0201_R
EMPTY
RAM_CODE2
4
GND
1%
0201_R
1
2
R9B1
100K
RAM_CODE1
PMU_RESET_IN_L
2
EMPTY
GPIO_PG5
1
6
1
2
R9B2
100K
1
I81
+1.8V_VDDIO
KB_COL0_AP
POWER
BUTTON
A
31B7>
31C8<
24B8<
31C6<
IN
1S
2
Q4E2
RTU002P02
SC70S_R
2
G
R4E4
200K
1%
0402_R
3 D
2
2
6
3
2
Q4E1
BSS138LT1
KB_COL0_GATE
1
J LEAD
GND
BOARD ID STRAPS
8D3<
+2.5V_AON_RTC
SW4E1
THICK_UNIV
BUTTON_6P
1
OUT
R3C8
100K
2
1%
0402_R
1
G
S23_R
R4E3
1M
3D
EMPTY
1
EMPTY
R3C7
100K
2
1%
0402_R
EMPTY
R2C8
100K
2
1%
0402_R
1
1
EMPTY
R2C9
100K
1%
0402_R
4
5
1
CR4E1
AOZ8231A
SOD882_R
I250
I107
2
23A2<
22D2<
BD_ID_STRAP3
BD_ID_STRAP2
BD_ID_STRAP1
BD_ID_STRAP0
2S
1
1 C4E7
1000PF
25B7<
2
0402_R
X7R
50V
10%
R3C9
100K
2
1%
0402_R
1
R3C10
100K
2
1%
0402_R
R2C7
100K
2
1%
0402_R
1
1
22C7<
22B6<
OUT
OUT
OUT
OUT
20D2<
33A2>
18D2<
32D4<
10D2<
26A2<
8D1<
IN
+1.8V_VDDIO
A
10A3<
10A3<
8C3<
8D3<
R2C10
100K
1%
0402_R
TITLE
1
2
SWITCHES & STRAPS
PHIDGET
EMPTY
J4E1
THR
ONKEY_L
1
OUT
25D2>
26A3<>
31C6<
I103
8
21D2<
1
5%
0402_R
GND
+1.8V_VDDIO
Tue Apr 08 14:39:29 2014
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
24
8
7
6
5
4
3
2
1
FRONT PANEL
+5V_SYS
D
10B7>
SATA_LED
IN
Q1A2
RJU003N03
+5V_SYS
3D
SC70S_R
1S
2
5%
0603_R
1
HDLED_PWR
HDLED_L
1
3
5
7
FP_9 9
1
2
R1A1
330
1
R1A3
330
D
5%
0603_R
5%
0603_R
J1A1
THR_R
1
RST_SWR_L
2
R1A7
0
R1A2
330
5%
0603_R
+3.3V_RUN
EMPTY
2
2
2
G
+5V_SYS
1
GRN_PWRLED
YLW_STBYLED
PWRBTN_R_L
2
4
6
8
1
R1A5
9
I144
ONKEY_L
2
0402_R
OUT
24A6>
26A3<>
31C6<
5%
33
YELLOW STANDBY LED LOGIC IS INVERTED.
FIX IN NEXT REV.
HDR2X5KEY10
FRONT_PANEL2
+5V_SYS
1
R1A6
0402_R
PMU_RESET_IN_L
2
OUT
22C8<
24B6>
26A3<>
2
31B2<
5%
33
D3
Q1A1
RHU002N06
2
G
C
S1
R1A4
100K
1%
0402_R
1
YLW_STBYLED_L
SC70S_R
D3
2
G
S1
23A2<
22D2<
22C7<
22B6<
21D2<
33A2>
20D2<
32D4<
18D2<
26A2<
10D2<
24A2<
8D1<
IN
2
BI
SDMMC3_DAT<3..0>
BI
30B1>
IN
8B8>
IN
8A8<
OUT
2
R6B2
4.7K
5%
0402_R
R6B1
10K
1%
0402_R
10
2
9
3
1
CD_DATA3
2
CMD
3
VSS1
4
VDD
5
CLK
6
VSS2
0
7
DATA0
1
8
DATA1
1
SDMMC3_CMD
+3.3V_SD_CARD
SDMMC3_CLK
11
32B3<
B
C_WR_PROTECT
GND_EMI2
A
WP
SDMMC3_WP_L
SNN_SDMMC3_CLMP
1 C7B2
4.7UF
5
EMPTY
7
1
3
4
6
CR7B2
TVS504PA
XSOP7_R
I95
5
7
1
3
4
6
CR7B1
TVS504PA
XSOP7_R
I93
0603_R
X5R
6.3V
2 10%
1 C7B1
.1UF
0402_R
X7R
16V
2 10%
TITLE
EMPTY
SD CONN & FRONT PANEL HDR
Wed May 07 10:30:26 2014
7
31C2>
SC70S_R
I87
8
31A8<
CD C_DETECT
SDMMC3_CD_L
A
OUT
30B8<
SM1_R
CON_SD
SC COMMON
8D3<
IN
30A5<
J5B1
EMPTY
GND_EMI1
DATA2
1
B
8B8>
PMU_REGEN1
+1.8V_VDDIO
EMPTY
8B8<>
C
Q1A3
RJU003N03
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
25
8
7
6
5
4
3
2
1
J3A1
SKT2X25
THR_R
TOUCH SPI
8C7>
8C7>
32B5>
8B8>
D
32B8<
32D3<
30D1<
30C5>
30D1<
23A2<
28D2<
22D8<
28C1>
22D2<
10B1>
10B1<>
18D2<
9A2<
31C2>
9B3<>
9B3<>
OUT
OUT
TS_SPI_SCK
TS_SPI_CS_L
IN
IN
+3.3V_RUN_TOUCH
TS_CLK
IN
IN
BI
IN
IN
+3.3V_SYS
GEN2_I2C_SCL_3.3V
GEN2_I2C_SDA_3.3V
+3.3V_RUN
BI
BI
EN_AVDD_LCD
DP_AUX_P
DP_AUX_N
9B3>
9B3>
IN
IN
LVDS_TXD1_P
LVDS_TXD1_N
9B3>
9B3>
IN
IN
LVDS_TXD2_P
LVDS_TXD2_N
9B2<
10C3>
10C3>
OUT
IN
IN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
EDP_HPD
LCD_BL_EN
LCD_BL_PWM
R2B3
100K
2
1%
0201_R
C
R2B4
100K
+5V_SYS
+1.8V_VDDIO
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
TS_SPI_MOSI
TS_SPI_MISO
OUT
IN
8C7>
8C7<
TS_SHDN_L
TS_RESET_L
IN
IN
10B3>
10B3>
GPIO_PK2
IN
10B3>
IN
BI
IN
IN
10B8>
18A6<
18D3<
20B7<
22C4<
26A7<
10B8<>
18A6<>
18D3<>
20B7<>
22C4<>
26A3<>
16A3<
27C7<
27D2>
28C4<
29C4<
34D8<
35D8<
8C7>
LVDS_TXD0_P
LVDS_TXD0_N
IN
IN
9B3>
9B3>
LVDS_TXD3_P
LVDS_TXD3_N
IN
IN
9B3>
9B3>
LVDS TO EDP MUX
LVDS_TXD4_N
LVDS_TXD4_P
IN
IN
9B3>
9B3>
LVDS
EDP
IN
8C3>
CH0
CH1
CH2
CH3
CH4
CH2
CH1
CH0
--CH3
GEN1_I2C_SCL
GEN1_I2C_SDA
+VDD_MUX
EN_VDD_BL
LCD_TE
D
2_X_2MM
I108
2
1%
0201_R
1
C
1
NOTES:
LVDS / EDP MODULES MAY USE +3.3V RUN
OR +3.3V_RUN GATED BY EN_AVDD_LCD (PMIC GPIO4)
32C4>
9A7>
32B4>
IN
IN
IN
9A8<>
9C8>
9D8>
BI
IN
IN
+1.8V_VDDIO
9D8<
9C8<
9D8<
B
9D8<
9D8<
9C8<
9C8<
22C7<>
31C6<
26D3<
22C4<
20B7<
18D3<
18A6<
8C3<
9C8<
9C8<
8B2>
OUT
OUT
OUT
+1.05V_RUN_CAM_REAR
CAM2_PWDN
+2.8V_RUN_CAM
CAM_I2C_SDA
CSI_A_CLK_P
CSI_A_CLK_N
CSI_A_D1_N
CSI_E_D0_P
CSI_A_D1_P
OUT
OUT
CSI_A_D0_N
CSI_A_D0_P
OUT
CSI_B_D1_N
OUT
CSI_B_D1_P
OUT
OUT
OUT
IN
9B7<>
10B8>
9A7>
9A7>
BI
IN
IN
IN
9A7>
9A7>
10C7>
IN
IN
IN
BR_UART1_RXD
CSI_B_D0_P
CSI_B_D0_N
PWR_I2C_SCL
CAM1_GPIO
GEN1_I2C_SCL
CAM1_AF_PWDN
CAM_FLASH
CAM1_PWDN
CAM1_MCLK
UART2_TXD
A
10C7>
IN
UART2_RTS_L
LDO7
LDO4
3
+5V_SYS
J3A2
THR_R
1
2
5
6
4
9
7
8
11
12
10
15
13
14
17
18
16
21
19
20
23
24
22
27
25
26
29
30
28
33
31
32
35
36
34
39
37
38
41
42
40
45
43
44
47
48
46
51
49
50
53
54
52
57
55
56
59
60
58
63
61
62
65
66
64
69
67
68
71
72
70
75
73
CAM_RST_L
CAM2_MCLK
CAM2_GPIO
CAM_I2C_SCL
IN
IN
BI
IN
CSI_E_CLK_N
CSI_E_D0_N
CSI_E_CLK_P
LDO5
LDO10
LDO 1
IN
OUT
IN
9B7>
9B7>
9B7<>
9A8>
9C8>
9C8<
9C8>
+1.8V_VDDIO
+1.2V_RUN_CAM_FRONT
+2.8V_RUN_CAM_AF
+1.8V_RUN_CAM
+1.2V_GEN_AVDD
HSIC1_STROBE
HSIC1_DATA
IN
IN
IN
IN
IN
BI
32C4>
32A5>
9B8< 32C5>
9C1< 9D8< 14D1<
9A8>
9A8>
BR_UART1_TXD
GPIO_PU0
GPIO_PU1
IN
BI
BI
8C3> 22C7<>
10C6<>
10C6<>
GPIO_PU2
GPIO_PU3
PWR_I2C_SDA
GPIO_PU4
GPIO_PU5
GEN1_I2C_SDA
GPIO_PU6
ONKEY_L
UART2_RXD
PMU_RESET_IN_L
FORCE_RECOVERY_L
UART2_CTS_L
CLK3_OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
OUT
IN
10B6<>
10B6<>
8B2<>
10B6<>
10B6<>
10B8<>
10B6<>
24A6>
10C7<
22C8<
22C7<
10C7<
10C7>
B
32C4>
31C6<>
18A6<>
25D2>
18D3<>
20B7<>
22C4<>
26D3<>
31C6<
24B6>
25C5>
24D5<>
31B2<
A
+1.8V_VDDIO
74
SKT3X25
FEMALE_VERT
I145
24A2<
31D5<
23A2<
30D1<
22D2<
29D2<
22C7<
29C1>
22B6<
27A2<
21D2<
20D2<
20D2<
33A2>
17D2<
18D2<
32D4<
16D2<
34D2<
10D2<
25B7<
15B7<
33B7<
8D1<
13D1<
32D4<
IN
IN
+1.8V_VDDIO
+5V_SYS
+5V_SYS
TITLE
EXP:TOUCH/DISP & GENERAL
Wed Mar 26 14:40:09 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
26
8
7
6
5
4
3
2
1
J5C1
THR_R
PWR_JACK_5P
POWER
+VDD_ACIN
1
2
SNN_JACK_RING
2
R5C8
3.9
5%
0603_R
TIP 3
1%
0402_R
1
SHIELD1 4
SHIELD2 5
R5C9
20K
2
1
R5C11
+VDD_MUX
2
R5C10
20K
1 C5D5
10UF
1 C5D1
10UF
1 C5D4
10UF
1206_R
X5R
25V
10%
1206_R
X5R
25V
10%
1206_R
X5R
25V
10%
1%
0402_R
1
2
2
2
BLEED RESISTORS
AC JACK
R4A12
2.49K
31C2>
U5C1
30C8<
30A8<
IN
8C3>
QFN32
29C4<
28C4<
27D2>
26D3<
16A3<
23
+VDD_MUX
IN
13
VREF2
TPS51220A_RF
2
0402_R
X5R
10V
2 10%
3
RF
29
VREG5
R5C4
200K
11
FUNC
22
VREG3
5%
0402_R
EMPTY
1
2
AGND0
IN
2
2
VOCL ULTRA LOW VOLTAGE
DISCHARGE ENABLE
3D
5%
0603_R
SC70S_R
EMPTY
1
SNN_FAN_TACH
J4A2
4PIN_FAN_R
4
3
FAN HEADER
2
1
1S
I501
2
C
5%
0
EMPTY
29B7<
27A7<
OUT
28C8<
0603_R
X5R
10V
10%
OUT
27A8<
27B8<
28C8<
VREF3 IOUT(MIN)=10MA
VREF3 IOUT(MAX)=20MA
R6B4
0
1
R5B5
TRIP
R5B2
0
5%
0402_R
EMPTY
5%
0
AGND0
R6B7
2
0402_R
12
TPS51220A_REG_EN
REG_EN
+5V_SYS
5%
2
0
EMPTY
1 C6C4
.1UF
2
31D5<
GND
28
30D1<
29D2<
29C1>
26A2<
20D2<
17D2<
16D2<
34D2<
15B7<
33B7<
13D1<
32D4<
IN
+5V_SYS
GND_PAD
33
AGND0
TITLE
V5SW
DC IN
0402_R
X7R
16V
10%
AGND0
Wed Mar 26 14:40:10 2014
7
A
+5V_SYS
ISO6C1
10MIL
1
2
2
0402_R
1
14
TPS51220A_TRIP
1
8
2
3 D
R4A7
0
5%
0402_R
1
31B6>
2
Q4A2
A03415
S23_R
AGND0
+5V_STBY
VOCL LOW VOLTAGE
DISCHARGE ENABLE
+VRTC_LDO_OUT EN PU OPTION??
AS3720_5V_VR_EN
29B8<
28B8<
IN
+3.3V_AON
1 C6C3
2.2UF
R6B3
0
OVP ENABLED
CURRENT MODE
+3.3V_AON
2S
1
G
0805_R
X5R
16V
TPS51220A_FUNC
2
IN
1
5%
0402_R
1
27B4>
28C8<
1%
0402_R
AGND0
R5B1
0
OVP ENABLED
D-CAP MODE
27B8<
POWER_FAN_SRC
R4A11
2.49K
B
2
A
1
0
R4A9
2
5%
G
5%
D
2 10%
+3.3V_AON
27B4>
R4A10
1 C6C5
10UF
1%
0402_R
28C8<
FAN_PWM
Q4A1
RJU003N03
FAN_EN_GATE
2
35D8<
VREF5 W/V5SW=5V IOUT(MIN)=200MA
VREF5 W/V5SW=5V IOUT(MAX)=400MA
+5V_STBY
1
IN
2
34D8<
AGND0
RF[KOHM]=(1X10E+5)/FSW[KHZ]
FSW~500[KHZ]
27A8<
R4A8
29C4<
1 C5B2
.22UF
0805_R
X7R
25V
27B4>
IN
VREF2 IOUT=100UA
+2V_STBY
OUT 28B7<
2 10%
28C8<
1
0402_R
2/2
VIN
PMU_REGEN3
0402_R
1 C5C3
1UF
B
19B8<
U_SWREG_TPS51220
C
2
1
FAN_EN_DR
28C4<
0
1%
0402_R
750-0147-000 FOR 12V BRICK
030-0364-000 FOR AC POWER CORD
27C7<
EMPTY
POWER_FAN
1 C5C11
10UF
26D3<
+5V_SYS
5%
0603_R
1
1
1206_R
X5R
25V
34D8<
R4A5
0
0603_R
2 10%
35D8<
2
VDD_AC_SNUB
I480
16A3<
OUT
1%
0.005
FAN_EN_L
RING 2
D
1
1206_R
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
27
8
7
6
5
4
3
2
1
+3.3V_SYS
32B8<
30D1<
28C1>
26D6<
22D2<
IN
+3.3V_SYS
D
D
CAD NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE LS FET GND
+3.3V_SYS
35D8<
2
OUT
29C8<
R5C3
10K
34D8<
29C4<
27D2>
27C7<
26D3<
16A3<
+VDD_MUX
IN
1 C5C6
10UF
U5C1
1%
0402_R
U_SWREG_TPS51220
27B4>
27A7<
IN
+5V_STBY
1
R5C1
0402_R
C
27B4>
27A8<
27B8<
IN
+3.3V_AON
6
TPS_SKIPSEL
2
1/2
SKIPSEL
DRVH
1
3.3V_MAIN_DRVH_R
1
5%
1
R5C6
0402_R
5
5%
0
S2
PGOOD
SW
EMPTY
31A8<
3.3V_MAIN_PGOOD_R
OUT
VBST
32
31
1
R6C7
2
3.3V_MAIN_VBST_RC
0402_R
5%
0
DRVL
FLOAT EN PIN TO TURN ON
30
3.3V_MAIN_DRVL
2
C6C7
.1UF
6
1
0402_R
X5R
25V
20%
D1
27A8<
31B6>
AS3720_5V_VR_EN
IN
1
R6C5
3.3V_MAIN_RST
0402_R
2
4
R6C12
1
2
1 C6C11
1000PF
0402_R
X7R
50V
2 10%
EN
7
3.3V_MAIN_CS_P
0402_R
X5R
25V
2 20%
+3.3V_SYS
EMPTY
1 RX
2
R6C9
3.48K
1
1
1
R6C11
0
5%
0402_R
R6C1
0402_R
1 C6C10
10UF
0805_R
X5R
16V
2 10%
OUT
22D2<
32B8<
26D6<
28D2<
30D1<
1 C5C10
330UF
DPOS_R
POSCAP
6.3V
2 20%
1
1 RC
2
1%
1.43K
EMPTY
CSP
EMPTY
0402_R
X5R
25V
2 20%
C
SMD
6TPE330MAP
IRMS = 2.4A
ESR = 25MOHM
1 CX
0402_R
X7R
16V
10%
1206_R
X5R
25V
2 10%
1 C6C13
.1UF
L5C2
2
SMD_R
1%
0402_R
3.3V_MAIN_SNUB
S1
1 C6C2
.1UF
2
7.3A
1
5%
0
EMPTY
5%
0805_R
2
G1
1
29B8<
3.3UH
1
2
1 C6C6
.1UF
SPM6530T-3R3M
DCR 27 MOHM TYP
3
3.3V_MAIN_SW
3.3V_MAIN_VBST
2 10%
Q6C2
P2503HEANV
DFN3X3
I87
4
G2
5%
0
QFN32
2
D2
3.3V_MAIN_DRVH
2
0603_R
0
R6C6
1206_R
X5R
25V
5
1
1 C5C7
10UF
2
C5C1
.1UF
1
0402_R
X7R
16V
10%
1
ISO5C2
4MIL
B
B
2
29B7<
27C4>
IN
CSN
+2V_STBY
2
EMPTY
2
R6B9
10K
1 C5B3
150PF
1%
0402_R
1
2
0402_R
C0G
50V
5%
3.3V_MAIN_CS_N
3.3V_MAIN_ISO
EMPTY
2
R5B6
1K
5%
0402_R
3.3V_MAIN_COMP_RC
VFB
EMPTY
1 C6B2
.1UF
0402_R
X7R
16V
R5B7
23.2K
1%
0402_R
1
2 10%
3.3V_MAIN_COMP
A
8
9
1
3.3V_MAIN_VFB
2
IOCL(PEAK)=VOCL*(1/DCR)*(RX+RC)/RC
1%
0402_R
VOCL~60MV
10
COMP
1
IOCL(PEAK)~7.0A, IOCL(AVG) = 6.3A
CX*(RX*RC/(RX+RC))=LX/DCR
LAYOUT NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE LS FET GND
RGV[KOHM]=200XIOUT(MAX)*IOUTMAX*VOUT/IOCL(PEAK*VDROOPMV
R6B8
10K
AGND0
A
TITLE
+3.3V VR
Wed Mar 26 14:40:11 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
28
8
7
6
5
4
3
2
1
+5V_SYS
D
D
31D5<
30D1<
29C1>
27A2<
26A2<
20D2<
17D2<
16D2<
34D2<
15B7<
33B7<
13D1<
32D4<
IN
+5V_SYS
IOCL(PEAK)=VOCL*(1/DCR)*(RX+RC)/RC
VOCL~60MV
IOCL(PEAK)~9.8A
CX*(RX*RC/(RX+RC))=LX/DCR
LAYOUT NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE LS FET GND
35D8<
34D8<
28C4<
27D2>
27C7<
26D3<
16A3<
1 C5C4
10UF
EMPTY
2
C
R5C2
100K
1206_R
X5R
25V
U5C1
1%
0402_R
2 10%
U_SWREG_TPS51220
IN
19
TPS_SKIPSEL
1/2
SKIPSEL
DRVH
24
5V_MAIN_DRVH_R
1
R5C5
2
0603_R
20
D2
5V_MAIN_DRVH
S2
PGOOD
SW
25
VBST
26
5V_MAIN_VBST
1
R5C7
0402_R
2
5%
DRVL
27
5V_MAIN_DRVL
5V_MAIN_VBST_RC
2
C5C8
.1UF
6
1
0402_R
X5R
25V
20%
B
27A8<
31B6>
IN
AS3720_5V_VR_EN
1
R6C4
5V_MAIN_RST
0402_R
2
21
0402_R
X5R
25V
C
0402_R
X5R
25V
2 20%
2 20%
SPM6530T-3R3M
DCR 27MOHM TYP
3.3UH
1
2
D1
EMPTY
R6C3
1K
7.3A
2
5%
0805_R
2
G1
5V_MAIN_SNUB
S1
0402_R
X7R
16V
EN
1
0
+5V_SYS
2
R6C10
0
5%
0402_R
1 C6C9
10UF
2
18
5V_MAIN_CS_P
330UF
31D5<
26A2<
15B7<
17D2<
29D2<
33B7<
DPOS_R
POSCAP
6.3V
2 20%
1
RC
1
R6C2
0402_R
2
1%
1.43K
6TPE330MAP
IRMS = 2.4A
ESR = 25MOHM
CX
CSP
0805_R
X5R
16V
10%
34D2<
30D1<
20D2<
13D1<
16D2<
27A2<
32D4<
OUT
EMPTY
1 C5C9
SMD
RX
EMPTY
5%
SMD_R
R6C8
3.48K
1 C6C1
.1UF
2 10%
L5C1
2
1%
0402_R
1
1
28B8<
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE LS FET GND
1 C6C12
.1UF
3
5V_MAIN_SW
0
FLOAT EN PIN TO TURN ON
1206_R
X5R
25V
2 10%
1 C6C8
.1UF
Q6C1
P2503HEANV
DFN3X3
I227
4
G2
5%
0
QFN32
5V_MAIN_PGOOD_R
1 C5C5
10UF
5
1
28C7>
CAD NOTE:
+VDD_MUX
IN
+5V_SYS
2
C5C2
.1UF
B
1
0402_R
X7R
16V
10%
1
ISO5C1
4MIL
2
28B7<
27C4>
IN
EMPTY
+2V_STBY
CSN
R6B5
10K
1 C5B1
150PF
1%
0402_R
1
2
0402_R
C0G
50V
5%
5V_MAIN_ISO
2
R5B4
1K
5%
0402_R
5V_MAIN_COMP_RC
VFB
EMPTY
16
1
5V_MAIN_VFB
2
1 C6B1
.1UF
0402_R
X7R
16V
10%
5V_MAIN_COMP
R5B3
40.2K
1%
0402_R
1
2
A
5V_MAIN_CS_N
EMPTY
2
2
17
1%
0402_R
IOCL(PEAK)=VOCL*(1/DCR)*(RX+RC)/RC
15
COMP
R6B6
10K
1
VOCL~60MV
A
IOCL(PEAK)~7.0A, IOCL(AVG) = 6.2A
CX*(RX*RC/(RX+RC))=LX/DCR
AGND0
LAYOUT NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE LS FET GND
RGV[KOHM]=200XIOUT(MAX)*IOUTMAX*VOUT/IOCL(PEAK*VDROOPMV
TITLE
+5V VR
Wed Mar 26 14:40:11 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
29
8
7
6
5
4
3
2
1
+5V_SYS
31D5<
29D2<
29C1>
27A2<
26A2<
20D2<
17D2<
16D2<
34D2<
15B7<
33B7<
13D1<
32D4<
IN
+5V_SYS
+3.3V_SYS
D
32B8<
DE-POP WHEN INSTALLED IN CHASSIS
28D2<
28C1>
26D6<
22D2<
IN
+3.3V_SYS
D
+3.3V_RUN
2
+3.3V_RUN
R5E10
330
32D3<
5%
0402_R
30C5>
26D6<
23A2<
22D8<
18D2<
9A2<
IN
+3.3V_RUN
1
1 AN
LED_5V_RUN
CR5E1
GRN
2 CAT
0603_R
2.1V
14MA
EMPTY
1
R5D2
2
0402_R
5%
0
U5D1
SLG5NV1430V
TDFN-6_R
C
+3.3V_SYS
D
D
C
+3.3V_SYS
S
+3.3V_RUN
S
19B8<
30A8<
30A5<
31C2>
32B3<
25C2<
31A8<
IN
PMU_REGEN3
1
R4D2
2
IN
23A2<
26D6<
30D1<
32D3<
EN_RUN_VREG
3.3V_LP0_CAP
R5D1
2
0402_R
1 C4B4
22UF
+5V_SYS
5%
0
1
22D8<
"ENABLE AFTER RTC RAIL IS UP"
0402_R
PMU_REGEN1
18D2<
TEGRA +3.3V SEQUENCING
"ENABLE AFTER RTC RAIL IS UP"
27C4<
31C2>
9A2<
OUT
5%
0
EMPTY
1 C5D3
2200PF
2
7
ON
CAP
VDD
GND
1
8
1 C5D2
.1UF
I321
2
0402_R
X7R
50V
10%
2
FOR RAILS OFF IN LP0
BASED ON PM359
0805_R
X5R
6.3V
2 20%
1 C4B5
.1UF
U4B2
0402_R
X7R
16V
BGA04_R
TPS22908
2 10%
A2 VIN
0402_R
X7R
16V
10%
8C3>
EN_VDD_SD
IN
VOUT A1
B2 ON
+3.3V_SD_CARD
OUT
25B7<
1 C4B6
.1UF
GND B1
0402_R
X7R
16V
2 10%
LOAD SWTICH
I490
B
B
TEGRA +1.8V VDDIO SEQUENCING
EMPTY
1
+1.8V_VDDIO
R2D7
1
C2C2 1
.1UF
EMPTY
0402_R
X7R
16V
10%
2
27C4<
31C2>
19B8<
30C8<
PMU_REGEN3
IN
5%
R2C2
FOR RAILS ON IN LP0
0
0402_R
2
5%
0
U2C1
A
+3.3V VDD GATING
2
0402_R
BGA04_R
TPS22908
A2 VIN
VOUT A1
B2 ON
GND B1
+1.8V VDDIO GATING
FOR RAILS OFF IN LP0
7
U2D1
SLG5NV1430V
TDFN-6_R
+3.3V_SYS
+1.8V_VDDIO_LP0_OFF
OUT
D
9A2<
D
S
S
+3.3V_LP0
OUT
9A2<
10D2<
13D1<
14D1<
15D1<
17D2<
18D2<
19D2<
A
22D2<
+5V_SYS
LOAD SWTICH
I489
32B3<
EMPTY
31C2>
31A8<
30B8<
25C2<
IN
PMU_REGEN1
+VCAP_SLUGO3
1 C9D1
3300PF
2
2
7
ON
CAP
1
8
VDD
GND
I466
0402_R
X7R
50V
10%
2
Wed Mar 26 14:40:12 2014
8
7
6
5
TITLE
1 C2C8
.1UF
4
LOAD SWITCHES
0402_R
X7R
16V
10%
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
30
8
7
30D1<
6
29D2<
29C1>
27A2<
26A2<
20D2<
17D2<
5
16D2<
34D2<
15B7<
33B7<
13D1<
32D4<
4
3
2
1
+5V_SYS
IN
1 C6D6
.1UF
D
0402_R
X7R
16V
D
2 10%
1 C5D16
.1UF
2
31B7>
24B8<
24A8<
31C6<
IN
PMU_REGEN3 AND PMU_REGEN1 MUST BE AT 1.8V LEVELS
FOR SEQUENCE/DISCHARGING
0402_R
X7R
16V
10%
+2.5V_AON_RTC
1
2
18A1>
IN
2
0402_R
5%
0
26A7<
8B2>
26A3<>
8B2<>
1 C4E1
.01UF
C
2
0402_R
X7R
16V
10%
I2C ADDR: 7'H40
BCTT-09
U6D1
BGA
AS3722
31B7>
24B8<
24A8<
31C8<
IN
BI
+2.5V_AON_RTC
IN
1 C6D5
.1UF
PWR_I2C_SCL
PWR_I2C_SDA
1
R6D11
0402_R
0402_R
X7R
16V
1
+1.8V_VDDIO
EMPTY
2
1%
R6D10
10K
R6D12
0402_R
2
SNN_AS3720_SDO
5%
0
2
25D2>
24A6>
26A3<>
IN
0
R5E1
1
ONKEY_L
ONKEY_PMU_L
5%
8B3<
1
8B3<
PMU_INT_L
OUT
LID_CLOSE_PMU_L
TEMP_THERM_PMU
CPU_OC_INT
OUT
29B8<
28B8<
27A8<
AS3720_5V_VR_EN
OUT
SEC 1 OF 3
VSUP_ANA
VSUP_GPIO
VDD_GPIO_LV
G4
F4
E2
H6
SCL_SCLK
SDA_SDI
ENABLE3_SDO
SCSB
B10
C1
D7
D8
E1
ONKEY
XINT
LID
THERM
OC_PWRGD
1
EMPTY
R4A6
0402_R
2
1%
100K
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
D6
G6
D5
E4
B3
C2
B4
D2
IGPU_PWRGD
PMU_REGEN3
PMU_REGEN1
AP_THERMISTOR
EN_AVDD_LCD
TP_CLK_32K_WIFI
SKIN_TEMP
+1.6V_LP0
CLK32K
D1
CLK_32KHZ_PMU_R
C
OUT
OUT
OUT
IN
OUT
8C3<
19B8<
25C2<
33C7<
26D6<
IN
OUT
31A1>
31B1<
27C4<
30A5<
30A8<
30B8<
1
R6D2
AS3720_EN5V
2
0402_R
XIN32K
XOUT32K
G1
G2
XRES_IN
XRES_OUT
J8
L5
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
GNDSENSE
VSS_GPIO
A1
A14
F7
J7
P1
P14
K4
F1
AS3720_XIN32K
AS3720_XOUT32K
PMU_RESET_IN_L
SYS_RESET_L
1
CER_2P_R
I320
R6D9
2
0402_R
32.768KHZ Y6D1
2
30C8<
31A8<
1
R6D5
1
0402_R
B
L6
L7
L8
5%
0
31C6<
24B8<
24A8<
OUT
+2.5V_AON_RTC
2
EMPTY
1 C5D8
1UF
R5D8
200K
1%
0402_R
0402_R
X5R
16V
1
2 10%
AS3720_RBIASJ2
0402_R
X7R
16V
2 10%
1 C6D4
0.014F
2
1 C6D3
.1UF
U5D2
2
28C7>
30A5<
31C2>
32B3<
25C2<
30B8<
3.3V_MAIN_PGOOD_R
IN
PMU_REGEN1
IN
1
R6D3
2
5%
1
0 2
0402_R
5%
R6D4
A
1%
0402_R
0402_R
1
AC_OK_CLK
AC_OK_CLR_L
0
D_FLIP_FLOP_6PIN
SC70_6
R5D3
200K
EMPTY
5
6
CLR*
2
SMD_3225
POLYACENE
2.6V
UNKNOWN
2
J4
R5D6
221K
1%
0402_R
1
V2_5
VBAT_BKUP
26A3<>
22C8<
24B6>
25C5>
8B3< 22A5<
23D7<
IN
OUT
2
R6D6
200K
1%
0402_R
I400
0402_R
C0G
50V
2 +/-0.25PF
1 C6D2
4.7PF
0402_R
C0G
50V
B
2 +/-0.25PF
+1.6V_LP0
I305
EMPTY
2
31C2>
OUT
31C2<
33D8<
R5D4
100K
1
SKIN_TEMP
0402_R
X7R
16V
10%
1 C5D7
56PF
0402_R
C0G
50V
2 5%
EMPTY
IN
1%
0201_R
LAYOUT NOTE:
GNDSENSE NEEDS TO HAVE
A QUIET CONNECTION TO GND
EMPTY
2
1 C6D1
4.7PF
RBIAS
CREF
1 C5D13
.1UF
0402_R
X7R
16V
10%
VCC
3 D
1 CLK
Q 4
GND
1 C5D6
.022UF
2
H2
H4
+VBACKUP
1 C5D14
.022UF
AS3720_CREF
31C8<
EN5V
VBAT
AC_OK
8B3<
OUT
20PPM
12.5PF
5%
+VDD_MUX_AS3720_VBAT
AC_OK_PMU_L
2
CLK_32KHZ_PMU
1%
10
0
+VDD_MUX
32B3<
33D8<
2
0201_R
1%
0402_R
H1
L9
F2
2 10%
100K
EMPTY
1%
100K
+1.8V_VDDIO
1%
0402_R
AP_OVERHEAT_L
2
0402_R
R4E2
100K
1
R4E1
1
EMPTY
R6D8
1
EMPTY
RT5D1
10K
THERM
0402_R
10V
A
2
1
0402_R
X7R
16V
2 10%
TITLE
PMIC: LOGIC AND GPIOS
Wed Mar 26 14:40:12 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
31
8
7
6
5
4
3
2
1
+5V_SYS
30D1<
29D2<
29C1>
27A2<
26A2<
20D2<
17D2<
16D2<
34D2<
15B7<
33B7<
13D1<
31D5<
+5V_SYS
IN
+1.8V_VDDIO
D
24A2<
23A2<
22D2<
22C7<
22B6<
21D2<
20D2<
33A2>
18D2<
26A2<
10D2<
25B7<
8D1<
+1.8V_VDDIO
IN
+3.3V_RUN
23A2<
30D1<
22D8<
30C5>
18D2<
26D6<
9A2<
IN
D
+3.3V_RUN
BCTT-09
U6D1
BGA
AS3722
32B8<
7A8<
6A8<
5B3< 5A8<
33B2>
+1.35V_LP0
IN
B14
SEC 2 OF 3
VIN_LDO0
LDO0
A13 +1.05V_RUN_AVDD
1 C6E6
4.7UF
5D2<
OUT
9C2<
9C4<
14C1<
14C7<
1 C6E7
2.2UF
0402_R
X5R
6.3V
0402_R
X5R
6.3V
2 20%
2 20%
+3.3V_RUN
A8
VIN_LDO1_6
LDO1
LDO6
1 C6D23
4.7UF
2
B9 +1.8V_RUN_CAM
A7 +VDDIO_SDMMC3
0603_R
X5R
6.3V
10%
C
1 C6D20
2.2UF
1 C7D9
2.2UF
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
2
2
9B8<
8A8<
OUT
OUT
26B4<
8B8<
RAIL DISCHARGE
C
+1.8V_VDDIO
+1.8V_VDDIO
A12
VIN_LDO2_5_7
LDO2
LDO5
LDO7
1 C6E4
2.2UF
2
A9
A10
A11
+1.2V_GEN_AVDD
+1.2V_RUN_CAM_FRONT
+1.05V_RUN_CAM_REAR
0402_R
X5R
6.3V
20%
1 C6E2
2.2UF
1 C6E1
2.2UF
1 C6E3
2.2UF
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
0402_R
X5R
6.3V
20%
2
28C1>
26D6<
30D1<
22D2<
28D2<
+3.3V_SYS
IN
A3
33B2>
32D8<
7A8<
6A8<
5B3<
5A8<
IN
B
2
C6D17
2.2UF
34A2>
11D8<
11A1<
IN
B6
2.2UF
+5V_SYS
26B4<
2
A2 +2.8V_RUN_CAM
OUT
31C2>
25C2<
30B8<
PMU_REGEN1
IN
Q5D2
BSS138LT1
1
Q5D1
BSS138LT1
3D
1
G
S23_R
3D
2S
1
G
S23_R
26B7<
PMU_REGEN1_L
R6D1
36
5%
0603_R
R6D7
10K
1%
0402_R
1
2
2S
1 C6D10
2.2UF
0402_R
X5R
6.3V
2 20%
B
1
NMOS
LDO
A4
C6D12
LDO4
VIN_LDO3_LV
0402_R
X5R
6.3V
20%
+VDD_CORE
2
2
14D1<
30A5<
31A8<
PMOS
LDO
0402_R
X5R
6.3V
20%
+1.35V_LP0
2
9C1< 9D8<
26B4<
26B7<
VIN_LDO3_4
1 C6D11
2.2UF
2
OUT
OUT
OUT
PWR
MUX
LDO3
+1.05V_LP0_VDD_RTC
B7
OUT
8C3<
OUT
OUT
26D6<
26B4<
1 C6D19
2.2UF
VIN_LDO3_SW
1
0402_R
X5R
6.3V
0402_R
X5R
6.3V
20%
2 20%
SW
+5V_SYS
A6
VIN_LDO9_10
LDO9
LDO10
1 C6D18
2.2UF
2
+3.3V_RUN_TOUCH
+2.8V_RUN_CAM_AF
A5
B8
1 C6D16
2.2UF
0402_R
X5R
6.3V
20%
1 C6D21
2.2UF
0402_R
X5R
6.3V
0402_R
X5R
6.3V
2 20%
2 20%
+3.3V_RUN
B1
VIN_LDO11
LDO11
B5
1
+1.8V_RUN_VPP_FUSE_R
R5D7
2
0402_R
1 C6D9
2.2UF
A
2
1 C6D13
2.2UF
I128
0402_R
X5R
6.3V
20%
2
+1.8V_RUN_VPP_FUSE
OUT
8A3<
5%
0
A
0402_R
X5R
6.3V
20%
TITLE
PMIC: CNTL, INT SW, LDOS
Wed Mar 26 14:40:13 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
REV
602-7R375-0000-D00
4.02
2
PAGE
1
32
8
31C2>
7
31B1<
IN
6
+1.6V_LP0
5
R6E1
1
4
3
2
1
2
0402_R
1%
100K
D
2
R5E5
100K
D
1%
0402_R
17B1>
1
IN
USB0_ID_PMU
BATT_TS
2
BCTT-09
U6D1
BGA
R5E4
69.8K
1%
0402_R
AS3722
1 EMPTY
31C2<
IN
AP_THERMISTOR
R5D5
1
2
0402_R
SEC 3 OF 3
B11
B12
PWM_CLK2
PWM_DAT2
F8
CORE_PWRREQ
D9
D10
PWM_CLK1
PWM_DAT1
E11
CPU_PWRREQ
5%
0
8B2>
10A3>
10A3<>
IN
IN
IN
CORE_PWR_REQ
DVFS_CLK
DVFS_PWM
1
R5E2
2
0402_R
5%
0
R5E3
DVFS_CLK_ASM
1
2
DVFS_PWM_ASM
0402_R
5%
0
C
8B2>
29D2<
29C1>
27A2<
26A2<
20D2<
17D2<
34D2<
16D2<
32D4<
15B7<
31D5<
13D1<
30D1<
IN
IN
CPU_PWR_REQ
(2A)
+5V_SYS
1 C6D15
10UF
1 C6D14
2.2UF
0805_R
X5R
16V
10%
0603_R
X5R
10V
10%
2
B
(1A)
2
1 C6D7
10UF
2
N6
P6
L1
L2
VSUP_SD2
VSUP_SD2
VSUP_SD3
VSUP_SD3
0805_R
X5R
16V
10%
TEMP2_SD6
TEMP1_SD6
CTRL2_SD6
CTRL1_SD6
FB_SD6_N
FB_SD6_P
L13
L14
C14
C13
G11
F11
AS3722_TEMP2_SD6
AS3722_TEMP1_SD6
AS3722_CTRL2_SD6
AS3722_CTRL1_SD6
VDD_GPU_SENSE_N
VDD_GPU_SENSE_P
TEMP4_SD0
TEMP3_SD0
TEMP2_SD0
TEMP1_SD0
CTRL8_SD0
CTRL7_SD0
CTRL6_SD0
CTRL5_SD0
CTRL4_SD0
CTRL3_SD0
CTRL2_SD0
CTRL1_SD0
FB_SD0_N
FB_SD0_P
K11
K13
J13
J14
H14
H13
G14
G13
F14
F13
E14
E13
J11
H11
SNN_AS3722_TEMP4_SD0
TEMP_SD1
CTRL2_SD1
CTRL1_SD1
FB_SD1_N
FB_SD1_P
K14
D14
D13
H9
G9
LX_SD2
LX_SD2
LX_SD2
LX_SD2
FB_SD2
VSS_SD2
VSS_SD2
VSS_SD2
VSS_SD2
N5
N7
P7
P5
K1
N4
N8
P4
P8
LX_SD3
LX_SD3
LX_SD3
FB_SD3
VSS_SD3
VSS_SD3
VSS_SD3
M1
M2
N1
K2
N3
P2
P3
IN
IN
BI
BI
IN
IN
34B7>
34C7>
34B7<>
34C7<>
11B2>
11B2>
IN
IN
IN
35A7>
35B7>
35C7>
AS3722_CTRL6_SD0
AS3722_CTRL5_SD0
AS3722_CTRL4_SD0
AS3722_CTRL3_SD0
AS3722_CTRL2_SD0
AS3722_CTRL1_SD0
VDD_CPU_SENSE_N
VDD_CPU_SENSE_P
BI
BI
BI
BI
BI
BI
IN
IN
35A7<>
35A7<>
35B7<>
35B7<>
35C7<>
35D7<>
11A2>
11B2>
AS3722_TEMP_SD1
AS3722_CTRL2_SD1
AS3722_CTRL1_SD1
VDD_CORE_SENSE_N
VDD_CORE_SENSE_P
IN
BI
BI
IN
IN
34A7>
34A7<>
34A7<>
11A2>
11A2>
AS3722_TEMP3_SD0
AS3722_TEMP2_SD0
AS3722_TEMP1_SD0
SNN_AS3722_CTRL8_SD0
0.47UH
1
1.35V_LP0_LX
5.5A
1.35V_LP0_FB
L6D1
2
SMD_R
SMD
1 C6D8
22UF
ISO5D1
4MIL
1
2
0805_R
X5R
6.3V
2 20%
(1A)
1 C6D24
10UF
2
VSUP_SD4
VSUP_SD4
LX_SD4
LX_SD4
FB_SD4
VSS_SD4
VSS_SD4
0805_R
X5R
16V
10%
N14
P13
L10
M13
M14
IOUT = 4.5A
IOUT+RIPPLE = 5A
0603_R
X5R
4V
2 20%
1.05V_RUN_LX
3.7A
(1A)
1 C6E5
10UF
2
0805_R
X5R
16V
10%
VSUP_SD5
VSUP_SD5
LX_SD5
LX_SD5
FB_SD5
VSS_SD5
VSS_SD5
N10
P10
J1
N9
P9
L6E2
2
SMDA_R
0805_R
X5R
6.3V
2 20%
1 C5D11
22UF
0805_R
X5R
6.3V
C5D17
1.8V_LP0_LX
1
1.8V_LP0_FB
7
6
5
4
7A8<
32B8<
32D8<
0603_R
X5R
4V
OUT
9D1<
9D2<
14C1<
14C8<
14D2<
19B8<
OUT
32D4<
8D1< 10D2<
18D2<
20D2<
21D2<
22B6<
22C7<
22D2<
23A2<
24A2<
25B7<
26A2<
1 C6E8
22UF
0603_R
X5R
4V
2 20%
SMDA_R
SMD
ISO5D2
1
+1.8V_VDDIO
4MIL
2
1 C5D15
22UF
1 C6D22
22UF
0805_R
X5R
6.3V
20%
0805_R
X5R
6.3V
20%
2
EMPTY
LAYOUT NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
ONE PAIR IS SHOWN HERE, PLEASE REPEAT
FOR SD2, SD3, SD4
8
6A8<
0603_R
X5R
4V
SENSE
+1.05V_RUN
1 C6E9
22UF
2
Wed Mar 26 14:40:13 2014
5B3<
2 20%
L6E1
2
IOUT = 1A
IOUT+RIPPLE = 1.3A
I381
5A8<
1
1.0UH
1
3.7A
OUT
1 C5D9
22UF
ISO5E1
4MIL REMOTE
2
2 20%
EMPTY
0402_R
X5R
16V
10% EMPTY
B
2 20%
SMD
IOUT = 1A
IOUT+RIPPLE = 1.2A
.01UF
N11
P11
1.0UH
1
1
1.05V_RUN_FB
2
A
1 C5D12
22UF
+1.35V_LP0
1 C5D10
22UF
1
N12
P12
C
SNN_AS3722_CTRL7_SD0
TITLE
PMIC: DCDC
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
33
A
8
29C4<
26D3<
27D2>
28C4<
16A3<
27C7<
35D8<
7
6
5
4
3
2
1
+VDD_MUX
IN
+5V_SYS
1 C8D1
10UF
1 C3D4
10UF
1206_R
X5R
25V
10%
1206_R
X5R
25V
10%
2
2
D
D2
E2
F2
+5V_SYS
C1
1.6MMX2.4MMX0.6MM
U8D1
CSP
AS3728
HVSUP4
HVSUP5
HVSUP6
HVSUP1
HVSUP2
HVSUP3
A2
B2
C2
5VSUP
BOOST1
LX11
LX12
LX13
A1
A3
B3
C3
1 C3D2
1UF
2
0402_R
X5R
16V
10%
B1
CTRL1
BOOST2
1 C8D2
10UF
1 C3D5
10UF
1206_R
X5R
25V
10%
1206_R
X5R
25V
10%
2
VDD_GPU_BOOST0
2
C3D1
.1UF
33C3<
BI
AS3722_CTRL1_SD6
E1
OUT
AS3722_TEMP1_SD6
D1
TEMP
D4
E4
F4
PVSS4
PVSS5
PVSS6
CTRL2
LX21
LX22
LX23
D3
E3
F3
PVSS1
PVSS2
PVSS3
A4
B4
C4
29C1>
27A2<
26A2<
20D2<
17D2<
16D2<
33B7<
15B7<
32D4<
13D1<
31D5<
IN
+5V_SYS
VDD_GPU_LX0
VDD_GPU_BOOST1
2
D
1
0402_R
X5R
25V
20%
0.68UH
1
4.7A
F1
29D2<
LAYOUT NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE AS37P018 GND PINS
C3D3
.1UF
33C3<>
2
30D1<
L8D2
2
SMD_R
+VDD_GPU_AP
1 C8D4
47UF
1
0402_R
X5R
25V
20%
1 C3D6
47UF
0805_R
X5R
6.3V
4.7A
11D4<
1206_R
X5R
6.3V
2 20%
2 20%
EMPTY
L8D1
2
SMD_R
11B1<
1 C3D7
47UF
1206_R
X5R
6.3V
2 20%
0.68UH
1
VDD_GPU_LX1
OUT
SMD
SMD
1 C8D3
47UF
0805_R
X5R
6.3V
2 20%
I19
C
1 C3E2
10UF
1 C8D7
10UF
1206_R
X5R
25V
10%
1206_R
X5R
25V
10%
2
2
D2
E2
F2
+5V_SYS
C1
HVSUP4
HVSUP5
HVSUP6
HVSUP1
HVSUP2
HVSUP3
A2
B2
C2
5VSUP
BOOST1
LX11
LX12
LX13
A1
A3
B3
C3
0402_R
X5R
16V
10%
B1
1 C3E1
10UF
1.6MMX2.4MMX0.6MM
U8E1
CSP
AS3728
1 C3E4
1UF
2
C
CTRL1
BOOST2
1 C8D8
10UF
1206_R
X5R
25V
10%
2
1206_R
X5R
25V
2 10%
IF REMOVING PMIC BLOCKS
CTRL2_SD6 MUST ALWAY BE USED!
IE, REMOVE THE OTHER BLOCK FIRST
VDD_GPU_BOOST2
2
C3E5
.1UF
VDD_GPU_LX2
33C3<>
33C3<
BI
OUT
AS3722_CTRL2_SD6
E1
AS3722_TEMP2_SD6
CTRL2
D1
TEMP
D4
E4
F4
PVSS4
PVSS5
PVSS6
0.68UH
1
4.7A
F1
VDD_GPU_BOOST3
2
C3E3
.1UF
B
1
0402_R
X5R
25V
20%
LX21
LX22
LX23
D3
E3
F3
PVSS1
PVSS2
PVSS3
A4
B4
C4
L8D3
2
SMD_R
SMD
1 C8D6
47UF
1
0402_R
X5R
25V
20%
0805_R
X5R
6.3V
4.7A
1 C3D9
47UF
1206_R
X5R
6.3V
2 20%
0.68UH
1
VDD_GPU_LX3
1 C3D8
47UF
1206_R
X5R
6.3V
2 20%
2 20%
SMD_R
B
EMPTY
L8D4
2
SMD
1 C8D5
47UF
0805_R
X5R
6.3V
2 20%
I126
1 C9A4
10UF
1206_R
X5R
25V
2 10%
1 C2A3
10UF
1206_R
X5R
25V
2 10%
+5V_SYS
D2
E2
F2
1 C9A1
1UF
A
2
33B3<>
C1
0402_R
X5R
16V
10%
BI
AS3722_CTRL1_SD1
B1
1 C9A3
10UF
SD1 CORE (8 MAX)
1.6MMX2.4MMX0.6MM
U2A2
CSP
AS3728
HVSUP4
HVSUP5
HVSUP6
HVSUP1
HVSUP2
HVSUP3
A2
B2
C2
5VSUP
BOOST1
LX11
LX12
LX13
A1
A3
B3
C3
CTRL1
BOOST2
1206_R
X5R
25V
2 10%
VDD_CORE_BOOST0
2
C2A1
.1UF
2
C2A2
.1UF
33B3<>
33B3<
BI
OUT
AS3722_CTRL2_SD1
E1
AS3722_TEMP_SD1
CTRL2
D1
TEMP
D4
E4
F4
PVSS4
PVSS5
PVSS6
LX21
LX22
LX23
PVSS1
PVSS2
PVSS3
1
0402_R
X5R
25V
20%
VDD_CORE_LX0
VDD_CORE_BOOST1
D3
E3
F3
VDD_CORE_LX1
1206_R
X5R
25V
2 10%
LAYOUT NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE AS37P018 GND PINS
0.68UH
1
4.7A
F1
1 C2A4
10UF
L2A2
2
SMD_R
+VDD_CORE
SMD
1
0402_R
X5R
25V
20%
1 C2A5
47UF
1 C9A6
47UF
1 C9A5
47UF
0805_R
X5R
6.3V
20%
0805_R
X5R
6.3V
20%
0805_R
X5R
6.3V
20%
2
0.68UH
1
4.7A
2
7
6
2
SMD_R
11D8<
32B8<
PMIC: TK1 GPU AND CORE
SMD
DATE
Mon Apr 07 08:53:07 2014
0805_R
X5R
6.3V
2 20%
5
11A1<
TITLE
1 C2A6
47UF
A4
B4
C4
OUT
EMPTY
L2A1
2
NVIDIA
CONFIDENTIAL
I64
8
A
4
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
34
8
27D2>
27C7<
34D8<
26D3<
29C4<
7
16A3<
28C4<
IN
6
5
4
3
2
1
+VDD_MUX
1 C4D21
10UF
1206_R
X5R
25V
2 10%
1 C7D7
10UF
+5V_SYS
C4D15
1UF
33C3<>
BI
U7D2
CSP
1206_R
X5R
25V
2 10%
D
2
1 C7D3
10UF
1206_R
X5R
25V
AS3728
HVSUP4
HVSUP5
HVSUP6
HVSUP1
HVSUP2
HVSUP3
A2
B2
C2
C1
5VSUP
BOOST1
LX11
LX12
LX13
A1
A3
B3
C3
BOOST2
F1
0402_R
X5R
16V
10%
B1
CTRL1
VDD_CPU_BOOST1
2
C4D13
.1UF
2
C4D17
33C3<
BI
AS3722_CTRL2_SD0
E1
CTRL2
OUT
AS3722_TEMP1_SD0
D1
TEMP
D4
E4
F4
PVSS4
PVSS5
PVSS6
LX21
LX22
LX23
D3
E3
F3
PVSS1
PVSS2
PVSS3
A4
B4
C4
D
1
0402_R
X5R
25V
20%
L7D2
0.68UH
1
4.7A
VDD_CPU_BOOST2
LAYOUT NOTE:
PLACE DCDC INPUT AND OUTPUT CAPS
SO THAT THEIR GNDS HAVE A COMMON SHAPE
WITH THE AS3728 GND PINS
2 10%
VDD_CPU_LX1
.1UF
33C3<>
1206_R
X5R
25V
2 10%
D2
E2
F2
1
AS3722_CTRL1_SD0
1 C4D8
10UF
2
SMD_R
SMD
1
0402_R
X5R
25V
20%
1 C7E1
47UF
L7D3
0.68UH
1
VDD_CPU_LX2
4.7A
2
SMD_R
SMD
0805_R
X5R
6.3V
2 20%
1 C4D7
47UF
1206_R
X5R
6.3V
2 20%
1 C7D5
47UF
0805_R
X5R
6.3V
2 20%
EMPTY
I144
C
C
+VDD_CPU_AP
1 C7E5
10UF
1206_R
X5R
25V
2 10%
1 C4E2
10UF
2
1UF
33C3<>
BI
U7E1
CSP
1206_R
X5R
25V
2 10%
+5V_SYS
C4E5
1 C4E3
10UF
1206_R
X5R
25V
AS3728
HVSUP4
HVSUP5
HVSUP6
HVSUP1
HVSUP2
HVSUP3
A2
B2
C2
C1
5VSUP
BOOST1
LX11
LX12
LX13
A1
A3
B3
C3
1
B1
CTRL1
BOOST2
VDD_CPU_BOOST3
2
C4E6
.1UF
2
C4E4
.1UF
33C3<>
B
33C3<
BI
OUT
AS3722_CTRL4_SD0
AS3722_TEMP2_SD0
E1
CTRL2
D1
LX21
LX22
LX23
D3
E3
F3
PVSS4
PVSS5
PVSS6
0.68UH
1
PVSS1
PVSS2
PVSS3
A4
B4
C4
1206_R
X5R
6.3V
2 20%
1 C4D10
47UF
1206_R
X5R
6.3V
2 20%
1 C4D18
47UF
1206_R
X5R
6.3V
2 20%
EMPTY
L7E1
2
SMD_R
SMD
1
0402_R
X5R
25V
20%
0.68UH
1
VDD_CPU_LX4
4.7A
TEMP
D4
E4
F4
2 20%
OUT
1 C4D19
47UF
11C8<
1
0402_R
X5R
25V
20%
VDD_CPU_LX3
VDD_CPU_BOOST4
1206_R
X5R
6.3V
2 10%
4.7A
F1
1 C4D11
47UF
1206_R
X5R
25V
2 10%
D2
E2
F2
0402_R
X5R
16V
10%
AS3722_CTRL3_SD0
1 C7E4
10UF
11B1<
1 C7D6
47UF
1 C4D6
47UF
1 C7D1
47UF
0805_R
X5R
6.3V
20%
1206_R
X5R
6.3V
20%
0805_R
X5R
6.3V
20%
L7E2
2
SMD_R
SMD
2
2
2
B
EMPTY
I153
1 C4D20
10UF
1206_R
X5R
25V
2 10%
1 C7D8
10UF
2
C4D14
1UF
33C3<>
BI
U7D3
CSP
1206_R
X5R
25V
2 10%
+5V_SYS
A
1 C7D4
10UF
HVSUP4
HVSUP5
HVSUP6
HVSUP1
HVSUP2
HVSUP3
A2
B2
C2
C1
5VSUP
BOOST1
LX11
LX12
LX13
A1
A3
B3
C3
B1
CTRL1
BOOST2
1206_R
X5R
25V
2 10%
D2
E2
F2
1
AS3722_CTRL5_SD0
1206_R
X5R
25V
AS3728
0402_R
X5R
16V
10%
1 C4D9
10UF
VDD_CPU_BOOST5
2 10%
2
C4D16
.1UF
VDD_CPU_LX5
33C3<
BI
OUT
AS3722_CTRL6_SD0
AS3722_TEMP3_SD0
E1
CTRL2
D1
F1
VDD_CPU_BOOST6
2
LX21
LX22
LX23
D3
E3
F3
PVSS1
PVSS2
PVSS3
A4
B4
C4
VDD_CPU_LX6
PVSS4
PVSS5
PVSS6
L7D4
2
SMD_R
SMD
1
0402_R
X5R
25V
20%
0.68UH
1
4.7A
TEMP
D4
E4
F4
A
0.68UH
1
4.7A
C4D12
.1UF
33C3<>
CAN EMPTY TWO PHASES FOR COST SAVINGS
1
0402_R
X5R
25V
20%
1 C7E2
47UF
1 C7D2
47UF
1 C7E3
47UF
0805_R
X5R
6.3V
20%
0805_R
X5R
6.3V
20%
1206_R
X5R
6.3V
20%
L7D1
2
SMD_R
SMD
2
2
7
6
VDD_CPU VR
DATE
Wed Mar 26 14:40:14 2014
EMPTY
NVIDIA
CONFIDENTIAL
I190
8
2
TITLE
5
4
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
35
8
7
6
5
4
3
2
1
REVISION HISTORY
D
D
REVISION 1.00
BOM REVISION D
- RELEASED FAB A
REVISION 1.01
BOM REVISION E
C
-
RELEASED FAB A
UPDATE I2C MAP (P3)
STUFF USB_VBUS_EN(0:1) PULLUPS (P17)
STUFF USB0_VBUS RESISTOR TO 3.3V (P9)
UPDATE EOL HDMI CONN (P13)
CHANGE R5C10 TO 5 MOHM FOR COST SAVINGS (P27)
CHANGE R3E5 -> 100K OHM; SATA POWER DIVIDER (P16)
CHANGE DFF CLEAR (P31)
CHANGE PMIC TO OTP TYPE 9 (P31-33)
EMPTY C4B2, EXCESS BYPASS FOR 3.3V SD CARD (P30)
CHANGE SLEW RATE CAP C9D1 TO 3.3NF (P30)
EMPTY 3.3V RESISTORS ON GEN2_I2C, STUFF 1.8V (P10)
EMPTY R2D6 & R2D8, ADD R2D7 FOR LAN ISOLATEB (P19)
BYPASS & EMPTY LOAD SWITCH U2C1 (P30)
C
REVISION 2.00
BOM REVISION B
B
-
CHANGE RC ON DFF W/ CLOCK OPTIONS (P28,31)
WIRE GPIO_PK2 TO EXPANSION HDR (P10, P26)
WIRE +5V_SYS TO R2A5 (P25)
RESIZE 0 OHM BYPASS RESISTORS TO 0402 (P30)
CHANGE GEN2 I2C PULLUPS TO +3.3V_LP0 (P10)
RESIZE FAN RESISTORS (P27)
REWIRE ISOLATEB ON LAN (P19)
DIRECT WIRE VDD_GPIO_LV TO +1.8V_VDDIO (P31)
REPLACE POWER FETS ON 3.3V SWITCHER (P28)
REPLACE SD CARD SWITCH (P30)
EMPTY USB ESD PROTECTION (P17)
EMPTY SD ESD PROTECTION (P25)
ADD BLEED RESISTORS ON DC INPUT (P27)
SIMPLIFY FEEDBACK, DROP BLEED RESISTORS (P11)
TUNE +5V_SYS & +3V3_SYS FOR 3.3UH INDUCTORS (P27-29)
ADD DEBUG CONNECTOR (P22)
ADD TEMP SENSOR BUFFERING OPTIONS (P18)
RELEASED FAB B
B
REVISION 3.00
BOM REVISION A
-
MODIFY EXPANSION HEADER (P11,P26)
STUFF FRONT PANEL HEADER (P25)
CHANGE AUDIO HEADER TO LIME/PINK (P21)
RELEASED FAB C
REVISION 4.00
A
REWIRE ONKEY TO KB_COL0 FET (P24)
REMOVE LED DIODE (P25)
UART4 INPUTS STUFFING OPTIONS (P24)
ADD EMI CAP (P21)
ADD EMI CAP ON VDD_MUX (P29)
REPLACE EOL SNUBBERS (P24)
ADD PMU_REGEN3 OPTION FOR LAN (P21)
RELEASED FAB D
A
REVISION 4.01
- COSMETIC COMMENT CLEANUP (MULTIPLE PAGES)
- REPLACE Q4E2 (P24)
- RELEASE BOM B FAB D
REVISION 4.02
-
ADJUST SEQUENCE ON SD5 (P2)
ADD FRONT PANEL NOTE - YELLOW STDBY LED (P25)
REPLACE Q9A1, Q9A2 - AVAILABILITY (P9)
REPLACE J1A1 - AVAILABILITY (P25)
RELEASE BOM E FAB D
TITLE
REVISION HISTORY
Wed May 07 10:30:25 2014
8
7
6
5
4
NVIDIA
CONFIDENTIAL
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
36
8
D
7
Title:
Basenet Report
Design:
beaver_t124_fabd
Date:
May 7 10:45:19 2014
A
+3.3V_RUN
4
3
2
30C5> 30D1< 32D3<
3.3V_MAIN_VBST_RC
28C5
9B3 9D2 18B4 23D4 25D4 30D5 32A7
3.3V_MAIN_VFB
28B5
32C7 9A2< 18D2< 22D8< 23A2< 26D6<
3.3V_RUN_AVDD_HDMI_A 9D3
30C5> 30D1< 32D3<
P_EN_L
9B3 9D2 18B4 23D4 25D4 30D5 32A7
5V_MAIN_COMP
29A7
beaver_t124_lib.BEAVER_T124_FABD(@beaver_t124_lib.beaver
32C7 9A2< 18D2< 22D8< 23A2< 26D6<
5V_MAIN_COMP_RC
29A7
_t124_fabd(sch_1))
30C5> 30D1< 32D3<
5V_MAIN_CS_N
29B5
+3.3V_RUN_TOUCH
26D6< 32B5>
5V_MAIN_CS_P
29B5
+3.3V_SD_CARD
25B7< 30B1>
5V_MAIN_DRVH
29C5
Location([Zone][dir])
+1.2V_GEN_AVDD
9C1< 9D8< 14D1< 26B4< 32C4>
+3.3V_SYS
22D2< 26D6< 28C1> 28D2< 30D1< 32B8<
5V_MAIN_DRVH_R
29C5
+1.2V_RUN_CAM_FRONT
26B4< 32C4>
+5V_HDMI
13A5
5V_MAIN_DRVL
29B5
+1.05V_LAN_REGOUT
19B3
+5V_HDMI_CON
13A4
5V_MAIN_ISO
29B2
+1.05V_LAN_REGOUT_L
19C4
+5V_SATA
16C2
5V_MAIN_PGOOD_R
29C7
+1.05V_LP0_VDD_RTC
8C3< 32B5>
+5V_STBY
27A7< 27B4> 28C8<
5V_MAIN_RST
29B7
+1.05V_RUN
9D1< 9D2< 14C1< 14C8< 14D2< 19B8<
+5V_SYS
13D1< 15B7< 16D2< 17D2< 20D2< 26A2<
5V_MAIN_SNUB
29B4
33A2>
27A2< 29C1> 29D2< 30D1< 31D5< 32D4<
5V_MAIN_SW
29C5
5D2< 9C2< 9C4< 14C1< 14C7< 32D5>
33B7< 34D2<
5V_MAIN_VBST
29B5
+1.05V_RUN_AVDD
B
5
Base nets and synonyms for
Base Signal
C
6
D
+1.05V_RUN_AVDD_HDMI 9C3
+5V_USB_HS
17B5
5V_MAIN_VBST_RC
29B5
_PLL_AP
+12V_SATA
16B2
5V_MAIN_VFB
29A5
+1.05V_RUN_AVDD_HDMI 9D5
+AVDD_LVDS0_PLL_AP_F 9B4
AC_OK_AP_L
10B4
_PLL_AP_GATE
+EMMC_VDDI
23C4
AC_OK_CLK
31A7
+1.05V_RUN_AVDD_PEX_ 14C3
+USB0_VBUS_SW
17C4
AC_OK_CLR_L
31A7
PLL_AP_F
+VBACKUP
31B5
AC_OK_PMU_L
31B5
+1.05V_RUN_AVDD_SATA 14C7
+VCAP_SLUGO3
30A5
AP_FORCE_RECOVERY_L
10C3< 24D5>
_PLL_F
+VDDIO_SDMMC3
8A8< 8B8< 32C5>
AP_OVERHEAT_L
18A1> 31C8<
C
+1.05V_RUN_CAM_REAR
26B7< 32C4>
+VDD_1V5_MPCIE
15B4
AP_OVERHEAT_R_L
18A3
+1.6V_LP0
31B1< 31C2> 33D8<
+VDD_ACIN
27D5
AP_OVRHT_G
18A3
+1.8V_LP0_AVDD_OSC_A 8A4
+VDD_CORE
11A1< 11D8< 32B8< 34A2>
AP_THERMISTOR
31C2< 33C7<
P_F
+VDD_CPU_AP
11B1< 11C8< 35C2>
AS3720_5V_VR_EN
27A8< 28B8< 29B8< 31B6>
+1.8V_RUN_AVDD_PLL_U 9A5
+VDD_GPU_AP
11B1< 11D4< 34D2>
AS3720_CREF
31A4
TMIP_AP_F
+VDD_MIC
20B4
AS3720_EN5V
31B5
+VDD_MUX
16A3< 26D3< 27C7< 27D2> 28C4< 29C4<
AS3720_RBIAS
31B5
34D8< 35D8<
AS3720_XIN32K
31B3
+1.8V_RUN_CAM
9B8< 26B4< 32C5>
+1.8V_RUN_VPP_FUSE
8A3< 32A4>
B
+1.8V_RUN_VPP_FUSE_R 32A5
+VDD_MUX_AS3720_VBAT 31B5
AS3720_XOUT32K
31B3
+1.8V_VDDIO
8D1< 10D2< 18D2< 20D2< 21D2< 22B6<
1.05V_RUN_AVDD_HDMI_ 9C3
AS3722_CTRL1_SD0
33C3<> 35D7<>
22C7< 22D2< 23A2< 24A2< 25B7< 26A2<
PLL_AP_EN_L
AS3722_CTRL1_SD1
33B3<> 34A7<>
32D4< 33A2>
1.05V_RUN_FB
33A4
AS3722_CTRL1_SD6
33C3<> 34C7<>
+1.8V_VDDIO_LP0_OFF
9A2< 30A6>
1.05V_RUN_LX
33A4
AS3722_CTRL2_SD0
33C3<> 35C7<>
+1.35V_LP0
5A8< 5B3< 6A8< 7A8< 32B8< 32D8<
1.8V_LP0_FB
33A4
AS3722_CTRL2_SD1
33B3<> 34A7<>
33B2>
1.8V_LP0_LX
33A4
AS3722_CTRL2_SD6
33C3<> 34B7<>
+1.35V_LP0_VDDIO_DDR 5B3
1.35V_LP0_FB
33B4
AS3722_CTRL3_SD0
33C3<> 35B7<>
_MCLK_AP
1.35V_LP0_LX
33B4
AS3722_CTRL4_SD0
33C3<> 35B7<>
+2.5V_AON_RTC
24A8< 24B8< 31B7> 31C6< 31C8<
1P5V_EN
15B5
AS3722_CTRL5_SD0
33C3<> 35A7<>
+2.8V_RUN_CAM
26B7< 32B4>
3.3V_LP0_CAP
30B7
AS3722_CTRL6_SD0
33C3<> 35A7<>
+2.8V_RUN_CAM_AF
26B4< 32A5>
3.3V_MAIN_COMP
28A7
AS3722_TEMP1_SD0
33C3< 35C7>
+2V_STBY
27C4> 28B7< 29B7<
3.3V_MAIN_COMP_RC
28B7
AS3722_TEMP1_SD6
33C3< 34C7>
+3.3V_342
22D7
3.3V_MAIN_CS_N
28B5
AS3722_TEMP2_SD0
33C3< 35B7>
+3.3V_AON
27A8< 27B4> 27B8< 28C8<
3.3V_MAIN_CS_P
28B5
AS3722_TEMP2_SD6
33C3< 34B7>
+3.3V_AVDD_HDMI_AP_G 9D5
3.3V_MAIN_DRVH
28C5
AS3722_TEMP3_SD0
33C3< 35A7>
ATED
3.3V_MAIN_DRVH_R
28C5
AS3722_TEMP_SD1
33B3< 34A7>
9A2< 10D2< 13D1< 14D1< 15D1< 17D2<
3.3V_MAIN_DRVL
28C5
AUD1_VREF1
20B4
18D2< 19D2< 22D2< 30A3>
3.3V_MAIN_ISO
28B2
AUD1_VREF2
20B4
9B3 9D2 18B4 23D4 25D4 30D5 32A7
3.3V_MAIN_PGOOD_R
28C7> 31A8<
AUDIO_AVDD
20B4
32C7 9A2< 18D2< 22D8< 23A2< 26D6<
3.3V_MAIN_RST
28B7
AUDIO_DACREF
20B4
30C5> 30D1< 32D3<
3.3V_MAIN_SNUB
28C4
AUDIO_GND
20A1 20A1 20A2 20A2 20A3 20A3 20A3
9B3 9D2 18B4 23D4 25D4 30D5 32A7
3.3V_MAIN_SW
28C5
32C7 9A2< 18D2< 22D8< 23A2< 26D6<
3.3V_MAIN_VBST
28C5
+3.3V_LP0
+3.3V_RUN
7
6
5
A
TITLE
? 20B2 20B2 20B2 20B3 20B3
20A3 20A6
NVIDIA
CONFIDENTIAL
<->
8
1
4
3
20C3 20C3
21A5 21A5 21A5 21B4
DOC21A4
NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
37
8
D
C
B
A
7
6
5
4
3
2
21B5 21C4
CSI_E_CLK_P
9C8> 26B4<
DDR_DQS5N
5A7<> 7C4<
AUDIO_LDO_EN
8C3> 20B7<
CSI_E_D0_N
9C8< 26B4>
DDR_DQS5P
5A7<> 7C4<
AUD_DCVDD
20A4
CSI_E_D0_P
9C8< 26B7>
DDR_DQS6N
5B7<> 7C8<
BATT_TS
33D7
DACDAT2
20C6
DDR_DQS6P
5B7<> 7C8<
BCLK2
20B6
DAP2_DIN
10B7< 20C8>
DDR_DQS7N
5A7<> 7C4<
BD_ID_STRAP0
8D3< 24A3>
DAP2_DIN_R
20C7
DDR_DQS7P
5A7<> 7C4<
BD_ID_STRAP1
8C3< 24A3>
DAP2_DOUT
10B7> 20C8<
DDR_RAS_L
4B3> 6C4< 6C8< 7C4< 7C8<
BD_ID_STRAP2
10A3< 24A3>
DAP2_FS
10A7> 20C8<>
DDR_RESET_L
4B3> 6B4< 6B8< 7B4< 7B8<
BD_ID_STRAP3
10A3< 24A3>
DAP2_SCLK
10A8> 20C8<>
DDR_WE_L
4B3> 6C4< 6C8< 7C4< 7C8<
BOARD_ID_A0
18D5
DAP2_SCLK_R
10A6
DDR_ZQ0_U27U1
6B7
BOARD_ID_A1
18D5
DAP_MCLK1
10B8> 20B7<
DDR_ZQ0_U27U2
6B3
BOARD_ID_A2
18D5
DAP_MCLK1_R
10B6
DDR_ZQ0_U28U1
7B7
BOARD_ID_WP
18D5
DDR0_CKE0
4B4> 6C4< 6C8<
DDR_ZQ0_U28U2
7B3
BR_UART1_RXD
8C3< 22C7<> 26B7>
DDR0_CKE1
4B4> 6C4< 6C8<
DDR_ZQ1_U27U1
6B7
BR_UART1_TXD
8C3> 22C7<> 26B4<
DDR0_CLKN
4D1> 6C4< 6C8<
DDR_ZQ1_U27U2
6B3
C1N
18C4
DDR0_CLKP
4D1> 6C4< 6C8<
DDR_ZQ1_U28U1
7B7
C1P
18C4
DDR0_CLK_TERM
4C3
DDR_ZQ1_U28U2
7B3
C2N
18C4
DDR0_CS0_L
4B4> 6B4< 6B8<
DEBUGGER_RESET_L
22C7
C2P
18C4
DDR0_CS1_L
4B4> 6B4< 6B8<
DP_AUX_N
9B3<> 26D6<>
CAM1_AF_PWDN
9A7> 26A7<
DDR0_ODT0
4A4> 6B4< 6B8<
DP_AUX_P
9B3<> 26D6<>
CAM1_GPIO
9B7<> 26A7<>
DDR0_ODT1
4A4> 6B4< 6B8<
DSI_CSI_RDN
9B7
CAM1_MCLK
9A7> 26A7<
DDR1_CKE0
4A4> 7C4< 7C8<
DSI_CSI_RUP
9B7
CAM1_PWDN
9A7> 26A7<
DDR1_CKE1
4A4> 7C4< 7C8<
DSR
18C2
CAM2_GPIO
9B7<> 26B3<>
DDR1_CLKN
4C1> 7C4< 7C8<
DTR
18B2
CAM2_MCLK
9B7> 26B4<
DDR1_CLKP
4C1> 7C4< 7C8<
DVFS_CLK
10A3> 33C7<
CAM2_PWDN
9A7> 26B7<
DDR1_CLK_TERM
4C2
DVFS_CLK_ASM
33C6
CAM_FLASH
9A7> 26A7<
DDR1_CS0_L
4B4> 7B4< 7B8<
DVFS_PWM
10A3<> 33C7<
CAM_I2C_SCL
9A8> 26B4<
DDR1_CS1_L
4B4> 7B4< 7B8<
DVFS_PWM_ASM
33C6
CAM_I2C_SDA
9A8<> 26B7<>
DDR1_ODT0
4A4> 7B4< 7B8<
EDP_HPD
9B2< 26C6>
CAM_RST_L
9B7> 26B4<
DDR1_ODT1
4A4> 7B4< 7B8<
EN_AVDD_HDMI
9D2
CAP_SLG_5V_SAT
16B3
DDR_A0<5..3>
4C3> 6D4< 6D8<
EN_AVDD_HDMI_PLL
9C3
CHGPUMP_N1
20B4
DDR_A1<5..3>
4C3> 7D4< 7D8<
EN_AVDD_LCD
26D6< 31C2>
CHGPUMP_N2
20B4
DDR_A<15..0>
4C3> 6B4< 6B8< 6D4< 6D8< 7B4< 7B8<
EN_RUN_VREG
30C7
CHGPUMP_P1
20B4
7D4< 7D8<
EN_VDD_12V_DRAIN
16A2
CHGPUMP_P2
20B4
DDR_BA<2..0>
4B3> 6C4< 6C8< 7C4< 7C8<
EN_VDD_12V_GATE
16A3
CLK3_OUT
10C7> 26A4<
DDR_CAS_L
4B3> 6C4< 6C8< 7C4< 7C8<
EN_VDD_BL
8C7> 26D3<
CLK3_OUT_R
10C6
DDR_COMP_PD
5A6
EN_VDD_HDMI
9C1< 9D1< 10A7<> 13A8<
CLK_32KHZ_PMU
8B3< 31B1>
DDR_COMP_PU
5A6
EN_VDD_SD
8C3> 30B4<
CLK_32KHZ_PMU_R
31B3
DDR_DM0
4B7> 6C8<
FAN_EN_DR
27C3
CODEC_IRQ_L
10C3< 20B7>
DDR_DM1
4A7> 6C4<
FAN_EN_GATE
27C3
CORE_PWR_REQ
8B2> 33C7<
DDR_DM2
4B7> 6C8<
FAN_EN_L
27D3
CPU_OC_INT
8B3< 31B7>
DDR_DM3
4A7> 6C4<
FAN_PWM
8C3> 27C4<
CPU_PWR_REQ
8B2> 33C7<
DDR_DM4
5A7> 7C8<
FB_1PV5
15B5
CPVDD
20B4
DDR_DM5
5A7> 7C4<
FORCE_RECOVERY_L
22C7< 24D5<> 26A3<>
CPVEE
20B4
DDR_DM6
5A7> 7C8<
FP_9
25D5
CPVPP
20B4
DDR_DM7
5A7> 7C4<
GEN1_I2C_SCL
10B8> 18A6< 18D3< 20B7< 22C4< 26A7<
CSI_A_CLK_N
9D8> 26B7<
DDR_DQ<63..0>
4D8<> 5C7<> 6D1<> 6D4<> 7D1<> 7D5<>
CSI_A_CLK_P
9C8> 26B7<
DDR_DQS0N
4B7<> 6C8<
GEN1_I2C_SCL_3.3V
15C3< 22C1>
CSI_A_D0_N
9D8< 26B7>
DDR_DQS0P
4B7<> 6C8<
GEN1_I2C_SDA
10B8<> 18A6<> 18D3<> 20B7<> 22C4<>
CSI_A_D0_P
9D8< 26B7>
DDR_DQS1N
4A7<> 6C4<
CSI_A_D1_N
9D8< 26B7>
DDR_DQS1P
4A7<> 6C4<
GEN1_I2C_SDA_3.3V
15C3<> 22C1<>
CSI_A_D1_P
9D8< 26B7>
DDR_DQS2N
4B7<> 6C8<
GEN2_I2C_SCL_3.3V
10B1> 26D6<
CSI_B_D0_N
9C8< 26A7>
DDR_DQS2P
4B7<> 6C8<
GEN2_I2C_SDA_3.3V
10B1<> 26D6<>
CSI_B_D0_P
9C8< 26B7>
DDR_DQS3N
4B7<> 6C4<
GND
4C2 4C3TITLE
5A6 5B4 5B4 5C4 5C4 5D4 6A2
CSI_B_D1_N
9C8< 26B7>
DDR_DQS3P
4B7<> 6C4<
6A3 6A6 6A7 6A7 6A7 6A8 6A8 6B4 6B4
CSI_B_D1_P
9C8< 26B7>
DDR_DQS4N
5A7<> 7C8<
6B5 6B8?6B8 7A2 7A3 7A6 7A7 7A7 7A7
CSI_E_CLK_N
9C8> 26B4<
DDR_DQS4P
5A7<> 7C8<
7
6
5
D
C
B
26D3<
A
26A3<> 26D3<>
NVIDIA
CONFIDENTIAL
<->
8
1
4
3
7A8 7A8DOC
7B4 NUMBER
7B4 7B6 7B8 7B8 8A3 8A3
602-7R375-0000-D00
2
REV
PAGE
4.02
1
38
8
D
C
B
A
7
6
5
4
2
8A4 8A4 8A4 8A4 8A6 8A7 8A7 8A7 8B3
GPIO_PG3
10C3<> 24D1>
JTAG_PD0
22A2
8B7 8B7 8B7 8C4 8C6 8C7 8D3 8D3 8D4
GPIO_PH7
9C1< 10C3<>
JTAG_PD1
22A2
8D4 8D6 8D6 8D8 9A3 9A3 9A4 9A4 9A4
GPIO_PI0
10C3> 24C5>
JTAG_RTCK
8A3< 22A4< 22C7>
9A4 9A4 9A7 9A7 9A7 9B4 9B4 9B4 9B4
GPIO_PK2
10B3> 26D3<
JTAG_SRST_B_L
22A2
9B7 9B7 9B8 9C2 9C3 9C3 9C3 9C4 9D3
GPIO_PU0
10C6<> 26B3<>
JTAG_SRST_L
22A4
9D3 9D4 9D4 9D4 9D7 9D7 10B2 10B3
GPIO_PU1
10C6<> 26B3<>
JTAG_TCK
8A3< 22A4> 22C7>
10B6 10B7 10D3 10D3 10D3 10D3 10D6
GPIO_PU2
10B6<> 26B3<>
JTAG_TDI
8A3< 22A4> 22C7>
10D7 11A4 11A4 11A8 11A8 11B4 11B8
GPIO_PU3
10B6<> 26A3<>
JTAG_TDO
8A3> 22A4< 22C7<
11B8 11C4 11C4 11C8 11D8 12A3 12A4
GPIO_PU4
10B6<> 26A3<>
JTAG_TMS
8A3< 22A4> 22C7>
12A6 12A6 12A6 12A7 12B6 12B6 12B6
GPIO_PU5
10B6<> 26A3<>
JTAG_TRST_L
8A3< 22C7<
12B7 13A4 13A4 13A5 13A7 13A7 13B4
GPIO_PU6
10B6<> 26A3<>
KB_COL0_AP
8D3< 24A5>
13B4 13C3 13C4 13C5 13C6 13C7 13D4
GPIO_PV0
8C7
KB_COL0_GATE
24A6
13D5 14A1 14A2 14C2 14C2 14C2 14C2
GPIO_PV1
8C7
LAN_CH_GND
19A1
14C3 14C3 14C3 14C3 14C6 14C6 14C6
GRN_PWRLED
25D4
LAN_ISOLATE
19B7
14C6 14C7 14D2 14D3 14D6 14D6 14D7
HDLED_L
25D5
LAN_ISOLATE_L
19B6
15B4 15B4 15B4 15B5 15B5 15B5 15B6
HDLED_PWR
25D5
LAN_ISO_BASE
19B7
15B6 15C2 15C2 15C3 15C4 16A2 16A2
HDMI_CEC
9C4<> 13C7<>
LAN_LED0
19A4
16A3 16B1 16B2 16B2 16B2 16B3 16B4
HDMI_CEC_A_PU
13B5
LAN_LED0_ACT_L
19A3
16C1 16C3 17A1 17A2 17A4 17A4 17A5
HDMI_CEC_CON
13C4
LAN_LED1
19A4
17A6 17B2 17B2 17B3 17B3 17B5 17B5
HDMI_CEC_L
13C5
LAN_LED2
19A4
17B5 17B5 17B6 17B6 17B7 17B8 17C1
HDMI_DDC_SCL
9C4> 13B7<
LAN_LED_100
19A3
17C3 17C5 17C6 17C6 17C6 17C7 17D3
HDMI_DDC_SCL_CON
13B5
LAN_LED_1000
19A3
17D6 18A2 18A3 18A4 18A4 18B2 18B3
HDMI_DDC_SDA
9C4<> 13B7<>
LAN_MDI0_N
19B4
18B4 18B5 18B6 18B6 18B7 18C3 18C4
HDMI_DDC_SDA_CON
13B5
LAN_MDI0_P
19B4
18C5 18C5 18C5 18C7 18D3 19A1 19A2
HDMI_FAULT_L
13A6
LAN_MDI1_N
19A4
19A2 19A3 19A5 19A6 19A6 19B3 19B3
HDMI_HPD
13D4
LAN_MDI1_P
19A4
19B4 19B4 19B4 19B4 19B4 19B4 19B6
HDMI_ILIM
13A6
LAN_MDI2_N
19A4
19B6 19C3 19C4 19C4 19C4 19C4 19C4
HDMI_INT
9C4< 13D5>
LAN_MDI2_P
19A4
20A4 20A4 20A4 20A4 20A4 20A4 20A5
HDMI_RSET
9C5
LAN_MDI3_N
19A4
20A6 20B7 20B7 20B7 21A3 21A6 21B5
HDMI_TXC_N
9C4> 13C8<
LAN_MDI3_P
19A4
22A1 22A1 22A2 22A2 22A2 22A3 22A3
HDMI_TXC_P
9C4> 13C8<
LAN_RSET
19A4
22A4 22A5 22B5 22B6 22B7 22C2 22C3
HDMI_TXD_N<2..0>
9C3> 13D8<
LAN_TRCT1
19B1
22C3 22C6 22C6 22D7 23A5 23B4 23C4
HDMI_TXD_P<2..0>
9C3> 13D8<
LCD_BL_EN
10C3> 26C6<
23C4 23C4 23C4 23D4 23D4 24A4 24A4
HEADSET1RC_L
20C3
LCD_BL_PWM
10C3> 26C6<
24A4 24A4 24A6 24A6 24A7 24A8 24A8
HEADSET1RC_R
20C3
LCD_LR
10C3> 24D1>
24B4 24B7 24B7 24B8 24C4 24C7 24C7
HEADSET1R_L
20C4
LCD_TE
8C3> 26C3<
24C8 25A4 25A4 25A4 25A5 25A6 25C3
HEADSET1R_R
20C4
LCD_UD
10C3> 24D1>
25C4 25C5 25D5 25D6 26A5 26A5 26C5
HEADSET_MIC_C
20B7< 21C8>
LED_5V_RUN
30D5
26C5 26C5 26C5 27A4 27A5 27A6 27B5
HEAD_DET_JACK_L
21B4
LID_CLOSED_L
8C4
27C2 27C3 27C5 27C6 27D3 27D3 27D3
HEAD_DET_L
20B7< 21B7>
LID_CLOSE_PMU_L
31B5
27D4 27D4 27D6 28B4 28B4 28B7 28C2
HEAD_DET_T124_L
8C3< 21B7>
LRCK2
20B6
28C2 29B2 29B4 29B4 29C3 30A4 30A4
HP1_LT
20C2> 21A7<
LVDS_RSET
9B5
30A5 30A7 30A8 30B2 30B2 30B4 30B6
HP1_LT_L
21A5
LVDS_TXD0_N
9B3> 26C3<
30B6 30B7 30C5 31A2 31A4 31A5 31A5
HP1_MIC_L
21C6
LVDS_TXD0_P
9B3> 26D3<
31A5 31A6 31A6 31A7 31B1 31B3 31B3
HP1_MIC_R
21C5
LVDS_TXD1_N
9B3> 26C6<
31B5 31B5 31C3 31C4 31C4 31C5 31C6
HP1_RT
20C2> 21A7<
LVDS_TXD1_P
9B3> 26C6<
31C7 31D5 32A5 32A5 32A6 32A7 32A7
HP1_RT_L
21A5
LVDS_TXD2_N
9B3> 26C6<
32B1 32B2 32B5 32B5 32B5 32B5 32B6
HP1_SENSE
20C4< 21A7>
LVDS_TXD2_P
9B3> 26C6<
32B7 32B7 32B7 32C5 32C6 32C6 32C7
HSIC1_DATA
9A8> 26B3<>
LVDS_TXD3_N
9B3> 26C3<
32C7 32C7 33A3 33A3 33A4 33A6 33A6
HSIC1_DATA_R
9A7
LVDS_TXD3_P
9B3> 26C3<
33B3 33B3 33B6 33B6 33B6 33C7 34A3
HSIC1_STROBE
9A8> 26B4<
LVDS_TXD4_N
9B3> 26C3<
34A4 34A5 34A5 34A6 34A7 34A7 34B3
HSIC1_STROBE_R
9A7
LVDS_TXD4_P
9B3> 26C3<
34B4 34B5 34B6 34B6 34C3 34C4 34C5
HSIC_REXT
9A7
LV_SATA_EN
16B3
34C5 34C6 34C7 34D5 34D6 34D7 35A4
IGPU_PWRGD
8C3< 31C2>
MIC1_BIAS
20B2> 21C5<
TITLE
35A5 35A5 35A6 35A7 35A7 35B2 35B4
JD_MIC_L
20A7< 21C7>
MIC1_BIAS_R
20B4
35B5 35B6 35B7 35C4 35C5 35C5 35C6
JD_MIC_R_L
21C4
MODEM_SAR0
10C3<> ?
24D1>
35C7 35D5 35D7 35D7
JD_MIC_T124_L
8D3< 21C7>
ONKEY_L
24A6> 25D2>
26A3<> 31C6<
DOC NUMBER
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<->
8
3
7
6
5
4
3
1
D
C
B
A
602-7R375-0000-D00
2
REV
PAGE
4.02
1
39
8
D
C
B
A
7
6
5
4
3
2
ONKEY_PMU_L
31B5
SATA_RX_P
16C2
SNN_DSI_B_D0_N
9B7
PCA9306_VREF21
22C2
SATA_TERMP
14C6
SNN_DSI_B_D0_P
9B7
PEX0_WAKE_R_L
19B6
SATA_TESTCLKN
14C7
SNN_DSI_B_D1_N
9B7
PEX_CLK1_N
14B3> 15D7<
SATA_TESTCLKP
14C7
SNN_DSI_B_D1_P
9B7
PEX_CLK1_P
14B3> 15D7<
SATA_TX_N
16D2
SNN_DSI_B_D2_N
9B7
PEX_CLK2_N
14A3> 19C7<
SATA_TX_P
16D2
SNN_DSI_B_D2_P
9B7
PEX_CLK2_P
14B3> 19C7<
SDMMC1_COMP_PD
8B6
SNN_DSI_B_D3_N
9B7
PEX_GIGE_PRSNT_L
8D7
SDMMC1_COMP_PU
8B6
SNN_DSI_B_D3_P
9B7
PEX_L0_CLKREQ_L
14A2< 15D7>
SDMMC2_COMP_PD
10B4
SNN_EN_BAT_SMB
10A6
PEX_L0_RST_L
14A3> 15C3<
SDMMC2_COMP_PU
10B4
SNN_FAN_TACH
27C2
PEX_L1_CLKREQ_L
14A2< 19C7>
SDMMC3_CD_L
8A8< 25A7>
SNN_GPIO_PFF2
14A4
PEX_L1_RST_L
14A3> 19C7<
SDMMC3_CLK
8B8> 25B7<
SNN_GPIO_PH3
10C4
PEX_MINI_PRSNT_L
8D7
SDMMC3_CLK_LB_IN
8A7
SNN_GPIO_PI4
10B4
PEX_RX2_C_N
16A4< 19C7>
SDMMC3_CLK_LB_OUT
8A7
SNN_GPIO_PI5
10B4
PEX_RX2_C_P
16A4< 19C7>
SDMMC3_CMD
8B8> 25B7<>
SNN_GPIO_PI7
10B4
PEX_RX2_N
14B3< 16A8>
SDMMC3_COMP_PD
8A6
SNN_GPS_IRQ_L
10A4
PEX_RX2_P
14B3< 16A8>
SDMMC3_COMP_PU
8A6
SNN_GPU_PWR_REQ
8C4
PEX_RX4_N
14B3< 15C7>
SDMMC3_DAT<3..0>
8B8<> 25B7<>
SNN_HDMI_PROBE
9C5
PEX_RX4_P
14B3< 15C7>
SDMMC3_WP_L
8D3< 25A7>
SNN_HSIC2_DATA
9A7
PEX_RX20_N
16A7
SDMMC4_CLK
8A7> 23D7<
SNN_HSIC2_STROBE
9A7
PEX_RX20_P
16A7
SDMMC4_CMD
8A7> 23D7<>
SNN_IN3N
20B4
PEX_TERMP
14A3
SDMMC4_COMP_PD
8A6
SNN_IN3P
20B4
PEX_TX2_C_N
14B3> 16B8<
SDMMC4_COMP_PU
8A6
SNN_JACK_RING
27D6
PEX_TX2_C_P
14B3> 16B8<
SDMMC4_DAT<7..0>
8A8<> 23C7<>
SNN_KB_COL1
8D4
PEX_TX2_N
16B4> 19C7<
SKIN_TEMP
31A1> 31C2<
SNN_KB_COL2
8D4
PEX_TX2_P
16B4> 19C7<
SNN_1P5V_POK
15B4
SNN_KB_COL6
8D4
PEX_TX4_N
14B3> 15C7<
SNN_ADCDAT2
20C6
SNN_KB_COL7
8D4
PEX_TX4_P
14B3> 15C7<
SNN_AS3720_SDO
31C5
SNN_KB_ROW8
8C4
PEX_TX20_C_N
16B7
SNN_AS3722_CTRL7_SD0 33C4
SNN_KB_ROW11
8C4
PEX_TX20_C_P
16B7
SNN_AS3722_CTRL8_SD0 33C4
SNN_KB_ROW12
8C4
PEX_WAKE_L
14A3< 15D7> 19B7>
SNN_AS3722_TEMP4_SD0 33C4
SNN_LOUTL
20B6
PE_TX4_C_N
15C6
SNN_CAMERA_SHUTTER
8B7
SNN_LOUTR
20B6
PE_TX4_C_P
15C6
SNN_CLK3_REQ
10C6
SNN_LVDS0_PROBE
9B5
PFO_JTAG_TRST_L
22A6
SNN_COMPASS_DRDY
10A4
SNN_MPCIE_3
15D6
PMU_INT_L
8B3< 31B5>
SNN_DAP3_SCLK
8C7
SNN_MPCIE_5
15D6
PMU_REGEN1
25C2< 30A5< 30B8< 31A8< 31C2> 32B3<
SNN_DCD
18C2
SNN_MPCIE_8
15D4
PMU_REGEN1_L
32B2
SNN_DGPU_3P3_EN
8C7
SNN_MPCIE_10
15D4
PMU_REGEN3
19B8< 27C4< 30A8< 30C8< 31C2>
SNN_DGPU_PWRGD
8C4
SNN_MPCIE_12
15D4
PMU_RESET_IN_L
22C8< 24B6> 25C5> 26A3<> 31B2<
SNN_DGPU_VDD_EN
8C7
SNN_MPCIE_14
15D4
POWER_FAN
27C2
SNN_DIRECTDC_CLK
14B6
SNN_MPCIE_16
15C4
POWER_FAN_SRC
27D2
SNN_DIRECTDC_IN
14B6
SNN_MPCIE_17
15C6
PWRBTN_R_L
25D4
SNN_DIRECTDC_OUT0
14B6
SNN_MPCIE_19
15C6
PWR_I2C_SCL
8B2> 26A7< 31C6<
SNN_DIRECTDC_OUT1
14B6
SNN_MPCIE_45
15C6
PWR_I2C_SDA
8B2<> 26A3<> 31C6<>
SNN_DIRECTDC_OUT2
14B6
SNN_MPCIE_47
15C6
RS232_CTS
18B3
SNN_DIRECTDC_OUT3
14B6
SNN_MPCIE_49
15C6
RS232_RTS
18C3
SNN_DSI_A_CLK_N
9C7
SNN_MPCIE_51
15C6
RS232_RXD_L
18B3
SNN_DSI_A_CLK_P
9C7
SNN_NFC_IRQ_L
10A4
RS232_TXD_L
18C3
SNN_DSI_A_D0_N
9C7
SNN_NFC_PROG
8C4
RST_SWR_L
25D6
SNN_DSI_A_D0_P
9C7
SNN_OWR
8B4
SATA_L0_RX_N
14C7< 16D3<
SNN_DSI_A_D1_N
9C7
SNN_PEX_REFCLKN
14A4
SATA_L0_RX_P
14C7< 16C3<
SNN_DSI_A_D1_P
9C7
SNN_PEX_REFCLKP
14A4
SATA_L0_TX_N
14C7> 16D3<
SNN_DSI_A_D2_N
9C7
SNN_PEX_RX1_N
14B3
SATA_L0_TX_P
14C7> 16D3<
SNN_DSI_A_D2_P
9C7
SNN_PEX_RX1_P
14B3
SATA_LED
10B7> 25D7<
SNN_DSI_A_D3_N
9C7
SNN_PEX_RX3_N
14B3
SATA_PWR_EN
16A3
SNN_DSI_A_D3_P
9C7
SNN_PEX_RX3_P
14B3
SATA_PWR_EN_T124
10B7> 16A5<
SNN_DSI_B_CLK_N
9B7
SNN_PEX_TX1_N
14B3
?
SATA_RX_N
16D2
SNN_DSI_B_CLK_P
9B7
SNN_PEX_TX1_P
14B3
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<->
8
7
6
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4
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D
C
B
A
TITLE
602-7R375-0000-D00
2
REV
PAGE
4.02
1
40
8
D
C
B
A
7
6
5
4
3
2
SNN_PEX_TX3_N
14B4
TPS51220A_REG_EN
27A6
USB0_ID_AP_R
17B2
SNN_PEX_TX3_P
14B4
TPS51220A_RF
27B6
USB0_ID_C
17C3
SNN_PG_OC_L
10B4
TPS51220A_TRIP
27A7
USB0_ID_GATE_L
17B3
SNN_PM_I2C_SCL_3.3V
22C7
TPS_SKIPSEL
28C7> 29C8<
USB0_ID_PMU
17B1> 33D7<
SNN_PM_I2C_SDA_3.3V
22C7
TP_ALS_IRQ_L
10A4
USB0_ID_PWR
17D5
SNN_RI
18B2
TP_AP_WP_L
8C4
USB0_VBUS
9A4
SNN_SDMMC1_CLK
8B7
TP_CLK_32K_WIFI
31C3
USB1D_N
9A4<> 15C3<>
SNN_SDMMC1_CMD
8B7
D
TP_CSI_DSI_TEST_OUT
9B7
USB1D_P
9A4<> 15C3<>
SNN_SDMMC1_DAT<3..0> 8B7
TP_DAP1_DIN
10B7
USB2DL_N
17B5
SNN_SDMMC3_CLMP
25A7
TP_DAP1_FS
10B7
USB2DL_P
17B5
SNN_SPKL_N
20C4
TP_DAP1_SCLK
10B7
USB2D_N
9A4<> 17B7<>
SNN_SPKL_P
20C4
TP_DAP4_DIN
10C7
USB2D_P
9A4<> 17B7<>
SNN_SPKR_N
20C4
TP_DAP4_DOUT
10C7
USBSS_RX0R_N
16B4< 17A7>
SNN_SPKR_P
20C4
TP_DAP4_FS
10C7
USBSS_RX0R_P
16B4< 17A7>
SNN_SYS_CLK_REQ
8C4
TP_DAP4_SCLK
10C7
USBSS_RX0_N
14C3< 16B8>
SNN_TVS_USB_VBUS0
17C2
TP_DMIC_CLK
20B6
USBSS_RX0_P
14C3< 16B8>
SNN_U27U1_Z1
6B7
TP_DMIC_DATA
20A6
USBSS_TX0C_N
16C4> 17A7<
SNN_U27U1_Z2
6B7
TP_GPIO_PH5
10C4
USBSS_TX0C_P
16C4> 17A7<
SNN_U27U1_Z3
6B7
TP_GPIO_PH6
10C4
USBSS_TX0_N
14C3> 16C8<
SNN_U27U1_Z4
6B7
TP_GPIO_PI2
10B3
USBSS_TX0_P
14C3> 16C8<
SNN_U27U2_Z1
6B3
TP_GPIO_PK0
10B4
USB_REXT
9A5
SNN_U27U2_Z2
6B3
TP_GPIO_PK3
10B4
USB_VBUS_EN0
9A4<> 17C8<
SNN_U27U2_Z3
6B3
TP_KBC_IRQ_L
10C4
USB_VBUS_EN1
9A4<> 17B8<
SNN_U27U2_Z4
6B3
TP_KBL_PWM
10C4
VDD_AC_SNUB
27D5
SNN_U28U1_Z1
7B7
TP_PEX_TESTCLK_N
14A4
VDD_CORE_BOOST0
34A5
SNN_U28U1_Z2
7B7
TP_PEX_TESTCLK_P
14A4
VDD_CORE_BOOST1
34A5
SNN_U28U1_Z3
7B7
TP_RESET_OUT_L
8B4
VDD_CORE_LX0
34A5
SNN_U28U1_Z4
7B7
TP_TOUCH_IRQ_L
10A4
VDD_CORE_LX1
34A5
SNN_U28U2_Z1
7B3
TP_ULPI_DATA1
8D7
VDD_CORE_SENSE_N
11A2> 33B3<
SNN_U28U2_Z2
7B3
TP_ULPI_DATA2
8D7
VDD_CORE_SENSE_P
11A2> 33B3<
SNN_U28U2_Z3
7B3
TP_USB_VBUS_EN2
14A4
VDD_CPU_BOOST1
35D5
SNN_U28U2_Z4
7B3
TS_CLK
8B8> 26D6<
VDD_CPU_BOOST2
35D5
SNN_UART3_CTS_L
10C7
TS_RESET_L
10B3> 26D3<
VDD_CPU_BOOST3
35B5
SNN_UART3_RTS_L
10C7
TS_SHDN_L
10B3> 26D3<
VDD_CPU_BOOST4
35B5
SNN_UART3_RXD
10C7
TS_SPI_CS_L
8C7> 26D6>
VDD_CPU_BOOST5
35A5
SNN_UART3_TXD
10C7
TS_SPI_MISO
8C7< 26D3<
VDD_CPU_BOOST6
35A5
SNN_ULPI_DATA4
8D7
TS_SPI_MOSI
8C7> 26D3>
VDD_CPU_LX1
35D5
SNN_ULPI_DATA5
8D7
TS_SPI_SCK
8C7> 26D6>
VDD_CPU_LX2
35C5
SNN_ULPI_DATA6
8C7
UART2_CTS_L
10C7< 26A4>
VDD_CPU_LX3
35B5
SNN_ULPI_DATA7
8C7
UART2_RTS_L
10C7> 26A7<
VDD_CPU_LX4
35B5
SNN_WF_RST_L
8B6
UART2_RXD
10C7< 26A4>
VDD_CPU_LX5
35A5
SPI4_CS0_L
10B3> 23B7<
UART2_TXD
10C7> 26A7<
VDD_CPU_LX6
35A5
SPI4_CS3_L
10C3> 24B2>
UART4_CTS_3V3_L
18B5
VDD_CPU_SENSE_N
11A2> 33C3<
SPI4_MISO
10C3< 23A7> 24B2>
UART4_CTS_L
10C3< 18B8> 22D7<
VDD_CPU_SENSE_P
11B2> 33C3<
SPI4_MOSI
10C3> 23A4< 24B2>
UART4_CTS_R_L
18B7
VDD_GPU_BOOST0
34D5
SPI4_SCK
10C3> 23A4< 24B2>
UART4_RTS_3V3_L
18C5
VDD_GPU_BOOST1
34D5
SPI_HOLD_L
23A4
UART4_RTS_L
10B3> 18C7< 22D7> 24D5>
VDD_GPU_BOOST2
34B5
SPI_ROM_WP_L
23A6
UART4_RXD
10C3< 18B8> 22D7<
VDD_GPU_BOOST3
34B5
SYS_RESET_L
8B3< 22A5< 23D7< 31B2>
UART4_RXD_3V3
18B5
VDD_GPU_LX0
34D5
TEMP_ALERT_L
10B3< 18A3>
UART4_RXD_R
18B7
VDD_GPU_LX1
34C5
TEMP_THERM_PMU
31B5
UART4_TXD
10B3> 18C7< 22D7> 24C5>
VDD_GPU_LX2
34B5
TEST_MODE_EN
8A4
UART4_TXD_3V3
18C5
VDD_GPU_LX3
34B5
THERMD_N
8B3< 18A7>
USB0DL_N
17C3
VDD_GPU_SENSE_N
11B2> 33C3<
THERMD_P
8B3< 18A7<
USB0DL_P
17C3
VDD_GPU_SENSE_P
11B2> 33C3<
TITLE
THERMD_R_N
18A6
USB0D_N
9A4<> 17C5<
VN
18C3
THERMD_R_P
18A6
USB0D_P
9A4<> 17C5<
VP
18C3
TPS51220A_FUNC
27B7
USB0_ID
9A4< 17B1>
VREF_DDR0
6B5> 6B8<
DOC NUMBER
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
1
C
B
A
?
602-7R375-0000-D00
2
REV
PAGE
4.02
1
41
8
D
C
7
VREF_DDR1
7B4> 7B8<
VVDD_CORE_PROBE
11A5
VVDD_CPU_PROBE
11A5
VVDD_GPU_PROBE
11B5
WF_DISABLE
15C2
WF_EN
10A3> 15C1<
WLAN_L
15C4
WLAN_LED
15C3
WPAN_L
15C4
WWAN_L
15C4
W_DISABLE_L
15C2
W_DISABLE_R_L
15C4
XTAL_IN
8A4
XTAL_LAN_N
19A6
XTAL_LAN_P
19A6
XTAL_OUT
8A4
YLW_STBYLED
25D4
YLW_STBYLED_L
25C4
Y_JTAG_TRST_L
22A5
6
5
4
3
2
1
D
C
B
B
A
A
TITLE
?
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
42
8
7
6
B
A
4
3
2
1
Title:
Cref Part Report
C2C7
CAP_0402_R
[18A6]
C4D3
CAP_0402_R
[23D4]
Design:
beaver_t124_fabd
C2C8
CAP_0402_R
[30A4]
C4D4
CAP_0402_R
[23D4]
Date:
May 7 10:45:19 2014
C2D1
CAP_0603_R
[19B3]
C4D5
CAP_0402_R
[23C4]
C2D2
CAP_0402_R
[19B3]
C4D6
CAP_1206_R
[35B4]
C2D3
CAP_0402_R
[19A6]
C4D7
CAP_1206_R
[35C4]
D
C
5
C1A1
CAP_0402_R
[18C5]
C2D4
CAP_0402_R
[19B4]
C4D8
CAP_1206_R
[35D5]
C1A2
CAP_0402_R
[18C5]
C2D5
CAP_0402_R
[19B4]
C4D9
CAP_1206_R
[35A5]
C1A3
CAP_0402_R
[18C3]
C2D6
CAP_0402_R
[19B4]
C4D10
CAP_1206_R
[35C3]
C1A4
CAP_0402_R
[18C3]
C2D7
CAP_0402_R
[16A6]
C4D11
CAP_1206_R
[35C3]
C1B1
CAP_0402_R
[13A4]
C2D8
CAP_0402_R
[16A6]
C4D12
CAP_0402_R
[35A5]
C1B2
CAP_0402_R
[13A4]
C2D9
CAP_0402_R
[16B6]
C4D13
CAP_0402_R
[35D5]
C1B3
CAP_0402_R
[13B4]
C2D10
CAP_0402_R
[16B6]
C4D14
CAP_0402_R
[35A7]
C1C1
CAPP_B2_R
[17B5]
C2D11
CAP_0402_R
[17C5]
C4D15
CAP_0402_R
[35D7]
C1C2
CAP_0402_R
[19B1]
C2D12
CAP_0402_R
[15C6]
C4D16
CAP_0402_R
[35A5]
C1D1
CAP_0402_R
[19A6]
C2D13
CAP_0402_R
[15C6]
C4D17
CAP_0402_R
[35D5]
C1D2
CAP_0402_R
[19C4]
C3A1
CAP_0402_R
[23B4]
C4D18
CAP_1206_R
[35C2]
C1D3
CAP_0603_R
[19C3]
C3B1
CAP_0201_R
[6A8]
C4D19
CAP_1206_R
[35C3]
C1D4
CAP_0402_R
[19C4]
C3C1
CAP_0201_R
[7A8]
C4D20
CAP_1206_R
[35A7]
C1D5
CAP_0603_R
[19C4]
C3C2
CAP_0201_R
[7A7]
C4D21
CAP_1206_R
[35D7]
C1D6
CAP_0402_R
[22C3]
C3D1
CAP_0402_R
[34D5]
C4E1
CAP_0402_R
[31C7]
C1D7
CAP_0402_R
[19A2]
C3D2
CAP_0402_R
[34D6]
C4E2
CAP_1206_R
[35C7]
C1D8
CAP_0402_R
[22C2]
C3D3
CAP_0402_R
[34D5]
C4E3
CAP_1206_R
[35C5]
C1D9
CAP_0402_R
[21A5]
C3D4
CAP_1206_R
[34D6]
C4E4
CAP_0402_R
[35B5]
C1E1
CAP_0402_R
[21C6]
C3D5
CAP_1206_R
[34D5]
C4E5
CAP_0402_R
[35B7]
C1E2
CAP_0402_R
[21B4]
C3D6
CAP_1206_R
[34D4]
C4E6
CAP_0402_R
[35B5]
C1E3
CAP_0402_R
[21A5]
C3D7
CAP_1206_R
[34D3]
C4E7
CAP_0402_R
[24A7]
C1E4
CAP_0402_R
[21A5]
C3D8
CAP_1206_R
[34B4]
C5A1
CAP_0402_R
[22A4]
C1E5
CAP_0603_R
[20B2]
C3D9
CAP_1206_R
[34B3]
C5B1
CAP_0402_R
[29A7]
C1E6
CAP_1206_R
[17C6]
C3E1
CAP_1206_R
[34C5]
C5B2
CAP_0402_R
[27C5]
C1E7
CAP_0805_R
[17C6]
C3E2
CAP_1206_R
[34C7]
C5B3
CAP_0402_R
[28B7]
C1E8
CAP_0603_R
[20B1]
C3E3
CAP_0402_R
[34B5]
C5C1
CAP_0402_R
[28B3]
C1E9
CAP_0402_R
[20B1]
C3E4
CAP_0402_R
[34B6]
C5C2
CAP_0402_R
[29B3]
C1E10
CAP_0603_R
[20A4]
C3E5
CAP_0402_R
[34B5]
C5C3
CAP_0805_R
[27C6]
C1E11
CAP_0603_R
[20B3]
C3E6
CAP_0603_R
[16A3]
C5C4
CAP_1206_R
[29C4]
C1E12
CAP_0402_R
[17B3]
C3E7
CAP_0402_R
[16A2]
C5C5
CAP_1206_R
[29C3]
C1E13
CAP_0603_R
[20B2]
C3E8
CAP_0402_R
[16B2]
C5C6
CAP_1206_R
[28C3]
C1E14
CAP_0402_R
[20B2]
C3E9
CAP_0805_R
[16C3]
C5C7
CAP_1206_R
[28C3]
C1E15
CAP_0402_R
[20B3]
C3E10
CAP_0402_R
[16C2]
C5C8
CAP_0402_R
[29B4]
C1E16
CAP_0402_R
[20B4]
C3E11
CAP_0402_R
[16B3]
C5C9
CAPP_DPOS_R
[29B2]
C1E17
CAP_0402_R
[20A3]
C4A1
CAP_0402_R
[22B1]
C5C10
CAPP_DPOS_R
[28C2]
C1E18
CAP_0603_R
[20A3]
C4A2
CAP_0402_R
[22B6]
C5C11
CAP_1206_R
[27D5]
C1E19
CAP_0402_R
[20C3]
C4B1
CAP_0201_R
[6A7]
C5D1
CAP_1206_R
[27D3]
C1E20
CAP_0402_R
[20A3]
C4B2
CAP_0201_R
[6A6]
C5D2
CAP_0402_R
[30B6]
C1E21
CAP_0402_R
[20C3]
C4B3
CAP_0402_R
[6A8]
C5D3
CAP_0402_R
[30B7]
C2A1
CAP_0402_R
[34A5]
C4B4
CAP_0805_R
[30C4]
C5D4
CAP_1206_R
[27D3]
C2A2
CAP_0402_R
[34A5]
C4B5
CAP_0402_R
[30C3]
C5D5
CAP_1206_R
[27D3]
C2A3
CAP_1206_R
[34A6]
C4B6
CAP_0402_R
[30B2]
C5D6
CAP_0402_R
[31A7]
C2A4
CAP_1206_R
[34A5]
C4C1
CAP_0402_R
[7A7]
C5D7
CAP_0402_R
[31A2]
C2A5
CAP_0805_R
[34A4]
C4C2
CAP_0201_R
[7B4]
C5D8
CAP_0402_R
[31B5]
C2A6
CAP_0805_R
[34A4]
C4C3
CAP_0201_R
[7A6]
C5D9
CAP_0603_R
[33B3]
C2B1
CAP_0201_R
[9B3]
C4C4
CAP_0201_R
[7A6]
C5D10
CAP_0603_R
[33B3]
C2C1
CAP_0402_R
[9A3]
C4C5
CAP_0201_R
[7B4]
C5D11
CAP_0805_R
[33B3]
C2C2
CAP_0402_R
[30A8]
C4C6
CAP_0402_R
[7A8]
C5D12
CAP_0805_R
C2C3
CAP_0805_R
[17B5]
C4C7
CAP_0201_R
[7A6]
C5D13
CAP_0402_R
C2C4
CAP_0402_R
[16C7]
C4C8
CAP_0201_R
[7A6]
C5D14
CAP_0402_R
C2C5
CAP_0402_R
[16C7]
C4D1
CAP_0402_R
[23C4]
C5D15
CAP_0805_R
?
C2C6
CAP_0402_R
[18A4]
C4D2
CAP_0402_R
[23C4]
C5D16
CAP_0402_R
DOC NUMBER [31D5]
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
D
C
B
A
[33B3]
[31A4]
TITLE
[31B5]
[33A3]
602-7R375-0000-D00
2
REV
PAGE
4.02
1
43
8
D
C
B
A
7
6
5
4
3
2
1
C5D17
CAP_0402_R
[33A4]
C7B8
CAP_0201_R
[6B8]
C8B26
CAP_0201_R
[9D4]
C5E1
CAP_0402_R
[24B7]
C7B9
CAP_0201_R
[6A6]
C8B27
CAP_0201_R
[8A4]
C6B1
CAP_0402_R
[29A7]
C7B10
CAP_0201_R
[6B4]
C8B28
CAP_0402_R
[5C2]
C6B2
CAP_0402_R
[28A7]
C7B11
CAP_0201_R
[6A6]
C8B29
CAP_0402_R
[11D7]
C6C1
CAP_0402_R
[29B4]
C7B12
CAP_0201_R
[6A6]
C8B30
CAP_0201_R
[5B4]
C6C2
CAP_0402_R
[28B7]
C7B13
CAP_0201_R
[6B8]
C8B31
CAP_0402_R
[5C2]
C6C3
CAP_0603_R
[27B5]
C7C1
CAP_0201_R
[7A6]
C8B32
CAP_0402_R
[11B8]
C6C4
CAP_0402_R
[27A6]
C7C2
CAP_0201_R
[7B8]
C8B33
CAP_0402_R
[11B8]
C6C5
CAP_0805_R
[27B5]
C7C3
CAP_0201_R
[6A6]
C8B34
CAP_0402_R
[11C4]
C6C6
CAP_0402_R
[28C2]
C7C4
CAP_0201_R
[7B8]
C8B35
CAP_0402_R
[11C4]
C6C7
CAP_0402_R
[28C5]
C7C5
CAP_0402_R
[6A7]
C8C1
CAP_0201_R
[4D4]
C6C8
CAP_0402_R
[29C3]
C7C6
CAP_0201_R
[6A6]
C8C2
CAP_0402_R
[11D7]
C6C9
CAP_0805_R
[29B3]
C7C7
CAP_0402_R
[7A8]
C8C3
CAP_0402_R
[11D4]
C6C10
CAP_0805_R
[28C3]
C7C8
CAP_0201_R
[7A6]
C8C4
CAP_0402_R
[11D4]
C6C11
CAP_0402_R
[28B4]
C7C9
CAP_0201_R
[7A6]
C8C5
CAP_0402_R
[11A7]
C6C12
CAP_0402_R
[29C3]
C7C10
CAP_0201_R
[7A7]
C8C6
CAP_0402_R
[11A7]
C6C13
CAP_0402_R
[28C2]
C7C11
CAP_0201_R
[7A8]
C8C7
CAP_0402_R
[5D4]
C6D1
CAP_0402_R
[31B1]
C7C12
CAP_0402_R
[7A7]
C8C8
CAP_0201_R
[5D4]
C6D2
CAP_0402_R
[31B3]
C7D1
CAP_0805_R
[35B4]
C8C9
CAP_0201_R
[11D8]
C6D3
CAP_0402_R
[31A6]
C7D2
CAP_0805_R
[35A4]
C8C10
CAP_0201_R
[5D4]
C6D4
CAPP_SMD_3225
[31B5]
C7D3
CAP_1206_R
[35D5]
C8C11
CAP_0402_R
[5D4]
C6D5
CAP_0402_R
[31C4]
C7D4
CAP_1206_R
[35A5]
C8C12
CAP_0201_R
[4C2]
C6D6
CAP_0402_R
[31D5]
C7D5
CAP_0805_R
[35C4]
C8C13
CAP_0402_R
[11B8]
C6D7
CAP_0805_R
[33B6]
C7D6
CAP_0805_R
[35B4]
C8C14
CAP_0402_R
[11A8]
C6D8
CAP_0805_R
[33B3]
C7D7
CAP_1206_R
[35D7]
C8C15
CAP_0402_R
[11C4]
C6D9
CAP_0402_R
[32A7]
C7D8
CAP_1206_R
[35A7]
C8C16
CAP_0201_R
[4C4]
C6D10
CAP_0402_R
[32B5]
C7D9
CAP_0402_R
[32C5]
C8C17
CAP_0402_R
[11C4]
C6D11
CAP_0402_R
[32B7]
C7E1
CAP_0805_R
[35C4]
C8C18
CAP_0201_R
[5C4]
C6D12
CAP_0402_R
[32B7]
C7E2
CAP_0805_R
[35A4]
C8C19
CAP_0402_R
[11C8]
C6D13
CAP_0402_R
[32A6]
C7E3
CAP_1206_R
[35A4]
C8C20
CAP_0402_R
[5C4]
C6D14
CAP_0603_R
[33B6]
C7E4
CAP_1206_R
[35C5]
C8C21
CAP_0402_R
[11A8]
C6D15
CAP_0805_R
[33B6]
C7E5
CAP_1206_R
[35C7]
C8C22
CAP_0402_R
[11C5]
C6D16
CAP_0402_R
[32A5]
C8B1
CAP_0402_R
[22D7]
C8C23
CAP_0201_R
[11B7]
C6D17
CAP_0402_R
[32B7]
C8B2
CAP_0402_R
[8A4]
C8C24
CAP_0402_R
[11C8]
C6D18
CAP_0402_R
[32A7]
C8B3
CAP_0402_R
[8A4]
C8C25
CAP_0201_R
[11B8]
C6D19
CAP_0402_R
[32B6]
C8B4
CAP_0402_R
[6A7]
C8C26
CAP_0201_R
[11B7]
C6D20
CAP_0402_R
[32C6]
C8B5
CAP_0201_R
[6A6]
C8C27
CAP_0201_R
[11D4]
C6D21
CAP_0402_R
[32A5]
C8B6
CAP_0201_R
[6A6]
C8C28
CAP_0402_R
[5C3]
C6D22
CAP_0805_R
[33A3]
C8B7
CAP_0201_R
[8B7]
C8C29
CAP_0201_R
[11B7]
C6D23
CAP_0603_R
[32C7]
C8B8
CAP_0402_R
[8B7]
C8C30
CAP_0201_R
[11D5]
C6D24
CAP_0805_R
[33A6]
C8B9
CAP_0402_R
[8A4]
C8C31
CAP_0201_R
[5C4]
C6E1
CAP_0402_R
[32C5]
C8B10
CAP_0201_R
[10D3]
C8C32
CAP_0201_R
[11B8]
C6E2
CAP_0402_R
[32C5]
C8B11
CAP_0402_R
[14C6]
C8C33
CAP_0201_R
[8D4]
C6E3
CAP_0402_R
[32C5]
C8B12
CAP_0402_R
[10D3]
C8C34
CAP_0201_R
[11B7]
C6E4
CAP_0402_R
[32C7]
C8B13
CAP_0201_R
[14C6]
C8C35
CAP_0201_R
[11B7]
C6E5
CAP_0805_R
[33A6]
C8B14
CAP_0402_R
[5C2]
C8C36
CAP_0402_R
[5C3]
C6E6
CAP_0402_R
[32C7]
C8B15
CAP_0402_R
[8C7]
C8C37
CAP_0201_R
[11B8]
C6E7
CAP_0402_R
[32C6]
C8B16
CAP_0402_R
[5C3]
C8C38
CAP_0402_R
[5C3]
C6E8
CAP_0603_R
[33A3]
C8B17
CAP_0201_R
[4C3]
C8C39
CAP_0201_R
[11B7]
C6E9
CAP_0603_R
[33A3]
C8B18
CAP_0201_R
[10D6]
C8C40
CAP_0201_R
[11B7]
C7B1
CAP_0402_R
[25A4]
C8B19
CAP_0201_R
[5C4]
C8C41
CAP_0201_R
[10B6]
C7B2
CAP_0603_R
[25A4]
C8B20
CAP_0402_R
[8D4]
C8C42
CAP_0402_R
[11A7]
C7B3
CAP_0402_R
[22C7]
C8B21
CAP_0402_R
[5C2]
C8C43
CAP_0402_R
C7B4
CAP_0201_R
[6B4]
C8B22
CAP_0402_R
[9D4]
C8C44
CAP_0201_R
C7B5
CAP_0201_R
[6A8]
C8B23
CAP_0402_R
[10D6]
C8C45
CAP_0402_R
C7B6
CAP_0201_R
[6A7]
C8B24
CAP_0201_R
[8D4]
C8C46
CAP_0201_R
?
C7B7
CAP_0402_R
[6A8]
C8B25
CAP_0201_R
[8C6]
C8C47
CAP_0402_R
DOC NUMBER [8D4]
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
D
C
B
A
[10B6]
[8A6]
TITLE
[8A7]
[7A6]
602-7R375-0000-D00
2
REV
PAGE
4.02
1
44
8
D
C
B
A
7
6
5
4
3
2
1
C8C48
CAP_0201_R
[14C3]
C9C17
CAP_0402_R
[14D7]
C8C49
CAP_0402_R
[14C3]
C9C18
CAP_0201_R
[14D6]
CR2D1
DIODECC_S23_R
[17D6]
C8C50
CAP_0805_R
[11A8]
C9C19
CAP_0402_R
[14C6]
CR4E1
TVS_BIDIR2_SOD882_R
[24A8]
C8D1
CAP_1206_R
[34D7]
C9C20
CAP_0201_R
[14C3]
CR5E1
LED_0603_R
[30D5]
C8D2
CAP_1206_R
[34D5]
C9C21
CAP_0402_R
[14C3]
CR5E2
TVS_BIDIR2_SOD882_R
[24C7]
C8D3
CAP_0805_R
[34C4]
C9C22
CAP_0402_R
[16A7]
CR5E3
TVS_BIDIR2_SOD882_R
[24B7]
C8D4
CAP_0805_R
[34D4]
C9C23
CAP_0402_R
[16A7]
CR7B1
DIODESER_QUAD_XSOP7_R
[25A5]
C8D5
CAP_0805_R
[34B4]
C9C24
CAP_0402_R
[16B7]
CR7B2
DIODESER_QUAD_XSOP7_R
[25A6]
C8D6
CAP_0805_R
[34B4]
C9C25
CAP_0402_R
[16B7]
CR10C1
DIODECC_S323_R
[13B5]
C8D7
CAP_1206_R
[34C6]
C9D1
CAP_0402_R
[30A5]
HS3C1
HEATSINK_50MMX67MM_ELLIPT [12C6]
C8D8
CAP_1206_R
[34C5]
C9D1A
CAP_0402_R
[21A5]
C9A1
CAP_0402_R
[34A7]
C9D2
CAP_0603_R
[19C4]
ISO3A1
GNDISO_4MIL
[8A7]
C9A2
CAP_0402_R
[18D3]
C9D3
CAP_0402_R
[19C4]
ISO5C1
GNDISO_4MIL
[29B2]
C9A3
CAP_1206_R
[34A5]
C9D4
CAP_0402_R
[16D2]
ISO5C2
GNDISO_4MIL
[28B2]
C9A4
CAP_1206_R
[34A7]
C9D5
CAP_0402_R
[16D2]
ISO5D1
GNDISO_4MIL
[33B4]
C9A5
CAP_0805_R
[34A3]
C9D6
CAP_0402_R
[16C2]
ISO5D2
GNDISO_4MIL
[33A3]
C9A6
CAP_0805_R
[34A4]
C9D7
CAP_0402_R
[16D2]
ISO5E1
GNDISO_4MIL
[33A3]
C9B1
CAP_0201_R
[9C3]
C9D8
CAP_0402_R
[17D7]
ISO6C1
GNDISO_10MIL
[27A5]
C9B2
CAP_0201_R
[9D4]
C9E1
CAP_0603_R
[15D3]
ISO8C1
GNDISO_10MIL
[5B1]
C9B3
CAP_0402_R
[9D4]
C9E2
CAP_0603_R
[15B4]
ISO10D1
GNDISO_4MIL
[21A4]
C9B4
CAP_0201_R
[9B4]
C9E3
CAP_0603_R
[15B6]
J1A1
HDR2X5KEY10_THR_R
[25D5]
C9B5
CAP_0402_R
[9C4]
C9E4
CAP_0805_R
[15D4]
J1A2
SERIAL_DSUB_DSUB9_R
[18C1]
C9B6
CAP_0402_R
[9B4]
C9E5
CAP_0402_R
[15B6]
J1C1
CON_HDMI_A_SMT_G_R
[13C3]
C9B7
CAP_0201_R
[9B4]
C10A1
CAP_0402_R
[18B3]
J1C2
USBX1_V3_RA_FLAG_TH_R
[17B4]
C9B8
CAP_0402_R
[11C7]
C10B1
CAP_0402_R
[18B5]
J1D1
RJ45_1X1GBIT_MAG_LED_RJ45 [19A2]
C9B9
CAP_0402_R
[9C2]
C10B2
CAP_0402_R
[18C5]
C9B10
CAP_0201_R
[11D8]
C10B3
CAP_0402_R
[18C7]
C9B11
CAP_0402_R
[11C8]
C10B4
CAP_0402_R
[18C7]
C9B12
CAP_0402_R
[11C7]
C10B5
CAP_0603_R
[13A7]
C9B13
CAP_0201_R
[9B7]
C10B6
CAP_0402_R
[13D4]
C9B14
CAP_0402_R
[9B7]
C10B7
CAP_0402_R
[13B4]
J2D1
SATA_THR_SHRD_R
C9B15
CAP_0402_R
[9A7]
C10C1
CAP_0402_R
[17B7]
J2D2
MINI_PCI_EXPRESS_SMT_HALF [15C5]
C9B16
CAP_0402_R
[11C7]
C10C2
CAP_0603_R
[17B8]
C9B17
CAP_0402_R
[9D7]
C10C3
CAP_0402_R
[17B6]
J3A1
SKT2X25_THR_R
[26D5]
C9B18
CAP_0402_R
[9A4]
C10C4
CAP_0402_R
[17B5]
J3A2
SKT3X25_THR_R
[26B5]
C9B19
CAP_0201_R
[8C4]
C10C5
CAP_0402_R
[17B5]
J4A1
HDR2X10_THR_RA_SHR2
[22A1]
C9B20
CAP_0201_R
[9A4]
C10D1
CAP_0402_R
[19B4]
J4A2
FAN1X4_4PIN_FAN_R
[27C2]
C9B21
CAP_0201_R
[9D7]
C10D2
CAP_0402_R
[19B4]
J4E1
HDR1X1_THR
[24A8]
C9B22
CAP_0201_R
[10D3]
C10D3
CAP_0402_R
[19B4]
J4E2
SKT_PWR_IDE_THR_R
[16B1]
C9B23
CAP_0402_R
[9A4]
C10E1
CAP_0402_R
[20B2]
J5B1
CON_SD_SM1_R
[25B3]
C9B24
CAP_0402_R
[10D3]
C10E2
CAP_0402_R
[20B2]
J5C1
PWR_JACK_5P_THR_R
[27D6]
C9C1
CAP_0201_R
[9A4]
C10E3
CAP_0603_R
[20B3]
J5E1
HDR1X1_THR
[24C8]
C9C2
CAP_0201_R
[11D7]
C10E4
CAP_0603_R
[20A4]
J5E2
HDR1X1_THR
[24A8]
C9C3
CAP_0201_R
[8D6]
C10E5
CAP_0402_R
[20A5]
J7B1
HDR_24_FPC_RA_SMT2_R
[22C6]
C9C4
CAP_0201_R
[11D8]
C10E6
CAP_0402_R
[20A4]
L1B1
INDUCTOR_0402_R
[13A4]
C9C5
CAP_0201_R
[9A7]
C10E7
CAP_0402_R
[20A4]
L1D1
INDUCTOR_0402_R
[21A5]
C9C6
CAP_0402_R
[8D6]
C10E8
CAP_0402_R
[20A4]
L1D2
INDUCTOR_0402_R
[21C6]
C9C7
CAP_0201_R
[14D3]
C10E9
CAP_0402_R
[20A4]
L1E1
INDUCTOR_0402_R
[21B6]
C9C8
CAP_0402_R
[14D3]
C10E10
CAP_0402_R
[20A3]
L1E2
INDUCTOR_0402_R
[21A5]
C9C9
CAP_0201_R
[11D4]
CR1B1
TVS_DUAL_DIFF_PAIR_SLP251 [13C5 13C4]
L1E3
CHOKE_2012_R
[17C4 17C4]
C9C10
CAP_0201_R
[14C3]
0P8_R
L1E4
INDUCTOR_0402_R
[20B1]
C9C11
CAP_0402_R
[14C3]
TVS_DUAL_DIFF_PAIR_SLP251 [13C6 13C6]
L1E5
INDUCTOR_0402_R
[20A2]
C9C12
CAP_0402_R
[14C3]
0P8_R
L2A1
INDUCTOR_SMD_R
[34A5]
C9C13
CAP_0201_R
[14C3]
CR1E1
TVS_USB_XSOP7_R
[17C3]
L2A2
INDUCTOR_SMD_R TITLE
[34A5]
C9C14
CAP_0201_R
[14C6]
CR1E2
LED_0603_R
[15C3]
L2D1
INDUCTOR_2016_R
[19C3]
C9C15
CAP_0402_R
[14D6]
CR2C1
TVS_USB_XSOP7_R
[17A4]
L2D2
INDUCTOR_SMD_R ?
[19C3]
C9C16
CAP_0402_R
[14A2]
CR2C2
TVS_DUAL_DIFF_PAIR_SLP251 [17A5 17A6]
L5C1
INDUCTOR_SMD_R DOC NUMBER [29C3]
CR1C1
0P8_R
IC_12V
7
6
5
C
_2_R
J1D2
AUDIO_JACK_2PORT_LIMEPINK [21C4 21A4]
_THR_R
J1E1
CON_USB_MICRO_AB_TH_UAB_1 [17C2]
1P
[16D1]
_STND_R
NVIDIA
CONFIDENTIAL
<->
8
D
4
3
B
602-7R375-0000-D00
2
A
REV
PAGE
4.02
1
45
8
D
C
B
A
7
6
5
4
3
2
1
L5C2
INDUCTOR_SMD_R
[28C3]
Q9E3
MOSFETNSOT23_S23_R
[17A2]
R2B4
RES_0201_R
[26C5]
L6D1
INDUCTOR_SMD_R
[33B4]
Q10B1
MOSFETNSOT23_S23_R
[13C5]
R2B5
RES_0201_R
[24D2]
L6E1
PWR_INDUCTOR_SMDA_R
[33A4]
R1A1
RES_0603_R
[25D4]
R2B6
RES_0201_R
[10B2]
L6E2
PWR_INDUCTOR_SMDA_R
[33A4]
R1A2
RES_0603_R
[25D5]
R2B7
RES_0201_R
[24D3]
L7D1
INDUCTOR_SMD_R
[35A5]
R1A3
RES_0603_R
[25D4]
R2B8
RES_0201_R
[10B2]
L7D2
INDUCTOR_SMD_R
[35D5]
R1A4
RES_0402_R
[25C3]
R2B9
RES_0402_R
[8C7]
L7D3
INDUCTOR_SMD_R
[35C5]
R1A5
RES_0402_R
[25D3]
R2C1
RES_0402_R
[8C8]
L7D4
INDUCTOR_SMD_R
[35A5]
R1A6
RES_0402_R
[25C6]
R2C2
RES_0402_R
[30A7]
L7E1
INDUCTOR_SMD_R
[35B5]
R1A7
RES_0603_R
[25D5]
R2C3
RES_0402_R
[22A4]
L7E2
INDUCTOR_SMD_R
[35B5]
R1A8
RES_0402_R
[18C2]
R2C4
RES_0402_R
[14A3]
L8B1
INDUCTOR_0402_R
[8A3]
R1B1
RES_0201_R
[24D7]
R2C5
RES_0201_R
[16B7]
L8D1
INDUCTOR_SMD_R
[34C4]
R1B2
RES_0201_R
[24C7]
R2C6
RES_0201_R
[16B7]
L8D2
INDUCTOR_SMD_R
[34D4]
R1B3
RES_0201_R
[24C7]
R2C7
RES_0402_R
[24A4]
L8D3
INDUCTOR_SMD_R
[34B4]
R1B4
RES_0201_R
[24D7]
R2C8
RES_0402_R
[24A4]
L8D4
INDUCTOR_SMD_R
[34B4]
R1B5
RES_0201_R
[24D6]
R2C9
RES_0402_R
[24A4]
L9B1
INDUCTOR_0402_R
[9B4]
R1B6
RES_0201_R
[24C6]
R2C10
RES_0402_R
[24A4]
L9B2
INDUCTOR_0402_R
[9A4]
R1B7
RES_0402_R
[13A7]
R2D1
RES_0402_R
[18A2]
L9C1
INDUCTOR_0402_R
[14C2]
R1B8
RES_0402_R
[13B6]
R2D2
RES_0402_R
[18B3]
L9C2
INDUCTOR_0402_R
[14D2]
R1B9
RES_0402_R
[13B6]
R2D3
RES_0402_R
[18B3]
L9C3
INDUCTOR_0402_R
[14C7]
R1B10
RES_0402_R
[18B7]
R2D4
RES_0402_R
[19A3]
L9C4
CHOKE_2012_R
[17B6 17B6]
R1B11
RES_0402_R
[18B7]
R2D5
RES_0402_R
[19A3]
L10B1
INDUCTOR_0402_R
[13B6]
R1C1
RES_0402_R
[13D4]
R2D6
RES_0402_R
[19A3]
L10B2
INDUCTOR_0402_R
[13B6]
R1C2
RES_0402_R
[17B7]
R2D7
RES_0402_R
[30A4]
L10B3
INDUCTOR_0402_R
[13C4]
R1D1
RES_0402_R
[19A4]
R2D8
RES_0402_R
[19B6]
L10E1
INDUCTOR_0402_R
[20A6]
R1D2
RES_0402_R
[19A1]
R2D9
RES_0402_R
[19C6]
M1A1
BRD_MOUNT_BRDMNT2
[12B7]
R1D3
RES_0402_R
[22D2]
R2D10
RES_0402_R
[19C6]
M1E1
BRD_MOUNT_BRDMNT2
[12A7]
R1D4
RES_0402_R
[22D2]
R2D11
RES_0402_R
[19B7]
M2E1
PEM_SMT_R
[15D4]
R1D5
RES_0402_R
[22D2]
R3A1
RES_0402_R
[23B6]
M3E1
PEM_SMT_R
[15C4]
R1D6
RES_0402_R
[21C5]
R3A2
RES_0402_R
[23B4]
M5A1
BRD_MOUNT_BRDMNT2
[12A6]
R1D7
RES_0402_R
[21C5]
R3B1
RES_0201_R
[24B4]
M5E1
BRD_MOUNT_BRDMNT2
[12B6]
R1D8
RES_0402_R
[21C5]
R3B2
RES_0201_R
[24B3]
Q1A1
MOSFETN_SC70S_SC70S_R
[25C4]
R1D9
RES_0402_R
[21C4]
R3B3
RES_0402_R
[10B2]
Q1A2
MOSFETN_SC70S_SC70S_R
[25D6]
R1E1
RES_0402_R
[21B4]
R3B4
RES_0201_R
[24D3]
Q1A3
MOSFETN_SC70S_SC70S_R
[25C3]
R1E2
RES_0402_R
[21B5]
R3B5
RES_0201_R
[24D3]
Q1E1
MOSFETN_SC70S_SC70S_R
[21B5]
R1E3
RES_0402_R
[21B5]
R3B6
RES_0201_R
[8C3]
Q2D1
MOSFETN_SC70S_SC70S_R
[18A2]
R1E4
RES_0402_R
[17D3]
R3B7
RES_0201_R
[8C3]
Q2D2
MOSFETN_SC70S_SC70S_R
[18A3]
R1E5
RES_0402_R
[20B1]
R3C1
RES_0201_R
[5A6]
Q2D3
MOSFETN_SC70S_SC70S_R
[17C6]
R1E6
RES_0402_R
[20B3]
R3C2
RES_0201_R
[5A6]
Q3E1
MOSFETN_SC70S_SC70S_R
[16A2]
R1E7
RES_0402_R
[20C7]
R3C3
RES_0201_R
[8C3]
Q3E2
MOSFETP_DFN3X3_DFN3X3_R
[16A2]
R1E8
RES_0402_R
[20B7]
R3C4
RES_0201_R
[10A6]
Q4A1
MOSFETN_SC70S_SC70S_R
[27C3]
R1E9
RES_0402_R
[20C3]
R3C5
RES_0201_R
[8C2]
Q4A2
MOSFETPSOT23_S23_R
[27D2]
R1E10
RES_0402_R
[20C2]
R3C6
RES_0201_R
[10B6]
Q4E1
MOSFETNSOT23_S23_R
[24A6]
R2A1
RES_0402_R
[18D6]
R3C7
RES_0402_R
[24A4]
Q4E2
MOSFETP_SC70S_SC70S_R
[24A6]
R2A2
RES_0402_R
[18D5]
R3C8
RES_0402_R
[24A4]
Q5D1
MOSFETNSOT23_S23_R
[32B1]
R2A3
RES_0402_R
[18D5]
R3C9
RES_0402_R
[24A4]
Q5D2
MOSFETNSOT23_S23_R
[32B2]
R2A4
RES_0402_R
[9D3]
R3C10
RES_0402_R
[24A4]
Q6C1
MOSFETN_DFN_DUAL_DFN3X3
[29C4]
R2A5
RES_0402_R
[9C3]
R3E1
RES_0402_R
[16A2]
Q6C2
MOSFETN_DFN_DUAL_DFN3X3
[28C4]
R2A6
RES_0402_R
[9D2]
R3E2
RES_0402_R
[16A3]
Q9A1
MOSFETPSOT23_S23_R
[9C3]
R2A7
RES_0402_R
[9C2]
R3E3
RES_0402_R
[16A3]
Q9A2
MOSFETPSOT23_S23_R
[9D3]
R2A8
RES_0402_R
[9D3]
R3E4
RES_0402_R
[16A3]
Q9A3
MOSFETNSOT23_S23_R
[9C3]
R2A9
RES_0402_R
[9D2]
R3E5
RES_0402_R
[16B2]
Q9A4
MOSFETNSOT23_S23_R
[9D3]
R2A10
RES_0402_R
[9D2]
R3E6
RES_0402_R
[16B4]
Q9D1
NPN_S363_R
[19B6 19B6]
R2A11
RES_0402_R
[9C2]
R4A1
RES_0402_R
Q9D2
MOSFETN_SC70S_SC70S_R
[15C2]
R2A12
RES_0402_R
[9C2]
R4A2
RES_0402_R
Q9D3
MOSFETN_SC70S_SC70S_R
[15C2]
R2B1
RES_0201_R
[24B3]
R4A3
RES_0402_R
Q9E1
MOSFETNSOT23_S23_R
[17B2]
R2B2
RES_0201_R
[24B3]
R4A4
RES_0402_R
?
Q9E2
MOSFETNSOT23_S23_R
[17B3]
R2B3
RES_0201_R
[26C6]
R4A5
RES_0603_R
DOC NUMBER [27D2]
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
D
C
B
A
[22B2]
[22B2]
TITLE
[22B2]
[22A2]
602-7R375-0000-D00
2
REV
PAGE
4.02
1
46
8
D
C
B
A
7
6
5
4
3
2
1
R4A6
RES_0402_R
[31C3]
R5E9
RES_0402_R
[11A4]
R8B11
RES_0201_R
[10B7]
R4A7
RES_0603_R
[27D2]
R5E10
RES_0402_R
[30D5]
R8B12
RES_0201_R
[10C6]
R4A8
RES_0402_R
[27C3]
R5E11
RES_0201_R
[24D7]
R8B13
RES_0201_R
[8A7]
R4A9
RES_0402_R
[27C3]
R6B1
RES_0402_R
[25B4]
R8B14
RES_0201_R
[8A3]
R4A10
RES_0603_R
[27D2]
R6B2
RES_0402_R
[25B5]
R8B15
RES_0201_R
[8A6]
R4A11
RES_0402_R
[27D3]
R6B3
RES_0402_R
[27B7]
R8B16
RES_0201_R
[10B3]
R4A12
RES_0402_R
[27C3]
R6B4
RES_0402_R
[27A7]
R8B17
RES_0201_R
[10B3]
R4A13
RES_0402_R
[22A2]
R6B5
RES_0402_R
[29A7]
R8B18
RES_0201_R
[8B7]
R4B1
RES_0201_R
[6B3]
R6B6
RES_0402_R
[29A1]
R8B19
RES_0201_R
[4C2]
R4B2
RES_0201_R
[6B4]
R6B7
RES_0402_R
[27A7]
R8B20
RES_0201_R
[8A4]
R4B3
RES_0402_R
[6B5]
R6B8
RES_0402_R
[28A2]
R8B21
RES_0201_R
[4C3]
R4B4
RES_0402_R
[6B5]
R6B9
RES_0402_R
[28B7]
R8B22
RES_0201_R
[8B7]
R4C1
RES_0402_R
[7B5]
R6C1
RES_0402_R
[28B3]
R8B23
RES_0201_R
[8A4]
R4D1
RES_0201_R
[23D6]
R6C2
RES_0402_R
[29B3]
R8C1
RES_0201_R
[4C2]
R4D2
RES_0402_R
[30C7]
R6C3
RES_0805_R
[29B4]
R8C2
RES_0201_R
[4C2]
R4E1
RES_0402_R
[31C7]
R6C4
RES_0402_R
[29B7]
R8C3
RES_0201_R
[8B3]
R4E2
RES_0402_R
[31C7]
R6C5
RES_0402_R
[28B7]
R8C4
RES_0201_R
[8A7]
R4E3
RES_0402_R
[24A6]
R6C6
RES_0402_R
[28C7]
R8C5
RES_0201_R
[11B4]
R4E4
RES_0402_R
[24A7]
R6C7
RES_0402_R
[28C5]
R8C6
RES_0201_R
[8A7]
R4E5
RES_0402_R
[24B7]
R6C8
RES_0402_R
[29B3]
R8C7
RES_0201_R
[11A4]
R5A1
RES_0402_R
[22A2]
R6C9
RES_0402_R
[28C3]
R8C8
RES_0201_R
[11A4]
R5A2
RES_0402_R
[22A2]
R6C10
RES_0402_R
[29B3]
R9A1
RES_0402_R
[18D5]
R5A4
RES_0402_R
[22B3]
R6C11
RES_0402_R
[28C3]
R9B1
RES_0201_R
[24B3]
R5B1
RES_0402_R
[27B7]
R6C12
RES_0805_R
[28C4]
R9B2
RES_0201_R
[24B3]
R5B2
RES_0402_R
[27A7]
R6D1
RES_0603_R
[32C1]
R9B3
RES_0201_R
[24D2]
R5B3
RES_0402_R
[29A1]
R6D2
RES_0402_R
[31B5]
R9B4
RES_0201_R
[10B2]
R5B4
RES_0402_R
[29A6]
R6D3
RES_0402_R
[31A7]
R9B5
RES_0201_R
[24D3]
R5B5
RES_0402_R
[27A7]
R6D4
RES_0402_R
[31A7]
R9B6
RES_0201_R
[10B1]
R5B6
RES_0402_R
[28B6]
R6D5
RES_0402_R
[31B5]
R9B7
RES_0201_R
[9B4]
R5B7
RES_0402_R
[28B2]
R6D6
RES_0402_R
[31A5]
R9B8
RES_0201_R
[9C4]
R5C1
RES_0402_R
[28C7]
R6D7
RES_0402_R
[32C2]
R9B9
RES_0201_R
[9B8]
R5C2
RES_0402_R
[29C7]
R6D8
RES_0402_R
[31C3]
R9B10
RES_0201_R
[9B8]
R5C3
RES_0402_R
[28C6]
R6D9
RES_0402_R
[31B2]
R9B11
RES_0201_R
[9B7]
R5C4
RES_0402_R
[27B6]
R6D10
RES_0402_R
[31B7]
R9B12
RES_0402_R
[8D8]
R5C5
RES_0603_R
[29C5]
R6D11
RES_0402_R
[31C5]
R9B13
RES_0201_R
[9B7]
R5C6
RES_0603_R
[28C5]
R6D12
RES_0402_R
[31C5]
R9C1
RES_0402_R
[8D8]
R5C7
RES_0402_R
[29B5]
R6E1
RES_0402_R
[33D6]
R9C2
RES_0201_R
[9A7]
R5C8
RES_0603_R
[27D4]
R6E2
RES_0402_R
[11A4]
R9C3
RES_0201_R
[9A7]
R5C9
RES_0402_R
[27D4]
R6E3
RES_0402_R
[11A2]
R9C4
RES_0201_R
[9A4]
R5C10
RES_0402_R
[27D4]
R7A1
RES_0201_R
[24D6]
R9C5
RES_0201_R
[9A7]
R5C11
RES_1206_R
[27D4]
R7B1
RES_0201_R
[6B7]
R9C6
RES_0402_R
[9A3]
R5D1
RES_0402_R
[30B7]
R7B2
RES_0201_R
[6B8]
R9C7
RES_0201_R
[14A3]
R5D2
RES_0402_R
[30C6]
R7C1
RES_0201_R
[7B7]
R9C8
RES_0201_R
[14C6]
R5D3
RES_0402_R
[31A7]
R7C2
RES_0201_R
[7B7]
R9C9
RES_0201_R
[14C8]
R5D4
RES_0201_R
[31A2]
R7C3
RES_0201_R
[7B3]
R9C10
RES_0402_R
[18A6]
R5D5
RES_0402_R
[33C6]
R7C4
RES_0201_R
[7B3]
R9C11
RES_0402_R
[18A6]
R5D6
RES_0402_R
[31B4]
R7C5
RES_0402_R
[7B5]
R9D1
RES_0402_R
[18A4]
R5D7
RES_0402_R
[32A5]
R8B1
RES_0201_R
[8A3]
R9D2
RES_0201_R
[16A6]
R5D8
RES_0402_R
[31B5]
R8B2
RES_0201_R
[24B3]
R9D3
RES_0402_R
[19C5]
R5E1
RES_0201_R
[31C5]
R8B3
RES_0201_R
[24B4]
R9D4
RES_0201_R
[16A6]
R5E2
RES_0402_R
[33C6]
R8B4
RES_0402_R
[22C8]
R9D5
RES_0201_R
[16B6]
R5E3
RES_0402_R
[33C6]
R8B5
RES_0402_R
[22D6]
R9D6
RES_0201_R
[16B6]
R5E4
RES_0402_R
[33D7]
R8B6
RES_0402_R
[22D7]
R9D7
RES_0402_R
R5E5
RES_0402_R
[33D7]
R8B7
RES_0402_R
[24D3]
R9D8
RES_0402_R
R5E6
RES_0402_R
[11B4]
R8B8
RES_0201_R
[8A4]
R9D9
RES_0402_R
R5E7
RES_0402_R
[11B2]
R8B9
RES_0402_R
[24D3]
R9D10
RES_0402_R
?
R5E8
RES_0402_R
[11B2]
R8B10
RES_0201_R
[10B8]
R9D11
RES_0402_R
DOC NUMBER [15C4]
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
D
C
B
A
[17C7]
[17C5]
TITLE
[15D2]
[15C3]
602-7R375-0000-D00
2
REV
PAGE
4.02
1
47
8
D
C
B
A
7
6
5
4
3
2
1
R9D12
RES_0402_R
[15C3]
T3B34
TEE_TEE
[4C7]
T4B3
TEE_TEE
[7D7]
R9D13
RES_0402_R
[15C3]
T3B35
TEE_TEE
[4B7]
T4B4
TEE_TEE
[6C7]
R9D14
RES_0402_R
[19B7]
T3B36
TEE_TEE
[4C7]
T4B5
TEE_TEE
[7C7]
R9E1
RES_0402_R
[15B5]
T3B37
TEE_TEE
[4B7]
T4B6
TEE_TEE
[6D7]
R9E2
RES_0402_R
[15B4]
T3B38
TEE_TEE
[4B7]
T4B7
TEE_TEE
[6D7]
R9E3
RES_0402_R
[15B4]
T3B39
TEE_TEE
[4A7]
T4B8
TEE_TEE
[6C7]
R9E4
RES_0402_R
[15B6]
T3B40
TEE_TEE
[4A7]
T4B9
TEE_TEE
[7B7]
R9E5
RES_0402_R
[17B3]
T3B41
TEE_TEE
[4B7]
T4B10
TEE_TEE
[6D7]
R9E6
RES_0402_R
[17B2]
T3B42
TEE_TEE
[4A7]
T4B11
TEE_TEE
[7C7]
R9E7
RES_0402_R
[17B1]
T3B43
TEE_TEE
[4B7]
T4B12
TEE_TEE
[6D7]
R9E8
RES_0402_R
[17B2]
T3B44
TEE_TEE
[4B7]
T4B13
TEE_TEE
[6D7]
R10B1
RES_0402_R
[13A5]
T3C1
TEE_TEE
[5C6]
T4B14
TEE_TEE
[6B7]
R10B2
RES_0402_R
[13D4]
T3C2
TEE_TEE
[5C6]
T4B15
TEE_TEE
[7D7]
R10B3
RES_0402_R
[13C5]
T3C3
TEE_TEE
[5B6]
T4B16
TEE_TEE
[7C7]
R10C1
RES_0402_R
[13B5]
T3C4
TEE_TEE
[5B6]
T4B17
TEE_TEE
[6B7]
R10E1
RES_0402_R
[17A3]
T3C5
TEE_TEE
[5B6]
T4B18
TEE_TEE
[4D5]
R10E2
RES_0402_R
[20B7]
T3C6
TEE_TEE
[5B6]
T4B19
TEE_TEE
[6D7]
R10E3
RES_0402_R
[20B6]
T3C7
TEE_TEE
[5C6]
T4B20
TEE_TEE
[6C7]
R10E4
RES_0402_R
[20C2]
T3C8
TEE_TEE
[5C6]
T4B21
TEE_TEE
[6D7]
R10E5
RES_0402_R
[20C3]
T3C9
TEE_TEE
[5C6]
T4B22
TEE_TEE
[6D7]
RT5D1
THERMISTOR_0402_R
[31A2]
T3C10
TEE_TEE
[5A6]
T4B23
TEE_TEE
[6C7]
SW4E1
BUTTON_6P_THICK_UNIV
[24A8]
T3C11
TEE_TEE
[5C6]
T4B24
TEE_TEE
[4D5]
SW5E1
BUTTON_6P_THICK_UNIV
[24B8]
T3C12
TEE_TEE
[5C6]
T4B25
TEE_TEE
[6C7]
SW5E2
BUTTON_6P_THICK_UNIV
[24C8]
T3C13
TEE_TEE
[5C6]
T4B26
TEE_TEE
[6D7]
T3B1
TEE_TEE
[4B7]
T3C14
TEE_TEE
[5B6]
T4B27
TEE_TEE
[7C7]
T3B2
TEE_TEE
[4D7]
T3C15
TEE_TEE
[5A6]
T4B28
TEE_TEE
[6B7]
T3B3
TEE_TEE
[4C7]
T3C16
TEE_TEE
[5A6]
T4B29
TEE_TEE
[7D7]
T3B4
TEE_TEE
[4C7]
T3C17
TEE_TEE
[5B6]
T4B30
TEE_TEE
[6B7]
T3B5
TEE_TEE
[4C7]
T3C18
TEE_TEE
[5A6]
T4B31
TEE_TEE
[6B7]
T3B6
TEE_TEE
[4C7]
T3C19
TEE_TEE
[5B6]
T4B32
TEE_TEE
[4C5]
T3B7
TEE_TEE
[4C7]
T3C20
TEE_TEE
[5B6]
T4B33
TEE_TEE
[4C5]
T3B8
TEE_TEE
[4C7]
T3C21
TEE_TEE
[5B6]
T4C1
TEE_TEE
[4C5]
T3B9
TEE_TEE
[4A7]
T3C22
TEE_TEE
[5C6]
T4C2
TEE_TEE
[4C5]
T3B10
TEE_TEE
[4C7]
T3C23
TEE_TEE
[5B6]
T4C3
TEE_TEE
[4B5]
T3B11
TEE_TEE
[4B7]
T3C24
TEE_TEE
[5A6]
T4C4
TEE_TEE
[4B5]
T3B12
TEE_TEE
[4D7]
T3C25
TEE_TEE
[5C6]
T4C5
TEE_TEE
[4C5]
T3B13
TEE_TEE
[4B7]
T3C26
TEE_TEE
[5C6]
T4C6
TEE_TEE
[4C5]
T3B14
TEE_TEE
[4B7]
T3C27
TEE_TEE
[5A6]
T4C7
TEE_TEE
[4C5]
T3B15
TEE_TEE
[4C7]
T3C28
TEE_TEE
[5B6]
T4C8
TEE_TEE
[4C5]
T3B16
TEE_TEE
[4C7]
T3C29
TEE_TEE
[5C6]
T4C9
TEE_TEE
[4B5]
T3B17
TEE_TEE
[4C7]
T3C30
TEE_TEE
[5A6]
T4C10
TEE_TEE
[4C5]
T3B18
TEE_TEE
[4C7]
T3C31
TEE_TEE
[5B6]
T4C11
TEE_TEE
[4B5]
T3B19
TEE_TEE
[4B7]
T3C32
TEE_TEE
[5A6]
T4C12
TEE_TEE
[4C5]
T3B20
TEE_TEE
[4B7]
T3C33
TEE_TEE
[5B6]
T4C13
TEE_TEE
[4C5]
T3B21
TEE_TEE
[4C7]
T3C34
TEE_TEE
[5B6]
T4C14
TEE_TEE
[4C5]
T3B22
TEE_TEE
[4C7]
T3C35
TEE_TEE
[5C6]
T4C15
TEE_TEE
[4B5]
T3B23
TEE_TEE
[4C7]
T3C36
TEE_TEE
[5C6]
T4C16
TEE_TEE
[4B5]
T3B24
TEE_TEE
[4C7]
T3C37
TEE_TEE
[5B6]
T4C17
TEE_TEE
[4B5]
T3B25
TEE_TEE
[4C7]
T3C38
TEE_TEE
[5B6]
T4C18
TEE_TEE
[4C5]
T3B26
TEE_TEE
[4B7]
T3C39
TEE_TEE
[5B6]
T4C19
TEE_TEE
[7D7]
T3B27
TEE_TEE
[4C7]
T3C40
TEE_TEE
[5A6]
T4C20
TEE_TEE
[7C7]
T3B28
TEE_TEE
[4C7]
T3C41
TEE_TEE
[5B6]
T4C21
TEE_TEE
[7D7]
T3B29
TEE_TEE
[4B7]
T3C42
TEE_TEE
[5A6]
T4C22
TEE_TEE
T3B30
TEE_TEE
[4B7]
T3C43
TEE_TEE
[5B6]
T4C23
TEE_TEE
T3B31
TEE_TEE
[4C7]
T3C44
TEE_TEE
[5B6]
T4C24
TEE_TEE
T3B32
TEE_TEE
[4B7]
T4B1
TEE_TEE
[6D7]
T4C25
TEE_TEE
?
T3B33
TEE_TEE
[4B7]
T4B2
TEE_TEE
[6D7]
T4C26
TEE_TEE
DOC NUMBER [7C7]
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
D
C
B
A
[7D7]
[7D7]
TITLE
[6B7]
[6D7]
602-7R375-0000-D00
2
REV
PAGE
4.02
1
48
8
D
C
7
6
5
4
T4C27
TEE_TEE
[7D7]
U5C1
U_SWREG_TPS51220_QFN32
[28B6]
T4C28
TEE_TEE
[7D7]
U5C1
U_SWREG_TPS51220_QFN32
[29B6]
T4C29
TEE_TEE
[7C7]
U5D1
SLG5NV1430V_TDFN-6_R
[30C6]
T4C30
TEE_TEE
[6C7]
U5D2
D_FLIP_FLOP_6PIN_SC70_6
[31A6]
T4C31
TEE_TEE
[4C5]
U6D1
AS3722_BGA
[31B4]
T4C32
TEE_TEE
[7D7]
U6D1
AS3722_BGA
[32C6]
T4C33
TEE_TEE
[7B7]
U6D1
AS3722_BGA
[33B5]
T4C34
TEE_TEE
[6C7]
U7B1
DDR3_X16_BGA100_2
[6C6]
T4C35
TEE_TEE
[7C7]
U7C1
DDR3_X16_BGA100_2
[7C2]
T4C36
TEE_TEE
[6C7]
U7D1
EMMC_BGA169_1
[23C5]
T4C37
TEE_TEE
[7B7]
U7D2
AS3728_CSP
[35D6]
T4C38
TEE_TEE
[6D7]
U7D3
AS3728_CSP
[35A6]
T4C39
TEE_TEE
[7D7]
U7E1
AS3728_CSP
[35B6]
T4C40
TEE_TEE
[7D7]
U8D1
AS3728_CSP
[34D6]
T4C41
TEE_TEE
[6D7]
U8E1
AS3728_CSP
[34B6]
T4C42
TEE_TEE
[7C7]
U9E1
APL5910_SOP8P_R
[15B5]
T4C43
TEE_TEE
[4C5]
Y2C1
XTAL_HC49_R
[19A6]
T4C44
TEE_TEE
[6C7]
Y6D1
XTAL_CER_2P_R
[31B2]
T4C45
TEE_TEE
[7D7]
Y8B1
XTAL_SMD4P_R
[8A4]
T4C46
TEE_TEE
[7B7]
T4C47
TEE_TEE
[7B7]
T4C48
TEE_TEE
[7D7]
T4C49
TEE_TEE
[7B7]
U1B1
SERIAL_RS232_3V3_TSSOP16_ [18C4]
3
2
1
D
C
R
U1B2
LEVEL_SHIFTER_2BIT_SSOP8_ [18C6]
R
U1B3
LEVEL_SHIFTER_2BIT_SSOP8_ [18B6]
R
B
A
U1B4
POWER_SW_SON7_R
[13A6]
U1C1
POWER_SW_SON8_R
[17B6]
U1D1
PCA9306_QFN8_R
[22C3]
U1E1
ALC5639_QFN48
[20B5]
U2A1
EEPROM_2WIRE_8PIN_DFN08_R [18D4]
U2A2
AS3728_CSP
[34A6]
U2C1
POWER_SW_BGA04_R
[30A7]
U2C2
TEMP_SENSOR_DFN08
[18A5]
U2D1
SLG5NV1430V_TDFN-6_R
[30A4]
U2D2
RTL8111GS_QFN-33_R
[19B5]
U2D3
POWER_SW_SOT23_5B_R
[17C7]
U3A1
EEPROM_SPI_8PIN_SOIC_R
[23A5]
U3C1
T124MID_BGA
[4C6]
U3C1
T124MID_BGA
[5B5]
U3C1
T124MID_BGA
[8C5]
U3C1
T124MID_BGA
[9C5]
U3C1
T124MID_BGA
[10B5]
U3C1
T124MID_BGA
[11C6]
U3C1
T124MID_BGA
[12B3]
U3C1
T124MID_BGA
[14C5]
U3E1
SLG5NV1430V_TDFN-6_R
[16B2]
U4A1
RST_MON_SOT23_6PIN_R
[22A5]
U4A3
RST_MON_SOT23_3_R
[22B5]
U4B1
DDR3_X16_BGA100_2
[6C2]
U4B2
POWER_SW_BGA04_R
[30B3]
U4C1
DDR3_X16_BGA100_2
[7C6]
U5A1
BUFFER_5PIN_SC70_R
[22A3]
U5C1
U_SWREG_TPS51220_QFN32
[27B5]
B
A
TITLE
?
NVIDIA
CONFIDENTIAL
<->
8
7
6
5
4
3
DOC NUMBER
602-7R375-0000-D00
2
REV
PAGE
4.02
1
49