SEMICONDUCTOR MEMORIES

Transcription

SEMICONDUCTOR
MEMORIES
Digital Integrated Circuits
Memory
© Prentice Hall 1995
Chapter Overview
• Memory Classification
• Memory Architectures
• The Memory Core
• Periphery
• Reliability
Memory
Semiconductor Memory
Classification
RWM
Random
Access
Non-Random
Access
SRAM
FIFO
DRAM
LIFO
NVRWM
ROM
EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
FLASH
Shift Register
CAM
Memory
Memory Architecture: Decoders
M bits
S1
N Words
S2
SN-2
SN_1
S0
Word 0
Word 0
Word 1
Word 2
Storage
Cell
Word 1
A1
Word 2
A K-1
Word N-2
Word N-2
Word N-1
Word N-1
Input-Output
(M bits)
Input-Output
(M bits)
N words => N select signals
Too many select signals
A0
Memory
Storage
Cell
Decoder
S0
M bits
Decoder reduces # of select signals
K = log2N
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
L-K
AK
AK+1
AL-1
Bit Line
Storage Cell
Row Decoder
2
Word Line
M.2
Sense Amplifiers / Drivers
A0
Column Decoder
A K-1
K
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
Input-Output
(M bits)
Memory
Hierarchical Memory Architecture
Row
Address
Column
Address
Block
Address
Global Data Bus
Control
Circuitry
Block Selector
Global
Amplifier/Driver
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Memory
Memory Timing: Definitions
Read Cycle
READ
Read Access
Read Access
Write Cycle
WRITE
Write Access
Data Valid
DATA
Data Written
Memory
Memory Timing: Approaches
MSB
Address
Bus
LSB
Row Address Colum n Address
Address
Bus
RAS
Address
Address transition
initiates memory operation
CAS
RAS-CAS timing
DRAM Timing
Multiplexed Adressing
Memory
SRAM Timing
Self-timed
MOS NOR ROM
VDD
Pull-up devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0]
BL[1]
Memory
BL[2]
BL[3]
MOS NOR ROM Layout
Metal1 on top of diffusion
WL[0]
GND (diffusion)
WL[1]
Polysilicon
Basic cell
10 λ x 7 λ
Metal1
2λ
WL[2]
WL[3]
Only 1 layer (contact mask) is used to program memory array
Programming of the memory can be delayed to one of
last process steps
Memory
MOS NOR ROM Layout
BL[0]
BL[1]
BL[2]
BL[3]
Threshold raising
implant
WL[0]
GND (diffusion)
Basic Cell
8.5 λ x 7 λ
Metal1 over diffusion
WL[1]
Polysilicon
WL[2]
WL[3]
Threshold raising implants disable transistors
Memory
MOS NAND ROM
VDD
Pull-up devices
BL[0]
BL [1]
BL[2]
BL[3]
WL[0]
WL[1]
WL[2]
WL[3]
All word lines high by default with exception of selected row
Memory
MOS NAND ROM Layout
Diffusion
Polysilicon
Basic cell
5 λx 6 λ
Threshold
lowering
implant
No contact to VDD or GND necessary;
drastically reduced cell size
Loss in performance compared to NOR ROM
Memory
Equivalent Transient Model for MOS NOR
ROM
VDD
Model for NOR ROM
BL
rword
WL
Cbit
cword
Word line parasitics
Resistance/cell: (7/2) x 10 Ω/q = 35 Ω
Wire capacitance/cell: (7λ × 2λ) (0.6)2 0.058 + 2 × (7λ × 0.6) × 0.043 = 0.65 fF
Gate Capacitance/cell: (4λ × 2λ) (0.6)2 1.76 = 5.1 fF.
Bit line parasitics:
Resistance/cell: (8.5/4) x 0.07 Ω/q = 0.15 Ω (which is negligible)
Wire capacitance/cell: (8.5λ × 4λ) (0.6)2 0.031 + 2 × (8.5λ × 0.6) × 0.044 = 0.83 fF
Drain capacitance/cell: ((3λ × 4λ) (0.6)2 × 0.3 + 2 × 3λ × 0.6 ×0.8) × 0.375 +
4λ × 0.6 × 0.43 = 2.6 fF
Memory
Equivalent Transient Model for MOS NAND
ROM
VDD
BL
CL
rbit
Model for NAND ROM
rword
WL
cbit
cword
Word line parasitics:
Resistance/cell: (6/2) x 10 Ω /q = 30 Ω
Wire capacitance/cell: (6λ × 2λ) (0.6)2 0.058 + 2 × (6λ × 0.6) × 0.043 = 0.56 fF
Gate Capacitance/cell: (3λ × 2λ) (0.6)2 1.76 = 3.8 fF.
Bit line parasitics:
Resistance/cell: ∼ 10 k Ω , the average transistor resistance over the range of interest.
Wire capacitance/cell: Included in diffusion capacitance
Source/Drain capacitance/cell: ((3λ×3 λ) (0.6)2 × 0.3 + 2 × 3λ× 0.6 × 0.8) × 0.375 + ( 3λ × 2λ) (0.6)2
× 1.76 = 5.2 fF
Memory
Propagation Delay of NOR ROM
Word line delay
Consider the 512×512 case. The delay of the distributed rc-line containing M
cells can be approximated using the expressions derived in Chapter 8.
2
2
tword = 0.38 (rword × cword ) M = 0.38 (35 Ω × (0.65 + 5.1) fF) 512 = 20 nsec
Bit line delay
Assume a (2.4/1.2) pull-down device and a (8/1.2) pull-up transistor. The bit
line switches between 5 V and 2.5 V.
Cbit = 512 × (2.6 + 0.8) fF = 1.7 pF
IavHL = 1/2 (2.4/0.9) (19.6 10 -6)((4.25)2/2 + (4.25 × 3.75 - (3.75) 2/2)) 1/2 (8/0.9) (5.3 10-6 ) (4.25 × 1.25 - (1.25)2/2) = 0.36 mA
tHL = (1.7 pF × 1.25 V) / 0.36 mA = 5.9 nsec
The low-to-high response time can be computed using a similar approach.
tLH = (1.7 pF × 1.25 V) / 0.36 mA = 5.9 nsec
Memory
Decreasing Word Line Delay
Driver
Polysilicon word line
WL
Metal word line
(a) Driving the word line from both sides
Metal bypass
WL
K cells
Polysilicon word line
(b) Using a metal bypass
(c) Use silicides
Memory
Precharged MOS NOR ROM
VDD
φpre
Precharge devices
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
BL[0] BL[1]
BL[2] BL[3]
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
Memory
Floating-gate transistor (FAMOS)
Floating gate
Gate
D
Drain
Source
tox
G
tox
p
+
n
+
S
n
Substrate
(a) Device cross-section
Memory
(b) Schematic symbol
Floating-Gate Transistor Programming
20 V
0V
20 V
10 V→ 5 V
S
D
Avalanche injection.
− 5V
S
5V
0V
D
Removing programming voltage
leaves charge trapped.
Memory
− 2.5 V
S
5V
D
Programming results in
higher V T.
FLOTOX EEPROM
Floating gate
I
Gate
Drain
Source
VGD
− 10 V
20-30 nm
10 V
n+
n+
Substrate
p
10 nm
(a) Flotox transistor
(b) Fowler-Nordheim I-V characteristic
BL
WL
VDD
(c) EEPROM cell during a read operation
Memory
Flash EEPROM
Control gate
Floating gate
Thin tunneling oxide
erasure
n+ source
programming
n+ drain
p-substrate
Memory
Cross-sections of NVM cells
Flash
Courtesy Intel
Memory
EPROM
Characteristics of State-of-the-art
NVM
Memory
Read-Write Memories (RAM)
• STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
• DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
Memory
6-transistor CMOS SRAM Cell
WL
VDD
M2
M4
Q
M6
Q
M5
M1
M3
BL
BL
Memory
CMOS SRAM Analysis (Write)
WL
VDD
M4
Q=0
M6
Q=1
M5
M1
VDD
BL = 1
V
,M6 (
kn
DD
BL = 0
2
2
VDD VDD
VDD VDD
= k
( V – V )----------– ----------- 
– VTn )----------- – ----------p
M4
DD
Tp
,
2
2

8 
8 
k n M5 V
VDD 2
V DD V 2
,
DD
DD 
-----------------------– VTn ----------- = k n ,M1 ( VDD – VTn )----------- – ----------2
2  2

 2 
8 
Memory
(W/L)n,M6 ≥ 0.33 (W/L)p,M4
(W/L)n,M5 ≥ 10 (W/L)n,M1
CMOS SRAM Analysis (Read)
WL
VDD
M4
BL
Q=0
M6
M5
Q=1
M1
VDD
BL
V DD
VDD
Cbit
C bit
2
VDD V DD
k n,M5 VDD
V DD 2





--------------- ------------ – VTn -----------= k n,M1 ( VDD – V Tn )------------ – ------------ 

 2 
2
2  2
8 
(W/L)n,M5 ≤ 10 (W/L)n,M1
(supercedes read constraint)
Memory
6T-SRAM — Layout
VDD
M2
M4
Q
Q
M1
M3
GND
M5
M6
BL
Memory
WL
BL
Resistance-load SRAM Cell
WL
VDD
RL
RL
Q
Q
M4
M3
BL
M1
M2
BL
Static power dissipation -- Want RL large
Bit lines precharged to VDD to address t p problem
Memory
3-Transistor DRAM Cell
BL1
BL2
WWL
WWL
RWL
RWL
M3
X
M1
X
M2
VDD -VT
BL1
VDD
BL2
VDD -VT
CS
∆V
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL -VTn
Memory
3T-DRAM — Layout
BL2
BL1
GND
RWL
M3
M2
WWL
M1
Memory
1-Transistor DRAM Cell
BL
WL
Write "1"
Read "1"
WL
M1
X
CS
VDD − VT
GND
VDD
BL
VDD /2
CBL
sensing
VDD /2
Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
CS
∆ V = VBL – V PRE = ( V BIT – V PRE )-----------------------C S + CBL
Voltage swing is small; typically around 250 mV.
Memory
DRAM Cell Observations
1T DRAM requires a sense amplifier for each bit line, due to
charge redistribution read-out.
DRAM memory cells are single ended in contrast to SRAM cells.
The read-out of the 1T DRAM cell is destructive; read and
refresh operations are necessary for correct operation.
Unlike 3T cell, 1T cell requires presence of an extra capacitance
that must be explicitly included in the design.
When writing a “1” into a DRAM cell, a threshold voltage is lost.
This charge loss can be circumvented by bootstrapping the
word lines to a higher value than VDD .
Memory
1-T DRAM Cell
Capacitor
Metal word line
M1 word
line
SiO2
poly
Field Oxide
n+
n+
poly
Inversion layer
induced by
plate bias
Diffused
bit line
Polysilicon
Polysilicon
plate
gate
(a) Cross-section
(b) Layout
Used Polysilicon-Diffusion Capacitance
Expensive in Area
Memory
SEM of poly-diffusion capacitor 1T-DRAM
Memory
Advanced 1T DRAM Cells
Word line
Insulating Layer
Cell plate
Capacitor dielectric layer
Cell Plate Si
Capacitor Insulator
Transfer gate
Refilling Poly
Isolation
Storage electrode
Storage Node Poly
Si Substrate
2nd Field Oxide
Trench Cell
Stacked-capacitor Cell
Memory
Periphery
•Decoders
•Sense Amplifiers
•Input/Output Buffers
•Control / Timing Circuitry
Memory
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Memory
Dynamic Decoders
Precharge devices
GND
GND
VDD
WL3
WL3
VDD
WL2
VDD
WL1
WL2
WL1
VDD
WL0
V DD φ
A0
A0
A1
A1
Dynamic 2-to-4 NOR decoder
WL0
A0
A0
A1
A1
φ
2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern
Memory
A NAND decoder using 2-input predecoders
WL 1
WL 0
A0A1 A0 A1 A0A1 A0A 1
A1 A 0
A0
A1
A 2A3 A2 A3 A2A3 A2A3
A3 A2
A2
A3
Splitting decoder into two or more logic layers
produces a faster and cheaper implementation
Memory
4 input pass-transistor based column
decoder
A0
A1
2 input NOR decoder
BL 0
BL1
BL 2
BL3
S0
S1
S2
S3
D
Advantage: speed (t pd does not add to overall memory access time)
only 1 extra transistor in signal path
Disadvantage: large transistor count
Memory
4-to-1 tree based column decoder
BL0
BL 1
BL2
BL 3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
Memory
Decoder for circular shift-register
VDD
VDD
VDD
WL0
VDD
VDD
WL 1
φ
φ
VDD
WL 2
φ
φ
φ
φ
...
R
φ
φ
R
φ
φ
R
φ
φ
VDD
Memory
Sense Amplifiers
t
make ∆V as small
as possible
C ⋅∆ V
= ---------------p
I av
large
small
Idea: Use Sense Amplifer
small
transition
s.a.
input
Memory
output
Differential Sensing - SRAM
VDD
VDD
PC
BL
VDD
EQ
VDD
y M3
BL
M1
x
SE
WLi
M4
M2
y
x x
x
M5
SE
(b) Doubled-ended Current Mirror Amplifier
VDD
SRAM cell i
y
Diff.
Sense
x
x
Amp
y
y
D
D
x
x
SE
(a) SRAM sensing scheme.
y
(c) Cross-Coupled Amplifier
Memory
Latch-Based Sense Amplifier
EQ
BL
BL
VDD
SE
SE
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
Memory
Single-to-Differential Conversion
WL
BL
x Diff.
x
+
_
S.A.
cell
y
Vref
y
How to make good V ref?
Memory
Open bitline architecture
EQ
L1
R
L0
R0
R1
L
VDD
SE
BLL
CS
...
CS
BLR
CS
SE
dummy
cell
CS
...
CS
CS
dummy
cell
Memory
DRAM Read Process with Dummy Cell
V (Volt)
6.0
4.0
BL
2.0
BL
5.0
1
2
3
t (nsec)
(a) reading a zero
4
5
6.0
4.0
V (Volt)
0.00
SE
3.0
2.0
EQ
1.0
0.00
V (Volt)
4.0
BL
2.0
0.00
WL
1
2
3
4
(c) control signals
5
BL
1
2
3
t (nsec)
4
5
(b) reading a one
Memory
Single-Ended Cascode Amplifier
VDD
Vcasc
WLC
WL
Memory
DRAM Timing
Memory
Address Transition Detection
VDD
A0
DELAY
td
A1
DELAY
td
AN-1
DELAY
td
ATD
ATD
...
Memory
Reliability and Yield
Memory
Open Bit-line Architecture — Cross Coupling
EQ
WL1
WL0
WL D
CWBL
WLD
WL 0
CWBL
WL1
BL
BL
Sense
CBL
C
C
C
Amplifier
Memory
CBL
C
C
C
Folded-Bitline Architecture
WL1
BL
...
BL
WL0 WL0
CWBL
WL1
WLD
WL D
CBL
C
y
x
C
C
C
C
Sense
C
EQ Amplifier
x
CBL
y
CWBL
Memory
Transposed-Bitline Architecture
BL’
Ccross
BL
SA
BL
BL"
(a) Straightforward bitline routing.
BL’
BL
Ccross
SA
BL
BL"
(b) Transposed bitline architecture.
Memory
Alpha-particles
α-particle
WL
VDD
BL
SiO2
n+
1 particle ~ 1 million carriers
Memory
Yield
Yield curves at different stages of process maturity
(from [Veendrick92])
Memory
Redundancy
Row
Address
Redundant
rows
:
Fuse
Bank
Memory
Array
Column Decoder
Memory
Row Decoder
Redundant
columns
Column
Address
Redundancy and Error Correction
Memory
Programmable Logic Array
Product Terms
x0x1
x2
AND
PLANE
OR
PLANE
f0
x0
x1
f1
x2
Memory
Pseudo-Static PLA
GND
GND
GND
VDD
GND
GND
GND
GND
VDD
x0
x0
x1
x1
x2
AND-PLANE
x2
f0
f1
OR-PLANE
Memory
Dynamic PLA
φAND
VDD
GND
φOR
φOR
φAND
V DD
x0
x0
x1
x1
x2
AND-PLANE
x2
f0
f1
GND
OR-PLANE
Memory
Clock Signal Generation
for self-timed dynamic PLA
φ
φAND
φ
Dummy AND Row
φAND
φAND
φOR
Dummy AND Row
φOR
(a) Clock signals
(b) Timing generation circuitry.
Memory
PLA Layout
And-Plane
VDD
x0 x0 x1 x1 x2 x2
Pull-up devices
Memory
Or-Plane
φ
f0 f1
Pull-up devices
GND
PLA versus ROM
Programmable Logic Array
structured approach to random logic
“two level logic implementation”
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLA’s has drastically reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
Memory
Semiconductor Memory Trends
Memory Size as a function of time: x 4 every three years
Memory
Increasing die size
factor 1.5 per generation
Combined with reducing cell size
factor 2.6 per generation
Memory
Technology feature size for different SRAM generations
Memory

SEMICONDUCTOR MEMORIES

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