Versatile RRAM Technology and Applications

Versatile RRAM Technology
and Applications
Hagop Nazarian
Co-Founder and VP of Engineering, Crossbar Inc.
Flash Memory Summit 2015
Santa Clara, CA
1
Agenda
 Overview of RRAM Technology
 RRAM for
• Embedded Memory
• Mass Storage Memory
• Storage Class Memory
• FPGA Configuration, NVRAM,
State Retainer
• Monolithic system integration
Flash Memory Summit 2015
Santa Clara, CA
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Crossbar’s RRAM Technology
• Simple device structure using fab friendly materials and process
• Information is stored in the form of metallic nano-filament in a non-conductive layer
• Filamentary-based switching by electric field
Program/set
Reading a programmed
cell
LOW RESISTANCE
(LRS or ON)
Flash Memory Summit 2015
Santa Clara, CA
Reset
Reading an
erased cell
HIGH RESISTANCE
(HRS or OFF)
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Crossbar Technology
+
Suited for low latency, high speed
embedded memory
Flash Memory Summit 2015
Santa Clara, CA
S
=
Normalized Current
R
Crossbar SR Cell
Crossbar Selector
Normalized Current
Normalized Current
Crossbar RRAM Cell
R
S
Suited for high density high performance
NAND or SCM memory
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Scaling Improves Crossbar RRAM
 Scaling RRAM device
• Roff increases by
Roff
Ron
1
𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴
• Ron Stays nearly constant




Roff/Ron ratio improves
Sensing window improves
Improves BER
Provides additional margin for MLC/TLC
r = 40nm
r = 20nm
Ioff=1uA
Roff=1MΩ
Ioff=0.25uA
Roff=4MΩ
Flash Memory Summit 2015
Santa Clara, CA
r = 10nm
Ioff=62nA
Roff=16MΩ
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Benefits of Crossbar Embedded RRAM
•
CMOS + RRAM
No Change to Front-end
CMOS
•
•
•
CMOS + e-Flash
•
Flash Memory Summit 2015
Santa Clara, CA
Major changes to Front-end
Complex cell
High voltage transistors
Adds 6+ Masks & 40 steps
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Benefits of Crossbar Embedded RRAM
•
•
•
•
•
Back-end process – minimum impact
RRAM located between metal layers
Adds only 2 masks & 8 steps
32% lower cost
Smaller die size
1T1R RRAM 1P9M
Flash Memory Summit 2015
Santa Clara, CA
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Advantages of RRAM for Embedded Memory
Scales with
advanced nodes
Reduced
Manufacturing
Complexity
 CMOS compatible
material
 Back-end process No change in front-end
Flash Memory Summit 2015
Santa Clara, CA
Cost
 Reduced masking
steps
Performance
 Byte/Page Alterability
 Write operation – no
need for block erase
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RRAM for Mass Storage
Performance




Latency reduction
Byte/Page alterability
Smaller page sizes
Write - no need for block erase
Superior endurance
& retention
Density and
Scalability
Utilizes standard
CMOS process
 3D crosspoint array
stackable at advanced
nodes
 Mass storage
available to Fabless
companies
Flash Memory Summit 2015
Santa Clara, CA
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Crossbar Memory Byte/Page Alterability
Demonstration
CROSSBAR
RRAM
Byte Alteration (µs)
CROSSBAR
RRAM
RRAM Device
RRAM Based System byte alteration within µSeconds
NAND or NOR FLASH device
NAND
FLASH
1) Copy to DRAM
NAND
FLASH
2) Block Erase (ms)
NAND
FLASH
3) Byte
Alteration
NAND
FLASH
DRAM device
4) Program to Flash
~100 of ms
NAND and NOR Flash Based System byte alteration within 100s of ms
Flash Memory Summit 2015
Santa Clara, CA
NAND-Based
StorageCard
Card
RRAM-Based Storage
Nand Memories are Replaced
with RRAM
Services 150K transactions per second
Responds to single transaction within 150us
Services
20X
More Transactions
Responds to
Transactions
30X Faster
Memory Controller
RRAM
Bank
NAND
Memory
RRAM Memory Chip
Bit-Error Rate
Requirement Decreases
Dramatically
RRAM
HOST
HOST
Interface
CTRL
Buffer
ECC
ECC
RRAM
NAND
I/F
Small Buffer due to Very Fast
Program and Read time
Configuration
Performance
Increases
Substantially
Flash Memory Summit 2015
Santa Clara, CA
NANDBank
Memory
RRAM Memory Chip
RRAM
NAND
Bank
NAND
Memory
Memory
RRAM Memory Chip
CPU
Command
Status
ROM
RAM
Small CPU due to
Simplicity of Managing
RRAMs
RRAM
NAND
NAND
Bank
Memory
Memory
RRAM Memory Chip
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Crossbar Patented IP Libraries
FPGA Configuration Bit
NVRAM
Vdd
BL
WL
DN
D
Combinational Logic
(MUX, LUT etc..)
WL
BLN
GND
State Retainer
• Instant On
• Eliminates external non-volatile
memory
DFF
D
Q
CLK
RST
IN
OUT
Combinational
Logic
WRRAM
RRRAM
DFF
D Q
CLK
RST
• Stores data at power down
• Recalls at power up
• Power saving
Flash Memory Summit 2015
Santa Clara, CA
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RRAM for FPGA Configuration Bits, NVRAM,
State Retainer
 Major Advantages:
• NV Configuration bit
• Area reduction
• Performance improvement
• Power reduction
• Instant on
– No need for external non-volatile memory
• Embedded non-volatile memory for data/code/storage
Flash Memory Summit 2015
Santa Clara, CA
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RRAM for Monolithic Integration
40bit
Mass Storage
45bit
NVRAM
Config
Power up/down
Code Memory
Data Memory
17bit
CPU + SRAM
6bit
DRAM
Data Memory-NOR
Mass Storage-NAND
Code Memory-SPI
• Elimination of large number of I/Os, and simplification of the external interface
• Reduction of components
• Power reduction due to elimination of large number of I/O
• Breakthrough performance
• Direct wide bus connection between memory and CPU/peripheral devices
Crossbar technology = True high performance integrated system
Flash Memory Summit 2015
Santa Clara, CA
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Monolithic Integration of NVMemory with
Crossbar RRAM
Crossbar RRAM Technology Enables Monolithic integration of:
Embedded memory with
1T1R
Code/Config/
NVRAM
Memory
SCM with 1T1R or 1TnR
Mass storage
with 1TnR
FPGA configurable logic,
CPU with 1T1R
Mass Storage Memory
Periphery
M4
M3
M2
M1
Periphery
Flash Memory Summit 2015
Santa Clara, CA
Crossbar Unique RRAM
Versatile Technology
 Monolithic integration of Storage, Code, Data,
FPGA configuration bit memories in one silicon
 Breakthrough system performance enabled with the
monolithic integration of various memory
architectures
 Fabless companies access IPs for a complete
memory solution (storage, code, data, and FPGA
configuration) from CMOS foundries
Flash Memory Summit 2015
Santa Clara, CA
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Ready for Business
Crossbar RRAM 300mm Wafer
Crossbar RRAM Die
Flash Memory Summit 2015
Santa Clara, CA
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Crossbar-inc.com
Flash Memory Summit 2015
Santa Clara, CA
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