Alexey Petrukhin - the CMS group at DESY!

Transcription

Pixel module testing at DESY
Alexey Petrukhin, DESY
24/02/2012
• Installation at DESY
• Progress since visit
to PSI
• Some test results
Setup at DESY
Module
adapter
Pixel
module
Support finger
Universal pixel
test board
A. Petrukhin: Module testing at DESY
2
Upgrade meeting, 24.02.2012
Pixel module
Signal & power
cables
High Density
Interconnect (HDI)
Silicon sensor
16 ROCs
Base stripes
3
Module testing procedure
• Progress since visit to PSI: we can see Ultra Black level now! Ultra
Black level is used to mark the beginning of the data packet and to
separate individual ROC information. It needed a code and a
configureation modification: thanks to Beat Meyer!
• 'Pretest': making a set of new DAC parameters for each ROC. Total
time per module = 15 min.
• 'Full test': making most important tests for module qualification.
Total time = 1 hour.
• Trimming procedure: setting Trim bits for each pixel to unify
thresholds. Total time = 80 min.
• Gain calibration: extract 4160 calibration factors for each ROC.
Total time = 7 hours (can be still optimized by time delays)
4
psi46 DACs, Pretest
13 VIBias_Bus 30
14
Vbias_sf 10
15 VoffsetOp 55
16
VIbiasOp 115
17 VOffsetR0 120
18
VIon 115
19 VIbias_PH 130
20 Ibias_DAC 122
21 VIbias_roc 220
1
Vdig
6
2
Vana 150
3
Vsf 160
4
Vcomp 10
5 Vleak_comp
0
6
VrgPr
0
7
VwllPr 35
8
VrgSh
0
9
VwllSh 35
10
VhldDel 130
11
12
253
254
Vtrim
7
VthrComp 124
CtrlReg
WBC
0
20
5
22
23
24
VIColOr 100
Vnpix
0
VSumCol
0
25
26
27
Vcal 200
CalDel 125
RangeTemp
0
psi46 pixel readout chip
4 trim bits
adjustable by programmable DAC, per ROC
programmable register, per pixel
6
psi46 pixel readout chip
adjustable by programmable DAC
7
Some test results
8
Module readout
• Arm 1 pixel in ROC 0
• ADC
Count 70
Data:
-724 -725 -731 -8 -196 -191 -190 176 :
-698 12 585 : -170 12 555 202 -171 -73 :
-695 26 569 : -698 -18 591 : -673 23 660 :
-702 -13 534 : -686 -3 569 : -706 12 611 :
-699 -12 532 : -697 -4 576 : -700 -39 555 :
-697 9 619 : -700 -7 551 : -701 -6 543 :
-693 25 636 -700 -7 566 : -702 -1 534 :
-731 -722 -17 -5 -183 167 -191 176
9
(TBM header)
(ROC with 1 hit)
(3 empty ROCs)
(3 empty ROCs)
(3 empty ROCs)
(3 empty ROCs)
(3 empty ROCs)
(TBM trailer)
Analog data
Ed Bartz (Rutgers University)
10
TBM Header – Trailer format
Ed Bartz (Rutgers University)
11
GUI
Calibrations
Individual
tests
Parameter
adjusting
12
counts
DACs after Pretest
DAC value
DACs for 16 ROCs changed after Pretest:
Vana – analog voltage regulator
Vtrim – trim bits scale factor
VthrComp – comparator threshold
VoffsetOp – shifts PH range
Ibias_DAC – analogue ROCs level
CalDel – delay of calib. signal
13
Power dissipation
M 1207
●
●
Module power consumption increased by factor of ~13
Different current behavior for single ROC and Module
ROC 2
14
CalDel and Time walk
• Pulse one pixel, read
data
noise limit
• Vcal 200 small DAC.
earlier
later
50 % of width
BC
BC
• Set by Pretest:
‣ VthrComp=105
‣ CalDel=80
50 DAC units
Vcal too
small
• Moving the threshold
shifts the timing:
Threshold
‣ time walk.
15
Threshold Scan and Power (Nov'11)
Id [mA]
• Chip 2 (no sensor)
• Id (mA) vs VthrComp
• Threshold into noise
• Chip consumes 2.5 times
more power at low
threshold (high VthrComp)
VthrComp [DAC]
Ia [mA]
• Chip 2 (no sensor)
• Ia (mA) vs VthrComp
• Small effect at low threshold
• The same trend for Chip 6
(sensor)
VthrComp [DAC]
16
Threshold Scan of M1207
noise peak
hard threshold
•
Drive threshold into noise:
•
Chip consumes 2 times more power at low threshold (high VthrComp)
•
The effect is not observed for Ia
17
Threshold optimization algorithm
●
●
●
●
If comparator thresholds are adjusted with global VthrComp only:
spread of thresholds in ROC ~300 e- due to transistor mismatches
Unify pixel thresholds by 4 trim bits (values from 0 to 15) and scale
with Vtrim DAC
Each trim bit value is set such that Vcal-threshold of the pixel differs
least from the selected target threshold in the procedure
Use as low target Vcal as possible: good charge sharing, good for
radiated chips with low charges
18
16 threshold maps, trimmed
• M1207, all pixels
• 4160x16 TrimBits set (target Vcal=60)
• 340 e threshold variation
• 6% spread: better than single chip
before trimming
• Peak is higher than expected: 5.2 ke
instead of 3.9 ke ?
19
Trimming results, M1207
TrimVcal=60
TrimVcal=50
TrimVcal=40
Underflows: bad fit of Scurves
Peaks are ~30% higher than
expected (?)
20
Summary
• Last trip to PSI was very useful: many new tests are working now
• The Module testing procedure is installed at DESY
• It gives the reasonable results
• Some issues in Trimming procedure → under investigation
• More tests are not really applied yet: the Cold Box test, IV test, usage of
DB ...
21
Back up
22
Gain and linear range
• One pixel.
preamp/shaper
saturation
• CtrlReg 4:
‣ 450 e/DAC
• Linearity is important
for spatial resolution
using charge sharing.
450 e/DAC
• Saturation around
45'000 e (~2 MIP).
23

Alexey Petrukhin - the CMS group at DESY!

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