UMC 0.18µm radiation hardness studies Sven Löchner CBM

Transcription

UMC 0.18µm radiation hardness studies
Sven Löchner
CBM-XYTER Family Planning Workshop
GSI Darmstadt
December 5th, 2008
Experiment Electronics
Agenda
• GRISU chip project
– Overview
• Single Event Effects test
–
–
–
–
Mechanism
Testability
Results
Summary
• Total Ionising Dose test
–
–
–
–
Pre-radiation test
Measurements after radiation
Annealing
Summary
December 5th, 2008
CBM-XYTER Family Planning Workshop - Sven Löchner
2
GRISU project
Project objectives:
• Characterisation of UMC 0.18µm CMOS process concerning
the vulnerability against Single Event Effects (SEE), especially
Single Event Upsets (SEU) and Single Event Transients (SET)
– SEU cross section for different Flip-Flop designs and layouts
– Characterisation of the critical charge Qcrit respectively the
Linear Energy Transfer (LETcrit )
– SET sensitivity of the UMC 0.18µm process
• Single Transistor measurements
– Comparison of transistor models by simulation
– Total Ionising Dose (TID)
Characterisation of the UMC 0.18µm process under irradiation,
especially leakage currents, threshold shifts, annealing, ...
December 5th, 2008
3
GRISU test ASIC
GRISU 1 chip
• UMC 0.18µm process
• 1.5 x 1.5 mm²
• 64 pads
– 28 core pads
– 36 pads
•
Test structures
for SEU
measurements
First tape out:
02/2007
Ring oscillator
for TID / SEU
measurements
Test structures
for TID
measurements
Test structures
for SET
measurements,
Qcrit
December 5th, 2008
4
GRISU 2 test ASIC
GRISU 2 chip
like previous version, but
• Modified LVDS receiver
• Test structures
– now with ESD
protection at gate
– one new transistor layout
• Second ring oscillator with
different W and L of inverters
Tape out 02/2008
December 5th, 2008
5
Single Event Effects (SEE)
SEE: two types of categories
• Cause of permanent damages (hard errors)
• Induce of temporary malfunctions (soft errors)
Only soft errors are analysed, especially:
• Single Event Upsets (SEU)
Bit flips, e.g. change of states in the digital logic
• Single Event Transient (SET)
Temporary change of the signal level in the circuit, e.g. a glitch
December 5th, 2008
6
Linear Energy Transfer (LET)
• Minimum amount of particle energy induced to a semiconductor device at which a SEE appears is called LETcrit
• The unit of LET is typical MeV·cm²/mg (related to Si for MOS)
LETcrit
3.6eV ⋅ Qcrit
=
e ⋅ ρ Si ⋅ d
d - sensitive depth of penetration
ρ - material density (Si: 2.33g/cm3)
Typical values for 0.18µm process technology:
• d = 0.5 ... 2µm
• Qcrit = 30 ... 60fC
=> LETcrit between 1.5 and 12 MeV·cm²/mg
December 5th, 2008
7
SEE Building Blocks
3 different building blocks for SEE characterisation:
• Test structures for SEU measurements
– 8 different types of flip-flops implemented, e.g. oversized flipflops, flop-flops with Dual Interlock Cell (DICE) architecture, ...
• Test structures for SET and Qcrit measurements
– Different inverter chains
=> Qcrit,sim from 20 ... 1000fC
• 2 ring oscillator test structure
December 5th, 2008
8
SEE Testability at GSI
SEE test with heavy ions => two possibilities at GSI:
• Low Energy
– 11.4 MeV / AMU
– 103 ... 1010 p/(cm·s)
– bunches of up to 5ms “length”, frequency up to 50Hz
– different ions (C, Ni, Xe, U, ...)
– low penetration depth
=> only usable for unpackaged chips
• High Energy
– 50 ... 2000 MeV / AMU
– 100 ... 1012 p/(cm2)
– different ions (C, Ni, Xe, U, ...)
– high penetration depth
=> usable for all un-/packaged chips
December 5th, 2008
9
Low Energy testing site
• Installation of a test facility for ASIC irradiation with heavy ions
at X6 cave at GSI (in cooperation with bio physics group)
• Beam monitoring via
ionisation chamber
• Dosimetry setup available
• Irradiation of DUT in air
• Easy access
Disadvantages of setup:
• Only one ion source
during beam time
• “Fixed” LET range for ion source
December 5th, 2008
•X6 cave at GSI
10
Simulation of C-12
But:
• Setup is movable along
beam axis
• Air is used as energy
degrader
• Simulation of LET for C-12
– including complete setup
– ionisation chamber
– chip material
• Max range is 41cm from
exit window
• LET from 1.5 ... 5 MeV·cm²/mg possible
December 5th, 2008
11
Simulation of Ni-58
• Maximum range is only
11cm
• LET from 15 ... 30
MeV·cm²/mg possible
For characterisation of the
LET cross-section several
irradiation test with different
ion sources are necessary.
December 5th, 2008
12
SEE Test setup
• Hardware: Xilinx Spartan-3E Starter Kit board
–
–
–
–
control unit is in the cave
programming of GRISU memory
readout of memory after irradiation
frequency measurement of
ring oscillators
– counting of ionisation chamber
pulses
– pre-analysing of test data
– sending data to control room
• Controlling the test setup via
LabVIEW
December 5th, 2008
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Cross-section results (Weibull-Fit)
SET cross-section measurement for a minimum size inverter
data from C-12
(2..5 MeV cm²/mg)
and Ni-58
(10..30 MeV cm²/mg)
=> LETcrit =
1.94 MeV cm²/mg
=> σsat =
1.62 10-8 cm²/bit
December 5th, 2008
14
SEE Summary
• Setup a heavy ion test environment for ASIC irradiation
at low energies
• Successful operation of 5 heavy ions beam times
with different ion sources
Still to do:
• Analysing data from last beam time
(=> more cross-section points, specially for higher LETs)
December 5th, 2008
15
GRISU 2 – test structures
• Access to single transistors via core pads
– small pad geometry
– close to neighbour test pads
=> Bonding challenge
• Automatic measurement of all 16 transistors
– Output characteristic (Uds – Ids)
– Transfer characteristic (Ugs – Ids)
• Controlled via LabVIEW
• Around 15 minutes for a complete characterisation
December 5th, 2008
16
Transfer function for a minimum size NMOS (0.24 / 0.18) at
Uds = 0.1V
=> problem to simulate this behaviour with the existing models
December 5th, 2008
17
Total Irradiation Dose (TID) tests
• TID testing with X-rays
• Irradiation facility at Institute for Experimental Nuclear Physics,
University of Karlsruhe
• 60keV X-ray
• 100 ... 600krad/h
• Thanks to Mr. Dierlamm
and Mr. Simonis
for support
December 5th, 2008
18
TID tests
•
•
•
•
9 GRISU chips irradiated
Total dose between 800krad and 2500krad(SiO2)
Operating dose rate between 200krad/h and 580krad/h
Two modes of operation
– single transistor test structure measurements
leakage current, threshold shift, characteristics (offline)
– complete chip measurements
frequency of ring oscillator, total power consumption (online)
December 5th, 2008
19
TID tests – complete chip
Measurement of two ring oscillators on GRISU 2 test chip
• Total dose: 1.5Mrad
– at 490krad/h
• Decrease of the transit time
– ~ 4% for minimum size inv.
– ~ 10% for up-sized inv.
• Good annealing at room
temperature
– for min. size: even faster
• Up to 250krad:
– min. size inverter gets faster
– up-sized inverter keeps stable
December 5th, 2008
20
Measurement of power consumption on GRISU 2 test chip (core)
– at 490krad/h
• Increase of the core power
consumption
– from 10mA (pre-rad) to
22mA (1.5Mrad)
• Annealing at room temp.
– power consumption back to
pre-radiated value after
6 weeks
December 5th, 2008
21
Measurement of power consumption on GRISU 2 test chip (pad)
– at 490krad/h
• Increase of the pad power
consumption
– from 1mA (pre-rad) to
105mA (1.5Mrad)
– power consumption also
back to pre-radiated value
after 6 weeks
December 5th, 2008
22
TID tests – single transistors
Measurements of the transistor characteristics and calculation of
the threshold voltages for different dose levels
(e.g. NMOS 0.24/1.80)
• In total 6 chips are irradiated
• Total dose up to 2.5Mrad
• Decrease of threshold voltage
– ~ 20% after 1Mrd
– no further change
after 1Mrad
December 5th, 2008
23
Measurements of the transistor characteristics and extraction of
the leakage current for different dose levels
(e.g. NMOS 0.24/1.80)
• In total 6 chips are irradiated
• Total dose up to 2.5Mrad
• Increase of leakage current
– no significant increase up to
200krad
– by 3 orders of magnitude
after 2.5Mrad
December 5th, 2008
24
Measurements of the annealing and calculation of the threshold
voltage for different dose levels (e.g. NMOS 0.24/1.80)
• Detailed annealing scans
only with one 1 chip
• 2.5Mrad total dose
• Increase of threshold voltage
after 6 weeks
– still 10% under pre-radiation
value
– but no saturation reached
(maybe further increase possible)
December 5th, 2008
25
Measurements of the annealing and extraction of the leakage
current for different dose levels (e.g. NMOS 0.24/1.80)
• Detailed annealing scans
only with one 1 chip
• 2.5Mrad total dose
• Decrease of leakage current
after 6 weeks
– almost back to pre-rad value
December 5th, 2008
26
TID summary
• Final analyse of measured data
• UMC process shows good annealing at room temperature
(at least at high dose rates)
– maybe a second irradiation campaign with low dose rates
– long term test with a gamma source
• Simulation models slightly differs from measured
characteristics (especially between small and large Ugs)
• Not shown:
– Offset current for zero-Vth transistors are much higher than
predicted from simulation
– measured transition time for minimum size inverters differs ~40%
from simulation
• ...
December 5th, 2008
27
Thank you
December 5th, 2008
28
Additional Transparencies
December 5th, 2008
29
Charge collection
cross-section through an ASIC
December 5th, 2008
charge collection under the gate
30
4 groups with each 4 single transistor test structures
NMOS transistors
Zero-Vt transistors
Low-Vt transistors
Enclosed transistors
Enclosed Zero-Vt
Finger transistor (10x)
PMOS transistors
Enclosed PMOS transistor
Finger transistor (10x)
December 5th, 2008
W = 0,24 µm
L = 1,80 µm
W = 2,40 µm
L = 0,18 µm
W = 0,24 µm
L = 0,18 µm
W = 2,40 µm
L = 1,80 µm
W = 2,40 µm
L = 3,00 µm
W = 0,24 µm
L = 0,30 µm
W = 0,24 µm
L = 0,24 µm
W = 2,40 µm
L = 2,40 µm
W = 2,28 µm
L = 0,18 µm
W = 6,70 µm
L = 1,80 µm
W = 4,48 µm
L = 0,30 µm
W = 10*0,24 µm L = 0,18 µm
W = 2,40 µm
L = 1,80 µm
W = 0,24 µm
L = 0,18 µm
W = 6,70 µm
L = 1,80 µm
W = 10*0,24 µm L = 0,18 µm
W/L = 0,13
W/L = 13,33
W/L = 1,33
W/L = 1,33
W/L = 0,80
W/L = 0,80
W/L = 1,00
W/L = 1,00
W/L = 12,67
W/L = 3,72
W/L = 14,93
W/L = 13,33
W/L = 1,33
W/L = 1,33
W/L = 3,72
W/L = 13,33
31
Dual Interlock Cell (DICE)
DICE (Dual Interlock Cell)
memory technologies are
(more or less) immune
against SEU flips.
Reference:
T. Calin, M. Nicolaidis, R. Velazco
Upset Hardened Memory Design for
Submicron CMOS Technology
IEEE Transactions on Nuclear Science,
Vol. 43, No. 6, December 1996
December 5th, 2008
32
Output characterisation of a minimum size NMOS transistor
(0.24 / 0.18) at Ugs = 0.6V (left) and Ugs = 1.5V (right)
Discrepancies between measurements and simulations.
December 5th, 2008
33
Vth – simulation vs. measurement
Threshold measurement for all test structures.
Tendency to higher threshold values for all test
structures is visible.
December 5th, 2008
34

UMC 0.18µm radiation hardness studies Sven Löchner CBM

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