Keynote Speech

Transcription

Keynote Speech

The 9th International Symposium
on Embedded Technology
CONTENTS
1. ISET 2014 Committee. ......................................................... 5
2. ISET 2014 Program................................................................ 6
3. General Chairs’ Message..................................................... 8
4. Welcome Address.................................................................. 9
5. Keynote Speech Ⅰ............................................................ 11
6. Keynote Speech Ⅱ............................................................ 15
7. Keynote Speech Ⅲ............................................................ 19
8. Keynote Speech Ⅳ............................................................ 23
9. Keynote Speech Ⅴ............................................................ 27
10. Keynote Speech Ⅵ............................................................ 31
11. Theme Session A. ............................................................... 35
12. Theme Session B................................................................. 43
13. Academic Session.............................................................. 51
14. Interactive Session Ⅰ....................................................... 61
15. Interactive Session Ⅱ..................................................... 109
16. Invited Session A.............................................................. 159
17. Invited Session B. ............................................................. 171
18. Invited Session C.............................................................. 181
ISET 2014 Committee
■General Chairs
Chaedeok LIM, ETRI, Korea
Sam H. NOH, Hongik University, Korea
■Organizing Committee
Yang Yu KIL, DIP, Korea
Dong Ha LEE, DGIST, Korea
Byung-Hyun MOON, Daegu University, Korea
Yongwan PARK, Yeungnam University, Korea
Hyun-Kyu YU, ETRI, Korea
■Advisory Committee
Byoung-Chul AHN, Yeungnam University, Korea
Shik KIM, Semyung University, Korea
Jong KIM, POSTECH, Korea
Kichul KIM, FKII, Korea
Byoung Hee OH, Samsung Electronics Co., Ltd., Korea
Sang Hyuk SON, DGIST, Korea
Chuck YOO, Korea University, Korea
Yong-Kee JUN, Gyeongsang National University, Korea
■Program Committee
Chair : Minsuk LEE, NHN NEXT, Korea
Younghyun, BAE, NHN NEXT, Korea
Frank BELLOSA, Karlsruhe Institute of Technology, Germany
Jongmoo CHOI, Dankook University, Korea
Li-Pin CHANG, National Chiao-Tung University, Taiwan
Sung Woo CHUNG, Korea University, Korea
Nikil DUTT, UC Irvine, USA
Junyoung HEO, Hansung University, Korea
Hyun-Wook JIN, Konkuk University, Korea
Beobkyun KIM, ETRI, Korea
Kanghee Kim, Soongsil University, Korea
Insup LEE, University of Pennsylvania, USA
Deron LIANG, National Central University, Taiwan
Sung-Soo LIM, Kookmin University, Korea
Yuseung MA, ETRI, Korea
Daniel MOSSE’, University of Pittsburgh, USA
Moonju, PARK, Incheon University, Korea
Dong Ik, SHIN, Asan Medical Center, Korea
■Publication Committee
Jin-Suk MA, ETRI, Korea
■Publicity Committee
In-Geol CHUN , ETRI, Korea
Euiseong Seo, Sungkyunkwan University, Korea
5
The 9th International Symposium
ISET 2014 Program
■May 22(THU), 2014
11:00-13:00 Registration
[ Geumkang Hall ]
Chair : HyungJun Kim (ETRI, Managing Director)
Keynote SpeechⅠ
13:00-13:50
【IoT, Ubiquitous Computing, and Open Data for Smart Environments】
Noboru Koshizuka
University of Tokyo, Japan
Professor, Sakamura Lab
[ Geumkang Hall ]
Chair : Minsuk Lee (NHN NEXT, Dean)
Keynote Speech Ⅱ, Ⅲ
Keynote Speech Ⅱ
13:50-14:20
【An Embedded SW Policy of the Ministry of Trade, Industry & Energy】
GyuTaek Lee
KEIT, Korea
PD for Embedded Software
Keynote Speech Ⅲ
14:20-14:50
【SW R&D Policies in Creative Economy Era】
14:50-15:10
Doohyun Kim
KEIT, Korea
SW Infra & Computing CP
Coffee Break
[ Geumkang Hall ]
[ Hankang Hall ]
Theme Session A : Mobile Platform
Theme Session B : CPS & Safety Critical Platform
Chair : Sung-Soo Lim
Chair : Hyun-Wook JIN
(Konkuk Univ., Professor)
15:10-15:40
(Kookmin Univ., Professor)
Mozilla Firefox OS, Its Technical Platform and Future How to Approach Smart Factory on New Trends
Seokchan Yun
Bang-Ho Cho
(Daum Communications Corp., Technology Evangelist)
15:40-16:10
Wearable Technology - Trends and Forecasts
A Fault-tolerant OFP based on Partition Computing
Hyun-Tae Jeong
Jung-Guk Kim
(ETRI, Director)
16:10-16:40
(LG CNS, Principal Researcher)
(Hankuk Univ. of Foreign Studies, Professor)
Open Source Hardware and ICT DIY
Trends of Robot SW Platform Technologies and Applications
Hugh Hyung-uk Choi
Sang Hoon Ji
(Magic Eco, Chief maker & CEO)
Interactive Session : PosterⅠ
(KITECH, Principal Researcher)
[ Hankang Hall Corridor ]
Chair : Gyu Sang Choi (Yeungnam Univ., Professor)
16:40-17:30 Interactive Session
Keynote Speech Ⅳ
17:30-18:20
18:306
[ Geumkang Hall ]
Chair : Hyungshin Kim (Chungnam Nat’l Univ., Professor)
【 Bump Free: Real-time Warning for Distracted Pedestrians with Smartphones】
Kang G. Shin
University of Michigan, USA
Kevin and Nancy O’Connor Professor
Banquet
[ Hankang Hall ]
■May 23(FRI), 2014
08:00-09:30 Registration
Academic Session :
Source Technology Trends
[ Geumkang Hall ]
[ Hankang Hall ]
Invited Session A : ETRI
Technology Trends of Scalable Open Platforms
Chair : YungJoon Jung
Chair : Euiseong Seo
(Sungkyunkwan Univ., Professor)
(ETRI, Director)
Embedded SW Platform Trends
Multicore/GPGPU for Cyber-Physical Systems
Chang-Gun Lee
(Seoul Nat'l Univ., Professor)
Smart OS-level Power Management Techniques for
Smartphones
Sung Woo Chung
AR Service Platform Technology Trends
Young-Chang You
(FALinux, CEO)
Chuwhan Kim
(Qualcomm Korea, Senior Director)
(Korea Univ., Professor) Open IoT Platform: Mobius
Jaeho Kim
(KETI, Team Manager)
09:30-10:50 Free Open Source Software(FOSS) - Can We
Prevent the Second OpenSSL Heartbleed Bug?
Data-centric Communication Middleware for CPS based
Sam Chung on OMG DDS
(Univ. of Washington, Professor)
Soo-Hyung Lee
(ETRI, Principal Researcher)
A Remote Power Analyzer based on Power
Modeling in Heterogeneous Embedded Linux
Trend of SW Platform for Heterogeneous Multi-core
Systems
system and OpenSEED Community Activity
Young-Joo Kim
Seung-hwa Song
(ETRI, Senior Researcher)
Interactive Session : Poster Ⅱ
(IDIS Co., Ltd, Open Project Leader)
[ Hankang Hall Corridor ]
Chairs : Won-Kee Hong(Daegu Univ., Professor) / Hyun Lee (Sunmoon Univ., Professor)
10:50-11:40 Interactive Session
[ Geumkang Hall ]
Chair : Kanghee Kim (Soongsil Univ., Professor)
Sang-bum Suh
Keynote Speech Ⅴ
11:40-12:30 【Tizen, OS for Smart Devices】
12:30-13:30
Samsung Electronics Co., Korea
Vice President
Luncheon
Keynote Speech Ⅵ
13:30-14:20 【Open Source based Commercial IVI Technology Trends】
14:20-14:40
[ Four Seasons ]
[ Geumkang Hall ]
Chair : Hee Bum Jung (ETRI, Vice President)
Carlos ChungSeob Ra
Infobank Corporation, Korea
Director, Smart Car Business Division
Coffee Break
Invited Session B : DGIST
CPS & Wellness
[ Geumkang Hall ]
[ Hankang Hall ]
Invited Session C : GNU & KAI
IMA Systems for Next Generation of Aircraft and Its Applications
Chair : Kyouho Lee
Chair : Yong-Kee Jun
(Inje Univ., Professor)
(Gyeongsang Nat'l Univ., Professor)
Noise induced Tracking Error in Systems with
Design of Software Configuration Tool for Integrated
Saturating Actuators
Modular Avionics
Yongsoon Eun
Eu-Teum Choi
(DGIST, Professor)
(Gyeongsang Nat'l Univ., Student)
Networking and Applications for Vehicular Cyber- Design of Development Environment to Support
Physical Systems
Detecting Races in Airborne Software
Jaehoon (Paul) Jeong
Sun-Sook Kim
14:40-16:00
(Sungkyunkwan Univ., Professor)
(Suresoft Technologies Inc., Researcher)
Recent Trends and Issues of Wellness Human-care Switching Video Technologies for Next Generation of IMA
System
Systems
Jae Sung Choi
Sang-cheul Lee
(DGIST, Senior Research Engineer)
Wearable Cyber-Physical Systems
(Intellics Inc., Department Manager)
A Study on Feasible Configuration of AFDX Networks in
Avionics Systems
Taejoon Park
Kyong Hoon Kim
(DGIST, Professor)
(Gyeongsang Nat'l Univ., Professor)
16:00-16:30
* This Program Subject to Change.
Prize Lottery
7
2014 International Symposium on Embedded Technology
General Chairs’ Message
Welcome to the 9th International Symposium on Embedded Technology!
We follow the tradition of successful symposia in previous years, but for
the very first time, the venue moves to Seoul, the heart of Korea. We are
expecting another exciting and successful symposium where exchange of
information on recent advances and developments in embedded systems
technology will abound.
This year the theme of the symposium is Globalization through Open
Source in the Embedded World. Open source has had a profound effect
on the development of software as a whole. Software is a key component
of embedded systems, and embedded systems is becoming ever more
prevalent and an integral part of our every day life. It is thus imperative
that we look in to the interactions of open source and embedded systems
to gain perspectives on how they may impact our future as the world
becomes ever so connected.
As in previous years, the technical program of this forum brings
together researchers and developers from academia and industry who
are leaders of the embedded systems field. We are especially delighted
to have the distinguished keynote speakers who are active members
of modern embedded systems developments that pertain to the open
source community. We are positive that their experience and insights will
help enlighten the views and perspectives of all participants of this year’s
symposium.
Finally, we would like to thank the members of the organizing committee,
advisory committee, program committee, publication and publicity
committee, and sponsors of this symposium for making this symposium
possible. We would like to especially thank the authors and you, the
participants, for joining us this year. It is only through your participation
that this forum can continue be a success. We are confident that you will
enjoy the high quality presentations and lively discussions with leading
researchers at the symposium.
Chaedeok Lim and Sam H. Noh, General Chairs
8
Seoul, Korea, 22-23 May, 2014
Welcome Address
On behalf of the organizing committee, I am pleased and honored
to welcome all of you to ninth International Symposium on Embedded
Technology (ISET 2014), held in Seoul in Korea.
Embedded systems have become an integral part of daily life. Embedded
systems combine computer hardware, software and other additional
mechanical or technical components in order to perform dedicated
functions. These systems have been touching and changing modern lives
as forms of smart devices, the electronics in an automobile, airplane or
vessel, a micro-sized RFID sensor to bio-chip.
In this symposium, we hope you have the opportunity to discuss
the ideas of advanced technologies and solutions for convergences
technologies of embedded system such as IoT Ubiquitous Computing, CPS
& Safety Critical Platform, Smart-Factory, Wearable Computing, and other
most upcoming technologies solutions.
Digital IT age has extensively progressed. IEMEK hopes to and will make
every effort to contribute to technology advancement in the embedded
systems, and everyone’s academic and intellectual achievement through
ISET 2014 international symposium.
We would like to thanks all authors, members of the organizing
committee, and sponsors of this symposium for making this symposium
successful. Particular thanks go to keynote speakers from various counties. I
am sure that they will make this symposium very fruitful.
Finally, Seoul is the most energetic cities in Korea. I know that many
foreign tourists visit this city for joining many cultural events. We wish all of
you to enjoy this city, the beautiful weather of May, friendship, so that you
will remember ISET 2014 for a long time.
Thank you very much.
Heung-Nam Kim, Ph.D.
President of IEMEK, Korea
9
The 9th
International Symposium
Keynote Speech Ⅰ
IoT, Ubiquitous Computing, and Open Data for Smart
Environments
Noboru Koshizuka
University of Tokyo, Japan
Professor, Sakamura Lab
Noboru Koshizuka, Ph.D.
Talk
IoT, Ubiquitous Computing, and Open Data for Smart Environments
Affiliation
The University of Tokyo
Position
Professor, Interfaculty Initiative in Information Studies
Research
Ubiquitous Computing, IoT, Embedded Systems
13
IoT, Ubiquitous Computing, and Open Data for Smart Environments
Noboru Koshizuka
Interfaculty Initiative in Information Studies, the University of Tokyo, Japan
YRP Ubiquitous Networking Laboratory, Japan
E-mail: [email protected]
Abstract
In this talk, we will briefly review the history of IoT (Internet of Things) and/or ubiquitous computing research.
Then, we will introduce the overview of current status of our IoT applications and services; Low-Energy Smart
House, Ubiquitous Emergency Medical Services, IoT Infrastructure Maintenance System, Tokyo Ubiquitous
Technology Project, and National Standard Geo-code Infrastructure.
In IoT system, embedded systems and cloud systems are the key technologies. T-Kernel is the globally open
standard real-time embedded kernel especially for IoT applications and services. In this talk, we will introduce
the latest version of T-Kernel (μT-Kernel 2.0) and its IoT network framework on the basis of 6LoWPAN.
On the other hands, IoT systems upload big data automatically to cloud systems. Open data is very important
paradigm in utilizing the big data. Lastly, we will suggest that we should start standardization activity of Open
Data for the next step of IoT
Keywords: IoT (Internet of Things), Ubiquitous Computing, M2M Communication, Open Data
TheISET
9th International
Symposium on Embedded Technology, Seoul, Korea
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2014
1
The 9th
Keynote Speech Ⅱ
An Embedded SW Policy of the Ministry of Trade,
Industry & Energy
GyuTaek Lee
KEIT, Korea
PD for Embedded Software
Gyu Taek Lee, Ph.D.
Talk
An Embedded SW Policy of the Ministry of Trade, Industry & Energy
Affiliation
Korea Evaluation Institute of Industrial Technology, Korea
Position
Program Director for Embedded Software
Research
Control, Instrumentation and Embedded Software
17
An Embedded SW Policy of the Ministry of Trade, Industry & Energy
GyuTaek Lee
PD for Embedded SW, KEIT
Republic of Korea
Abstract
Recently Korea's R&D strategy has been changed to the first mover from the fast follower. This embedded SW
policy is made in order to jump to the advanced industrial nation. Legacy SW policy was concentrated on the
packaged SW and the maintenance SW. However as the first government policy in the field of the embedded SW,
this policy shows the Korean government's strong will which focuses on the embedded SW for the sake of the
high added-value to the existing industries. Based on the industries' needs, this policy covers 6 domains including
car, aviation, shipbuilding, electronics, machinery/robot and medical device industries. Furthermore this policy
contains creating new markets, developing highly qualified human resources and making fair trades.
In particular, this policy is connected to "SW Innovation Programme ('13.10, Ministry of Science, ICT and
Future Planning)" and "The 6th Industrial Technology Innovation Programme ('13.12, Ministry of Trade,
Industry and Energy)".
Keywords: Embedded SW, R&D, Policies, SW Innovation Programme
TheISET
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The 9th
Keynote Speech Ⅲ
SW R&D Policies in Creative Economy Era
Doohyun Kim
KEIT, Korea
Doohyun Kim, Ph.D.
Talk
Affiliation
Korea Evaluation Institute of Industrial Technology, Korea
Position
Research
Distributed Embedded SW, Open Source SW
21
Doohyun Kim
Software Infra & Computing CP, KEIT
Republic of Korea
Abstract
In this talk, the presenter will explain directions and plans for leading software technologies and industry in
creative economy era. The role of software is getting more important in building up new paradigms of industries
in the 21C. The annual growth rate of global software market is forecasted as high as 12.3% from 2013 to 2017.
It is also said that the software market in total including the game and contents is of size of the sum of mobile,
semi-conductor, and automobile market. In the last decade, software market was led by several global companies
at the leading edge in software domain. But, recently, the software is essentially utilized by non-IT industrial
domains such as military, shipbuilding, aviation, and etc. Thus, such dramatic expansions allow us to foresee the
coming new age of Software-oriented Society.
Meanwhile, although the software technologies and industry in Korea have been rapidly developed during past
20 years, the global market share of Korea software industry is only 2.8% in 2012. The amount of qualified
software engineers is under insufficiency. In order to make a monumental turning point by reversing such
deficient situations, the “Software R&D Leading Policies” has been prepared and announced. These policies
include Software Fundamental Research Center program, Software Grand-Challenge project, and Global
Creative Software package program. In this talk, those core polices will be explained in the view of the
backgrounds, structures, directions for action plans, and expectation effectiveness.
Keywords: Software, R&D, Policies, Creative Economy
TheISET
9th International
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2014
1
The 9th
Keynote Speech Ⅳ
BumpFree: Real-time Warning for Distracted Pedestrians
with Smartphones
Kang G. Shin
University of Michigan, USA
Kevin and Nancy O’Connor Professor
Kang G. Shin, Ph.D.
Talk
Bump Free: Real-time Warning for Distracted Pedestrians with
Smartphones
Affiliation
The University of Michigan
Position
Kevin & Nancy O’Connor Professor of Computer Science Department of
Electrical Engineering and Computer Science
Research
QoS-sensitive Networking and Computation, Networked Cyber-physical
Systems, Security and Privacy, Operating Systems
25
BumpFree: Real-time Warning for Distracted Pedestrians
with Smartphones
Kang G. Shin
The University of Michigan
Ann Arbor, U.S.A
Abstract
In this talk, I will present a new way of reducing the accident rate of pedestrians who make most of their
commute on foot while using smartphones. Studies have shown that using smartphones while walking – called
distracted walking –significantly increases the probability of pedestrians colliding with dangerous objects. Our
user study shows that 43% of participants have bumped into obstacles
when they walk and use their phones, and 86% of them have heard friends walking into obstacles due to
distracted walking.
A novel solution to this problem, called BumpFree, is developed as a mobile app, by using sensors commonly
available in smartphones to detect and warn users, in real time, of imminent collision with dangerous objects in
front of them via a series of vibrations on their phones. A generalized solution without any prior knowledge of
the user's environment is developed by estimating distances to nearby objects using the speakers and
microphones on the phone. This process is enhanced further by using images acquired from the phone's rear
camera, if necessary. BumpFree has been evaluated under a variety of scenarios ranging from an open lobby
and aisle to outdoor environments with walls, pillars, signboards, dustbins and people, etc., that can be commonly
found in our daily surroundings. Moreover, BumpFree consumes only a small fraction of computation and
energy resources, thus leaving the phone's intended functions and performance almost unaffected. Its
acceptability and usefulness are also demonstrated via a limited users study.
This is joint work with Yu-Chih Tung, Yaohui Li, Wenbo Wang
TheISET
9th International
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1
The 9th
Keynote Speech Ⅴ
Tizen, OS for Smart Devices
Sang-bum Suh
Samsung Electronics Co., Korea
Vice President
Sang-bum Suh, Ph.D.
Talk
Affiliation
Samsung Electronics Co.
Position
Vice President
Research
Embedded SW, Virtualization, Operating Systems
29
Sang-bum Suh
Vice President, Samsung Electronics Co
Abstract
Tizen (www.tizen.org) is a web-centric open-source, standards-based software platform for smart devices,
such as smartphones, smart TVs, IVI (In-Vehicle Infotainment) and other consumer devices like cameras,
printers, and more. Tizen is web-centric in that it directly supports web apps applications written in HTML5 and
Javascript. In this talk, we present Tizen offers an innovative operating system, applications, and a user
experience that consumers can take from various device
TheISET
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The 9th
Keynote Speech Ⅵ
Open Source based Commercial IVI Technology Trends
Carlos ChungSeob Ra
Carlos ChungSeob Ra, Ph.D.
Talk
Affiliation
Infobank Corporation
Position
Research
Management of Technology
33
Carlos ChungSeob Ra
Abstract
Recently, standardization and research about Open-source based Car Infotainment platform are made process
actively in the world vehicle market. Especially, in European vehicle market, GENIVI is organized, GENIVI
standardize that requirements achieved from OEM insert to middle ware. On the other hand, in North
America/Asia, Open Automotive Alliance for Automotive android is organized. Some Car OEM’s are already
applying the commercialization of the android platform in progress. Google, Apple also provide with
connectivity solution based on Open-source platform. This paper provides an Open-source platform for
technology trends and status of commercialized present status.
Keywords: Open Source, Linux, Android, GENIVI.
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The 9th
Theme Session A
15:10-16:40, May 22, 2014
Mobile Platform
Chair : Hyun-Wook JIN (Konkuk Univ., Professor)
NO
1
2
3
Theme Session
Mozilla Firefox OS, Its Technical Platform and Future. .................................................................................................. 36
Seokchan Yun(Daum Communications Corp., Technology Evangelist)
Wearable Technology – Trends and Forecasts................................................................................................................. 38
Hyun-Tae Jeong(ETRI, Director)
Open Source Hardware and ICT DIY.................................................................................................................................. 40
Hugh Hyung-uk Choi(Magic Echo, Chief maker & CEO)
Mozilla Firefox OS, Its Technical Platform and Future
Seokchan Yun
Daum Communications Corp.
Jeju-city, Republic of Korea
Abstract
The Firefox OS is the alternative mobile web operating system developed by Mozilla, non-profit global open
source community. This presentation explains why Mozilla developed Firefox OS as end-user product and its
innovated way of web technologies adopting embedded system. In fact, most of modern mobile devices are using
Apple's iOS and Google's Android with own native platforms and APIs, whereas Firefox OS has open standards
of Web APIs to connect between hardware as like cellular, Wi-Fi, Bluetooth and Gecko, web rendering engines.
It consists of Gonk, an embedded OS and Gaia, a web-based user interface. So web developers can make web
applications with HTML, CSS and JavaScript compared with developer's platforms of iOS's Object-C and
Android's Java application. Recent web technologies are evolved to a speed level of native applications, i.e.
asynchronous data process with Offline storage, Web Notifications API, Web Worker, Web Socket, IndexedDB
and WebRTC. It means over 8 million web developers can participate new mobile ecosystem, Firefox
Marketplace and get new opportunities to distribute fast and efficient web applications supporting multiple
devices including PCs and tablets. For this, Mozilla and its partners already released various devices as like ZTE
Open, Alcatel One Touch and LG Fireweb in 14 countries of Europe and South America in 2013. In this year,
Firefox 1.4 will be released with as like additional dual-core reference phones and $25 smartphone with ZRAMbased chipset design. Mozilla Korean community has localized Firefox OS Korean version and developed
Hangul keyboard as a voluntary based. In the future, Mozilla developed innovated technologies for low price
leadership extending global accessibility of mobile web.
Keywords: Mozilla Firefox OS, Mobile, Web API
TheISET
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Mozilla Firefox OS
its Technical Platform and
Future
Seokchan Yun
[email protected]
Daum Communications Corp.
Agenda
• Introduction - The status of Mobile
• What’s Open Web App Platform?
– Mobile Web OS and Mozilla Web APIs
• The technical structure of Firefox OS
– Gonk, Gecko and Gaia
– Development process
• Firefox OS Developer’s platform
– How to develop Mobile Apps in HTML5?
– Firefox Marketplace and app review
• The status for Korean version
• Technical Demo with real devices
• Conclusion
37
Wearable Technology – Trends and Forecasts
Hyun-Tae Jeong
Electronics and Telecommunications Research Institute
Daejeon, Republic of Korea
Abstract
Since Google has introduced the “Google Glass”, the interest in wearable devices is so hot. Through the
release of the Android Wear, Google has shown movement to preempt the wearable market such as an eyewear, a
watch and various wearable products. Samsung has unveiled the Galaxy Gear and Gear Fit, and many ICT
companies such as Sony, Pebble, and Apple are jumping into the market competition.
When accelerating competition in wearable product markets, it is very important to know what a key element
of wearable computers is. Also, it is important to consider which technology to be focused in order to settle
successfully the wearable computer market.
This talk will first present a brief history and definition of the wearable computer, and an overview of the core
technologies and applications. And then, the trend from the recently launched wearable products and
technologies will be shown. Finally, we will discuss about the forecasts of wearable industry.
Keywords: Wearable Computer/Device
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1
Table of Contents
39
Open Source Hardware and ICT DIY
Hugh Hyung-uk Choi
MagicEco
Abstract
Open source hardware is the phenomenon of new paradigm shift to makers era. Using open source hardware
with various open source softwares and tools, every single individual can be a maker. Based upon this trend, ICT
DIY(Do-It-Yourself) is becoming a totally new life style of indie makers. They create concepts, develop
prototypes in rapid, manufacture them in various open processes, and distribute through crowd sourcing
platforms to individual consumer directly. It is completely different way of new industry 2.0 revolution. It is all
about open innovation over open communities of makers. The focal point of this talk is the trend of open ICT
DIY of designers and developers how they can freely download, modify or launch prototypes. I cover several
case studies on open source hardware and their real potentials and applications. I also describe the trend of open
source communities and spaces where people are gathered in various purposes.
Keywords: ICT DIY, Open source Hardware
TheISET
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2014
1
ISET2014 Program
Open Source Hardware
and ICT DIY
!
!
Hugh Hyung-uk Choi
1
Chief maker & CEO , MagicEco
Agenda
!
1.
2.
3.
4.
Why and what open source hardwares are
Use cases of ICT DIY
Trend of communities and spaces
Direction and future
41
The 9th
Theme Session B
15:10-16:40, May 22, 2014
CPS & Safety Critical Platform
Chair : Sung-Soo Lim (Kookmin Univ., Professor)
NO
1
2
3
Theme Session
How to Approach Smart Factory on New Trends. .......................................................................................................... 44
Bang-Ho Cho(LG CNS, Principal Researcher)
A Fault-tolerant OFP based on Partition Computing. ................................................................................................... 46
Jung-Guk Kim(Hankuk Univ. of Foreign Studies, Professor)
Trends of Robot SW Platform Technologies and Applications.................................................................................... 48
Sang Hoon Ji(KITECH, Principal Researcher)
How to Approach Smart Factory on New Trends
Bang-Ho Cho
Engineering Solution Unit
LG CNS, Seoul, Republic of Korea
Abstract
Manufacturing industry is not only the key factor for one country’s overall development (economy, culture,
society), but also a criterion for the national competitive advantage. As mentioned at CPS, Industry 4.0,
manufacturing industry is facing both challenge and opportunity due to the technology development, change of
market and social trend. To overcome this situation, the mass customization production system is considered as
alternative. That system need to provide efficiency in cost, safety, environment as well. To realize that, overall
life cycle approach is required to meet customer's need dynamically in every manufacturing phase such as
product design, production, delivery, A/S. Also, for flexible manufacturing system, modular design is essential in
product, equipment, material and system. To realize that subject effectively, system model is designed under
customizing and considering in each industry properties as like business shape (B2B or B2C), industry
classification(Continuous or Discrete), the production methods and so on. Also, step-by-step approach is required
based on mid & long term road map and standardization should be utilized in ecosystem widely with
participation of economic agent which government, academia, industry.
Keywords: CPS, Industry 4.0, Manufacturing, Smart Factory, Individualized production.
TheISET
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1
How to Approach Smart Factory on new
trends
•
•
•
•
•
•
Agenda
Bang-Ho Cho
Engineering Solution Unit
LG CNS
[email protected]
2014. 5. 22
1.
Importance and Meaning of Manufacturing
2.
Changing forces for Manufacturing
3.
Emerging Technology to apply as Alternative
4.
Future Framework of Smart Factory
5.
How to Approach to Develop
6.
Consideration and Homework
7.
Conclusions
45
A Fault-tolerant OFP based on Partition Computing
Jung-Guk Kim
Department of Computer Engineering
Hankuk University of Foreign Studies, Kyunggi, Republic of Korea
Abstract
When developing a new Operational Flight Program (OFP), field tests with a new OFP include various hazards
such as S/W and H/W failures. To overcome this, a primary-shadow active replication system is commonly used.
In case that an UAV can cope with a heavy payload, dual H/W’s can be used so that the primary H/W executes a
new OFP while the shadow executing a stable legacy OFP. For an UAV with a small affordable payload, a dual
(two-version) S/W scheme on a single H/W can be used based on the partition computing. On a single H/W, an
under-development OFP is assigned to a primary partition and a stable OFP is assigned to the shadow partition.
This scheme is a S/W fault-tolerant system, however, it is not recoverable in the case of H/W faults. In this paper,
a new fault-tolerant OFP scheme called Double-Primary Double-Shadow (DPDS) system to cover both H/W and
S/W faults based on the TMO.p model is introduced. In this novel scheme, dual H/W platforms are used and each
of the hardware has a primary OFP under development and a stable-shadow OFP as non-overlapping partitions.
Keywords: OFP, UAV, TMO.p, Partition computing, DPDS, Fault-tolerant.
TheISET
9th International
46
2014
1
A Fault-tolerant OFP based on
Partition Computing
Prof. Jung-Guk Kim
Dept. of Computer Eng.
Hankuk University of Foreign Studies
[email protected]
2014. 5. 22
Real-time Operating system for Dependable Embedded Operation
http://www.rodeolab.org
Agenda
1. TMO model for real-time computing
2. TMO.p model for partition computing
3. RT-eCos.p; The RTOS platform for TMO.p
4. An OFP for an unmanned helicopter based on the TMO
model
5. PSTR (Primary-Shadow TMO.p Replication) for a S/W faulttolerant OFP system
6. DPDSTR (Double-Primary Double-Shadow TMO.p
Replication) for a H/W & S/W fault-tolerant OFP system
7. Conclusions
Real-time Operating System for Dependable Embedded Operation (http://www.rodeolab.org)
47
Trends of Robot SW Platform Technologies and Applications
Sang Hoon Ji , Sang Moo Lee and Su Jeong You
Robot R&BD Group
Korea Institute of Industrial Technology, Gyeonggi, Republic of Korea
E-mail: {robot91, lsm, sjyou21}@kitech.re.kr
Abstract
Often when a robot application is created, some elements or parts of the devices on the robot are not available
because the particular hardware items are unavailable. Sometimes, before the items are arrived, it may needed to
begin the creation of the robot application. With the help of robot SW platform, it is possible to design an
application with a mixture of real devices and virtual devise and have experience with the robotic service in the
virtual environment. This is the one case of a number of advantages taken from robot SW platform.
Moreover, there are some distinguishable challenges in robotic services including a big data issue and cloud
services, safety, and the process standardization. This makes it more difficult to select the suitable robot SW
platform and build up our robot software for the requested robotic service. So, in this paper, we look into the
development of robot SW platform and how to build up our robot software on the robot software platform.
Especially, we introduce an open source robot SW platform, OPRoS, which is composed of a simulator, an IDE
and a communication protocol.
Keywords: Intelligent Robot, Open Robot SW Platform, OPRoS (Open Platform for Robotic Services).
TheISET
9th International
48
2014
1
2014 International Symposium on
Embedded Technology
JI SANG HOON
Robot R&BD Group
Korea Institute of Industrial Technology
[email protected]
2014. 5. 22
Agenda
Introduction
Trends of Robot SW Platform
15
Development
Direction of
Conclusions
49
The 9th
Academic Session
09:30-10:50, May 23, 2014
Source Technology Trends
Chair : Euiseong Seo(Sungkyunkwan Univ., Professor)
NO
1
2
3
4
Academic Session
Multicore/GPGPU for Cyber-Physical Systems................................................................................................................ 52
Chang-Gun Lee(Seoul Nat’l Univ., Professor)
Smart OS-level Power Management Techniques for Smartphones........................................................................... 54
Sung Woo Chung(Korea Univ., Professor)
Free Open Source Software(FOSS) - Can We Prevent the Second OpenSSL Heartbleed Bug?............................ 56
Sam Chung(Univ. of Washington, Professor)
A Remote Power Analyzer based on Power Modeling in Heterogeneous Embedded Linux Systems............... 59
Young-Joo Kim(ETRI, Senior Researcher)
Multicore/GPGPU for Cyber-Physical Systems
Chang-Gun Lee
School of Computer Science and Engineering
Seoul National University, Seoul, Republic of Korea
Abstract
For future cyber-physical systems, massive sensor data processing and complex control computations are
needed in real-time, Regarding this, we discuss the possibility of using multicore/GPGPU. Major hurdles for this
are difficulty of using multicore/GPGPU parallelism under real-time constraints and difficulty of validating the
performance of multicore/GPGPU based cyber-physical systems. We present ideas to overcome these two
hurdles.
Keywords: Cyber-physical systems, Multicore/GPGPU
TheISET
9th International
52
2014
1
May 23, 2014
Multicore/GPGPU for
Cyber-Physical Systems
Chang-Gun Lee
Seoul National University
Real-Time Ubiquitous Systems Lab.
SIGCS 2014 Workshop
Contents
 Properties of Future CPS Applications
 Hurdles
 Solutions
 Simulation Results
 Conclusion
Real-Time Ubiquitous Systems Lab.
SIGCS 2014 Workshop
2
53
Smart OS-level Power Management Techniques for Smartphones
Sung Woo Chung
Division of Computer and Communication Engineering
Korea University, Seoul, 136-713 Republic of Korea
Abstract
There have been numerous OS-level power management techniques, but most of them are not so realistic
unfortunately (eg. too complicated to adopt or potential gain is marginal). On the other hand, power management
techniques in off-the-shelf mobile devices are too simple such as changing frequency and voltage by looking at
core utilization. In this research, I introduce smart OS-level power management techniques, which are applicable
to real mobile devices, as follows: 1) user-aware display power management, 2) profile-based CPU power
management, 3) thermal-aware CPU power management, and 4) battery-aware power management. All the
results shown here are based on real measurement (not simulation).
Keywords: Power management, DVFS(Dynamic Voltage Frequency Scaling), Smartphone.
TheISET
9th International
54
2014
1
Smart OS-level Power Management
Techniques for Smartphones
Sung Woo Chung
Korea University
http://smrl.korea.ac.kr
SMRL |
SoC & Microprocessor
Research Laboratory
Sung Woo Chung | May 13, 2014 | 1
Contents
1. User-aware Display Power Management
2. Profile-based CPU Power Management
3. Thermal-aware CPU Power Management
4. Battery-aware Power Management
SMRL |
SoC & Microprocessor
Research Laboratory
Sung Woo Chung | May 13, 2014 | 2
55
Free Open Source Software (FOSS)
- Can We Prevent the Second OpenSSL Heartbleed Bug?
Sam Chung*†, William Kim*, Barbara Endicott-Popovsky†
*
†
Institute of Technology, Univ. of WA, Tacoma, WA, USA
Center for Information Assurance & Cybersecurity, Univ. of WA, Seattle, WA, USA
E-mail: {chungsa, willkim, endicott}@uw.edu
Abstract
The purpose of this research is to propose software architecture driven Free Open Source Software (FOSS)
development to increase productivity of current contributors and to expedite participation of new ones. The
actual number of active participants in top FOSS projects is surprisingly very small compared to the number of
people who are using them. Also, the complexity of a popular FOSS grows over time and it prohibits
participation of new contributors. For this purpose, an architecture driven approach is proposed: software
architecture of an FOSS is re-documented from the given source code of the FOSS and is released in parallel
with the main version release of the FOSS. The architectural model is shared with FOSS contributors who need
to comprehend the FOSS.
Keywords: Free Open Source Software, FOSS, Software Architecture Re-documentation
1. Introduction
Recent news of „OpenSSL‟ Heartbleed bug exactly demonstrates how a small vulnerability of an FOSS can
affect around half a million “secure” web servers that were certified by trusted authorities. Although FOSS
projects welcome any developers to join their activities and distribute the software, the actual number of
participants is not large. Most effort depends upon the very small number of top contributors, which is shown in
Table 1. In Table 1, we chose top three most starred „GitHub‟ projects. Top contributors were measured by
number of code commits. By using statistics gathered by commits to master branch only on „GitHub‟ hosted
project (incomplete commit data may cause contributor percentages to be inaccurate), we attempted to discover
the percentage of top 3 contributors of commits in the FOSS projects.
Table 1. FOSS Project Contributors (Data gathered on April 15, 2014)
Project Name
twbs/bootstrap*
jquery/jquery*
joyent/node*
openssl/openssl
mitreid-connect/OpenID-ConnectJava-Spring-Server
Total # of
Contributors
523
191
505
21
Top Contributor
% of Commits
40.8%
28.5%
29.8%
<35.6%
Top 3 Contributors
% of Commits
56.1%
43.2%
58.7%
<36.6%
12
57.2%
81.8%
Also, since the complexity of a popular FOSS has been increased, it is not easy for new contributors to join
an active FOSS project. The general FOSS development pattern may not necessarily map directly to the stages of
traditional software development life cycle—requirements, design, implementation, testing, and maintenance. We
can see that the common lifecycle of a FOSS iteration—1) Report bug. 2a) Developer is tasked or 2b) code pull
request is submitted. 3) Change is committed to the code base—fits nice and tight to the highly iterative
implementation, testing, and maintenance loop. Currently, the vast majority of design and requirements manifest
in the form of developer documentation [1]. These take various forms such as like public wiki pages, gettingThe 9th International Symposium on Embedded Technology, Seoul, Korea
56 ISET 2014
1
started articles, reference documentations, engineering specifications, code comments, etc. At this point, we
would like to note that this documentation is essentially all textual information.
2. Architectural Visual Model as One of FOSS Resources
It is a foundational principle of software engineering that a good design is critical towards the success of a
complex and large software project. It is nearly a foregone conclusion that visual modeling of software
architecture as part of the design efforts can have significant benefits to the software maintenance process [2].
In this research, software architecture of a FOSS is re-documented from the given source code of the FOSS
and is released in parallel with the main version release of the FOSS, which is shown in Figure 1. The
architectural model is shared with FOSS contributors who need to comprehend the FOSS. As a case study, a free,
open Identity and Access Management (IAM) project‟s repository called MITREId, which is equipped with a
visual UML model link, is demonstrated. A UML visual model is created by the use of a re-documentation
methodology known as 5W1H Re-documentation, based loosely on the journalistic 5 W‟s and 1 H of Who, What,
When, Where, Why, and How [3].
(a) A link to its architectural model
(b) A visual model
Figure 1. A FOSS Project Site Equipped with an Architectural Visual Model
3. Discussion
We assert that having visual documentation in the form of UML models can have a positive impact on FOSS
development and maintenance. Architecture of a FOSS improves comprehension of developers and quality
assurance team of the FOSS so that productivity of FOSS developers can be increased and defects of the FOSS
can be decreased. At the very least, additional meaningful documentation may draw in more newcomers who
choose open source projects based strictly on the availability of good starter documentation to break into the
project.
References
[1] Dagenais, B. & Robillard, M. P., Creating and Evolving Developer Documentation: Understanding the
Decisions of Open Source Contributors. Proceedings of ACM SIGSOFT International Symposium on FSE,
2010, pp. 127-136.
[2] Dzidek, W. J., Arisholm, E., Briand, L. C., A Realistic Empirical Evaluation of the Costs and Benefits of
UML in Software Maintenance. IEEE TSE, Vol. 34, No. 3, 2008, pp. 407-432.
[3] Chung, S., Won, D., Baeg, S. H., & Park, S., Service-Oriented Reverse Reengineering: 5W1H ModelDriven Re-Documentation and Candidate Services Identification. Proceedings of IEEE International
Conference on SOCA, 2009, pp. 1-6.
The 9th International Symposium on Embedded Technology, Seoul, Korea
2
57
Software Education and Research
at UW Tacoma
Sam Chung, Ph.D.
Smart & Secure Computing Research Group (SSCRG)
Institute of Technology
University of Washington, Tacoma
Center for Info. Assurance & Cybersecurity (CIAC)
University of Washington, Seattle
1/12/2014
SW Maestro 2014
1
Schedule
• 2:30 PM - 3:00 PM
•
•
•
•
•
•
•
Greetings,
About UW Tacoma & Speakers
3:00 PM - 3:30 PM Soon Bang
3:30 PM - 3:40 PM Break
3:40 PM - 4:00 PM William Km
4:00 PM - 4:20 PM Sky Moon
4:20 PM – 4:30 PM Break
4:30 PM - 5:10 PM Joowoo Choi, Sungbong Lee,
Yeonil Yoo, Joosung Park
5:10 PM - 6:00 PM SW Maestro Students
1/12/2014
58 ISET 2014
SW Maestro 2014
2
A Remote Power Analyzer based on Power Modeling in
Heterogeneous Embedded Linux Systems
Young-Joo Kim
Abstract
As a variety of powerful embedded systems with heterogeneous multi-cores are becoming more common,
power consumption has been positioning as one of the important issues in these systems. There are three
mechanisms which grasp power consumption of the systems and programs: simulation, estimation, and
measurement. These mechanisms have pros and cons respectively. In this talk, we focus on power estimation
based on power modeling. Power modeling extracts power coefficient for each HW component through power
measurement, and then power related to HW and SW components is estimated by the extracted coefficient. Also
we propose a remote power analyzer which uses power modeling. The analyzer estimates power for HW
components (such as CPU and GPU) and SW components (such as processes and programs) in real-time via USB
gadget as well as provides GUI environment based on eclipse to users. For this, three target agents must be
worked in embedded systems, and users executes and operates a host program in order to show estimated powers
as bar chart.
Keywords: Embedded systems, Heterogeneous, Power consumption, Estimation, Power modeling
1
59
A Remote Power Analyzer Based on Power
Modeling in Heterogeneous Embedded
Linux Systems
2014. 05. 23
ETRI
김영주 ([email protected])
Contents
60 ISET 2014
The 9th
Interactive SessionⅠ
NO
1
2
3
4
5
6
7
8
9
10
11
12
13
16:40-17:30, May 22, 2014
Interactive Session
Performance Evaluation for an Inter Vehicle Communication System based on WAVE Technology ................. 63
Yoo-Seung Song, Hyun-Seo Oh (ETRI)
Design and Implementation of Fusion Map Provider for Autonomous Driving Systems .................................... 65
Kyounghwan An, Wooyong Han (ETRI)
Dynamic Duty-Cycle Scheduling Scheme for Wireless Sensor Networks in Greenhouse .................................... 67
Jinhong Kim, AekyungMoon, Sooin Lee (ETRI)
IoT-based Indoor Environmental Monitoring System using Open Source Physical Computing Platforms...... 69
YoungJin Choi, Dae-Young Kim, Cheol-Hee Kwon, Sang-Myung Lee (LIG Nex1)
A Design of Semantic IoT for Interoperability of Things............................................................................................... 71
Min-woo Ryu, Sang-Shin Lee, Il-Yeop Ahn, Kwang-Ho Won (KETI)
Smart Service Design using Internet of Things............................................................................................................... 74
Jaeseok Yun, Jaeho Kim, Il-Yeop Ahn, Kwang-Ho Won (KETI)
L-V-C Gateway Architecture based on DDS and HLA for L-V-C interoperability...................................................... 77
Hyung Kook Jun(Sungkyunkwan University), Kyeong Tae Kim, Woosuk Cha, Won Tae Kim (ETRI),
Young Ik Eom(Sungkyunkwan University)
Digital Controller Design for Aerial Robot Control. ....................................................................................................... 79
Youn-Ho Choi, Jung-Eun Joung, Dong-Ha Lee (DGIST)
MQTT Protocol Binding for the REST-based IoT Architecture...................................................................................... 82
Sung-Chan Choi, Kwang-Ho Won, Sang-Shin Lee, Il-Yeop Ahn (KETI)
Adaptive GUI Reconfiguration Mechanism for Mobile Learning Devices. ............................................................... 84
Choongbum Park, Jae-Guk Gwon (ETRI), Kyung-Min Park, Hoon Choi (Chungnam National University)
RTiK-MP: Real-Time implant Kernel for x86-based Multi-Processor Windows ........................................................ 89
Jae Guk Gwon (ETRI), Chang-In Song (ARA Networks Company)
Single Camera-based Positioning Method using Image Database............................................................................ 92
Jin Seon Song, Yongwan Park (Yeungnam University)
Evaluation of Cache Partitioning : ImprovingCPUUtilization of Multi-core Embedded Processors ................. 94
Eunji Pak (ETRI)
NO
14
15
16
17
18
Interactive Session
The Memory Core in 3D Die-Stacked DRAM. .................................................................................................................. 96
Yongjoo Kim, Taeho Kim, Chaedeok Lim (ETRI)
A Dumb Battery Consumption Prediction Method of Mobile Device without Smart Battery............................. 98
Ho-Joon Park (ETRI)
Qplus-hyper : A Hypervisor for Safety-critical Systems. .............................................................................................102
Taeho Kim, Dongwook Kang, Soo-Young Kim, Jin-Ah Shin, Donghyouk Lim, Vicent Dupre (ETRI)
EcoVerifier : Tool Support for Formal Verification of ECML using SpaceEx.............................................................104
Jaeyeon Jo, InGeol Chun, WonTae Kim (ETRI)
Autonomic Computing Research Challenges for CPS.................................................................................................106
Prajakta Jadhav, Won-tae Kim, In-Geol Chun (ETRI)
62 ISET 2014
Performance Evaluation for an Inter Vehicle Communication System
based on WAVE Technology
Yoo-Seung Song, Hyun-Seo Oh
IT Convergence Technology Research Laboratory
Daejeon, Electronics and Telecommunication Research Institute
E-mail: {yssong, hsoh5}@etri.re.kr
Abstract
ITS technologies have been applied into transportation systems and played important roles for traffic safety
and convenient driving. A wireless communication technology named as WAVE for high speed vehicles has been
developed based on IEEE802.11p specifications. Lots of vendors and institutes have made the WAVE devices
and tested the performance. However, CSMA/CA based WAVE technology has a weak point when many service
devices exist at near space. In this paper, we introduce an implemented WAVE communication module for IVC
system and analyze the PER of WAVE by increasing the number of OBUs to observe the performance changes.
Keywords: WAVE, Inter Vehicle Communication (IVC), V2V, ITS.
1. Introduction
Recently, ITS (Intelligent Transportation System) technologies have been applied into personal vehicles as
well as public transportation systems and played important roles for traffic safety and convenient driving. One of
the key technologies in the ITS field is a wireless communication system for high speed vehicles, which is called
WAVE (Wireless Access in Vehicular Environments) based on IEEE802.11p specifications. Lots of companies
and research institutes have made OBUs (On Board Units) and the experimental results of PDR (Packet Delivery
Ratio) are compared under the real environments [1]. The performance of WAVE has been examined under V2X
environment in [2] and its application is verified for cooperative driving service in [3]. However, CSMA/CA
based WAVE technology has a weak point when many service devices exist at near space. In this paper, we
introduce an implemented WAVE communication module for IVC (Inter Vehicle Communication) system and
analyse the PER (packet error rate) of WAVE by increasing the number of OBUs to observe the performance
changes.
2. Implemented IVC System
We have implemented the IVC demonstration system as shown in Figure 1. It is composed of a MGU
(Message Generation Unit), a WCU (WAVE Communication Unit) and a monitor. The MGU generates BSM
(Basic Security Message) 80 ~ 320 byte packets every 10ms. The BSM packet is composed of the vehicle
information of speed, direction, acceleration, location, etc. The MGU is connected to the WCU with Ethernet
cable. The WCU transmits the generated packet in RF and communicates each other based on CSMA/CA MAC
protocols.
1
63
Figure 1. The implemented IVC demonstration system for cooperative driving services using WAVE
technology
3. Experimental Results
The implemented IVC demonstration system using WAVE technology is tested under an indoor environment
and the results are shown in Figure 2. The number of OBUs are changed from 2 to 4 with different size of packet
length. The BSM transmission rate is fixed to 10ms. The PER is measured by changing the modulation rate from
3 to 18Mbps. It is observed that 3 ~18Mbps modulation schemes can be supported under the condition of 3
OBUs with an 80 byte packet to meet less than 10% PER. But 18Mbps modulation scheme can’t meet 10% PER
when packet size is 320 bytes. 18Mbps modulation scheme shows more sensitive than others when the packet
size is increased.
Figure 2. PER results of the implemented IVC system using WAVE technology according to the number of
OBUs with different size of packet length
4. Conclusions
This paper have shown the implemented IVC demonstration system and tested the PER performance under an
indoor environment. The test was done by changing the number of OBUs with different size of packet length. It
is observed that 3 ~ 18Mbps modulation scheme can be established in stable when OBUs are less than 4 with
packet size of 80bytes in IVC communication systems.
References
[1] John B. Kenney at al., "Comparing Communication Performance of DSRC OBEs from Multiple Suppliers,"
19th ITS World Congress, Vienna, Austria, October 2012.
[2] Seungcheon Kim, "An Evaluation of the Performance of Wireless Network in Vehicle Communication
Environment," KICS, vol.36, No.10, 2011.
[3] Shin Kato et al., "Vehicle Control Algorithms for Cooperative Driving with Automated Vehicles and
Intervehicle Communications," IEEE Transactions on intelligent transportation systems, vol.3, pp.155-161,
September 2002.
64 ISET 2014
2
Design and Implementation of Fusion Map Provider for
Autonomous Driving Systems
Kyounghwan An, Wooyong Han
IT Convergence Technology Research Laboratory
ETRI, Daejeon, Republic of Korea
E-mail: {mobileguru, wyhan}@etri.re.kr
Abstract
ADAS (Advanced Driver Assistance System) and autonomous driving systems use sensors such as cameras,
radars, lidars to recognize driving situations. However, there have been several limitations due to the sensor
coverage, poor environments for sensing, inaccuracy of recognition results, and etc. To overcome previous
problems, map data can be used to enhance the results. The map data are also important resource for planning
path or deciding driving behavior in autonomous driving systems. The map data used for the ADAS and
autonomous driving systems have different requirements compared with those of CNS (Car Navigation System).
The map should include more detailed lane level geometries and need to be provided in soft real time to meet
control interval of the system. In this paper, we suggest requirements of the detailed map and necessary queries.
We also propose the system architecture of the map provider with implementation results.
Keywords: Autonomous driving, ADAS, Fusion map, CNS
1. Introduction
In ADAS (Advanced Driver Assistance System) and autonomous driving systems, map data are used for
enhancing recognition results, planning path or deciding driving behavior[1][2]. The map data used for the
systems have different requirements compared with those of CNS (Car Navigation System). The map (in this
paper, we call the map as fusion map) should include more accurate and more detailed lane level features. Also
the fusion map should be provided to the systems in soft real time to meet control interval of the system. In this
paper, we suggest the requirements of the fusion map and the system architecture in section 2. In section 3, we
explain the implementation result of the fusion map and conclude in section 4.
2. Fusion Map Provider
Since the fusion map are used for control purposes, they need more accurate and detailed lane level features.
The features includes lane center line points, lane numbers, divider types (solid/dash, double/single), lane colors
(white, yellow, blue), lane width, stop line, crosswalk, traffic signal, etc. In this paper, we also suggest fusion
map provider providing other systems with the fusion map periodically around ego vehicle as the vehicle moves.
To receive the map data at the right time, the systems registers queries which have time intervals and window
sizes as parameters. Once the queries are registered to the fusion map provider, the queries are executed and the
data are transmitted periodically like other sensors do.
1
65
Map
Matching
Continuous Fusion
Map Query Processor
Snapshot Fusion
Map Query Processor
Query Repository
Spatial database
Map Loader
Figure 1. Architecture of Fusion Map Provider
The architecture of the fusion map provider is shown in Figure 1. It consists of five modules: Map Loader,
Query Repository, Map Matching, Continuous Fusion Map Query Processor, and Snapshot Fusion Map Query
Processor. The Map Loader is for loading raw spatial data into database and the Query Repository is for
registering queries. The Map Matching module finds current position of the vehicle in the map to calculate query
windows of the registered queries. The Continuous Fusion Map Query Processor continuously evaluates
registered queries using the specified interval and newly calculated query windows. The Snapshot Fusion Map
Query Processor processes non periodic queries requested from other systems.
5. Implementation
Figure 2 shows the implementation result of the fusion map provider. The fusion map provider is implemented
on PC running Linux. In the figure, the box is query window which is dynamically calculated from the position of
ego vehicle. The query window size was 170m X 50m and the query interval was 100ms. Polygons are lane level
road segments. As the graph shows average processing time was about 1ms.
Figure 2. Implementation of Fusion Map Provider
6. Conclusions
In this paper, we explained the map contents of the fusion map and suggested the architecture of the fusion
map provider. We also explained implementation results satisfying our control interval (100ms). The suggested
system can be used various components of the intelligent car.
References
[1] SAFESPOT Core Architecture - LDM API and Usage Reference, http://www.safespot-eu.org/.
[2] Zott Christian, et al., "Safespot Local Dynamic Maps - Context-Dependent View Generation of a Platform's
State & Environment", 15th World Congress on ITS and ITS America's 2008 Annual Meeting, 2008.
Acknowledgement
This work was supported by the IT R&D program of MSIP/KEIT. [10041417, Development of Decision Making
/Control Technology of Vehicle/Driver Cooperative Autonomous Driving System(Co-Pilot) Based on ICT]
66 ISET 2014
2
Dynamic Duty-Cycle Scheduling Scheme for Wireless Sensor
Networks in Greenhouse
Jinhong Kim, Aekyung Moon, Sooin Lee
Embedded System Research Section
Daegu-Gyeongbuk Research Center
ETRI, Daegu, Republic of Korea
E-mail: {jinhong, akmoon, silee}@etri.re.kr
Abstract
There are increasing demands for the environment monitoring in the agriculture facilities such as greenhouse
using wireless sensor networks(WSNs). Due to each sensor node in WSNs operates with their limited energy,
power management is a critical problem. In this paper, we propose dynamic duty-cycle scheduling scheme for
WSNs in greenhouse environment in order to increase the energy efficiency considering the variation of
temperature and light intensity. Through NS-2 simulations, we have verified that our proposed scheme
outperforms existing scheme which has constant duty-cycle in terms of accumulate energy consumption.
Keywords: Duty-cycle scheduling, Wireless sensor networks, Greenhouse.
1. Introduction
Recently, plant cultivation through the artificial facilities such as plastic or glass greenhouse and plant factory
have increased. The greenhouse provide optimal conditions such as temperature, humidity and light intensity to
plant for increasing the quality and yields of plant product through the controlled greenhouse environments.
Among the various environmental factors which may influence to plant growth in greenhouse, one of the most
major thing is indoor temperature (hereinafter, called temperature). In the most of conventional greenhouse,
wired networks have been adopted to deliver these environmental information to the farmers. However, due to
the expansion of greenhouse and increased demands for the high control accuracy, the number of sensor nodes
deployed in greenhouse became increasing. Therefore, wireless sensor networks(WSNs) are emerging as a new
solution to decrease the cost of deployment of sensor nodes and to change the location of sensor nodes easily[1].
However, since each sensor node operates with their limited energy, power management is a critical problem in
WSNs. Therefore, the major factor of energy consumption of sensor nodes is caused by the wireless data
transmission, many researches have been studied to improve the energy efficiency. Among them, in the medium
access control (MAC) layer, especially duty-cycle scheme[2] is known as an appropriate method for WSNs.
In this paper, we propose dynamic duty-cycle scheduling scheme for WSNs in greenhouse environment to
increase the energy efficiency of sensor nodes. The proposed scheme allows each sensor node to calculate and
update their duty-cycle according to the variations of temperature and light intensity in greenhouse.
2. Proposed Scheme
In order to increase energy efficiency, the proposed scheme allows each sensor node i determines its duty) based on the variation of temperature and light intensity. Whenever node i wakes, it calculates the
cycle(
(=
) and
(
). Each
and
are variation of light intensity and temperature,
respectively. Also,
greater value between
greenhouse.
and
and
are system parameter. In Equation (1), node i chooses the
in order to make node i cope actively with the environmental changes in
1
67
Equation 1.
Equation 2.
When, therefore, temperature and light intensity are increased/decreased more than their threshold, node i
according to Equation (2). In the proposed scheme, however,
should not be too large a
updates their
is
value to guarantee the minimum QoS requirement of the greenhouse applications. Therefore, the maximum
an application-specific parameter.
3. Performance Evaluation
Through the NS-2 simulator, we tested the feasibility of our proposed dynamic duty-cycle scheme. For the rest
of operation of MAC protocol, the RI-MAC[3] was employed in our simulation. To emulate real light intensity
and temperature for a day, we measured these information using our test and applied the light intensity and
temperature data (Figure 1.(a)).
(a)
(b)
Figure 1. (a) Measured data, (b) Accumulate energy consumption
Figure 1(b) shows the accumulate energy consumption of our proposed scheme scheduling and original RIMAC. In our proposed scheme, from 8 a.m. to 4 p.m., the accumulate energy consumption increases rapidly
since the short duty cycle is calculated. On the other hand, during the night, the accumulate energy consumption
is almost stationary since the light intensity and indoor temperature are invariable. However, the accumulate
energy consumption of the original RI-MAC is consistently increased because the each sensor nodes has the
constant duty-cycle schedule.
4. Conclusions
In this paper, we proposed dynamic duty-cycle scheduling scheme for wireless sensor nodes in greenhouse in
order to increase the energy efficiency. In the proposed scheme, each sensor node adjusts its duty-cycle
according to the variation of temperature and light intensity in greenhouse. Through NS-2 simulation, we
observed that our proposed scheme shows better performance in terms of accumulate energy consumption as
compared to the static duty-cycle scheduling scheme of RI-MAC.
References
[1] Qian Zhang, Xiang-long Yang, Yi-ming Zhou, Li-ren Wang, Xi-shan Guo, "A wireless solution for
greenhouse monitoring and control system based on ZigBee technology", Journal of Zhejiang University
SCIENCE A, Vol 8, No 10, pp. 1584-1587, 2007.
[2] W. Ye, J. Heidemann, and D. Estrin, “An Energy-Efficient MAC Protocol for Wireless Sensor
Networks,”Proc. IEEE INFOCOM, 2002, pp. 1567-76.
[3] Y. Sun, O. Gurewitz, and D. B. Johnson, "RI-MAC: A receiver initiated asynchronous duty cycle MAC
protocol for dynamic traffic load," in Proc. of ACM Sensys, Nov. 2009.
68 ISET 2014
2
IoT-based Indoor Environmental Monitoring System
using Open Source Physical Computing Platforms
YoungJin Choi, Dae-Young Kim, Cheol-Hee Kwon, Sang-Myung Lee
Software Research and Development Laboratory
LIG Nex1, Pangyu, Republic of Korea
E-mail: {youngjin.choi, dykim2010, kwoncheolhee369a, sangmyung.lee}@lignex1.com
Abstract
This paper presents the design and development of an indoor environmental monitoring system employing
Netduino Plus and Arduino Uno which are kind of open source physical computing platform. The system has
five sensors: temperature, humidity, light (CdS), gas and nuclear radiation sensors to monitor the indoor
environment. Our proposed system is connected to the Internet for Internet of Things (IoT). Moreover, our
system can send sensor data to Xively periodically. As a case study, an indoor environmental monitoring system
using physical computing devices such as Netduino and Arduino has been developed. From our experiment, we
found out that our approach provides cost-effectiveness and easiness when constructing this kind of system with
using physical computing platforms quickly.
Keywords: Monitoring, IoT, Arduino, Netduino, Xively
1. Introduction
Currently, indoor monitoring systems are becoming more and more important. The temperature and humidity
have a critical influence on large categories of physical, electronic, chemical, mechanical, biological systems and
so on. In order to avoid malfunction and damage of the systems, certain applications (in industries, laboratories,
commercial and residential buildings) need to measure temperature, humidity, light and gas [1]. Moreover,
nuclear radiation measurement is needed for safety. Earlier measurements had been done by manual methods
from analog instruments such as thermometers, hygrometers and the like. Such type of measurements cannot
satisfy the current requirements in terms of the time duration, accuracy and cost-effectiveness [2].
The good way to solve this problem is to develop a data logger and to control the physical parameters in
monitoring systems. Some researches solved the problem by using PC since PC became very common, cheap and
reliable. In addition to that, PC-Based monitoring systems were proposed in order to make use of graphical user
interface (GUI) based applications [1, 2, 3]. However, PCs consume more electricity than embedded systems as
to energy consumption. In terms of cost, generally, PCs are still expensive compared to embedded boards.
Mostly, PC-Based systems need to execute additional PC application to operate the system properly. In other
words, a PC side application must be always executed in order to operate the entire system.
In the proposed IoT-based indoor environmental monitoring system, open source physical computing devices
are used so that problems of PC-based monitoring systems can be solved. Physical computing has been
extensively researched these days. There are several physical computing devices such as Arduino and Netduino.
These open source platforms are flexible and easy-to-use hardware and software. The proposed system has
temperature, humidity, light, gas and nuclear radiation sensors to monitor the indoor environment. Additionally,
our system is connected to the Internet so that interested users can have access to sensor data through the Web
and Xively which is related to IoT Service Platform and an on-line database service allowing developers to
connect sensor-derived data to the Web.
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2. Implementation and Results
Figure 1. Block diagram of the proposed system
As shown in Figure 1, the radiation sensor is integrated into Arduino Uno and the rest of sensors are connected
to Netduino Plus. For communicating the Netduino board with the Arduino board, a pair of Xbee modules is used.
In order to monitor several sensors through the Web, a lightweight web server is included in the Netduino Plus.
In addition to that, HTML, XML and Ajax are also used so that sensor data can be automatically updated every
five seconds in all web browsers. Through Xively, users can get five sensor values and graphs based on
accumulated sensor data [4].
Figure 2. Implemented hardware (Upper Left) and Experimental results (Lower Left and Right)
Figure 2 shows the implemented system and experimental results. Google Chart is also used to show gauges
and users can see some graphs of sensor data through Xively. The system has been running for over six months.
3. Conclusions
The proposed system will be useful in research and laboratories where acquisition for the monitoring and
analysis of the ambient temperature, humidity, light, gas and nuclear radiation is necessary. With open source
physical computing devices, our approach provides cost-effectiveness and easiness when constructing this kind of
the system quickly. In the future, we will conduct the large-scale experiments with multipoint monitoring systems
with using multiple sensors placed in different locations.
References
[1] Gabriel Gasparesc, “Development of a Low-Cost System for Temperature Monitoring”, Telecommunications
and Signal Processing (TSP), pp 340-343, 2013.
[2] Numgleppam Monoranjan Singh, Kanak Chandra Sarma, “Design and Development of Low Cost PC Based
Real Time Temperature and Humidity Monitoring System”, IJECSE, Vol. 1, No. 3, pp. 1588-1592, 2012
[3] I. Oghogho,“PC Based Temperature Monitoring and Alarm System”, Indian J.Sci.Res, Vol. 3, No. 2, pp. 17-20, 2012
[4] YoungJin Choi, “Implementation of an Indoor Environmental Monitoring System using Netduino”, Micro
Software Magazine, October 2013 ~ January 2014.
70 ISET 2014
2
A Design of Semantic IoT for Interoperability of Things
Min-woo Ryu, Sang-Shin Lee, Il-Yeop Ahn, Kwang-Ho Won
Embedded Software Convergence Reserach Center, Convergence Emerging Industries R&D Division,
Korea Electronics Technology Institute, Gyeonggi-do, Republic of Korea
E-mail: {minu, sslee, ilahn, khwon}@keti.re.kr
Abstract
Through numerous Internet technology advances, the world is moving towards an any time, any place, anyone
connected paradigm. According to this paradigm, a new idea has emerged taking into account these ideas, the
so-called Internet of Things (IoT). The IoT can connect between physical devices and virtual devices and derive
information through Internet. In addition, it can accommodate existing other technologies such as machine-tomachine (M2M) and wireless sensor network (WSN). Therefore the IoT is issued as next generation future
internet technology. However, for improving future internet technology via IoT, there are a couple of issue we
need to address. To do this we proposed a design of sematic IoT for interoperability of things.
Keywords: Semantic IoT, Internet of Things, Interoperability, Intelligence system.
1. Introduction
Through numerous Internet technology advances, the world is moving towards an any time, any place, anyone
connected paradigm. According to this paradigm, a new idea has emerged taking into account these ideas, the
so-called Internet of Things (IoT) [1]. The IoT can connect between physical devices and virtual devices and
derive information through Internet. In addition, it can accommodate existing other technologies such as
machine-to-machine (M2M) [2] and wireless sensor network (WSN) [3]. Theses characteristic of IoT, many
studies have been propose IoT system. However, for improving future internet technology via IoT, there are a
couple of issue we need to address. To do this, we propose a design of sematic IoT for interoperability of things.
The proposed design is used ontology and it can interact between things such as physical things and virtual things
via predefined expression. To do this, we were defined resource for IoT and relation between them.
2. Design of Ontology Model
In this section, we describe the design of sematic IoT for interoperability of things. In the IoT, various devices
has characteristic of them such as name, type and location. Therefore, to interact between Things, there is defined
common language for communicating with them. To do this, we were defined upper ontology model and
designed semantic based IoT system.
2.1 Design of Upper Ontology Model
This section was described our upper ontology model. The upper ontology model consist of five resource such
as profile, device, data, method, and storage. Figure 1 show upper ontology model
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Figure 1. Upper Ontology Model
In the figure 1, each resource is defined as super class and has “dis Joint” property. Each resource is
described as follow:
 Profile: this resource define attribute of device such as name, IP address and description
 Device: this resource define device type such as sensor or things
 Data: this resource define information
 Method: this resource define function of devices
 Storage: this resource define data storage such as database or text file.
Each resource has sub resource or attributes and they has relationship through expressions. The expressions is
defined as property. Figure 2 show our ontology model for interoperability Things.
2.2 Design of Ontology Model
In this section, ontology model was introduced. Figure 2 show our ontology model
Figure 2. Ontology Model for Interoperability Things.
In the figure 2, the PROFILE has relation with ID, NAME, and IP Address. Therefore, IoT devices can
identify profile of another IoT devices such as ID, NAME, and IP. And also, the profile resource has relation
with DEVICE and METHOD. In the DEVICE, it has attribute resource such as type, sub device. The type can
define device type such as sensor or electric device and the sub device can define number of sub device. In the
72 ISET 2014
2
METHOD can define functions of IoT device such as create, update, read, and delete. Therefore, the METHOD
is used to data handling.
3. Design of Semantic IoT System.
In this section, we are described architecture of semantic IoT system. The system is designed based on our
ontology model. Figure 3 show architecture of semantic IoT system.
Figure 3. Architecture of Semantic IoT System.
In the figure 3, the semantic IoT system consists of five components. Each component is introduced as follow:
 Ontology Model: this component consist of owl language. The detail description was section 2.
 Event Handler: this component was operated by input value, which can define from user of another
IoT devices. Event Handler define operations to Operation System based on Ontology Model and
saved data in Storage from user command of another IoT devices
 Data Coordinator: this component convert collected data from physical world to RDF format.
4. Conclusions
In this paper, we propose a design sematic IoT for interoperability Things. The proposed design was define
resource and relationship between resources on IoT environment. However, for interoperability of various IoT
devices, integrated resource must have defined. Therefore, future research will include integrated resource and
relationship.
5. Acknowledgment
This work was supported by the IT R&D program of MKE/KEIT. [10041262, Open IoT Software Platform
Development for Internet of Things Services and Global Ecosystem]
References
[1] M. W. Ryu, S. S. Lee, J. H. Kim, J. Y, “Survey of Internet of Things,” Smart Computing Review, Vol 1, No.
1, Oct 2011
[2] Chen, Kwang-Cheng. "Machine-to-Machine Communications for Healthcare." JCSE 6.2, 2012
[3] Yick, Jennifer, Biswanath Mukherjee, and Dipak Ghosal. "Wireless sensor network survey." Computer
networks 52.12, 2008
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Smart Service Design using Internet of Things1
Jaeseok Yun, Jaeho Kim, Il-Yeop Ahn, Kwang-Ho Won
Embedded Software Convergence Research Center
Korea Electronics Technology Institute,
25 Saenari-ro, Bundang-gu, Seongnam, S. Korea
E-mail: {jaeseok, jhkim, iyahn, khwon}@keti.re.kr
Abstract
With the advent of the Internet of Things (IoT) technology, the world’s things are connected with people and
to one another in their home, work, and public places. The fully connected things can be aware of people and
environment, and then provide people with smart services accordingly. Although various smart services have
been widely developed over the past decades, IoT technology will offer limitless possibility to smart services,
and eventually change the design, development, and implementation of smart services in the near future. In this
paper, we present several important aspects of smart services that should be considered when designing smart
services using IoT technologies, and then shown a couple of examples.
Keywords: Internet of Things, Smart service, Service design, Human-computer interaction.
1. Introduction
Our dwelling places, work, and public places have been instrumented with a large number of sensors and actuators, in particular, connected each other due to ubiquitous computing and networking technology. For example,
by embedding a small, low-power, and low-cost wireless transceiver into the everyday objects we use such as a
pill bottle cap, we can realize a reminder system which can help patients adhere to their medication [1]. The
world’s objects are fully connected each other, and create a dynamic network of networks, called the Internet of
Things (IoT), and ready to offer smart services for people [2]. Providing smart services has been one of important research topics in the field of computing and engineering, and a myriad of smart services have been developed. However, the IoT technology allows everyday objects to connect with people and one another (even at a
low cost), and we can imagine new forms of smart services that can be offered in our home, work, and public
places. In 2006, researchers chose four key technologies for the Internet of Things: RFID (radio frequency identification), sensing technology, embedded intelligence, and nano technology [2]. In this paper, we present several
important aspects that should be considered when developing IoT-based smart services, including sensor & actuator, network, intelligence, and user interface, and show several examples we have proposed.
2. Smart Services using Internet of Things
The Internet of Things will have broad impact on our everyday lives, revolutionizing the way we live, the way
we interact, and the way we do business—offering smart services in home, work, and public places. Such smart
services should be designed, developed, and implemented by considering several important aspects: sensor &
actuator, platform, network, intelligence, and user interface.
1
This work was supported by the IT Research and Development Program of MKE/KEIT under Grant 10041262
through the Open IoT Software Platform Development for Internet of Things Services and Global Ecosystem
74 ISET 2014
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We first need to choose which information will be necessary to build a smart service, and pick corresponding
sensors, e.g., pyroelectric infrared (PIR) sensor in case of detecting human occupancy. Also, we need to choose
actuators corresponding to the service provided for users based on sensed information, e.g., light switch in case
of occupancy detection of PIR sensor. Because there may be hundreds of thousands of sensors and actuators from
a variety of manufacturers, and thus we need a hardware and software platform that can provide a common interface and network capabilities. Examples include Raspberry-Pi [3] and Arduino [4]. Using a combination of
Raspberry-Pi and Arduino, we will be able to construct an intelligent computing system that collect and analyze
data, and then control actuators accordingly, as shown in Figure 1.
Figure 1. An example of IoT system using Raspberry-Pi and LED circuit
Although a complicated algorithm based on machine learning and data mining could be implemented into service platforms, we also consider a combination of simple ‘if A, then B’ rules such as IFTTT [5]. For example, we
can imagine an energy-saving scenario as follows: if a heater consumes more than 1000 W of electricity, do blink
a light to alert users until they turn off or down temperature so that energy usage becomes back down to the
threshold. If a remote switch is pressed, its corresponding devices will be turned off. The scenario will be implemented with a combination of two rules: 1) if electricity usage of a heater > 1000 W, then blink a light, 2) if a
switch is pressed, then change the status of its corresponding device (i.e., heater). Finally, in order for users to
easily create new rules or delete existing rules, and start or stop using the rules, we should offer an intuitive and
interactive user interface. Since smartphones have been widely used everyday life, and provide people a userfriendly interface including microphones and touch screen. Figure 2-(a) shows an example of IoT smart service,
called iThing, a voice command-based home appliance control [6]. Figure 2-(b) shows another example, a smart
flower pot (Planty, nthing.net) that can be remotely controlled by a smartphone app, e.g., watering, lighting, and
self-growing [7].
(a)
(b)
Figure 2. Examples of smart services using IoT technologies (a) voice command-based home appliance control, (b) Planty, a smart plant pot that can be controlled using smartphone app
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3. Conclusion and Future Works
In this paper, we have presented several important aspects that should be considered when developing smart
services based on Internet of Things technology. Once we have defined a service scenario in our home, work, or
public places, it should be considered which types of information will be used for the smart service, and then
select appropriate sensors and actuators. At the same time, we also need to consider device hardware and software platforms that can provide a common interface for collecting and transmitting data, e.g., Raspberry-Pi and
Arduino. In order for a service application or program to be smart, it should be able to aware of the current status
of the user and surroundings, and then control actuators appropriately based the user’s preferences—intelligence.
Finally, systems provide a simple and efficient way for users to monitor and interact with the smart service. For
examples of smart services based on the Internet of Things technology, we have shown a voice command-based
home appliance control and a smart flower pot that can be controlled by a smartphone app. We are also further
investigating a way of systematically developing various smart services using the Internet of Things technology.
References
[1] GlowCap, http://www.vitality.net/, Available: April 18, 2014.
[2] ITU Internet Reports 2005: The Internet of Things -- Executive Summary, 2005.
[3] Raspberry-Pi, http://www.raspberrypi.org/, Available: April 18, 2014.
[4] Arduino, http://www.arduino.cc/, Available: April 18, 2014.
[5] IFTTT, https://ifttt.com/, Available: April 18, 2014.
[6] iThing, http://www.youtube.com/watch?v=6pe1HdpUOnA, Available: April 18, 2014.
[7] Planty, http://www.nthing.net/, Available: April 18, 2014.
76 ISET 2014
3
L-V-C Gateway Architecture based on DDS and HLA for L-V-C
interoperability
Hyung Kook Jun† *, Kyeong Tae Kim*, Woosuk Cha*, Won Tae Kim*, Young Ik Eom†
*
Embedded Software Research Department
Electronics and Telecommunications Research Institute, Daejeon 305-700, Korea
E-mail: {hkjun, ktkim, wscha, wtkim}@etri.re.kr
†
School of Information and Communication Engineering
Sungkyunkwan University, Suwon, Korea
E-mail: {junhk, yieom}@skku.edu
Abstract
Distributed simulation systems demand for interoperable simulation environment and communication
middleware such as DDS and HLA, as the growth in Live, Virtual, and Constructive interoperability and
requirements of real time communication. In this paper, we provide the design of L-V-C Gateway which
interconnects between DDS that is pub-sub based data-centric middleware and HLA that is high level
architecture simulation model to support communication for distributed Virtual and Constructive simulation
Keywords: DDS, HLA, L-V-C, Gateway
1. DDS and HLA
DDS(Data Distribution Serice) proposed by OMG(Object Manage Group) is a Data Centric, PublisherSubscriber based communication middleware that is adequate for real-time and massive data dissemination. It has
the advantages of providing of QoS(Quality of Service) such as reliability, data filtering, deadline, transport
priority, also it is suitable to transmit real time data among Live simulation systems to support real time and
highly reliable communication. Besides, as DDS includes features of reusability, ease of development, and
maintenance, we can reduce the development period. As HLA(High Level Architecture) is a simulation
architecture for distributed simulation systems, it enables a simulation systems to interact with other simulation
systems. HLA provides a set of simulation functionality that manages and coordinates its operations and data
exchange to support distributed simulation environment for virtual systems and constructive systems. Even
though HLA has a great deal of advantages for simulation communication, it has performance problems when
the scale of the system increase, so that we might consider to resolve scalability problems of L-V-C
interoperability.
2. L-V-C Gateway
The purpose of L-V-C Gateway is to interoperate DDS with HLA. DDS is suitable for Live real time systems
while HLA is adequate for virtual and constructive simulation systems. If we support interoperability between
DDS and HLA, we can get better flexible L-V-C simulation environments. But there are lots of problems to solve
such as time synchronization and federation management, and QoS support between DDS and HLA
interoperability. Therefore, we have focused on the design of L-V-C Gateway for data translation between them
and we will depict the architecture for more details in next chapter.
3. Structure of L-V-C Gateway
In this paper, we describe the design of L-V-C Gateway architecture based on DDS and HLA for LThe 9th International Symposium on Embedded Technology, Seoul, Korea
1
77
V-C interoperability which enables L-V-C Gateway to support flexible distributed simulation environment. Fig. 1
illustrates the overall architecture of L-V-C Gateway. First, L-V-C Gateway parses FOM(Federation Object
Model) file. FOM file contains data object properties based on XML(Extensible Markup Language) describing
the information being used in distributed L-V-C simulation. FOM Parser parses FOM XML file using FOM DTD
and produces FOM information for HLA and Topic information for DDS, and then stores them into FOM/Topic
repository. FOM/Topic Information in FOM/Topic repository will be used (when Object/Entity Creator makes
out HLA object and interaction and DDS Entity to transmit data from HLA federation to DDS Domain). Here,
HLA object and DDS entity form a logical communication channel between HLA federation and DDS Domain
(Each of Object and Entity created registers in HLA Object Manager and DDS Entity Manger and will be
controlled by them). Object/Entity Mapping has a relationship between HLA object and DDS entity regarding the
same FOM/Topic information, so it relays data from HLA Federation to DDS Domain and vice versa. In order to
relay data we need to obtain event of data arrival from HLA Federation and DDS Domain, HLA Callback
handler and DDS Event Handler play a roll of event handler of data arrival respectively. As Object/Entity
Mapping observes data arrival through HLA Callback Handler and DDS Event Handler, it call Data Translation
to convert data with mapping information between them as soon as on arriavl.
Figure 1. The Structure of L-V-C Gateway for DDS and HLA interoperability.
4. Conclusion
Now, we have designed L-V-C Gateway for Live, Virtual, and Construtive distributed simulation systems
based on DDS and HLA. In this paper, we have presented the structure of L-V-C Gateway to deliver simulation
data and information between DDS Domain and HLA Federate In the future, we will investigate time and
federation management and then implement L-V-C Gateway.
Acknowledgment
This work was supported by Dual Use Technology Program through Civil Military Technology Cooperation
Center funded by MINISTRY OF TRADE, INDUSTRY & ENERGY and DEFENSE ACQUISITION
PROGRAM ADMINISTRATION.
References
[1] Object Management Group: Data Distribution Service for Real-time Systems Ver. 1.2, 2007,
http://www.omg.org/spec/DDS/1.2
[2] IEEE, IEEE standard for modeling and simulation high level architecture federate interface specification,
IEEE Std. 1516.1-2000, 2000.
78 ISET 2014
2
Digital Controller Design for Aerial Robot Control
Youn-Ho Choi, Jung-Eun Joung, Dong-Ha Lee
Wellness Convergence Research Center
Daegu Gyeong Institute of Science & Technology, Daegu, Republic of Korea
E-mail: {yhchoi, jin0110, dhlee}@dgist.ac.kr
Abstract
In everyday routine life, robots help daily human life ever more, and, for the development of such robots,
there are attempts to design robots which mimic a living organism's activities. Studies on analyzing and
investigating mechanism and behavior of living organisms, and developing a robot which runs under each
respective environment has been made. Further to the studies on biomimetic mechanisms, techniques on
designing and manufacturing of robots are also required. Furthermore, for the development of robots, it is
necessary to develop designing and manufacturing of electronic robots as well as the mechanical design, analysis,
and manufacturing. With the advancement of electronic devices, it is much easier and simpler than ever before to
implement such hardware configuration and digital control to manipulate robots. In the paper, we propose an
implementation for digitally controlling aerial robot, in which the implementation realizing a digital controller
for manipulating biomimetic robot, and which configured to analyze and establish each task processing phase,
and to build a stable performing period including the processing phases.
Keywords: Bio-inspired, Flapping, Robot.
1. Introduction
Biomimetics is gained much recognition in which it can mimic the form of a living organisms, and can raise
the efficiency by implement the activity of the living organisms. Still far to invent a flying machine, researches
are focused to the different power sources and materials which imitate shapes and actions of birds. Festo
introduced a robotic Smart bird which can fly while it imitates the biomimetics of a bird[1]. For such kind of
flapping robots, the wings are consist of outer wing and inner wing, and the robots can fly by the generated
thrust and lift by the motions of wings[2, 4]. In the paper, we describe the technique and characteristics of the
control program used in the design of aerial robot, Seagull, which mimics a bird.
2. Robot Design
In the paper, the aerial robot is configured to comprise a mechanical component of composite materials, an
electronic component based on the high performance DSP, and a communication component possible to remote
control and monitoring in real-time[3].
The main structures of the body and wing are formed with high density carbon fiber materials, and the outer
cloth is formed of polyurethane for the lightness. The electronic component has electronic control board part and
actuator part, and configured to have BLDC motor for the moving the main wing, and servo motors to control
the attack angle of outer wing and to change the direction of the robots. The electronic component uses small
form factor signal processing board. Moving speed and position of the wings are determined by the Hall sensor,
and the attack angle of the wings are controlled by the flapping motion of the wings. Three axis accelerator
sensor, gyro sensor, and compass sensor embedded in the signal processing board may determine the moving
direction and the attitude of the robot. The signal processing board is disposed in the front side of the breast
frame of the robot, in which the Hall sensors are configured in symmetry, and it can determine the position and
speed by sensing the Neodymium magnet which located in the moving part of respective wings. With the
communication component, sensed data, such as, motions, attitudes, and environments of the robots can be sent
to the monitoring system[3].
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3. Timing of Processing Phase
Program for controlling the robot basically includes an acquisition of sensor information, input of control
command, processing of the control signal, and output of the motor control command. With configuring the
controller, it is also required to design control board for flight and driving program for the controller to control
the robot. Figure 1 depicts the basic configuration of the program applied to the motion of a robot.
For scheduled task in unit control cycle, we divided the task into 5 basic phases within the unit control cycle,
each phase can be performed separately. Data collection which does not affect the main control logic has been
assigned to have a longer execution cycle. Each of processing time and condition can be expressed as in equation
(1) and (2).
Tn0
Tn1
Tn2
Tn3
Tn4
R:read
W:write
Phase 0
Phase 1
Phase 2
Phase 3
Sensor read
Sensor filter
Motor out
Command
R
Tn+0
Control
W
Tx
Sensor read
R
Tn+1
R
Tx
Sensor filter
Tx
Motor out
Control
W
Tx
Sensor read
Tx
R
Tn+2
Ref.
Control
Tx
Command
W
Tx
Sensor read
Ref.
R
Tn+3
R
Tx
Sensor filter
Tx
Motor out
Control
W
Tx
CMD FIFO
push
Rx buffer
MSG FIFO
pop
Tx buffer
Tx
Command
Make data
Ref.
C
Tx
processing segment
Tx
Motor out
C
Tx
Tnk
R
Tx
Sensor filter
Data Ack. period
Command
C
Tx
C:calculation
pop
Ref.
C
Tx
Phase 4
push
W
R
Tx
Tx
Tx
Figure 1. Processing Map1
Equation 1. Control Period1
Tc ≥ ∑ Tpn , Tn : processing time of phase(n)
Equation 2. Unit phase processing time2
Tpn = ∑ Ttm + Trn , where Ttm : task processing time, Trn : redundancy of phase(n)
4. Conclusions
Using the proposed design scheme in this paper, it can be possible to divide each repeating task in unit control
cycle into separated phases, such that the time for performing each process can be precisely determined. And,
according to the paper, with a higher control performance, minimizing process time, and reassignment of phases
for optimization, it can be expected to implement advanced performance robot.
Acknowledgment
This work was supported by the DGIST R&D Program of the Ministry of Science, ICT and Future
Planning of Korea(14-BD-01).
80 ISET 2014
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References
[1] W.Send, M.Fischer, K.Jebens, R.Mugrauer, A.Nagarathinam, F. Scharstein, "Artificial hinged wing bird
with active torsion and partially linear kinematics", ICAS 2012-3.6.1, 28th ICAS Congress Brisbane, pp.2328 Sep. 2012.
[2] Youn-Ho Choi, Nae-Soo Cho, Jung-Eun Joung, Woo-Hyen Kwon, Dong-Ha Lee, "The wing structure
modeling of the bioinspired aerial robot", Jounal of the Korean Solar Energy Society, Vol. 32, No. 3, pp.269274, 2012.
[3] Jung-Eun Joung, Youn-Ho Choi, and Dong-Ha Lee, "Design of Biomimetic Robot for Efficiency Flight",
IEMEK Fall Symposium, pp.323-325, 2013.
[4] Youn-Ho Choi, Jung-Eun Joung, and Dong-Ha Lee, "A Wing Motion of Flapping Aerial Robot",
Proceedings of 2013 International Symposium on Embedded Technology, pp.144-145, 2013.
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MQTT Protocol Binding for the REST-based IoT Architecture
Sung-Chan Choi, Kwang-Ho Won, Sang-Shin Lee, Il-Yeop Ahn
Embedded Software Convergence Research Center
Korea Electronics Technology Institute,
68 Yatap-dong, Bundang-gu, Seongnam, S. Korea
E-mail: {csc, khwon, sslee, iyahn}@keti.re.kr
Abstract
By 2020, we anticipate that there will be over 50billion devices connected to the Internet. In this Internet of
things environment, each device would produce tremendous data delivered to a server platform and the server
would save, process, and forward the data to the other devices when it receives the request. Under this
circumstance, we are facing a problem with decision making which architecture style or messaging protocol is
adequate for the IoT. In relation to this, REST and MQTT can be one of leading candidates for the IoT’s
architecture style and messaging protocol. In this paper, we will study MQTT protocol binding for the RESTbased IoT Architecture.
Keywords: REST Architecture, MQTT, Internet of Things
1. Introduction
REST stands for Representational State Transfer and is a type of software architecture for distributed hyper
media systems [1]. In REST, resource is a crucial abstraction and it is identified by a resource identifier.
Regarding to this, World Wide Web (WWW) is the largest REST-based architecture implementation. The
resource in the WWW is identified by an Uniform Resource Identifier (URI). MQTT represents Message
Queuing Telemetry Transport and is a lightweight broker-based publish/subscribe messaging protocol [2].
MQTT is also designed for constrained devices and low bandwidth so it is suitable for the constrained
environments such as devices with limited processor/memory and network with low bandwidth and no reliability.
MQTT supports three level of Quality of Service (QoS), in which characterize best effort, guaranteed delivery
with duplicates possible and guaranteed delivery with no duplicates. It is built over TCP/IP for basic network
connectivity. Comparing to Simple Object Access Protocol (SOAP) based on XML to provide messaging
services [3], REST uses simple and lightweight APIs consist of Create, Read, Update, and Delete called CRUD
operations and URI. So because of not heavyweight and easy to use, REST is more popular when used for the
Web service system. Furthermore, in IoT architecture, REST is increasingly popular. However, when we
combine MQTT protocol with REST, there are some obstacles to use MQTT protocol in the REST-based
architecture. In this paper, we study how MQTT could be bridged to the REST-based IoT Architecture.
2. MQTT Binding
As shown in Fig. 1, MQTT system architecture consists of MQTT clients and MQTT server. In initial setup
stage, each client in MQTT system architecture tries to connect to the server called broker. After establishing
connection, the client sends subscribe message including topic name to the server. The topic name in the
subscribe message is used to determine where the received message is delivered when the server receives a
publish message including topic names from a client. MQTT server compares the topic name in the publish
message with its subscribed topic name list and forwards the message to the matching clients which previously
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subscribed to the server with the topic name. In view of the client’s role in the MQTT system architecture,
MQTT client can be classified as a gateway or a device. The MQTT gateway aggregates data from sensor nodes
and sends the data to the server. The MQTT device generates data and sends its data to the server.
Figure 1. MQTT System Architecture
Figure 2. Publish/Subscribe Message Flow
REST-based architecture conventionally consists of clients and servers. Clients create requests to servers and
servers process requests and get back the appropriate responses (Request/Response model). Each resource in the
REST-based architecture can be identified by URI and can be manipulated by CRUD operations. These
principles fit well in Hypertext Transfer Protocol (HTTP) since HTTP provides CRUD operations through GET,
PUT, POST, DELETE and a couple of other methods. In addition, it uses URIs to refer to identifiable resources.
However, MQTT is based on Publish/Subscribe model and CRUD operations are not supported. So, in order to
integrate MQTT to the REST-based architecture, we need to take some integration methods into consideration.
To this end, first of all, we assume that each client has its ID and can be identified by the ID among others. Each
client subscribes to the server using its ID to be able to receive the messages published to its ID. As shown in Fig.
2, MQTT clients subscribe to the MQTT server with its Resource ID. If MQTT client want to send the message
to other MQTT clients, it publishes the message with the intended MQTT client’s Ids. In addition, we define four
elements: Origin ID, Operation, MetaData, Contents. The Origin ID is the identifier of the client, which sends the
publish messages. Operation represents CRUD function corresponding to one of Create, Read, Update, and
Delete. MetaData is an optional parameter related with CRUD Operations. The last element, Content includes
resource URI and additional data.
3. Conclusions
REST have received plenty of attention as an IoT Architecture style lately since its characteristics are easy
implementation and lightweight approach comparing to SOAP. MQTT protocol is emerging as a representative
IoT protocol because it enables efficient and lightweight communication that is required in the IoT environments.
In this paper, we studied how the REST-based architecture can be supported using MQTT protocol. To this end,
we define four elements which would be contained in the MQTT message payload. For the future work, we will
implement our proposed MQTT binding with REST-based architecture and perform its feasibility test.
References
[1] R. T. Fielding. Architectural styles and the design of network-based software architectures. PhD thesis, 2000.
[2] Mqtt v3.1 protocol specification. http://public.dhe.ibm.com/software/dw/webservices/ws-mqtt/mqtt-v3r1.html.
[3] P. Cesare, O. Zimmermann, and F. Leymann. "REST vs. SOAP: making the right architectural decision."
Proceedings of the 17th international conference on World Wide Web. ACM, 2008.
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83
Adaptive GUI Reconfiguration Mechanism for Mobile Learning
Devices
Choongbum Park*, Jae-Guk Gwon*, Kyung-Min Park†, Hoon Choi†
*
Department of Embedded Software
E-mail: {here4you, jagugi}@etri.re.kr
†
Department of Computer Science and Engineering
Chungnam National University, Daejeon, Republic of Korea
E-mail: {mumeprunus, hc}@cnu.ac.kr
Abstract
This paper describes the smart GUI reconfiguration capability of the AIMOL middleware. According to the
user’s ability of handling the device and learning the educational contents, AIMOL dynamically reconfigures
GUI of the device.
Keywords: Mobile Learning, Mobile Computing, GUI Reconfiguration
1. Introduction
The advancement in mobile technology has introduced us various network-based information and business
services to the developed countries. However, major areas of the world still have little or no network
infrastructure, leaving the people in such areas without access to information, education, and public services
while excluding them from acquiring equal rights and securing their well-being. One possible way to help remedy
the deficiency in access to public services and empower the extremely underserved is to provide them with
mobile computing devices with essential applications and educational contents [1,2,3].
Such mobile computing devices need to be designed to function self-sufficiently and adaptively enough to
operate and sustain with minimal maintenance effort. For this purpose, we are working on a middleware, AIMOL
(Adaptive and Interactive Mobile Learning) system [4] for mobile learning devices. In a nutshell, the middleware
lets the mobile computing device discover educational content objects in neighbor mobile devices and exchange
the content objects in peer-to-peer manner. It generates and manages content tracking information associated with
the content objects. It also generates and regenerates an appropriate GUI of the device based on user’s usage
pattern.
In following, we describe how the middleware functions.
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Figure 1. Functional Architecture of AIMOL Middleware
A simple human-computer interface with basic features may serve better for the user who is not familiar with
mobile computing devices or educational contents. However, it makes sense to introduce more features and
higher level contents as the user becomes familiarized with the overall UI experiences and progresses in the given
learning path. The key for the adaptive GUI design is to develop an algorithm to measure ultimate “cognitive
load” level and continue to maintain the level in an increasingly sophisticated and challenging fashion.
In order to achieve the highest usability for users with minimal access to support and least prior UI exposure,
the mobile computing devices need to dynamically reconfigure the GUI based on the users’ ability. The AIMOL
middleware has the following functional components for this purpose.
A.
AISE(Adaptive Interactive System Engine)
AISE is the core component of the AIMOL. It includes a lightweight inference engine suitable to mobile
computing devices[5,6].
B.
PMC(Profile Management Component)
Profiles contain the information for automated system operation. PMC extracts GUI related information,
such as the size and location of a GUI object, from the profile of a GUI package and passes the
information to the GMC.
C.
GMC(GUI Management Component)
GMC receives the GUI related information from the PMC and it deploys GUI objects accordingly on the
window (LCD panel) of the device.
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2. GUI System Of The AIMOL
A.
GUI Package
Figure 2. Structure of a GUI Package
GUI Package consists of GUI objects and a profile. GUI objects are to be displayed on the window and the
profile contains XML type information about the GUI Package.
<?xml version="1.0" encoding="UTF-8"?>
<area>
<name>Basic</name>
<x>0</x>
<y>0</y>
<width>300</width>
<height>280</height>
<configuration>
<shortcut>
<image>short_img1</image>
<width>40</width>
<height>50</height>
<text>step1</text>
<app>Learning_App1</app>
</shortcut>
</configuration>
</area>
Figure 3. Part of a Profile
Area of the profile in Figure 3 is a group of GUI objects. The profile specifies the location and size of the area
as well as the location and size of the GUI objects along with the linked applications.
B.
GUI Package
GUI objects displayed on a window can be classified as follows.
1) BASE(Basic Application Shortcut Area)
Contains shortcuts of the mobile learning service applications.
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2) EAA(Extend Application Area)
Contains shortcuts of auxiliary applications such as games and a media player.
3) SPA(System Programs Area)
Contains shortcuts of the system programs used for control of resource such as speaker volume or LCD
brightness.
Figure 4. Window Layout
3. GUI System Of The AIMOL
In the early stage of using the mobile learning service, the minimum of GUI objects are included in the BASA
area and therefore limited numbers of applications are shown to naïve users.
Figure 5. Structure of a GUI Package
As learning is being progressed, EAA or SPA area are added to the window and more GUI objects are
included in each area, based on the user’s ability. AISE monitors users ability and usage pattern in order to adapt
GUI to the user. Monitoring procedure is depicted in Figure 5.
AISE increases the usage counter associated with an application whenever a user clicks the shortcut to run the
application. It also accumulates the run time of the application to the usage timer of that application.
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Figure 6. Restructuring the GUI Components
When the timer or the counter exceeds threshold values, AISE starts to build a new GUI package. AISE passes
the profile of the new GUI package to PMC. PMC passes the GUI related information to GMC as explained in
Section I. GMC registers GUI objects to the corresponding areas of the window and links them to the
corresponding applications.
5. Conclusions
As an approach to create an accessible education model for underserved populations with minimal technology
and HCI exposure, the AIMOL middleware can contribute to provide an intelligent and adaptive learning service
on mobile computing devices. This paper described the GUI reconfiguration capability of the AIMOL
middleware. According to the user’s ability of handling the device and learning the educational contents, AIMOL
dynamically reconfigures GUI of the device.
References
[1] Paul Kim, Talia Miranda and Claudia Olaciregui, “Pocket School: Exploring mobile technology as a
sustainable literacy education option for underserved indigenous children in Latin America.” International
Journal of Educational Development. Vol. 28. No. 4. pp. 435-445. 2008.
[2] One Laptop Per Child(OLPC), online http://laptop.org/, 2008.
[3] Yanhui Zhang, Wu Li, Yingzi Fu, “A Mobile Learning System Based on Bluetooth,” Third International
Conference on Natural Computation(ICNC 2007), pp. 768-771, 2007.
[4] C. Park, H. Choi, and P. Kim, "Adaptive Open Mobile Learning Device For the Underserved," The 26th
IEEE International Conference on Consumer Electronics, Jan. 13, 2009.
[5] Yong-Duck You, Choong-Bum Park and Hoon Choi, "The Lightweight Runtime Engine of the Wireless
Internet Platform for Mobile Devices," Lecture Notes in Computer Science: Yann-Hang Lee(Ed.), SpringerVerlag, Vol.4523, pp.25-36, May 2007.
[6] Yong-Duck You, Hoon Choi and Dongwon Han, "Autonomic System Management for the PDA," The 26th
IEEE International Conference on Consumer Electronics, Jan. 12, 200
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RTiK-MP: Real-Time implant Kernel for x86-based Multi-Processor
Windows
Jae Guk Gwon*, Chang-In Song†
*
Electronics and Telecommunications Research
Institute, DaeJon, Republic of Korea
†
ARA Networks Company, Limited
, DaeJon, Republic of Korea
Abstract
This study addresses design and realization of RTiK-MP (Real-Time implant Kernel-Multi Processors) in
order to provide real-time capabilities to the user space of the x86-based multiprocessor Windows environment.
RTiK-MP utilizes x86 processor's Local APIC timer interrupt by implanting an extended kernel into Windows to
support real-time execution of user threads to irrespective of the current load of Windows. By sending signals to
corresponding user-space threads using the ISR(Interrupt Service Routine) and DPC(Deferred Procedure Call)
mechanisms in the kernel space, each user thread is guaranteed to execute in real-time. Experimental results show
that RTiK-MP guarantees real-time execution of periodic threads with up to 1ms period which is almost equal of
the performance of the commercial RTX products of IntervalZero. Therefore, we believe that RTiK-MP can
replace the expensive RTX products in many application domains.
Keywords: Real-Time, Windows, Implant Kernel
1. Introduction
Recently, processor clock speed of computers and portable electronic devices have reached the limit due to
various physical factors such as heat, power dissipation and power leakage. Thus, processor specifications tend to
change from single processor to multiprocessor. In particular, studies for the real-time support in multiprocessor
environment have been required along with changes in the embedded system processor requiring real-time to
multiprocessor-based processor. Although Windows is commonly used in order to provide convenience of
development in such an embedded system environment, there is a problem that the Windows operating system
cannot provide real-time. Costly third parties such as RTX and INtime must be used in order to provide real-time
to Windows in embedded environment. Therefore, this study suggests RTiK-MP for supporting real-time to
Windows that runs on x86-based multiprocessors. RTiK-MP causes periodic timer interrupts independently from
Windows through control of the processor's Local APIC (Advanced Programmable Interrupt Controller) timer
interrupt by having different implant kernel from Windows. The occurrence of the timer interrupt guarantees that
threads in user space operate with minimum period of 1ms by sending an event signal from inside Interrupt
Service Routine (ISR) to threads in user space.
2. RTiK-MP( Real Time implant Kernel-Multi Processors)
RTiK-MP is implanted in the form of device driver into Windows and supports real-time using the Local APIC
interrupts ox x86 processors. Figure 1 shows the whole operation process of RTiK-MP. As shown in Figure 1, in
case of dual-core, each core has a unique Local APIC, respectively. Between the two cores, RTiK-MP provides
real-time by using the Local APIC timer of the AP(Application Processor). When the Local APIC timer occurs in
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AP, the timer interrupt handler is executed using IDT(Interrupt Descriptor Table) of the AP. First, the interrupt
handler resisters a DPC(Deferred Procedure Call) to the DPC Queue of each processor. In addition, when the
IRQL(Interrupt Request Level) value reachs the level of the DPC Dispatch, the registered DPCs are processed by
the DPC routine[1-3].
Figure 1. Method of operation of RTiK-MP
Figure 2 shows the results of operation of RTiK-MP with the minimum period of 1ms, by displaying
level 0 and level 1 toggle at every timer interrupt.
Figure 2. 1ms operation of RTiK-MP in user space
Table 1 shows the performance results (average, minimum, and maximum values) of both RTiK-MP and
RTX after 1.8 million tests (for more than 30 minutes) using threads with periods of 1, 10, and 15ms,
respectively. With this table, we can see that the performances of the RTiK-MP and RTX are almost exact.
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Table 1. performance results
Period
1ms
10ms
15ms
RTiK-MP & RTX
Avg. (ms)
Min.(ms)
Max.(ms)
RTiK-MP
0.99438
0.97162
1.01594
RTX
1.00029
0.98131
1.01862
RTiK-MP
10.00112
9.99395
10.01050
RTX
10.00023
9.99856
10.00905
RTiK-MP
15.00163
14.99365
15.00527
RTX
15.00098
14.99968
15.00454
3. Conclusions
This study was conducted in order to provide real-time for x86-based multiprocessor Windows environment.
The proposed RTiK-MP is an extended implant kernel realized in the form of device driver, and can access and
control the multi-core based Windows kernel resources and x86 hardware resources. This enables RTiK-MP to
provide real-time capabilities to Windows by causing the timer interrupts independently from Windows through
the use of the Windows Local APICs. Furthermore, experimental results show that the minimum operational
period is at least 1ms by using the event signals between the kernel and user space in order to provide real-time to
the Windows user space. These results are comparable to them of RTX which is the most popular and expensive
commercial world-wide product. We believe that RTiK-MP can replace RTX in most application domains.
References
[1] Intel, “Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1 : Basic Architecture",
September, 2009.
[2] Intel, “Intel 64 and IA-32 Architectures Software Developer’s Manual Vol.2 : Instruction Set Reference”,
Intel, 2009(9).
[3] Intel, “Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3 : System Programming
Guide", 2009(9).
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Single Camera-based Positioning Method using Image Database
Jin Seon Song, Yongwan Park
Dept. of Information and Communication
Yeungnam University
Gyeungsan Republic of Korea
E-mail: [email protected], [email protected]
Abstract
In this paper, we propose a method of estimating the distance to the desired object using a single camera only. .
In our scheme, we create a database of the images on the target object, which should be taken from different
locations. The database incorporates the distance to the object and the features points from the Speeded up
Robust Features (SURF) algorithm alongside each image. When we have an image from the arbitrary position,
we search the database for the most similar image and accept its distance as the real distance to our desired object.
We evaluate the similarity of images from the feature points. Our method can be applied to the indoor
environments as well as the outdoor and its accuracy improves with the size of the database.
Keywords: Database, Camera, SURF, Distance matching, Feature point, Estimation
1. Introduction
This paper proposes a positioning method based on feature comparison between the images stored in database,
which are acquired using camera sensor, and user’s input images. The proposed method takes advantage of both
the database-based fingerprint technique and the camera sensor-based image recognition technique. The
proposed technique does not require unique information about individual positions, such as the information about
WLAN and the geomagnetic field. In addition, it can overcome the weak point of infrastructure management,
which is demanded by the image recognition-based positioning technique utilizing marker
2. Proposed Method
The test is the complicated experiment unlike the test in the indoor environment using grid. It is the big task to
process bright data, height of image, angle in the work creating Database We could solve this problem through
SURF(Speeded Up Robust Features) algorithm. The One’s strength, extracting the feature point after a while, as
to SURF, angle and height of object was changed. So, it is the algorithm which surely is necessary in this
research. We created Database in advance and inputted real image and compared real image
A. The database construction
We created the total 10 database with 5M space in 50M section. Database is including feature point and
distance every ten each image data. Figure 1.
Figure 1. The test environment
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B. The real image input
In order to find out distance value from image, We obtained an image in the arbitrary three spot 19M,
23M, 31M
C. The feature point extraction
We used SURF algorithm in order to evaluate similarity of other two image.
D. The similarity evaluation
Figure 2. Database image comparison of input image
We wished to confirm easily by the both eyes feature point of input image was how to be changed. So, I
expressed the total range of the feature point with the box and observed a change. When the box is smaller than
the image of Database, I could know being more near input image location than the image of database image. On
the contrary In the case of bigger than the image of database, I could know being more far input image location
than database image. Figure 2.
E. Distance assignment
I got distance data from adjacent database which I find through above test. And then, an assignment did the
corresponding distance value. TABLE 1.
Table 1. Database distance assignment result
DISTANCE OF INPUT IMAGE
19M
23M
31M
DISTANCE OF MATCHING IMAGE
20M
25M
30M
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Evaluation of Cache Partitioning:
Improving CPU Utilization of Multi-core Embedded Processors
Eunji Pak
Embedded SW Research Department,
Abstract
In multi-core embedded processors, concurrently running tasks compete for the shared cache and cause interthread cache interference. That interference increases the WCET of real-time tasks, allocates excessive time and
resources to tasks, and negatively affects the system resource utilization. In this paper, we exploit the cache
partitioning capability of modern server processors and show the potential of cache partitioning technique to
alleviate the cache interference problem in modern embedded multi-core processors.
Keywords: Real-time embedded system, Multi-core processors, Cache partitioning
1. Introduction
Embedded processors are increasingly using multi-core processors to achieve better performance and energy
efficiently. In multi-core processors, different cores often share the cache to improve the efficiency of limited onchip cache resources. However, concurrently running tasks compete for the shared cache capacity and cause
inter-thread cache interference.
In real-time embedded systems with multi-core processors, because of the cache interference, accurate
estimation of the worst-case execution time (WCET) is difficult. Because developers must budget for WCETs,
tasks are allocated excessive and unnecessary resources and the CPU utilization is significantly degraded.
In this paper, to address this problem, we utilize the cache partitioning technique which is implemented in few
modern server processors. In those processors such as AMD bulldozer, developers can control the cache capacity
allocated for each core. We evaluate the performance of cache partitioning technique and suggest the way of
maximizing CPU utilization without compromising safety criticality of real-time embedded systems.
2. Cache Partitioning
For an evaluation of cache partitioning, we use AMD bulldozer processor designed for servers. System
consists of 4 cores with each of 2 cores share a 2MB L2 cache and all cores share 8MB L3 cache. L3 cache can
be divided into four 2MB sub-caches and developers can decide the allocated cache capacity for each core in
2MB granularity [1].
We use five applications from SPEC CPU 2006 benchmark [2] and measure the execution time with various
application-to-core mappings. In Figure 1, y-axis presents the performance of ‘bzip2’ application when it is coallocated and shares cache with other four applications and x-axis presents the co-allocated application. Note that
the value in the y-axis is normalized to the execution time of ‘bzip2’ without any cache interference. Figure 1
represents the performance without cache partitioning (w/o Cache Part.) and the performance when we exploit
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the cache partitioning capability of bulldozer processor (w Cache Part.). In experiments, we allocate 6MB cache
for ‘bzip2’ application and 2MB cache for other application.
Figure 1. Performance of application 'bzip2'
As shown in the left graph in Figure 1, the performance of ‘bzip2’ is affected a lot with respect to the coallocated application. Performance gap is up to 14.8% which imposes that estimation of WCET in multi-core
environment is difficult due to the inter-thread cache interference.
Besides, as shown in the right graph, performance gap is decreased a lot when we exploit cache partitioning. It
indicates that the cache partitioning makes application execution time more deterministic by controlling the cache
allocation among applications and mitigating the cache interference. Developers can budget execution time more
tightly, thereby keeping system resource utilization high. Moreover, by controlling the cache interference,
performance is improved a lot. Results impose that cache partitioning technique may provide performance and
power efficiency of real-time embedded systems.
As a few modern server processors implement hardware cache partitioning and expose control to the developer,
controlling the interference via cache partitioning can be a practical way to improve the safety and CPU
utilization in real-time embedded systems with multi-core processors.
5. Conclusions
In this paper, we evaluate the performance of cache partitioning capability which is implemented in few
modern processors to present the potentials of cache partitioning technique in real-time, multi-core embedded
system.
We show that the cache partitioning provides an effective means of controlling the inter-thread cache
interference among applications, thus bounding the WCET much more tightly. It allows developers can set
WCET relatively tight and maximize CPU utilization without compromising the safety criticality.
References
[1] Bios and kernel developer's guild for AMD family 15h processors, March 2012.
[2] John L. Henning, Spec cpu2006 benchmark descriptions, SIGARCH Computer Architecture News 34 (2006),
no. 4, 1-17.
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95
The Memory Core in 3D Die-Stacked DRAM
Yongjoo Kim, Taeho Kim, Chaedeok Lim
Electronics and Telecommunication Research Institute (ETRI)
218 Gajeongno, Yuseong-gu, Daejeon, 305-700, Republic of Korea
E-mail: {y.kim, taehokim, cdlim}@etri.re.kr
Abstract
With the growth of technology and the improvement of architecture, contemporary von Neumann computer
system can execute most of applications efficiently. Nevertheless, some memory intensive applications that
access memory irregularly and have large dataset expose the limitations of the von Neumann computer system on
the low cache efficiency. Therefore, these applications suffer from significant memory stall time in the
conventional computer system. In this paper, we proposed a computer system model that consists of conventional
system and 3D die-stacked memory containing co-processor within its logic layer to address the memory-wall
problem.
Keywords: Core, Memory, 3D.
1. Introduction
In this paper, we propose a computer system model that consists of a conventional CPU and a 3D die-stacked
memory containing co-processor within its logic layer to address the problem of a lot of cache miss. With the
emerged stacking technology and hybrid DRAM architecture such as HMC [1] comprised of some DRAM layers
and an additional logic layer, it become possible to integrate a small core (now refer as memory core) that
accesses whole memory banks equally within DRAM. Residing in memory, the core can exploit shorter latency
by avoiding off-chip transfer. For that reason, the core in DRAM can executes the parts of application, which is
bottlenecked by the data transfer between DRAM and CPU more efficiently. Accordingly, we can achieve the
improvements on performance and power efficiency when these parts are partitioned from the whole of
application and mapped to the core in memory.
2. 3D Die-Stacked DRAM Architecture With Separated Layers
Three dimensional die-stacked DRAM is emerging as a promising solution for future memory to satisfy the
demand of performance, power and cost [2]. Although there are several models for 3D die-stacked DRAM, the
DRAM architecture that has separate die types for DRAM core and peripheral circuits shows substantial
improvements in performance and power efficiency [1-2]. Fig.1 shows the DRAM architecture that has two types
of die. One is a conventional DRAM die type for DRAM core such as cells and sense amp, which require
integration density. The other is a logic die type for peripheral circuits such as DRAM internal bus and row
buffer, which needs fast operation speed. By arranging DRAM components to proper die, this hybrid memory
system can obtain substantial improvements in aspect of performance and power efficiency.
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Figure 1 Hybrid layer stacking of HMC
In addition to the advantages, the DRAM architecture shows the possibility of further improvements for
overall system. Because peripheral circuits of DRAM do not require large area, a logic die in the DRAM
architecture remains considerable space unused so that this space can be utilized for other objectives. In [3], for
example, this unused space is used for row buffer cache to improve memory reuse in DRAM. We propose to use
the unused space for a memory core for memory intensive tasks.
3. 3D DIE-STACKED DRAM ARCHITECTURE WITH SEPARATED
LAYERS
Fig.2 depicts the overall system that we propose which consists of CPU and 3D die-stacked DRAM with a
memory core. In this system, the main CPU is a modern high-performance microprocessor but a memory core
located on a logic layer in DRAM is a small low-power core because of area constraints. Instead, a memory core
can access DRAM faster owing to its location. As a result, this system has two heterogeneous cores in respect of
computation power and accessibility to memory. It is very important to understand the heterogeneous
characteristic and apply it to the SW partition to maximize the benefit.
Figure 2 Block Diagram of Proposed System
4. Conclusions
In this paper, we propose a computer system model that consists of conventional CPU and 3D die-stacked
memory containing co-processor within its logic layer to address the problem of a lot of cache miss.
References
[1] J. T. Pawlowski. Hybrid Memory Cube: Breakthrough DRAM Performance with a Fundamentally ReArchitected DRAM Subsystem. In Proc. of the 23rd Hot Chips, Stanford, CA, August 2011..
[2] Ke Chen; Sheng Li; Muralimanohar, N.; Jung Ho Ahn; Brock-man, J.B.; Jouppi, N.P.; , "CACTI-3DD:
Architecture-level modeling for 3D die-stacked DRAM main memory," Design, Automation & Test in
Europe Conference & Exhibition (DATE), 2012 , vol., no., pp.33-38, 12-16 March 2012
[3] Gabriel H. Loh. 2011. A register-file approach for row buffer caches in die-stacked DRAMs. In Proceedings
of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-44 '11). ACM, New
York, NY, USA, 351-361.
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A Dumb Battery Consumption Prediction Method of Mobile Device
without Smart Battery
Ho-Joon Park
Electronics and Telecommunications Research Institute, ETRI
Republic of Korea
Abstract
It is very important that the battery consumption management with population of smartphone era. But Smart
Battery which needed by battery management only uses laptop and higher price products because of unit costs
and mass. In this paper, we propose a battery consumption prediction method based on power measurement,
which calculates a similar-consumption current capacity and measures power like to smart battery in Dumb
battery without BMS.
Keywords: Smart Battery, Dumb Battery, Power Measurement, DVFS, BMS
1. Introduction
Smartphone to the public, use of battery for a mobile device has increased explosively. Battery use is a major
smartphones, tablets, navigation, etc. vary. The battery management also is very important increasingly. The
management of the mobile device battery is efficient when BMS (Battery Management System) [1, 2] by
mounting the smart battery equipped.
BMS mounted on the smart battery is consist of various sensors through the voltage, current, temperature and
other information into the system informing the battery. And like lithium ion battery, the voltage is as shown, to
prevent dangerous power-off circuit has been built up.
The problem is price and size of smart battery. As for mobile devices, a unit price is very important at mobile
device market. Smart battery is the cause of poor price competitiveness. BMS is not equipped with extra
batteries place and only a very limited to provide the system[2]. Dumb battery is not equipped BMS and
provides very limited function to the system. It has power-cut circuit and measuring voltage. But it has
advantages than BMS(Smart battery). Dumb battery is smaller than smart battery and cheaper.
Dumb battery cannot measure its current originally itself [4]. Power which computes product of workload on
the device and current consumption is the key calculation point to predict battery consumption on mobile devices.
Because the system equipped in dumb battery cannot measure its power, like Smart phones and Tablet which
equipped in dumb battery also cannot measure power. However, measuring voltage between workloads, the
remaining power will be guess.
Thus, if the system can measure current its circuit even if they have dumb battery indirectly, it can calculate
power like laptops equipped in BMS with additional some calculation.
98 ISET 2014
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In this paper, the current measurement is not possible on a mobile device equipped with dumb battery in the
lab environment, equipment pre-measured for all the states of the pre-measured current value stored in the
database as a way to infer the value of current consumption, and the remaining power is calculated proposes a
method to predict the time.
2. Related Works
The power of the DC link voltage across the load (V) and current (A) in a closed circuit can be calculated by
the product of load and current. In general, because mobile devices have CPU and a set of devices, the CPU
workload increases, also increasing the amount of current consumption, CPU is in standby state, the amount of
current consumption is reduced [5].
Most of the batteries used in the mobile device is a lithium ion battery. This battery is the power per unit
volume can be increased compared with other cells, have little or no memory effect. In contrast, the
disadvantages of a lithium-ion battery voltage drops below a certain amount or a risk of battery explosion
protection circuit is needed to be sure. Most mobile devices based on the no-load by using 4.2V to 3.3V see [6].
The shape of the battery current provided by the direct current or the discharge the voltage across the load is
reduced the more. This voltage drop we used, depending on the amount of current consumption, as shown in
Figure 1 takes the form of a curve. The shape of the voltage drop of the battery temperature, the amount of
current consumption is shown in accordance with another form.
Figure 1. Curves for Voltage Drop.
3. Measurement of Power
A prediction method of power measurement, we proposed, is product of measured workload voltage and
pseudo current value along state of mobile device, because the system equipped in dumb battery cannot measure
actual current. To do for that, the following assumptions are needed.
(1) All devices in mobile device is impossible ever to put on and take off.
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99
(2) All devices use unique power consumption value.
(3) The sum of current consumption of a mobile device in each module is same to the total of the
consumption current value.
To measure consumption power of mobile device equipped in dumb battery, it is necessary to measure current
value along the state of modules in mobile device. To do this, figure 3 shows an experiment in case.
In Figure 3, the current and voltage value are measured with DMM 4065 digital multi-meter of NI through the
LabView software in the host computer. For precise measurement, the experiment shown in figure 2 uses
precision power supply. And the equipment used to workload device is ODROID Q of hardkernel.
Figure 2. An environment of power measurement
Adjustable from mobile device side workload modules are CPU, WiFi, DMB, CDMA, etc. vary, but all other
modules for experiment to OFF, and only measurements of the CPU using only the DVFS capabilities. At this
time, the load of CPU is always set to be 100%.
Thus obtained value is similar to the mobile device power consumption at the moment is a certain amount of
current, as shown in Figure 3.
𝑃𝑃𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = 𝑉𝑉𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 × 𝐴𝐴(𝐶𝐶𝐶𝐶𝐶𝐶𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 )
𝑊𝑊𝑊𝑊𝑊𝑊𝑘𝑘𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
=∫
𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐
𝑡𝑡=0
𝑉𝑉(𝑡𝑡) × 𝐴𝐴(𝑡𝑡)𝑑𝑑𝑑𝑑
Figure 3. Expressions of power consumption
At some point in the power value can obtained by product of the corresponding voltage and current. Because
mobile devices equipped in dumb battery cannot measure current directly, equipment on the basis of the current
state of each module is calculated with status of each module. The total power consumption of the battery of the
mobile device from the moment when power is applied to can be obtained.
100 ISET 2014
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4. Conclusions
It is difficult to use smart battery equipped in BMS to manage battery, because of higher unit price and weight.
However, unlike the past, a variety of smartphone applications and a variety of built-in modules are much higher
battery consumption than older devices. In other words, the battery management than before is needed.
Dumb battery using the battery itself, so that the voltage measurement is possible only by the value of current
necessary for the power measurement cannot be obtained. Of course, the required current can be measured when
the device is added, but it is also possible to affect the unit price. In addition, most of the products released so far
it is impossible to apply.
In this paper, the various functional elements of the battery are not covered for parts. Nevertheless, the
calculation is similar to the current consumption since the battery's life can help to calculate the total power
consumption can be obtained proved.
In addition, ACPI standard which power management specification of PC defines the battery device equipped
with BMS for sure that use a smart battery. For this reason, there is no mobile devices that satisfy definition of
ACPI compliant. Following ACPI specification are standardized, the internal power management and battery life
of more than one module to predict and can help you manage.
Mobile devices in the future to deal with the battery management is similar to current consumption and above
all, to match the actual current consumption of calibration. In addition, repeated charging and discharging of the
battery reduce capacity of the battery. This part is also needed for the calculation.
References
[1] Thomas Stuart and Fang Fang, "A Modular Battery Management System for HEVs“. Lecture Note in
Computer Science (PACS 2003)
[2] Battery management system, http://en.wikipedia.org/wiki/Battery_Management_System
[3] HP and Intel Corporation, “Advanced Configuration and Power Interface Specification”, Volume 3
[4] Linden, D., “Maintenance-free Batteryies”, 2nd Ed, Research Studies Press Ltd,. Somerset, England, 1997.
[5] Wonyoung Kim, Gupta, M.S, Gu-Yeon Wei and Brooks, D., “System level analysis of fast, per-core DVFS
using on-chip switching regulators”, High Performance Computer Architecture, 2008.
[6] “SLPB 654374 1S1P SP Battery Manual”, KOKAM
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101
Qplus-hyper : A Hypervisor for Safety-critical Systems
Taeho Kim, Dongwook Kang, Soo-Young Kim,
Jin-Ah Shin, Donghyouk Lim, Vicent Dupre
Electronics and Telecommunication Research Institute
218 Gajeong-ro, Yuseong-gu, Daejeon, Republic of Korea
E-mail: {taehokim, dkang, sykim, jashin, befree, vdupre}@etri.re.kr
Abstract
In recent days, virtualization is one of most popular system software technologies. However, the embedded
system virtualization is not prevalent as others. The main barrier was performance degradation. Most of
embedded systems have low performance processor and less memory than other systems and no spare resource to
execute virtualization. However, the change is now starting. Since the performance of the embedded processors
gets improved, we can have high-performance embedded systems nearly similar as a laptop. In particular, ARM
processors include the virtualization extensions for hardware-based virtualization support. We expect that the
utilization of virtualization in embedded systems will grow rapidly.
Keywords: Virtualization, Hypervisor, ARM
1. Introduction
Our hypervisor, named Qplus-Hyper, targets safety-critical systems such as avionics and automotive vehicles.
Consolidation issues to reduce the SWaP(Size, Weight and Power) is a traditional research topic in this area. For
this issue, we think that the best solution for optimized SWaP system is hardware consolidation using
virtualization. Therefore, hypervisors for safety-critical systems should be developed with verification and safe
process for practical use.
2. Qplus-Hyper in detail
Qplus-hyper is a hypervisor based on micro-kernel architecture and currently in development. The number of
core in recent microprocessors is increasing and the scalability remains the main issue in recent system software.
Therefore, reducing the synchronisation cost is fundamental. For this purpose, we have implemented InterProcess Communication using message passing schemes as stated in previous studies such as Corey[2] and
Barrelfish[3].
Qplus-hyper targets a hybrid virtualization scheme in order to gain both advantages of full-virtualization and
para-virtualization. As latency in I/O systems is critical, we use para-virtualization while the other systems, fullvirtualization will be implemented with the ARM virtualization extensions. Currently, our I/O virtualization
framework is compatible with virt-IO so we can benefit from the legacy drivers implemented in open-source
operating systems. Following the micro-kernel approach, we split the I/O management from the kernel for
reliable and small hypervisor. For performance improvement, the direct interrupt handling mechanisms like
ELI[1] is in implementation for ARM architecture.
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Real-time VM scheduling is one of the most important features of Qplus-hyper. As mentioned, our target is the
mixed criticality system like IVI and Controller systems. For controller system, real-time responsiveness is main
requirement. On the other hand, performance is more important in IVI. For this problem, we consider
hierarchical scheduling for VMs and process in VMs and study issue on it. For practical use, software
development process and quality assurance activities are most important parts. We are following the AutomotiveSPICE development process and consider the ISO-26262 certification for automotive systems. In addition, we
conduct a formal verification for memory manager and interrupt manager modules. After that, we will prepare a
plan for formal verification for all architecture independent modules.
Figure 1. Micro-kernel architecture & Hybrid Virtualization with Safe and reliable development process
5. Conclusions
In Qplus-hyper, safety and reliability are top priority by minimizing SWaP. To minimize SWaP, qplus-hyper
adopts the form of microkernel. However, to overcome the performance issue of microkernel, we apply ARM
virtualization extensions to our hypervisor. For safety and reliability, we perform formal verification and process
development to be certified automotive SPICE. We will run qplus-hyper with Autosar OS and avionics OS
complied with the ARINC653 interface as guest OS. Therefore, we can prove that our system model is suitable
for safe-critical system.
References
[1] A. Gordon et. al, ELI: Bare-Metal Performance for I/O Virtualization, In Proceedings of ASPLOS’12
[2] S. Boyd-Wickizer et. al, Corey: An Operating System for Many Cores, In Proceedings of OSDI’08
[3] The Multikernel: A new OS architecture for Scalable multicore systems, In Proceedings of SOSP’09
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103
EcoVerifier : Tool Support for Formal Verification of ECML using
SpaceEx
Jaeyeon Jo, InGeol Chun, WonTae Kim
CPS Research Team, Embedded SW Research Dept
Electric and Telecommunications Research Institutes,
Daejeon, 305-700, Republic of Korea
E-mail: {jaeyeonjo, igchun, wtkim}@etri.re.kr
Abstract
Cyber-Physical Systems (CPS) are integration of computation and physical systems. Most of CPS are safetycritical systems such as avionic, vehicle, medical, etc. Formal verification finds faults of the safety-critical
systems model. We developed a connection tool EcoVerifier which is implemented as a plugin of CPS modeling
framework named EcoPOD. EcoVerifier provides input interface of properties and output interface of formal
verification result for connecting with a hybrid system verification tool named SpaceEx.
Keywords: Formal Verification, Hybrid System, Cyber-Physical Systems
1. Introduction
Cyber-Physical Systems (CPS) are combinations of computational systems and physical systems. As growing
complexity of embedded systems, CPS are important issue for controlling complicated systems. CPS are widely
used in the industry such as medical, avionic, military, or autonomous, etc. For improvement of CPS reliabilities,
ETRI(Electric Technology Research Institute) developed a CPS Modeling Framework ETRI CPS Open Platform
Developer (EcoPOD)[1]. The main modelling language of EcoPOD is ETRI CPS Modeling Language(ECML)
[2] which is specified to simulation. For improving assurance of safety of an ECML model, we need to develop a
safety verification method and integrates it into EcoPOD. Formal verification checks unpredictable behaviour of
a model, therefore it is used for a safety verification method. A formal verification tool of an ECML model is not
yet developed. However, previous researches [2] show that the formal verification of ECML model can be
available using model checking tools through the translation from ECML model into hybrid automata[3]. Our
concern is providing user interface for formal verification of ECML model. We implemented EcoVerifier which
is an EcoPOD plugin to use SpaceEx[4] indirectly through the translation tool. SpaceEx is an analysis tool for
non-linear hybrid automata which are widely used to research area. EcoVerifier provides input interface for
writing safety properties and environment and visualizing verification results. In the Section 2, we describe the
function of EcoVerifier and formal verification process using EcoVerifier, in the Section 3, we conclude our
discussion.
2. EcoVerifier
The process of formal verification of an ECML model is bellows: designing the model, writing properties such
as safety requirements, executing model checker and analysing execution results. Figure 1 shows overall process
of formal verification of an ECML model using EcoPOD and EcoVerifier. EcoPOD provides ECML model
designing method. For formal verification of the ECML model, the model needs to be translated to hybrid
automata which are input front-end of SpaceEx because the semantic of ECML model is different with the
104 ISET 2014
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semantic of hybrid automata. The translator is under-going developments and planned to be included in
EcoVerifier. In the translation phase, specification of the ECML model and translated hybrid automata are
different each other. Therefore, input properties of the ECML model and the hybrid automata are different. The
safety properties must be the form of formula because the model checker checks whether behaviour of model
meets safety requirements. EcoVerifier provides an input interface for writing safety properties for ECML model,
and then translates into input properties of SpaceEx. After the hybrid automata and properties are ready for
formal verification, SpaceEx starts analysing, and then generates result which describes whether model meets
properties or explored spaces of the hybrid automata. EcoVerifier visualizes the results for analysing an ECML
model by providing graphs or tables.
Figure 1 A Process of Formal Verification of an ECML Model
3. Conclusions
In this paper, we showed a translation approach to formal verification of an ECML model. EcoVerifier
provides a connection between the modelling framework named EcoPOD and hybrid system verification tool
named SpaceEx. It contributes to user convenience for formal verification as providing user interfaces. We are
not yet presented about translation rule and tool. Our future works are publishing about implementation of the
translator which translates from ECML model to Hybrid Automata.
Acknowledgment
References
[1] J. Jeon, I. Chun, W. Kim, "Metamodel-Based CPS Modeling Tool", Embedded and Multimedia Computing
Technology and Service, pp.285-291, 2012.
[2] J. Jo, J. Yoo, H. Choi, S. Cha, H. Y. Lee, W.T. Kim, "Translation from ECML to Linear Hybrid Automata",
Embedded and Multimedia Computing Technology and Service, pp.293-300, 2012.
[3] Alur, Rajeev, et al. Hybrid automata: An algorithmic approach to the specification and verification of hybrid
systems. Springer Berlin Heidelberg, 1993.
[4] Frehse, Goran, et al. "SpaceEx: Scalable verification of hybrid systems." Computer Aided Verification.
Springer Berlin Heidelberg, 2011.
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105
Autonomic Computing Research Challenges for CPS
Prajakta Jadhav*†, Won-tae Kim†, In-Geol Chun*†
*
Korea University of Science and Technology
†
Cyber Physical Systems Research Lab
E-mail: {prajakta65,wtkim,igchun}@etri.re.kr
Abstract
Cyber-Physical System (CPS) is a combination of physical and engineered systems whose operations are
controlled by using various computing and communication systems. As physical systems are the part of cyberphysical systems, it is very difficult to control and monitor the system because of its unpredictability and
uncontrollability. Hence an autonomic computing system helps to develop CPSs, which will have an ability of
self-managing, self-configuring, self-healing and self-protecting. To develop self-managing systems, analyses of
the data and planning the resources required to execute the policies are the crucial part of the system. This paper
describes challenges in analyses and planning of autonomic computing for cyber-physical system.
Keywords: Cyber-Physical Systems, Autonomic Computing, Artificial Intelligence, Machine Learning.
1. Introduction
A Cyber-physical system is combination of physical systems with computing and communication [1].
Examples of CPSs include aerospace systems, health care and medicine, automotive systems, advanced power
grids, smart cities etc. The size, complexity and dynamism of these systems are increasing. This necessitated the
investigation of alternative for system and application design and hence autonomic computing systems are
developed. Using an autonomic computing system in development of cyber-physical systems is beneficial for
seamless management. Its goal is to realize computer and software systems and applications that will not only
make decisions on its own using high level policies, but also adapt to unpredictable changes.
This paper will discuss about autonomic computing systems in section 2. And research challenges of
Autonomic computing in CPSs are covered in section 3. Conclusion is described in section 4.
2. Autonomic Computing System
In 2001, IBM introduced autonomic computing, which refers to self-managing characteristics of distributed
computing, adapting to unpredictable changes while hiding intrinsic complexities from users and operators [3].
The autonomic computing system is self-configuring, self-healing, self-optimizing, and self-protecting [4]. It is a
four step procedure to build autonomic computing applications. The four steps called MAPE loop are: Monitor
which will monitor the loops and collects the details from resources. Analyse function will observe and analyse
conditions to find out the reason for an issue. Plan function creates plan from the information collected by
analysing the system. Execute function will provide mechanism to control the execution of plan. Some of the
approaches like agent oriented or component based are used for developing autonomic systems. In order to
106 ISET 2014
1
analyse the data artificial intelligence and machine learning techniques can help to make the decisions. These
decisions can be used to plan the task as well as resources. Next section covers the research challenges in
analyses and planning phase of autonomic computing.
3. Research Challenges in Autonomic Computing
The research challenges in autonomic computing include communication standardization, relationship among
autonomic element, robustness and analysis theory. As this system will be a combination of many systems, there
will be multitasking of various processes simultaneously; hence it requires monitoring, analysis, planning, and
execution. Various technologies are used for analysing monitored data and files to identify conditions of a system.
The challenge here is to determine a good set of rules that will describe the condition properly [3]. Artificial
intelligence and machine learning techniques can be used to analyse the input data [5]. Analyses phase gives
intelligence to the system. Therefore, designing robust learning procedure is one of the main research challenges
of autonomic computing system. Dynamic changes in the system must be adapted quickly. Based on the analysis,
planning phase assigns the task and the resources according to the predefined policies. Machine learning methods
enable the dynamic modification of the policies. These policies are forwarded for execution.
Some of the other challenges include self-configuration, if a new element is added to the system then seamless
integration of that new element into the system. Self-healing can face the problem of localization and
determination; the problem can be anywhere in the system or in website or in the connecting networks. It is
challenging to detect the problem and heal it. Co-ordination between autonomic elements is one of the main
problems in self-optimization. Finally for self-protection, the systems continuously monitor all the parts of the
system. The challenge in self-protection includes network threats and malfunction of the system.
4. Conclusion
Autonomic computing helps to overcome the limitations of cyber-physical systems. In this paper, we presented
challenges in autonomic computing technologies for cyber physical systems. In order to develop robust and
reliable system, all these challenges should be considered. This paper mainly concentrated on challenges of
analysis and planning phase. The future research will mainly focus on developing techniques for analysing and
planning phase in autonomic computing.
Acknowledgement
This work was supported by the IT R&D Program of MSIP/KEIT [10035708, "The Development of CPS (CyberPhysical Systems) Core Technologies for High Confidential Autonomic Control Software"]
References
[1] Shi Jianhua, Jiafu Wan, Hehua Yan, and Hui Suo. "A survey of cyber-physical systems." In Wireless
Communications and Signal Processing (WCSP), 2011 International Conference on, pp. 1-6. IEEE, 2011.
[2] Parashar, Manish, and Salim Hariri. "Autonomic computing: An overview." InUnconventional Programming
Paradigms, pp. 257-269. Springer Berlin Heidelberg, 2005.
[3] Computing, Autonomic. "An architectural blueprint for autonomic computing."IBM White Paper (2006).
[4] Chun Ingeol, Jeongmin Park, Wontae Kim, Woochun Kang, Haeyoung Lee, and Seungmin Park. "Autonomic
computing technologies for cyber-physical systems." In Advanced Communication Technology (ICACT),
2010 The 12th International Conference on, vol. 2, pp. 1009-1014. IEEE, 2010.
[5] Kephart, Jeffrey O. "Research challenges of autonomic computing." In Software Engineering, 2005. ICSE
2005. Proceedings. 27th International Conference on, pp. 15-22. IEEE, 2005.
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The 9th
Interactive SessionⅡ
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10:50-11:40, May 23, 2014
Interactive Session
Write Performance Analysis with Buffered FUSE .........................................................................................................111
Chanhyun Park, Youjip Won (Hanyang University)
Design and Implementation of Broadcasting Content Authoring Tool based on HTML5 ................................113
Sungjoo Park, Chang-Mo Ynag, Chai-Jong Song (KETI)
Content Recommendation Algorithm based on Usage History Analysis ..............................................................116
Sungjoo Park, Chang-Mo Ynag, Chai-Jong Song (KETI)
New Memory Translation Layer for Fast and Effective use of New Memory as Storage......................................119
Hyun Sub Song, Young Je Moon, Tae Jin Kim, Sam H. Noh (Hongik University)
The Merge Chaining Hashing Scheme with NAND Flash Memory .........................................................................121
Woong-Kyu Park, Sung-Chul Kim, Gyu Sang Choi (Yeungnam University)
The GPGPU Virtualization Performance in Actual Network Environment .............................................................123
Geun-yeong Bak, ShinHyoung Lee, Chuck Yoo (Korea University)
A Research on Improving the Computational Overhead of SLAM with SmartPhone . .......................................125
Cheol-Won Lee, Daeyoung Na, Heung-Seok Jeon (Konkuk University)
Real-time Schedulability Analysis for Hardware Supported Virtual Machine on ARM Cortex-A15 Processor .......127
Tae Kyoung Kim, Se Won Kim, Chuck Yoo (Korea University)
Software based Virtual Router Platform as a Super-peer in Software-Defined Network . .................................129
Dae-Myeong Kang, Shin-Hyoung Lee, Sung-Won Ahn, Chuck Yoo (Korea University)
Explore “Decrease-All-By-One” on DDoS Packet Filtering using Counting Bloom Filter ....................................131
Suk-Young Oh, Shin-Hyung Lee, Chuck Yoo (Korea University)
Design of a Route Guidance System for the Visually Impaired . ...............................................................................133
Hyunho Yoo, Byung-Jae Choi (Daegu University), Jong-Hwan Song (Mine Corporation)
Barriers to Real-Time Network I/O Virtualization: Observations on a Legacy Hypervisor . ................................135
Sang-Hun Lee, Jong-Soo Seok, Hyun-Wook Jin (Konkuk University)
A Power Replay Attack in Electronic Door Locks .........................................................................................................138
Seongyeol Oh, Joon-sung Yang, Andrea Bianchi, Hyoungshick Kim (Sungkyunkwan University)
NO
Interactive Session
User-level Memory Performance on a big.Little ARM Processor . ............................................................................140
Beomhee Lee, Jibum Kim, Moonju Park (Incheon National University)
15 API-Level Mapping Between HLA and DDS for the Interoperable Middleware System .....................................143
Minchul Shin, Seokjoon Hong, Kyungrak Lee, Ramesh Kumar, Jongsang Yi, Inwhee Joe (Hanyang University),
Kyeongtae Kim, Hyungkook Jun, Woosuk Cha, Wontae Kim (ETRI)
16 A Mechanism for Tracking Interactive Episodes in Mobile Devices . .......................................................................145
Nicolas Badano (Sungkyunkwan University), Jeaho Hwang (KAIST), Euiseong Seo (Sungkyunkwan University)
17 PA-Pfair: A New Pfair Scheduling Policy for Performance Asymmetric Multiprocessors ...................................151
Peng Wu, Minsoo Ryu (Hanyang Universit)
18 A Study on Storing Environmental Data on SEDRIS for Cyber Physical Systems . ................................................153
Hyun Seung Son (Hongik University), In-geol Chun, Jae Ho Jeon (ETRI),
Woo Yeol Kim (Daegu National University of Education), R. Young Chul Kim (Hongik University)
19 Zero-Copy Load Balancing for OpenCL Platforms on Mobile Systems with Unified Memory Architecture .......155
14
Jonghyun Park, Jaemin Hwang, Byeong-Gyu Nam (Chungnam National University)
110 ISET 2014
Write Performance Analysis with Buffered FUSE
Chanhyun Park, Youjip Won
Department of Computer and Software
Hanyang University, Seoul, Republic of Korea
E-mail: {parkch0708, yjwon}@hanyang.ac.kr
Abstract
With the development of technology, the size of files handled by smart devices is increasing. This phenomenon
can cause the storage to be the biggest bottleneck of smart devices. There is a study that presents a major factor
in this phenomenon is overhead in user level filesystem (FUSE). And it proposed buffered FUSE (bFUSE) and
increased size of FUSE I/O as a solution of this problem. In this paper, we reproduced it in ODROID-Q2 and
measured write performance. As a result, we can raise the write performance up to 96% compared to raw device
bandwidth with FUSE.
Keywords: Android, Storage, User level filesystem, Write buffer
1. Introduction
Penetration rate of smart devices is increasing every year. And with the development of technology, utilization
range of smart devices is widening. Latest smart devices can take and retouch a picture of 10 million pixels or
more, and record and playback video of ultra HD class. This means that the size of the file handled by smart
devices is increasing. According to Kim et al. [1], this phenomenon can cause the storage to be the biggest
bottleneck of Android-based smart devices.
The study of Jung et al. [2] proposed buffered FUSE to solve this problem. They analyzed I/O workload of
user partition on Samsung Galaxy S3, and discovered an overhead of user level filesystem (FUSE). For the
reasons of the overhead, they pointed out the fact that FUSE I/O’s unit of 4KB caused the I/O fragmentation and
excessive context switch. They proposed to use buffered FUSE (bFUSE) and increased size of FUSE I/O to solve
this problem and to raise the write performance up to 99% compared to raw device bandwidth with FUSE.
In this paper, we reproduced bFUSE environment on ODROID-Q2 that has lower performance than Samsung
Galaxy S3 and measured sequential buffered write performance. As a result, with the use of specific filesystem
and I/O scheduler, we can raise the write performance up to 96% ratio of raw device bandwidth with FUSE.
2. Evaluation Design
Table 1. Specifications of ODROID-Q2
Samsung Exynos4412 Prime Cortex-A9 Quad Core 1.6Ghz with 1MB L2 cache
Processor
2GB LP DDR2 880Mega data rate
Memory
16GB eMMC
Storage
Android 4.1 Jelly Bean (3.0.51 Kernel)
OS
Hardware specifications of ODROID-Q2 which are used in experiment are shown in Table 1. ODROID-Q2
uses Samsung Exynos4412 Prime as a processor. It has 4 cores and 1.6GHz clock speed. Memory of total 2GB is
installed. And 16GB eMMC was used for storage. OS was Android 4.1 Jelly Bean and Kernel is 3.0.51 Kernel.
To measure I/O performance, benchmark tool MobiBench [3] was used. During the measurement of
performance, the size of file was set to 100MB and the size of I/O was set to 512KB. We measure performance
of sequential buffered write for ten times, and calculate minimum, maximum and average value.
1
111
We use EXT4 and XFS filesystem. And the experiments were performed in six environments. The basic
environment of ODROID-Q2, BASE (FUSE with EXT4 filesystem, BFQ scheduler, 4KB FUSE I/O unit) and
environment capable of maximum performance, MAX (raw device, NOOP scheduler, without FUSE) was the
standard environment. We changed I/O scheduler to the Deadline, which was suggested as the most appropriate
scheduler from previous studies [2]. After changing size of FUSE I/O, we conducted the experiment with the
same workload in two different environments with EXT4 and XFS respectively – 512KB-EXT4 (FUSE with
EXT4, Deadline scheduler, 512KB FUSE I/O unit) and 512KB-XFS (FUSE with XFS, Deadline scheduler,
512KB FUSE I/O unit). Finally, we conducted an experiment in two different environments with 8MB FUSE
buffer applied to them – bFUSE-EXT4 and bFUSE-XFS.
3. Experiment
Figure 1. Result of sequential buffered write (100MB file, 512KB I/O size)
Figure 1 shows sequential buffered write performance in six environments which Chapter 2 presented. MAX
environment shows 35.5MB/sec throughput. BASE environment shows only 17% throughput of MAX
environment. When changing I/O scheduler to Deadline, and increasing size of FUSE I/O to 512KB, buffered
write performance showed 86% of performance compared to that of raw device in EXT4 filesystem. In XFS
filesystem, showed 90% of performance compared to that of raw device. And two environments with 8MB FUSE
– bFUSE-EXT4 and bFUSE-XFS environments show 90% and 96% of performance compared to that of raw
device.
4. Conclusions
As a result, changing I/O scheduler and size of FUSE I/O could increase performance more than five times.
And the use of buffered FUSE could show an additional performance improvement of 5%. Than we can raise the
buffered write performance up to 96% compared to that of of raw device bandwidth with FUSE. This technology
is expected to be able to minimize storage bottlenecks of Android-based Smart device in the future.
References
[1] H. Kim, N. Agrawal, and C. Ungureanu, “Revisiting storage for smartphones” In Proc. Of the 10th USENIX
Conference on File and Storage Technologies, San Jose, CA, USA, Feb. 2012
[2] S. Jeong, Y. Won, “Buffered FUSE: optimizing the Androi IO stack for user-level filesystem”, International
Journal of Embedded Systems (IJES), Special issue for Embedded and Ubiquitous Computing, IEEE EUC-13,
Zhangjiajie, China, November 13-15, 2013
[3] S. Jeong, K. Lee, J. Hwang, S. Lee, Y. Won, "Framework for Analyzing Android I/O Stack Behavior: from
Generating the Workload to Analyzing the Trace", Future Internet 2013, 5(4), Special Issue for "Mobile
Engineering², MDPI(ISSN 1999-5903), 591-610; doi:10.3390/fi5040591
112 ISET 2014
2
Design and Implementation of Broadcasting Content Authoring Tool
based on HTML5
Sungjoo Park, Chang-Mo Ynag, Chai-Jong Song
Smart Media Research Center, Broadcasting & ICT R&D Division
KETI, Gyeonggi Province, Republic of Korea
E-mail: {bpark, cmyang, jcsong}@keti.re.kr
Abstract
This paper proposes a broadcasting content authoring tool base on HTML5. The format of the edited content
in the proposed authoring tool is defined as User Edited Content (UEC). We also defined the specification of
UEC metadata based on TV-Anytime Forum and TTA standard. The main difference of the proposed authoring
tool is that edited broadcasting contents are scene or shot units, not title unit. So, user can easily search and create
UEC. For the performance evaluation, we implement the real broadcasting content authoring tool combined with
media player in HTML5 browser and the metadata generation method.
Keywords: Authoring tool, HTML5, UEC, Metadata
1. Introduction
Recently, with the proliferation of digital broadcasting content, the demand for making their own content using
combination of small broadcasting content units. In order to satisfy the needs of users, the authoring tool based on HTML5
which supports easily browsing and editing contents is need. And in order to create user content more conveniently, the
content that edited in the authoring tool should be small unit like scene or shot unit, not title unit. About content metadata, it
is required to define the new content metadata format for distribution of edited content to users.
2. HTML5
HTML5 is the essential web standard and technology for providing the convergence multimedia service in
various device environments [1]. HTML5 means the Hyper Text Markup Language 5 and it is proposed next
version of HTML. Whereas the existing HTML can only display the test and hyper-link, HTML5 can support
various presentations and multimedia services. The main advantage of HTML5 is compatibility. HTML5 is the
only cross-platform for both developer and consumer and supports the device independency in many platforms.
So, most of web browsers are compatible with HTML5 includes Chrome, Android web-view and Internet
explorer browser. New technologies of HTML5 are shown as Table 1.
Table 1. New technologies of HTML5
Function
Semantics
Styling effect
2D/3D graphics/effects
Video/Audio
Device Access
Application Cache
Web Sockets
Geolocation
Description
To be accurately and easily in retrieval engine and web documents parser
Support new input methods likes range, color, determine without script
support tags(canvas) and APIs for 2D/3D graphic in web environment
support tags and APIs for video/audio in web environment
Support bi-directional communication with server
Support offline application without network interface
Sopport APIs for bi-directional communication with server
Support APIs for using the geographic information
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3. Metadata for UEC
The metadata for UEC defined in this paper consists of UEC content metadata and UEC segmented list (edit
information) and the basic schema of metadata is refer to TV-Anytime Forum and TTA standard [2]. UEC
content metadata means additional information describe characteristic information of multimedia content. UEC
segmentation list is defined as edit information. Fields of proposed metadata for UEC are shown as Table 2.
Table 2. Fields of proposed content metadata for UEC
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field Name
content_ID
program_title
Subtitle
episode_sequence_number
production_date
product_duration
Storyline
program_genre_code
broadcast_person
name_korean
cast_name
image_URL
main_image_url
Essence
clip_type_code
Number
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Field Name
essence_ID
media_url
file_format
file_size
video_bitrate
file_name
video_codec
width
height
aspect_ratio
audio_codec
audio_bitrate
audio_channel
audio_sampling_rate
4. Framework of Authoring Tool
This paper proposes a broadcasting content authoring tool base on HTML5. Broadcasting contents edited in
the authoring tool are divided into scene or shot units, not title unit. So, users can retrieve broadcasting contents
which they want to edit easily. And these scene or shot units of broadcasting contents are provided from content
server with MP-QF interface. After creating UEC, authoring tool should generate new metadata includes edit
information and content metadata. Functional requirements of the proposed authoring tool are shown as Table 3.
It includes functions of authoring tool and user interface [3].
Table 3. Functional requirements of the proposed authoring tool
Required Function
User Registration
Login/Logout
Query input
List of Retrieval Results
Video Player
Time-line
Gathering of Edited Content
Preview
Content Registration
My Contents
Description
Support the registration of new user interface with user management server
Support the function for user login/logout
Support the text query input for the content retrieval
Support the viewer of content list about retrieval results includes thumbnail,
image, title and synopsis
Support the video playback for edited content and the result of content
retrieval
Support the time-line display for video playback and content editing
Support the content gathering about edited (cut, paste) content
Support the preview function of the edited content
Support the content registration to content management server after edition
Support the presentation of content list which edited by user
5. Result of Implementation
We have used both Chrome and Internet Explorer 9 browsers for the implementation of authoring tool. The
114 ISET 2014
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proposed authoring tool not only supports to edit and create UEC and, but also provide the method for generating
UEC metadata. Fig.1 shows the result of the implemented authoring tool and Fig.2 shows the generation process
of UEC metadata respectively.
Figure 1. Result of the implemented authoring tool
Figure 2. Generation process of UEC metadata
5. Conclusions
The number of contents in the multimedia service is increasing rapidly. It causes the increase of consumers’
requests about convenient and efficient content creation services. From this perspective, the content authoring
tool including generation of metadata attracts attention. In this paper, we proposed the practical content authoring
tool for broadcasting contents based on HTML5. And we found that the proposed authoring tool can create UEC
easily and efficiently.
6. Acknowledgement
This work was supported by the IT R&D program of MSIP/KEIT. (10044615, Development of OpenPlatform/Social Media Production and Delivery System for Fused Creation, Editing, and Playing of Broadcasting
Media Contents on Cloud Environments)
References
[1] HTML5 Living Standard, http://www.whatwg.org/specs/web-apps/current-work/multipage/
[2] TV-Anytime Forum, “Specification series: S-3 on metadata,” SP003v13, 2002.
[3] Britta Meixner, Katarzyna Matusik, Christoph Grill and Harald Kosch, "Towards an easy to use authoring
tool for interactive non-linear video", Multimedia Tools and Applications, 2012
3
115
Content Recommendation Algorithm based on
Usage History Analysis
Sungjoo Park, Chang-Mo Ynag , Chai-Jong Song
Smart Media Research Center, Broadcasting & ICT R&D Division
KETI, Gyeonggi Province, Republic of Korea
E-mail: {bpark, cmyang, jcsong}@keti.re.kr
Abstract
This paper proposes a content recommendation algorithm based on the analysis of usage history information.
The proposed recommendation algorithm classifies usage history information which occurs in the consumption of
multimedia contents. And it analyzes the user preference from usage pattern information. The proposed algorithm
is designed to resolve the inaccuracy problem of content recommendation efficiently. For the performance
evaluation, we implement the real recommendation system and prove that the proposed recommendation
algorithm improves the accuracy of recommendation.
Keywords: Content recommendation, Usage history analysis, User preference
1. Introduction
As a useful application in multimedia content services, the recommendation algorithm has been studied to
improve user’s satisfaction. The content recommendation system is defined as a system to provide the best
content to users based on analysis and forecast techniques of user preferences. The content recommendation is
expanding its domain from documents to multimedia contents and goods [1, 2].
2. Usage History Analysis Algorithm
Recently, many recommendation algorithms have been adopted in various real service environments. Most of
them try to predict the user preference using the restricted user information like preference points. It is one cause
of the performance degradation in recommendation system. This paper proposes a new algorithm for
classification and analysis of implicit user’s information [3, 4]. The proposed algorithm predicts the user
preference based on the usage history pattern information analysis.
In order to predict the user preference, we collect usage history (usage patterns) from consumption information
of contents, such as play, stop, download, bookmark and etc. Usage patterns are stored in buffers and can be
classified based on the frequency of occurrence [5]. After classifying usage patterns, we predict user preference
about features of content. To do so, the proposed algorithm calculates the incidence of patterns and it can be
mathematically formulated as follows:
N pos
Equation 1.
f
preference _ user 
w
l 1
l
N neg
f l   wl  f l 
l  1
N
w
g
Where, l means the incidence of pattern l and l means the weight of pattern l . Features k mean
distinguishing feature information of content like genre, actor, director, title, keyword, and etc. N is defined as
the total number of patterns.
116 ISET 2014
1
3. Preference Evaluation
Because the proposed algorithm uses the implicit user information which gathered from the consumption of
contents, the performance can not be exactly evaluated using the existing dataset for well-known
recommendation algorithm. So, we build our own quantified evaluation dataset for the performance evaluation.
The detailed information of our evaluation dataset is illustrated in Table 1. Usage information of total 70 users
are gathered for 2 months and this dataset is classified into training set and test set, 70% and 30% of whole
dataset, respectively. In this paper, we use the precision and recall as the index for the performance evaluation.
Table 1. Detailed information of dataset
Item of evaluation dataset
The number of contents
The number of total features
The sum of used contents
The average of used contents
The number of data
491
1,002
3,780
80.43
Table 2 and Table 3 shows the precision, recall, coverage and sensitivity performance of the proposed
recommendation algorithm which compared with existing approaches. This result explains that our algorithm is
designed to resolve the previous inaccuracy problem efficiently and improve the recommendation accuracy. In
our implementation, the proposed recommendation algorithm achieves the precision of 27.16, the recall of 16.51,
the coverage of 100 and the sensitivity of 67 respectively.
Table 2. Comparison of precision and recall performance
Recommendation algorithm
User-based CF algorithm
Item-based CF algorithm
Category-based algorithm
Proposed algorithm
Precision
22.38
22.14
17.70
27.16
Recall
12.20
12.18
8.72
16.51
Table 3. Comparison of coverage and sensitivity performance
Recommendation algorithm
User-based CF algorithm
Item-based CF algorithm
Hybrid Collaborative Filtering algorithm
Hybrid Recommendation algorithm
Proposed algorithm
Coverage
99.424
99.221
99.572
99.920
100.000
Sensitivity
40
38
43
55
67
4. Conclusion
In this paper, we proposed the efficient recommendation system for multimedia contents. To alleviate the
inaccuracy problem of recommendation in existing studies, we designed the recommendation algorithm using
usage pattern information and the performance was also investigated. To improve the performance of the
proposed system, a more accurate analysis of user information will be further studied.
5. Acknowledgement
This work was supported by the IT R&D program of MSIP/KEIT (10047058, Development of
Smart Media Asset Management Technology based on Service Component for Activating Multimedia
data Consumption/Distribution).
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References
[1] G. Adomavicius and A. Tuzhilin, “Toward the next generation of recommender systems: a survey of the stateof-the-art and possible extensions”, IEEE Transactions on Knowledge and Data Engineering, Vol. 17, No. 6,
pp. 734-749, 2005
[2] K. Chorianopoulos, “Personalized and mobile digital TV applications”, Multimedia Tools and Applications,
Vol. 36, No. 10, pp. 1-10, 2008
[3] J. Wang, A. Vries, and M. Reinders, “A user-item relevance model for log based collaborative filtering”,
Proceedings of the 28th European Conference on Information Retrieval, pp. 37-48, 2006
[4] M. Ghazanfar and A. Prugel-Bennett, “A scalable, accurate hybrid recommender system”, Proceedings of the
3rd International Conference on Knowledge Discovery and Data Mining, pp. 94-99, 2010
[5] S. Jung, J. Hong, and T. Kim, “A formal model for user preference”, Proceedings of IEEE International
Conference on Data Mining, pp. 235-242, 2002
118 ISET 2014
3
New memory Translation Layer for Fast and Effective use of New
Memory as Storage
Hyun Sub Song, Young Je Moon, Tae Jin Kim, Sam H. Noh
Hongik University, Seoul, Republic of Korea
E-mail: [email protected], [email protected], [email protected],
[email protected]
Abstract
New memory that has characteristics of both DRAM and storage is opening a new storage era. This paper
proposes a New memory Translation Layer (NTL) as a technology to make effective use of new memory as
storage. With the addition of the NTL layer, conventional I/O is left to be served with disk-based file systems
providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte
addressability feature of new memory.
Keywords: New memory, File system, I/O, Storage
1. Introduction
Performance limitation due to the mechanical nature of HDDs (Hard Disk Drives) in conventional computing
systems has provoked the need for new storage media [1]. While flash memory is being accepted as a new and
effective supplement to HDDs, many in industry and academia are anticipating that new memory such as PCM,
RRAM, or STT-MRAM will also be excellent candidates as new storage media as they are non-volatile [2]. New
memory is byte-addressable and is expected to have access speed close to DRAM. This paper proposes a
software layer that we call NTL (New memory Translation Layer) that allows for high compatibility from the
users‟ perspective as it allows for existing file systems are used without modification, while providing high I/O
performance by providing a means to exploit the beneficial characteristics of new memory.
Previous research that considers using new memory as storage can be distinguished into two approaches. The
first approach is to provide a dedicated new memory aware file system [3, 4]. In particular, the file system is
developed to exploit the byte addressable characteristics of new memory. The downside of this approach is that
the time-tested traditional disk-based file systems have to be abandoned. The second approach is to simply
replace the storage media with new memory [5, 6]. This approach has a merit that the operating systems can
remain untouched. Unfortunately, this results in new memory being viewed only as a block device, not being able
to take advantage of the beneficial features of new memory, resulting in sub-maximum performance.
2. The New memory Translation Layer
This paper proposes the New memory Translation Layer (NTL) to provide compatibility, while at the same
time reaping the performance benefits of new memory. With NTL, minimum modification is done to the
operating system in order to provide compatibility. This allows conventional disk-oriented file systems such an
Ext4, Btrfs, ZFS, etc. to be used with new memory. Also, NTL allows a means to exploit the byte-addressable
feature of new memory to reap its best performance. This is done by bypassing the block software layer of the
operating system avoiding the overhead of converting byte unit data to block unit data, and vice versa.
1
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Figure 1. Conceptual architecture of NTL.
Figure 1 illustrates the system architecture of the NTL approach. Here the Upper Layer refers to a specific file
system. Service requests to the file system follow either of two tracks. The first track, „(1)‟, is simply the
conventional block-oriented software architecture track, while the other track, „(2)‟, is the new software
architecture track where NTL resides and dedicated for new memory. Note that NTL is not a file system but a file
system independent module that exists under a specific file system. This allows users to use traditional diskoriented file systems alongside NTL and new memory providing high compatibility to users. Also note that NTL
does not pass through the block translation and buffering layers as is done in conventional systems when data is
transferred to slow storage. Bypassing this overhead allows users to retain the potential high I/O performance
offered by new memory.
Acknowledgement
This work was financially supported by Semiconductor Industry Collaborative Project between Hongik
University and Samsung Electronics Co. Ltd.
References
[1] M. H. Kryder and C. Kim. “After Hard Drives—What Comes Next?” IEEE Transactions on Magnetics, 2009.
[2] R. F. Freitas and W. W. Wilcke. "Storage-class memory: The next storage system technology." IBM Journal
of Research and Development, 2008.
[3] J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee, “Better I/O through byteaddressable, persistent memory,” Proc. ACM Symposium Operating Systems Principles (SOSP), 2009.
[4] X. Wu and A. L. Reddy. “SCMFS: a file system for storage class memory,” Proc. ACM International
Conference for High Performance Computing, Networking, Storage and Analysis (SC11), 2011.
[5] A. M. Caulfield, A. De, J. Coburn, T. I. Mollov, R. K. Gupta, and S. Swanson, “Moneta: A HighPerformance Storage Array Architecture for Next-Generation, Non-volatile Memories,” Proc. IEEE/ACM
Symposium Microarchitecture (Micro), 2010.
[6] A. Akel, A. M. Caulfield, T. I. Mollov, R. K. Gupta, and S. Swanson, “Onyx: a prototype phase change
memory storage array,” Proc. USENIX Hot topics in Storage and File systems (HotStorage), 2011.
120 ISET 2014
2
The Merge Chaining Hashing Scheme with NAND Flash Memory
Woong-Kyu Park*, Sung-Chul Kim*, Gyu Sang Choi†
*
The Department of Information and Communication Engineering
Yeungnam University, Gyeongbuk, Republic of Korea
E-mail: {pwkyu, borame30}@ynu.ac.kr
†
The Department of Information and Communication Engineering
Yeungnam University, Gyeongbuk, Republic of Korea
Abstract
Hashing is a well-known data structure which efficiently retrieves information in large data set and is well
optimized in HDD, while NAND Flash memory is quite difference characteristics compared to HDD. In this
paper, we revisit the separate chaining hash scheme in NAND Flash memory, and propose the new chaining hash
scheme. We measured the completion times between the proposed and original schemes in Flash-based SSD and
the proposed scheme shows 4.46 times better performance at insert operation, 1.20 times better performance at
Search Operation, 4.92 times better performance at modify operation with maximize buffer efficiency.
Keywords: NAND Flash memory, SSD, Separate chaining, Hash scheme;
1. Introduction
NAND Flash memory is widely used in embedded systems, laptops and even server computers nowadays.
However, the characteristic of NAND Flash memory is quite different from HDD [1]. Hashing is a well-known
data structure which easily maintains large data set and efficiently searches the certain key in the data set [2].
Hash schemes are divided into tore categories: closed and open hashes. The directory is not increased while the
number of records increases in closed hashing. In contrast, the directory size increases as the number of keys
increases in open hashing. Separate chaining [3] is one of popular closed hash schemes, and can maintain
multiple buckets in each directory entry using linked list. The separate chaining is also well-optimized on HDD
and could be show poor performance in NAND Flash memory. In this paper, we evaluate the performance of the
separate chaining hash scheme in HDD and NAND Flash memory and propose the new chaining hash scheme in
NAND Flash memory.
2. Merge Chaining
A bucket size is exactly matched with a page size in NAND Flash Memory. It means that when one bucket is
read from or written to NAND Flash Memory, it needs to access only one NAND Flash page. In our proposed
merge chaining scheme, a bucket maintains records of several hashes in a bucket in order to maximize efficiency
of buffer. A bucket is fully occupied soon and will generate another bucket that Amount of read operations is
increased but Efficiency of buffer is significantly increased compare to separate chaining that Amount of NAND
Flash Memory operations is declined that Merge chaining shows better performance compare to Separate
chaining.
1
121
Figure 1. Merge chaining.
Figure 2. Total elapsed time of insert operation.
Figure 3. Total elapsed time of search operation.
Figure 4. Total elapsed time of modify operation.
3. Conclusions
In this paper, we proposed merge chaining hash scheme which maintains several hashes in a bucket. It show
better performance at insert operations and modify operations because efficiency of a bucket is much higher than
separate chaining that efficiency of buffer is significantly increased. Even in search operation Merge chaining can
show better performance in case there are enough buffer space.
References
[1]
[2]
[3]
[4]
[5]
Eran Gal and Sivan Toledo. Algorithms and data structures for flash memories. ACM Comput. Surv.,
37(2):138.163, 2005.
J. Clerk Maxwell, A New Dynamic Hash Index for Flash-Based Storage, Proceedings of The Ninth
International Conference on Web-Age Information Management. Oxford: Clarendon, 2008, pp.93–98
Fagin, Ronald, et al. "Extendible hashing—a fast access method for dynamic files." ACM Transactions on
Database Systems (TODS) 4.3 (1979): 315-344
Min-hee Yoo, Bo-kyeong Kim and Dong-Ho Lee, Hybrid hash index for NAND flash memory-based storage
systems, Proceedings of the 6th International Conference on Ubiquitous Information Management and
Communication, 2012, pp. 55:1-55:5
Samsung Electronics , ―Samsung SSD 840 PRO Series. datasheet,‖
http://www.samsung.com/us/pdf/memory-storage/840PRO_25_SATA_III_Spec.pdf.
122 ISET 2014
2
The GPGPU Virtualization Performance in Actual Network
Environment
Geun-yeong Bak*, ShinHyoung Lee†, Chuck Yoo†
*
Graduate School of Convergence IT
Korea University, Seoul, Republic of Korea
†
Collage of Information and Communication
E-mail: { shlee, hxy }@os.korea.ac.kr
Abstract
Due to development of GPU, GPGPU attempts to use the GPU device for high-performance computing rise.
When apply the GPGPU attempts to virtualization environment, the inter-VM communication is inevitable
because of nature of the GPU virtualization technology that the virtualized GPU can be used independently in
only one VM. The inter-VM communication is significant overhead in virtualizing GPU. In this paper, we
verified how the trade-off between improving performance achieved by GPU virtualization and the inevitable
inter-VM overhead presents, implementing the GPGPU network routing structure of the relevant research in the
actual network communication environment.
Keywords: Savanna, GPU, GPGPU, Xen.
1. Introduction
Thanks to support for floating-point operations and the technology-intensive development, GPU becomes not
only simple graphics processing unit but operational accelerating device. These changes in the GPU raise
attempts to use the GPU device for high-performance computing. GPGPU[1] is a collective term for these
attempts.
There are the tendencies to apply GPGPU system performance improvement to virtualized environments as
well as general environments, and GPGPU performance improvement in the virtualized system can be realized by
way of GPU virtualization. For GPU virtualization, the intel’s VT-d hardware virtualization technology [2]
emulates the GPU hardware to make VM (Virtual Machine) use the GPU device directly and exclusively.
Due to the nature of the VT-d technology that the virtualized GPU can be used independently in only one VM,
a number of inter-VM communication is inevitable for multiple VM to share the GPU. That’s because the virtual
machine with virtualized GPU (DomG) must process all of the GPU-required tasks instead of other virtual
machines without authorization to access the virtualized GPU (DomU). As a result of the method, sharing GPU
with multiple VM could add the inter-VM communication overhead, and this overhead could act as a variable in
deciding the system performance. Thus, if the GPU is used by multiple VMs, we should check the trade-off
between VM performance improvements and overhead of inter-VM communication well.
In this paper, we verified how the trade-off presents implementing the GPGPU network routing structure of the
relevant research in the actual network communication environment.
1
123
2. Relevant Researches
Implementing module that route virtual packets using virtualized GPU and return the results to client VM, the
paper [3] shows measuring result of a trade-off between improved performance with GPGPU in a virtualized
environment and inter-VM communication overhead: In the case that GPGPU handles the routing process, the
routing rate is six times faster than in the otherwise case, but overhead occurring in the process of data
transmission among VMs exceeds the amount of improved performance, so the overall performance declined
greatly.
The paper [4], the subsequent paper of [3], suggests a structure for reducing inter-VM communication
overhead (Savanna). With Savanna which was suggested in the paper [4], the whole time of GPGPU routing
process including inter-VM communication could become lower than the general routing time.
3. Experiment
In this paper, with experiments using the forwarding module attached to Savanna, we verified how the system
performance appears in the actual environment in which packets are transmitted among a network. The combined
module (Savanna + original packet forwarding module) was operated in the same system as the one used in the
paper [4], and the network communication environment is as follows.
First, the packets forwarding through the combined module had 13075000 pps (packet per second) rate when
size of one packet was 64byte, and 820000 pps rate when one packet size was 1500byte (the maximum pps the
packet sending node can pour to other nodes). All incoming packets received by the experiment module were
sent to one node, and we used receiving pps rate of the node in which all packets come as a measure.The packet
forwarding module used to experiments batched the 448 packets, the number of packets the GPU can treat at a
time in parallel.
To see how the savanna affects in the performance in the actual network communication environment, the
original packet forwarding module (origin. Module) and combined module were compared each other. The result
of the comparison is presented in Table 1.
Table 1. Experiment Results
Packet size
64byte packet
1500byte packet
Module
Origin. Module
Combined Module
Origin. Module
Combined Module
Send rate
13075000 pps
13075000 pps
820000 pps
820000 pps
Receive rate
4901809 pps
29702 pps
565603 pps
65631 pps
4. Conclusion
As shown in the experimental results, savanna structure application to a real network environment makes
significant performance degradation. Considering that the original forwarding module attached to Savanna is a
forwarding-only version, the degradation of performance seems to be significant. Then, there are needs to
analysis more detailed factors in the performance degradation and to design the ways to reduce degradation in
performance.
Acknowledgement
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea
government(MEST) (No.2010-0029180) with KREONET.
References
[1] GPGPU, http://en.wikipedia.org/wiki/General-purpose_computing_on_graphics_processing_units
[2] VT-d, https://software.intel.com/en-us/articles/intel-virtualization-technology-for-directed-io-vt-d-enhancingintel-platforms-for-efficient-virtualization-of-io-devices
[3] Yoo-kyung Uh, Chi-Young Lee, Chuck Yoo. 2013. "Communication Performance Evaluation in GPU
Virtualized Environments." Korea Computer Congress, 63-65.
[4] Yoo-kyung Uh, Chuck Yoo, 2014. “Savanna: Xen 기반의 최소 통신을 이용한 GPGPU 가상화 기법”.
Korea university master's thesis. http://www.riss.kr/link?id=T13383400
124 ISET 2014
2
A Research on Improving the Computational Overhead of SLAM
with SmartPhone
Cheol-Won Lee, Daeyoung Na, Heung-Seok Jeon
Konkuk University, Chungju, Republic of Korea
Abstract
This paper presents a new framework for enhancing the SLAM performance by utilizing idle resource of
smartphone. In the new framework, the smartphone computes SLAM process using the sensor data wirelessly
transferred from the robot and takes the results back to the robot. According to the our experimental results, the
limit of maximal robot speed for valid SLAM results has increased 0.036m/s to 0.058m/s .
Keywords: Robot, SLAM, Computational overhead, Smartphone
1. Introduction
Simultaneous Localization And Mapping(SLAM) is the process by which a mobile robot can build a map of
the environment and, at the same time, use this map to compute its location[1]. Many solutions for SLAM
problem have been developed such as EKF-SLAM[2], FastSLAM[3], DP-SLAM[4]. However, most of the
SLAM solutions are hard to be used in practical situation because of computational overhead. Therefore, in this
paper, we propose a new framework that could utilize the resource of idle smartphone. In the new framework, the
SLAM process is divided into three modules, One of the divided SLAM modules is computed in smartphone. As
a result, the new framework shows better SLAM results than when the robot only does.
2. A new framework for SLAM with smartphone and experiment
2.1. A new framework for SLAM with smartphone
In this paper, we propose a new framework for SLAM enhancement. For reducing the overhead of SLAM
computation in robot system with the help of smartphone, we divide existing SLAM solution into three modules
such as Sensing module, Making Task module and Navigation module. Sensing module collects environment
data from sensor. Making Task module calculates SLAM information(map, robot pose) on the basis of sensing
data. Navigation module makes path of the robot on calculated SLAM information. In addition to the existing
SLAM modules, we added State-check and Communication modules. State-check module checks state of
smartphone. And, Communication module sends sensing data to smartphone and receives SLAM information.
The new framework starts at Sensing module and flows by yellow arrows as shown in Figure 1.
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Figure 1. A new framework for SLAM with smartphone
2.2. Experiment
Table 1. The number of SLAM cycle
robot speed
(m/sec)
0.036
0.047
0.058
number of SLAM cycles
DP-SLAM
cycle
84
72
58
new framework
SLAM cycle
90
87
76
Figure 2. Result of DP-SLAM and a new
framework PMC(Robot speed 0.047, 0.058m/s)
Experiment environment for new framework evaluation is 13.8×3.9 meters polygon in a WiFi zone. The robot
with CPU Intel Pentium M processor 1.5 GHz, RAM 740MB and Laser sensor and the smartphone iPhone4S are
used for the experiments. For evaluating the quality of the maps generated by SLAM, we proposed a new idea,
which we called as PMC value. The PMC value represents the similarity between the map from SLAM and map
of the original real map. We used the DP-SLAM for this experiment.
Table 1 shows the number of SLAM cycles. The 0.036m/s case in robot speed, DP-SLAM calculated 84 cycles,
the new framework calculated 90 cycles. The new framework shows improvement about 16.3 percent in average.
Figure 2 shows the maps generated by the experiments. When robot speed is 0.047 m/s, the PMC value of DPSLAM is 83.1%. But the PMC value of the new framework is 88.6%. And the cases of 0.036m/s and 0.058m/s
also showed improved PMC value as 4.2% and 5.6%.
3. Conclusions
HIn this paper, we proposed a new framework for increasing the limit of robot speed to get valid result of SLAM
with the help of idle smartphone. From the experiments, we showed the new framework could extends the
maximal robot speed limit from 0.036m/s to 0.058m/s.
Extending the framework to platform of multiple smartphones is the future works.
References
[1] Hugh Durrant-Whyte and Tim Bailey, “Simultaneous Localization And Mapping: Part 2”, IEEE Robotics & Automation
Magazine, pp. 108-117, 2006.
[2] G. Dissanayake, P. Newman, H.F. Durrant-Whyte, S. Clark, and M. Csobra, “A Solution to the Simultaneous
Localization And Mapping (SLAM) Problem”, IEEE Transactions of Robotics and Automation, vol. 17, no. 3, pp. 229241, 2001.
[3] Montemerlo, M. and Thrun, S. and Koller, D. and Wegbreit, B, “FastSLAM: A Factored Solution to the Simultaneous
Localization and Mapping Problem”, AAAI National Conference on Artificial Intelligence, 2002.
[4] Austin Eliazar, Ronald Parr, “DP-SLAM: Fast, Robust Simultainous Localization and Mapping Without Predetermined
Landmarks”, International Joint Conferences on Artificial Intelligence, 2003.
126 ISET 2014
2
Real-time Schedulability Analysis for Hardware Supported Virtual
Machine on ARM Cortex-A15 Processor
Tae Kyoung Kim*, Se Won Kim†, Chuck Yoo†
*
Department of Convergence Software
†
Department of Computer Science and Engineering
E-mail: {swkim, hxy}@os.korea.ac.kr
Abstract
The researches applying virtualization techniques to mobile environment have been studied. Previous mobile
virtualization researches needed to modify its guest OSes. Newly published processor, ARM Cortex-A15,
provides hardware support for a virtualization (HVM) and it is no more necessary to modify the guest OSes.
Thus, we investigated real-time schedulability and bottleneck of performance for the virtualized mobile system
with this processor. In our performance analysis, we found that hardware supported virtual machine was hard to
guarantee the real-time support and the bottleneck of performance was guest OS, not the hypervisor.
Keywords: Mobile virtualization, Hardware supported virtual machine, Real-time support.
1. Introduction
The technology of virtualization has been developed through decades, and recently, this techniques flow into
the mobile environment. Applying virtualization techniques to mobile derives benefits as following: providing
multiple OSes[1] and security through isolation[2]. The researches to accommodate virtualization into mobile
have been studied. The one of the main obstacles of mobile virtualization is real-time support. In [3], the author
suggested ‘SH-quantization’ algorithm to support real-time scheduling in Xen-ARM virtual machine.
Nevertheless, previous researches have limitation that their guest OSes need to be modified called as Paravirtualization. Newly published processor, ARM Cortex-A15, provides hardware support for a virtualization.
Therefore, in this paper, we show whether virtualization with this processor guarantees real-time support, and
investigate the bottleneck of performance in the virtualized mobile system through the performance analysis.
2. Implementation
The hardware platform we used in our experiments was Arndale Board which applied ARM Cortex-A15
processor. The board had an Exynos 5250 CPU with 1.7GHz core frequency, dual cores, and 2GB memory size.
For software platforms, we used Xen 4.4(arch/arm) as a hypervisor and linux kernel 3.9 as the Domain0 and
DomainU guest OSes. The memory size of the Domain0 was 256MB as a default and 128MB for the DomainU.
Scheduling policy for Xen, we followed the default policy, credit scheduling, and for Domains we followed
default linux scheduler.
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3. Performance analysis
To determine whether real-time schedulability was guaranteed in HVM, we did performance analysis in two
different perspectives. First, we used benchmark, called ‘Cyclictest’, to confirm the deadline of the interrupt
handling was guaranteed. The table 1 shows result of benchmark executing. The interrupts were occurred by
POSIX interval timer with 10ms interval and 10000 loops. This result showed that the deadline of XenARM(HVM) could not guaranteed because of its maximum latency value, about 7ms, instead the native linux
system satisfied deadline within maximum value of 0.4ms. In real-time schedulability perspective, it is more
significant that finishing tasks within deadline than lower average latency.
Table 1. Interrupt latency on the native linux and the virtualized system.
Target
Native Linux
Xen-ARM(HVM) - Domain0
Min
12
20
Interrupt latency (us)
Max
482
7187
Avg
83
167
The other performance analysis was that calculating interrupt handling time to define where the bottleneck of
performance was in virtualized mobile system. It was measured section by section using a performance
monitoring unit (PMU). Figure 1 illustrates the measurement boundary of interrupt handling either the native
linux and Xen-ARM(HVM). In the native linux system, we counted the CPU cycles from vector table to
__irq_svc(), and calculated the execution time by dividing cycle by CPU clock speed (actual survey clock speed
was 1GHz). The average interrupt handling time of the native linux was 17us. On the other hand, in case of XenARM(HVM), there was the hypervisor vector table that determined which domain should be delivered the
interrupt. Therefore, there was one more stage than the native linux’s case. The average time of interrupt
handling in the hypervisor only took 0.25us, but in domain0 kernel it took 24.78us until the interrupt handling
was finished.
Figure 1. Measurement boundary of interrupt handling with PMU.
4. Conclusions
The performance experiments we had done in section 3 indicated two essential phenomena. First, the XenARM hypervisor with hardware support is hard to guarantee a real-time schedulability because of its maximum
interrupt latency. The other feature is that the bottleneck of performance during the interrupt handling comes out
Domain0 not the hypervisor. In the future, we will demonstrate cause of overhead in the Domain0, and will
measure performance in DomainU with a real-time operating system such as a uC/OS-II.
Acknowledgement
References
[1] Heiser, Gernot. "Hypervisors for consumer electronics." Consumer Communications and Networking
Conference, 2009.
[2] Brakensiek, Jörg, et al. "Virtualization as an enabler for security in mobile devices." Proceedings of the 1st
workshop on Isolation and integration in embedded systems. ACM, 2008.
[3] Yoo, Seehwan, and Chuck Yoo. "Real-time Scheduling for Xen-ARM Virtual Machines." IEEE Transactions
on Mobile Computing, 2013
128 ISET 2014
2
Software based Virtual Router Platform as a Super-peer
in Software-Defined Network
Dae-Myeong Kang, Shin-Hyoung Lee, Sung-Won Ahn, Chuck Yoo
College of Information and Communications
E-mail: {dmkang, shlee, swahn, hxy}@os.korea.ac.kr
Abstract
SDN is a future-oriented network for efficient network management, which decouples the control plane and the
data plane. A typical example is OpenFlow. OpenFlow is a standard protocol that operates between the controller
and switches, which is a new method for controlling flows in a network. But, OpenFlow has a big challenge about
some overheads between the controller and switches. In this paper, we discuss the challenge of OpenFlow based
on the overheads between the controller and switches. We also show that software based virtual router platform
that named XEBRA can address this challenge.
Keywords: Xen Hypervisor, OpenFlow, SDN, Super-Peers
1. Introduction
SDN(Software-Defined Network) is a new approach to designing, building and managing networks. The basic
concept is that SDN separates the network’s control as Control Plane and forwarding as Data Plane to make it
easier to optimize each. A typical example is OpenFlow[1]. OpenFlow is a standard protocol that operates
between the controller and switches, which is a new method for controlling flows in a network. OpenFlow defines
a standard for sending flow rules to network devices so the control plane can add them to the forwarding table for
the data plane. OpenFlow is one of the most suitable methods for implementing SDN, but there is still a challenge
like reducing the centralized overheads. SDN controller performs all of control plane functions, including
running the control plane protocols that connect with the outside world[2]. When the OpenFlow switch receives
unknown packets in the flow table, the switch requests the policy for the packet from the controller via OpenFlow
control message using TCP/IP Communication. If massive packets arrive because of the requirements of a Cloud
service, the switch frequently contacts the controller to request the policies for each packet so there are major
overheads for the controller and the network[3]. Our software based virtual router platform that named
XEBRA(Xen hypervisor based Router Architecture)[4][5] can support these challenges as a new hybrid switch
and controller with OpenFlow standard and IP routing, or even by using other protocols simultaneously. In this
paper, we discuss the challenges of OpenFlow based on the overheads between the controller and switches. We
also show that XEBRA can address these challenges.
2. XEBRA with SDN Architecture
The positions of the XEBRA platform in the SDN are represented as a switch or as a controller with a gateway.
The XEBRA is open source so it can provide flexibility and portability. Figure 1 shows the XEBRA gateway
with multiple controllers. We implemented a Floodlight[6] controller, which is a well-known OpenFlow
controller in the XEBRA platform. In addition, the XEBRA platform can support any type of controller. The
XEBRA platform also has a virtual router to operate generic routing protocol.
The XEBRA platform can act as super-peers in a large-scale network, as shown in Figure 1. Centralized
control is definitely a big advantage of SDN in terms of virtual network manageability. However, a distributed
system has better performance than a centralized system. The reason why the IP protocol used by routers has
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been employed for the past 30 years on the global Internet and this routing process works on distributed nodes[3].
Therefore, it is necessary to reduce the overheads.
The super-peer architecture can counteract the deficiencies of centralized system. In Figure 1, the XEBRA
platforms are super-peers, which represent SDNs. The SDN controllers that is shown at the top of the figure
control these super-peers. The super-peers have a flow table for each SDN. When a controller orders a network
policy from the super-peers, the super-peers have the policy and they execute their roles during flow switches. A
super-peer manages its own switches. In this architecture, the switches send requests to the XEBRA platform as a
super-peer to process unknown packets. This method can reduce the communication overheads. This effect will
increase if the network becomes too large. The super-peer architecture is also beneficial for managing large-scale
SDNs.
Figure 1. SDN implementation with XEBRA platform as super-peers
3. Conclusions
This paper presented XEBRA with the SDN Architecture for solving the well-known challenge of SDN such
as overhead for processing new arrived packets in large-scale SDNs. To show that, we implemented well-known
SDN switch and controller in XEBRA. We also introduced the XEBRA platform as a super-peer in large-scale
SDNs and explained that the architecture is beneficial for managing large-scale SDNs.
Acknowledgement
References
[1] McKeown, Nick, et al. "OpenFlow: enabling innovation in campus networks, "ACM SIGCOMM Computer
Communication Review 38.2 (2008): 69-74.
[2] Openflow/sdn is not a silver bullet for network scalability, http://highscalability.com/blog/2012/6/4/
openflowsdn-is-not-a-silverbullet-for-network-scalability.html, 2011. 79, 80
[3] J.H. Yoo. Et al. A technical trend and prospect of software defined network and openflow. KNOM Review, 15. 80,
84
[4] The Xen Project, http://www.xenproject.org
[5] Shin-Hyoung Lee, et al. “Network Virtualization Techniques for Future Internet” Telecommunications
Review 21.3 (2010): 413-424.
[6] Floodlight, http://www.projectfloodlight.org/floodlight/
130 ISET 2014
2
Explore "Decrease-All-By-One" on DDoS packet Filtering using
Counting Bloom Filter
Suk-Young Oh, Shin-Hyung Lee, Chuck Yoo
College o f Information and Communication, Korea University, Seoul, Republic of Korea
E-mail: {syoh, shlee, chuckyoo }@os.korea.ac.kr
Abstract
This paper explores a method which can improve bot IP detection rate and reduce false positive rate in DDoS
attack packet filtering using counting Bloom filter. False positive occurs due to inherent characteristic of Bloom
filter. We examine a technique, "decrease-all-by-one", that can improve bot detection performance without false
positive rate increase and we prove a optimized condition in which "decrease-all-by-one" operation should be
performed through simulation experiments.
Keywords: DDoS, Counting Bloom Filter, Packet Filtering, False Positive.
1. Introduction
There have been many DDoS attack packet filtering method using a traditional counting Bloom filter(CBF)[1].
the most widely known problem that Bloom filter(BF) inherently has is a presence of false positive(FP). In the
view of DDoS security, FP means a fault in which a packet sent from normal user is determined as bot packet.
Ji Hun Ha el al. [2] present a "decrease-all-by-one" technique which can reduce FP rate. It decreases all field
of Bloom filter array by 1 at a specific condition in which the probability of FP occurrence become increased.
they defined the pre-mentioned condition depend on the following mathematical formula.
In this formula, k is the number of hash functions, m is BF array size and n is the number of inserted packets.
they explain that if the non-zero portion exceeds the 50%(1/2) of the total BF array, the probability of FP become
increased over 50%. It, however, is difficult for this premise to be applied into CBF because the non-zero portion
doesn't directly affect FP rate in CBF. In fact, a factor affecting FP rate in CBF is the ratio of fields counted up to
a count threshold.
In this paper, we experiment on the specific point of time when "decrease-all-by-one" is performed in DDoS
attack packet filtering using CBF. After experiments, we analyze a result data so that we estimate a optimized
condition.
2. Simulation "Decrease-All-By-One".
We assume a fixed DDoS attack situation for the experiment on bot IP detection performance and FP. Each
randomly generated 100,000 bot source IP and 2M normal source IP are added into CBF at 100pps rate and
2000pps rate individually. The size of BF array is 32768byte and the count threshold of each field of array is four.
In addition, four hash functions are used. A IP address is hashed by 4 hash functions, each result value from hash
functions passes an modulo 32768B operation so that the count values of field of index corresponding with the
result value are increased by one. If count values of four corresponding fields exceed threshold(we use 4), the
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packet is determined as attacking packet.
we examine results following each condition performing "decrease-all-by-one" operation (non-zero portion of
total array is 10%, 20%, 30%, ..., 90% ratio). This experiment is performed 10 times with randomly differently
generated IP address set while 10000ms. Finally, the average value of ten results is used to analyze these
experiments.
Figure 1. the performance of bot detection
Figure 2. the ratio of false positive per 1 bot
detection
In case of 10%, 20%, 30% "decrease-all-by-one", the CBF cannot catch any bot IP. This is because "decreaseall-by-one" is too frequently performed to detect bot IP in which most of the field in CBF cannot reach minimum
threshold(we use 4). So, we only examine result from 40% to 90%.
In the Figure 1, in case of performing "decrease-all-by-one" when non-zero portions of total array are 90%
and 80%(both are being shown overlapped in Fig. 1), the Bot detection performance is noticeably better than
others.
The Figure 2. shows the ratio of FP per one bot IP detection in each "decrease-all-by-one" experiment. we
focus on a difference between 90% and 80%. In the Fig. 1, Both 80% and 90% have shown almost same
performance. In case of condition that non-zero portion of total array is 80%, FP rate is dramatically more
reduced than any other experiments. We conclude that in this pre-assumed situation(array size is 32768B, and the
number of bot IP and normal IP, etc.), rather than a fixed "decrease-all-by-one" operation as 50%(1/2),
performing "decrease-all-by-one" under the condition that non-zero portions of total array is 80% is more
optimistic. Therefore we can choose 0.8(80%) enable to obtain higher performance and low FP.
3. Conclusions
we think that a"decrease-all-by-one" operation is critical method to accomplish high bot IP detect performance
and low FP rate. However, if a "decrease-all-by-one" operation occur much frequently, CBF cannot have a
enough bot information so that cannot distinguish bot IP among surged traffics. On the other hand, if a "decreaseall-by-one" operation occur too slowly, normal packets cannot pass through CBF(false positive). we prove that
there exists a appropriate condition to improve a "decrease-all-by-one" operation. In the future work, we will find
a normalized mathematical formula with variety variable in real network system for DDoS attack filtering using
the CBF.
Acknowledgement
References
[1] L. Fan, , P. Cao, J. Almeida, and A. Z. Broder. “Summary cache: a scalable wide-area web cache sharing protocol”. IEEE
Trans on Networking, 8(3), 281–293, 2000.
[2] Ji Hun Ha, Hyo Gon Kim, "Identifying and Blocking Botnet-based DDoS Attacks Using Counting Bloom Filter". The
Korean Institute of Communications and Information Sciences, 2012.
132 ISET 2014
2
Design of a Route Guidance System for the Visually Impaired
Hyunho Yoo*, Byung-Jae Choi*, Jong-Hwan Song †
*
Department of Electronic Engineering
Daegu University, Gyeongbuk, Republic of Korea
†
Mine Corporation
Beomeo-dong Suseong-gu Daegu, Republic of Korea
Abstract
Nowadays, many assistive devices for the visually impaired have been studied. In this paper, we propose a
few devices that help route guidance for a visually impaired person. It is composed of a smart phone, cane, and
hands-free device. The smart phone helps a route guidance. The cane detects an obstacle and transmits it to the
hands-free device. The hands-free device communicates with a visually impaired person. We here present their
architecture, signal flow, and configuration.
Keywords: Visually impaired person, White cane, Hands-free device, Route guidance system.
1. Introduction
During walking to the destination, the visually impaired person has many difficulties and is exposed to the
dangerous situations. Even many studies and systems have been made to eliminate them. However, the visually
impaired person still feels difficult. They also think that commercial products are concentrated in ICT
convergence without considerations for the visually impaired person.
In this paper we propose a route guidance system for a visually impaired person. It is composed of a smart
phone with a navigation application, cane, and hands-free device. It assists a route guidance and obstacle
avoidance as a subsidiary walking device for the visually impaired. In order to implement this whole system, this
is divided into three parts. The first part is a stick functioned obstacle recognition and it is a kind of white cane.
The second part is the smart phone implemented a navigation application. The last is the hands-free part that
communicates among a smart phone with navigation system, stick, and the user.
2. Design of Subsidiary Walking Device for the Visually Impaired
The overall system is composed of three parts. The design of walking stick part consists of a few switches for
operating each function, ultrasonic sensors for obstacle detection (MB1220), SoC(CC2540) with integrated
Bluetooth function, vibration motor for judgment the obstacle presence/absence and others. As the major
components for this system, the CC2540 processor which is SoC chip based on 8051 Core for Bluetooth 4.0
configuration is used for the low-power design because of low-power process with 2~3.6[V] operation power
supplies.
The hands-free part consists of SoC(CC2540) such as the design of walking stick, Micro SD card stored MP3
sound source data, Cortex M3 (STM32F103), codec chip (VS1003B) and others. This is designed to transmit the
audio information by itself as voice processing. MP3 sound data is stored into the Micro SD card. The
STM32F103 chip that is embedded by Cotex-M3 core plays MP3 files using VS1003B codec chip.
The GPS sensor, gyro sensor and other diverse sensors are embedded in smart phones. These sensors make
possible to implement a navigation algorithm in the smart phone. We realize the route guidance system using the
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navigation app. program in the existing smart phone.
For the development of a subsidiary walking device for the visually impaired person, one of the system
operation diagrams is shown in Figure 1.
Figure 1. Signal flow diagram of the cane part.
3. Conclusions
We proposed a subsidiary walking assist device that supports safe walking of the visually impaired. It was
composed of a smart phone based navigation system, hands-free system, and a smart cane of environment
recognition. These were linked to each other for supporting a safe walking of the visually impaired. This may
lead to a significant contribution to ensuring the rights movement of the visually impaired.
134 ISET 2014
2
References
[1] J. H. Bang and B. J. Choi, "Development of Smart Phone based White Cane for Visually Impaired Persons,"
IEMEK, 2013.
[2] I. H. Kim, J. U. Cha, C. H. Kim and Y. J. Gwon "A Study on a Destination Guide Cane for Visual
Disturbance Person," Korea Multimedia Society, no.78, pp.317-320, 2008.
[3] S.Y. Kim, et. al. “Electronic Cane for Visually Impaired Persons: Empirical Examination of Its Usability and
Effectiveness,” Lecture Note in Electrical Eng., vol.182, 2012.
[4] Y. Wei, X. Kou, and M. Lee “Development of a Guide-dog Robot System for the Visually Impaired by
Using Fuzzy Logic Based Human-robot Interaction Approach ,” ICCAS 2013, no.10, 2013.
3
135
Barriers to Real-Time Network I/O Virtualization: Observations on a
Legacy Hypervisor
Sang-Hun Lee, Jong-Soo Seok, Hyun-Wook Jin
Department of Computer Science and Engineering, Konkuk University
Seoul, Republic of Korea
E-mail: {mir1004,bluz, jinh}@konkuk.ac.kr
Abstract
Virtualization is considered as one of promising technologies to provide an efficient run-time environment for
real-time embedded systems with respect to easy consolidation and safety. However, there are still several issues
have to be addressed for real-time network I/O virtualization. In this paper, we briefly discuss about the clock
synchronization, the jitter of I/O latency, and the tradeoff between latency and bandwidth.
Keywords: Real-Time, Virtualization, Network I/O, VirtualBox.
1. Introduction
As the complexity of real-time embedded software increases drastically, providing an efficient run-time
environment especially in terms of consolidation and safety is becoming more important. The virtualization
technology is considered as an authentic solution to provide an isolated run-time environment for real-time
applications. Thus, there have been several researches to extend existing hypervisors to consider real-time
constraints [1-2]. However, due to the high overheads of legacy hypervisors, it is not easy to exploit widely
these on various embedded systems. To overcome such limitations, lightweight hypervisors originally targeting
embedded systems are recently introduced [3-4]. However, we believe that there are still several additional
issues have to be addressed to provide a “real” real-time network I/O virtualization. In this paper, we try to
briefly discuss some of those issues.
2. Observations on a Legacy Hypervisor
There should be many design issues for real-time hypervisor in terms of network I/O, but in this paper, we
selectively discuss three issues: i) clock synchronization, ii) jitter of I/O latency and iii) tradeoff between latency
and bandwidth. Our discussions are based on observations with VirtualBox [5], an open-source type-II full
virtualization hypervisor.
Clock Synchronization: In real-time embedded systems, the clock synchronization between guest domains is
highly desirable for various application domains [6]. However, it is very tricky in virtualized environments
because the hypervisor provides a virtual timer to the guest domain and keeps adjusting it based on the real (i.e.,
physical) timer. For example, VirtualBox inspects the virtual timer every 10 seconds and tries to adjust it
gradually by changing the speed of the timer. That is, the virtual timer is basically not accurate, and its speed
keeps changing. Such inaccuracy results in discrepancy between virtual timers in different guest domains. In
order to mitigate the inaccuracy, we apply IEEE 1588, a time synchronization protocol, to guest domains running
on the same node and measure its performance. Figure 1(a) shows the time differences between two guest
domains, but the results still show the time difference larger than 100ms even with IEEE 1588.
136 ISET 2014
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Jitter of I/O Latency: The hypervisor (or back-end driver) handles many kinds of I/O events generated by the
guest domains. The I/O event handling is hardly parallelized until these events are finally passed to the physical
I/O devices. This increases I/O overheads but also induces significant jitters of I/O latency. For example, Figure
1(b) shows cumulative probability of virtualized Controller Area Network (CAN) I/O latency [7]. As we can see,
the virtualized CAN has a very high jitter. The VirtualBox creates various threads for each virtual machine to
handle different classes of I/O events. These threads compete against each other for processor resources and
dominantly cause the jitter of I/O latency.
Tradeoff between Latency and Bandwidth: Real-time networks, such as Audio Video Bridging (AVB) [8],
estimates the worst case latency between two end nodes, which is utilized importantly in providing QoS.
However, the worst case latency can be under or over estimated in virtualized environments because of the I/O
buffering of hypervisor. For example, the virtio [9] implemented in VirtualBox checks transmission requests of
guest domains every 250us. Thus, in the worst case, a message of a guest domain can be delayed up to 250us.
Figure 1(c) shows the increased latency due to the I/O buffering. However, we cannot blindly remove the
buffering for low latency because this degrades the network bandwidth.
3. Conclusion
In this paper, we have briefly observed three issues; clock synchronization, jitter of I/O latency and
tradeoff between latency and bandwidth. As on-going work, we are trying to overcome these issues.
Figure 1. (a) Time difference between guest domains, (b) Cumulative probability of CAN latency, (c) Impact of
buffering on TCP/IP latency
4. Acknowledgement
This work was supported by the Dual Use Technology Program (UM13018RD1).
References
[1] Han, S. and Jin, H.-W., Resource Partitioning for Integrated Modular Avionics: Comparative Study of
Implementation Alternatives. Software: Practice and Experience, DOI: 10.1002/spe.2210, 2013.
[2] Xi, S., Wilson, J., Lu, C. and Gill, C.D., RT-Xen: Towards Real-time Hypervisor Scheduling in Xen. In Proc.
of EMSOFT'11, 2011.
[3] XtratuM, http://www.xtratum.org/.
[4] Hypervisor for ARMv7 Virtualization Extensions, https://github.com/kesl/khypervisor.
[5] VirtualBox, https://www.virtualbox.org/
[6] Lee, S.-H., Jin, H.-W. and Kim, K., A Simulation Tool for Optimal Phasing of Nodes Distributed over
Industrial Real-Time Networks. In Proc. of WATERS, 2013
[7] Kim, J.-S., Lee, S.-H. and Jin, H.-W., Fieldbus Virtualization for Integrated Modular Avionics. In Proc. of
ETFA, 2011.
[8] IEEE 802.1 TG. The Audio/Video Bridging Task Group. http://ieee802.org/1/pages/avbridges.html.
2
137
A Power Replay Attack in Electronic Door Locks
Seongyeol Oh, Joon-sung Yang, Andrea Bianchi, Hyoungshick Kim
College of Information and Communication Engineering
Sungkyunkwan University, Gyeonggi, Republic of Korea
E-mail: {seongyeol, js.yang, abianchi, hyoung}@skku.edu
Abstract
Electronic door locks should be designed to prevent various attacks on the locks themselves for their original purpose.
However, manufacturers have only focused on one particular type of adversary – a stranger who tries to open doors from
outside – but ignores an insider attacker with temporal access to the inside of a lock. We found that the most popular
electronic door locks are vulnerable to the insider attacker. A malicious hardware component can be covertly inserted in an
electronic door lock to implement a hidden backdoor for an unauthorized use of the lock. Attackers can replay a valid DC
voltage pulse to open the door since the door lock solenoid can be controlled with a DC voltage alone.
Keywords: Electronic door lock, Power replay attack, Backdoor
1. Introduction
Electronic door locks have recently become popular since they have many benefits compared with traditional
mechanical locks. For example, in the case of keyless locks which are the most popular types of electronic door
locks, a physical key is not needed anymore. They might also be invulnerable to the existing physical attacks
against mechanical door locks [1]. Despite these known benefits of electronic door locks, we question whether
electronic door locks are really secure enough against any possible intrusion and alterations. Manufacturers often
claim that their electronic door locks are secure and against a wide range of attacks despite the fact that several
flaws have been recently discovered (e.g, [2] and [3]), but the current focus was only directed to one particular
type of adversary attacks by a stranger who tries to open doors from outside - ignoring an insider attacker with
temporal access to the inside of a lock. However, the second type of adversary models can also be found in many
real life scenarios. For example, a thief who sojourns in a hotel room protected by an electronic door, obtains
complete physical access for a prolonged period of time to the electronic door lock. Hence, the thief would have
plenty of time to modify some parts of the lock in the room or implement a hidden backdoor switch that could be
used to steal the belongings of future guests who will stay later in the same hotel room. We found that the most
popular and commercially endorsed electronic door locks cannot cope with this type of threats. An insider
attacker can covertly insert malicious hardware components into an electronic door lock to replay a valid DC
voltage pulse to illegally open the door. We name this attack the “Power Replay'' attack since the inserted
component replays a power supplement irrespective of the central processing unit in the target door lock. Our
experiments with the four electronic door locks showed the feasibility of power replay attacks: all door locks that
we investigated were vulnerable to power replay attacks.
2. Power Replay Attack
We experimentally investigated the possibility of power replay attacks with the four most popular electronic
door locks made by Gateman, Samsung, Mille and Hyegang, which account for over 65% of the total Korea
market share in 2013. These electronic door locks follow a common architecture. An electronic door lock
consists of three functional units: a keypad for the user input, a central processing unit which detects the input
and denies or grants authentication, an actuator (a solenoid) which is used to open or close the lock, and batteries
for power supply.
All electronic door locks that we observed use the same procedure to open the lock. When a user provides
valid credential (e.g., PIN), the credential information is transformed to a coded signal at the keypad part and
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then the coded signal is delivered to a central processing unit that controls a solenoid to actuate the lock by
supplying a positive (or negative) DC voltage. Here there are two communication channels that attackers might
be interested in: (1) the data channel between keypad and central processing unit for coded signal transfers and
(2) the power line between central processing unit and solenoid for the delivery of DC voltages.
Figure 1. The overview of power replay attacks: Dotted lines represent a malicious operation by attacker while
solid lines represent a normal operation of door lock.
Although these communication channels are not physically exposed to the outside of an electronic door lock
device, we found that the communication channels do not remain protected in the inside of the lock device. Thus
an insider attacker who has accessed to the inside of a lock can intercept, might manipulate, fabricate, or interrupt
the transmitted data and/or power over these channels. In this paper, we have focused on replay attacks for the
power line, which is a simple but powerful attack to which most electronic door locks are susceptible.
Figure 1 shows the overview of a power replay attack. The core idea is to insert some malicious hardware
components inside the door lock (a backdoor) which can remotely supply voltage to the lock actuator and
therefore control the lock itself. The backdoor circuit is installed as a spurious parallel circuit to the original
circuit, which does not substitute but choosiest with the original. From the user perspective, no changes of the
hardware can be noticed during the regular usage of the device. However, if an attacker sends a triggering
message through a communication module, then the backdoor supplies an adequate voltage to the solenoid
resulting in a door open or close from the outside. We implemented a power replay attack with Arduino and
Bluetooth module. An Arduino provides voltage to solenoid when receives triggering message via Bluetooth.
3. Conclusion and Future work
We found that the current electronic door locks are susceptible to a hardware backdoor by insiders with
temporal access to the inside of a lock. We implemented a prototype to show the feasibility of such attacks - the
prototype can be covertly inserted to the electronic door lock without any modification in the appearance or in
the standard functionalities. We also focus on logging PIN information between keypad and central processing
unit as a future work.
References
[1] Matt Blaze. Cryptology and Physical Security : Rights Amplification in Master-Keyed Mechanical Locks. In
IEEE Security and Privacy, April 2003
[2] Cody Brocious. My arduino can beat up your hotel room lock. In Black Hat USA 2012, July 2012
[3] Andy Greenberg. Hotel Lock Hack Still Being Used In Burglaries, Months After Lock Firm’s Fix. In Forbes,
Available: http://www.forbes.com/sites/andygreenberg/2013/05/15/hotel-lock-hack-still-being-used-in-burglariesmonths-after-lock-firms-fix/,[Last accessed: 15 August 2013], May 2013
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User-level Memory Performance on a big.Little ARM Processor
Beomhee Lee, Jibum Kim, Moonju Park
School of Computer Science and Engineering
Incheon National University, Incheon, Republic of Korea
E-mail: [email protected], {jibumkim,mpark}@incheon.ac.kr
Abstract
Balancing power consumption and performance is an important issue in embedded systems. To this end, ARM
developed a new architecture called a big.Little architecture. In this paper, we measured user-level memory
performance on the big.Little architecture and analyzed the energy efficiency. The energy efficiency is closely
related to the clock frequency of the memory and the parallelism in the program.
Keywords: big.Little, Memory performance, Energy efficiency
1. Introduction
Multicore processors are employed for many high-performance embedded systems such as smartphones and
tablets. Parallel processing on a multicore processor is able to improve performance, but more power is required
for increased number of processing units. Various kinds of low power processors have been introduced, since it
is important to balance the performance and the energy consumption for embedded systems with limited power
sources like battery. Recently, ARM developed the big.Little architecture [1], which combines high performance
cores and low power cores. The big.Little processing technique provides a way to trade-off between performance
and power consumption [2, 3]. However, standard techniques for efficient use of the new architecture have not
been established yet.
In this paper, we focus on a user-level memory I/O performance on an embedded system with the big.Little
multicore processor. Memory I/O has been considered as a main performance bottleneck on multi-processor
systems. Thus, optimizing memory performance is an important issue in designing and implementing an
application, especially when we are using a processor based on newly developed architecture. By running a
memory benchmark, we found that the energy efficiency of big.Little processing is closely related with the clock
frequency of the main memory, and affected more by the parallelism in the program than the CPU frequency.
This paper is organized as follows. Section 2 describes experimental environments such as the embedded
board and the processor used in this paper. The experimental results are presented in Section 3 and analysed.
Finally, Section 4 concludes our work.
2. Experimental Environments
Hardkernel’s Odroid-XU embedded board [4] was used for our experiments. The processor is Samsung
Exynos5410, which has 4 ARM Cortex-A15 cores and 4 ARM Cortex-A7 cores. Cortex-A15 cores are used as
high-performance (big) cores and Cortex-A7 cores are low-power (Little) cores. It has 32/32 KB I/D cache and 2
MB L2 cache. The target board has 2 GB LPDDR3 DRAM with 800 MHz clock frequency. A 16 GB micro
SDHC memory is used as a persistent storage. Ubuntu 3.3.84 is used for the operating system.
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The processor supports a DVFS (Dynamic Voltage and Frequency Scaling) technique, with which we can
change the operating frequency from 0.25 GHz to 1.6 GHz. But the processor does not allow us to use all 8 cores
simultaneously; instead, by adjusting the operating frequency (which can be done by the operating system
interface), we can switch between big and Little cores. If we set the operating frequency lower than or equal to
0.6 GHz, Little cores are activated while big cores are off. On the other hand, if we set the operating systems
higher than or equal to 0.8 GHz, big cores are made online while Little cores go off. Migration of processes
between cores is automatically done by the dedicated hardware in the processor. So the operating system sees
only 4 processors at maximum, and do not know whether these are the same cores or not.
For measuring the user-level memory performance, a memory-intensive benchmark, RAMspeed/SMP [5], is
used. In our experiments, memory operations (copy, addition, multiplication, and multiplication with addition)
are performed on 1 GB memory for each operation type, with a 32 MB buffer. We have measured performance
for 1, 2, and 4 threads. Each thread is pinned to one core and utilizes it 100%.
3. Experimental Results
Figure 1 shows the average memory performance measured in MB/s for each CPU frequency. Note that under
0.7 GHz, only Little cores are activated. Big cores are activated when the frequency is over 0.7 GHz. As shown
in Figure 1, there are drastic performance changes between Little and big cores. It is interesting to note that the
clock frequency of the DRAM is 0.8 GHz. When the CPU clock is slower than the DRAM clock, the processor
could not use all the bandwidth the DRAM supports. We also observe that the performance gain from parallel
execution (up to 3.36 times with 4 threads) is greater than the gain from the CPU frequency increase (up to 1.45
times).
Figure 1. Average memory performance on big.Little architecture
For big cores, increasing threads also gives more performance gain than increasing the processor speed, but
the gain is smaller comparing to Little cores. Memory performance goes up to 1.82 times with 4 threads than 1
thread. On the other hand, performance improves with increased speed up to 1.52 times with single thread and up
to 1.23 times with multiple threads on big cores.
To see the energy efficiency during memory operations, we measure the power consumption during the
benchmark tests. The target board supports monitoring of power consumption for the entire board. By combining
the power consumption data with benchmark results, we calculated the energy efficiency of the user-level
operations as processed data per energy (Mb/J). Figure 2 shows the experimental results.
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Figure 2. Energy efficiency of memory I/O
As shown in Figure 2, the maximum energy efficiency is at 0.9 GHz with 4 threads (996.7 Mb/J), which is
slightly higher than the memory clock frequency. With 2 threads, the highest energy efficiency is obtained with
1.1 GHz (977.7 Mb/J), because DRAM bandwidth is not fully utilized yet. Little cores are expected to be used
with low power consumption. However, we observe that Little cores are not energy efficient, if their clock speed
is not fast enough to utilize the memory bandwidth.
4. Conclusion
In this paper, we investigated both the memory performance and the energy efficiency of user-level processes
on the big.Little processor. We observed that both the memory performance and the energy efficiency are lower
than expected, when Little processor’s clock speed is not fast enough to exploit the memory’s bandwidth. Our
experiments show that when Little cores are used, increasing parallelism results in better memory performance
and energy efficiency than increasing the CPU frequency. We also observed that for memory intensive
applications, energy efficiency is closely related with the memory clock speed.
Acknowledgement
This work was supported by the Industrial Convergence Source Technology Development Program (NO.
10041332) through the Ministry of Science, ICT and Future Planning, Korea.
References
[1] Peter Greenhalgh, “big.LITTLE Processing with ARM Cortex-A15 & Cortex-A7(Improving Energy
Efficiency in High-Performance Mobile Platforms)”, White Paper released by ARM, Sep. 2011.
[2] Brian Jeff, “Advances in big.LITTLE Technology for Power and Energy Savings”, White Paper released by
ARM, Sep. 2012.
[3] Hyun-Duk Cho, Ki-suk Chung, Tae-hoon Kim, “Benefits of the big.LITTLE Architecture”, White Paper
released by Samsung, Feb. 2012.
[4] http://www.hardkernel.com
[5] M. R. Hollander and P. V. Bolotoff, "RAMspeed, a cache and memory benchmarking tool," [Online].
Available: http://alasir.com/software/ramspeed/ (retrieved 2014, Apr. 10).
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API-Level Mapping Between HLA and DDS for the Interoperable
Middleware System
Minchul Shin*, Seokjoon Hong*, Kyungrak Lee*, Ramesh Kumar*, Jongsang Yi*,
Inwhee Joe*, Kyeongtae Kim†, Hyungkook Jun†, Woosuk Cha†, Wontae Kim†
*
Department of Electronics and Computer Engineering, Hanyang University, Korea
E-mail: {smc516, daniel379, esilote82, rameshkumar, yjs20104, iwjoe}@hanyang.ac.kr
†
ETRI (Electronics and Telecommunications Research Institute), Korea
E-mail: {ktkim, hkjun, wscha, wtkim}@etri.re.kr
Abstract
In this paper, we present prominent mappings between HLA (High Level Architecture) and DDS (Data
Distribution System) APIs for the interoperable middleware using ontology concept. For this purpose, we have
studied and analyzed HLA and DDS specifications in detail at the API level. After that, we have mapped the
similar functions and APIs of both HLA and DDS.
Keywords: HLA, DDS, Middleware, API, Mapping
1. Introduction
There are several research works which compared and mapped between HLA and DDS [1]. Those have
described the equivalent terminology, concepts and highlight the key similarities and differences between those
standards. In this paper, we present the prominent mappings between HLA management APIs and DDS APIs,
which can be used for the design of the interoperable middleware using ontology concepts.
2. Mapping between HLA and DDS
HLA uses the Federation concept to define and share the data among the various federates/simulations. In
order to share the data, the federate needs to be part of some federation. Federates can be connected/disconnected
with RTI using connect/disconnect services of the HLA federation management. If federate that was connected
with RTI is disconnected, RTI checks the federate status using connection lost service. Federate uses create
federation execution/destroy federation execution services to create/destroy federation, and also utilizes the
joined/resigned services to enter/leave the federation. Likewise, DDS provides the domain based concept to share
the data among all of the joined participants. DDS doesn’t have connect/disconnect, create/destroy join/resign
concept. However create_participnat/destroy_participant DCPS API can be similar with HLA functions and also,
to determine whether an entity is active, liveliness QoS Policy can be used. HLA has synchronization service, but
DDS doesn’t have this kind of service due to real-time based system nature.
In HLA, federates employ the Declaration Management Service to specify what the information to be
generated and shared in the federation. The federate uses Publish/Subscribe Object class attributes or Interaction
classes Services to declare the object class attributes and interactions class. After declaring the classes, RTI shall
notify the joined federates to register new object instance of specified class by using Start Registration for object
class service or interactions by using Turn Interactions On service. Similarly, in DDS, participants can publish or
subscribe the topics using DCPS APIs such as create_publisher/create_writer and create_subscriber/create_reader.
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After the data declaration phase in HLA, federates are ready to exchange the data with the help of Object
Management Services. Before the data exchange, federates need to register and discover the object instances of
the object class attributes through which they can send or receive data through Update/Reflect Attribute Values
Service for the Object Classes, and they can also share through Interaction parameters with the help of Send
Interaction/Receive Interaction Services. In the same way, DDS participants create data_writer in publisher and
data_reader in the subscriber to send and receive the Topic through write and read operation.
In HLA, the data sharing is restricted to specific regions of attribute/interaction using the Data Distribution
Management Services is possible. Federates can define the routing spaces for exchanging the updated attributes
values and interaction parameters. Federates create/destroy region of attribute using create region/delete region
service. DDS provides the same kind of functionality using content filtering options. DDS participants can
create/delete contentfilteredtopic using create_contentfilteredtopic/delete_contentfilteredtopic functions. These
two kinds of service are similar, but it has difference in terms of mechanism that determining region range and
contentfilteredtopic.
HLA provides the synchronization of data exchange among federates by invoking the Time management
services. Federates receive the data either as Time Stamp Order (TSO) or Receive order; TSO is used to ensure
that the data must be delivered in the consistent order and RO doesn’t provide the ordering consistency. If any
federates want to send or/and receive TSO messages, they should be either time regulating federates or/and time
constrained federates by using Enable Time Regulation Service/Enable Time Constrained Service respectively.
In DDS, there is a QoS Policy for sending and receiving TSO messages. The name of QoS Policy is
DESTINATION_ORDER and it can be set as either Receive Order or Time Stamp Order. But there is no
restriction for data_writer or data_reader to send or receive TSO messages. And when data_writer is going to
send TSO message, it should use write_w_stamp.
HLA provides ownership management to assign owner to each object instance. Similarly, DDS depicts this
feature using the OWNERSHIP QoS Policy. OWNERSHIP QoS Policy consists of two kinds of ownership. One
is SHARED kind, it means shared ownership each instance. The other is EXCLUSIVE kind which means each
instance can only be owned by one DataWriter. EXCLUSIVE ownership kind is similar to the HLA ownership
management, but SHARED kind is different because ownership management of HLA can assign only one owner
to the object instances.
3. Conclusions
In this paper, we present prominent mappings between HLA and DDS for the interoperable middleware using
ontology concept. We need more studies about Synchronization and Time Management.
Acknowledgements
References
[1] Rajive Joshi, Grrardo-Pardo Castellote, "A Comparison and Mapping of Data Distribution Service and HighLevel Architecture", Real-Time Innovations, 2006.
144 ISET 2014
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A Mechanism for Tracking Interactive Episodes in Mobile Devices
Nicolas Badano*, Jeaho Hwang†, Euiseong Seo*
*
Computer System Laboratory
College of Information and Communication Engineering
Sungkyunkwan University (SKKU), Suwon, Republic of Korea
E-mail: {nicolas, euiseong}@skku.edu
†
Computer Architecture Laboratory
Department of Computer Science
KAIST, Daejeon, Republic of Korea
Abstract
Dynamic thermal and power management is a current trend in mobile systems design. However, current low
power policies such as DVFS don’t consider interactiveness. This affects user perception of the system and
overall experience. In this paper we describe the design for a mechanism to identify and gather episode data of
interactive operations at runtime. The episode of an interactive operation refers to the time it takes for a user
input event to come back to the user as visual feedback. We also show experimental results that validate the
correctness of our mechanism. With this episode data, smarter thermal and power policies that consider
interactiveness can be implemented. This will result in a better user experience while still coping with thermal
and power dynamic constraints.
Keywords: Mobile systems, Interactiveness, Thermal and power management.
1. Introduction
More than ever before mobile platform users expect and demand longer battery life and higher computing
power from their devices. Better performing processors with higher clock speed come with a drawback, they
drain battery life and raise the chip's temperature very quickly. To overcome this issues power management
strategies come into play. Some of this strategies include novel microarchitectures such as heterogeneous
multicores or well known policies such as DVFS (Dynamic Voltage and Frequency Scaling). Commonly this
strategies apply power policies based on CPU load.
Operations handled by a processor can be classified into two categories: background and interactive.
Interactive are those that are initiated by user input, namely a touch on the touchscreen, a mouse click, or a
keyboard press. Because this kind of operations are latency-sensitive, any delay on the feedback will make the
system be perceived as clumsy or slow [1]. Power management strategies mentioned above apply low power
policies to all operations carelessly due to the fact that they can not pinpoint the interactive ones, which leads to
unresponsive GUIs [4].
Our first motivation is to detect interactive operations on the fly and classify them as such. Once we know that
the operation is interactive we can further analyze it and make an informed decision on wether or not apply a
power management policy to it. This further analysis implies knowing the episode of the interactive operation.
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An episode refers to the time it takes for a user input stimuli to go all the way though processing and back to the
user as screen feedback [2].
This brings us to our second motivation, to construct a mechanism to measure the episode of an interactive
operation. The gathered episode data can then be used to improve existing power and thermal policies, which is
our ongoing research topic. In addition, this tracking mechanism can serve as a tool for other research interests
such as thread to core mapping policies or GUI interactivity. Our main contributions are:
1) A way to classify interactive operations. This allows the OS to treat them differently from
background threads improving GUI responsiveness.
2) A mechanism to measure and gather interactive episodes. With this data smarter power and
thermal policies can be created to be applied to interactive episodes.
3) A tool that can be used for other research interests.
This paper is organized as follows: section two will describe the interactive episode measurement mechanism
in a platform agnostic way. In this manner the reader can become familiar with the concepts in section three
where we describe our implementation for the Android mobile platform. In section four we show micro
benchmarking results that validate our work. Finally in section five we give concluding remarks for our work.
2. Interactive Episode Tracking
In this section, we describe the design of our episode tracking mechanism. As we mentioned before, the
episode of an interactive operation begins with a user input event. This can be tracked by intercepting the Input
Framework of the implementing platform. On the other hand, the end of an episode is not as straightforward,
there is no place in the OS or system where we can observe an event or change in state that might imply the end
of an interactive operation [2]. Because of this, we must keep track of all tasks involved in serving a specific user
input stimuli. Then mark the end of the episode when all the tasks finish processing their work. For the rest of
this paper we will refer to as the episode’s task set to the group of tasks involved in serving the same single
interactive operation.
The challenge lies on how to construct the episode task set for a given interactive operation. This can be done
as follows: when the input event is detected at the Input Framework, the task responsible for handling the event
will become the first task in the set. Secondly, if this task communicates with any other task in the system, namely
another application or service, the second task will be added to the set. In the same manner, if any task in the set
communicates with any task that is not in the set, then the tasks that do not belong to the set will be included in it.
To accomplish this, the IPC (Inter Process Communication) mechanism of the implementing platform has to be
intervened with tracking code. Finally, once the task set is built, to mark the end of the episode all task in the task
set need to finish processing all their work. This can be detected when a task relinquishes the CPU voluntarily
and not when it gets preempted. To oversee this, the scheduler code of the implementing platform needs to be
extended.
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Figure 1. Execution trace of an interactive operation
Figure 1 depicts the basic flow of interactive episode monitoring, showing the places where task
tracking takes place. Next follows the description of the steps illustrated in Figure 1:
1) The input hardware generates an input event.
2) The OS input framework gets the “raw” input event and “forwards” a processed event to all
applications or services subscribed to handle the event. At this point the beginning of the
episode is marked and those handlers are flagged as being part of the episode task set.
3) The corresponding application handles the event and does some work.
4) The application communicates via IPC with other applications or services. Any task involved
in the communication, that is not part of the episode task set, is added to it.
5) (6) and (7) The episode does not finalize until all tasks in the episode task set finish
communicating and processing pertinent work. In other words until all of them voluntarily
relinquish the CPU.
Our mechanism places monitoring code at the OS level, namely at the input framework, IPC framework and
scheduler. Therefore third party apps do not need to be modified.
3. Implementation
In this section we describe our implementation for the mechanism described in the previous section. The
implementation is based on the Android 4.2 Jelly Bean mobile operating system. All modifications are done
within the Android kernel except for one custom system call placed at the Android framework level.
First thing to be done is to detect user inputs. This requires a simple modification to the Android Input
Framework. Inside the Input Framework two important threads of execution exist: the InputReader and the
InputDispatcher. The InputReader thread collects “raw” input event data generated by the input devices. Then it
passes the “processed” input event data to the InputDispatcher who is responsible of forwarding the event to all
subscribed applications or services that have interest in handling the event. Looking at the Input Dispatcher we
can recognize that an input event was generated and who is the responsible task for handling it. We made a
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simple custom system call to send this information into the kernel. On the kernel side the first task is added to the
episode’s task set. Also the process descriptor (task_struct structure) for this task is flagged as being part of an
episode and starts to be under the “watching eye” of the monitoring mechanism.
As explained in the previous section we need to monitor all the IPCs of tasks that are inside the episode’s task
set with those outside the set. This needs to be done to include in the episode all involved tasks that serve the
same interactive operation. All IPCs in Android are done via the kernel’s Binder module. Therefore we track
only Binder and not other IPC mechanisms in Linux such as sockets, shared memory, pipes or signals.
Figure 2. Binder Driver transaction sequence diagram
Every time a process wants to communicate with another process, a Binder Transaction is created (see Figure
2). Basically what binder does is behave as an intermediary between the two communicating processes. It
manages two thread pools, one for the the caller and one for the callee process. When the caller process initiates
a Binder Transaction it uses one of the threads in it’s thread pool (BC_TRANSACTION). Binder gets message
arguments form this thread and passes them to an available thread in the callee thread pool
(BR_TRANSACTION). Once the callee thread finishes processing the data it will send it back to Binder
(BC_REPLY) and Binder will wake up the original caller thread with the results of the IPC (BR_REPLY). Our
mechanism tracks the involved threads from the thread pools and adds them to the episode’s task set.
When all communications are done and all the tasks in the task set finished processing, we can consider the
episode as completed. To know when each of the tasks finishes working we modified the schedule function in the
CFS Scheduler. The modification calls into our mechanism when a flagged task yields the CPU voluntarily
implying that the task finished it’s work. At this point we unset the flag in the task descriptor and the task is no
longer under the observation of our mechanism. When all tasks in the task set have done this the episode is
considered finished.
Currently our mechanism has a limitation, it can only track single threaded interactive episodes. If a
multithreaded interactive operation is initiated, and the handling task decides to fork at some point, our
mechanism looses track of the episode. We are currently working to enhance our mechanism to support this
feature.
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4. Validation
To validate our mechanism we first conducted an experiment with a simple Android application that consists
of a single GUI button. The handler function for the onClick event for the mentioned button will keep the thread
busy by sleeping or looping for a fixed amount of time, say 50ms. We clicked on the button ten times and our
mechanism logged nine episodes of 55ms of duration and one of 50ms.
Our mechanism has a measurement granularity of 5ms. This granularity is equal to the time between system
ticks, which is defined by the frequency of the clock interrupt of the executing hardware. Therefore a 50ms
episode measurement means the episode duration falls in the range of 50ms to 55ms. Similarly the measurement
for the 55ms episode actually means the episode duration falls in the range of 55ms to 60ms.
Still we can observe an overhead of 10ms in the worst case. Our mechanism traces indicate the overhead is
caused by two factors: the time consumed in the IPC between the test application and Android’s SurfaceFlinger,
plus the processing done by the latter service. SurfaceFlinger is an Android service responsible for preparing a
frame buffer with the screen’s content before the display hardware performs the next render.
Table 1. Experimental environment configuration
Hardware
Board
Processor
Memory
ODROID-XU+E
Samsung Exynos5 Octa: Cortex™-A15 and Cortex™-A7 big.LITTLE
2GByte LPDDR3 RAM
Software
OS
Kernel
Android 4.2 Jelly Bean
Modified 3.4.5 kernel
The previous experiment validates that our mechanism measures interactive episodes correctly. Then we did an
experiment to further test our mechanism and gain some preliminary insight into the potential for improving
power policies. The experimental environment is described in Table 1. The experiment consist of three simulated
scenarios:
1)
2)
3)
No power policy applied, simulated by setting the clock speed to 1600MHz.
Power policy applied, simulated by setting the clock speed to 400MHz.
Power policy applied, simulated by setting the clock speed to 400MHz. Plus a background
workload executing concurrently.
For this preliminary experiment, we executed the benchmarks on the built-in Calculator application that ships
with Android. For the background job, we used a cross-compiled version of the 444.namd workload from the
SPEC CPU2006 benchmarking suite.
Table 2. Experimental results
Scenario
High performance
Low power
Low power + background work
# episodes (1ms - 5ms)
59
50
18
# episodes (5ms - 50ms)
63
70
34
# episodes (50ms - inf)
0
1
68
total # episodes
122
121
120
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In each scenario the benchmark was executed by hand with a mouse input device. Each run consisted of 20
clicks. Even though is very difficult to replicate all clicks exactly in every run, we believe that clicking at a steady
pace and over the same GUI elements is fair enough for this experiment. Each of the 20 clicks generates more
than one input event corresponding to the mouse up, mouse down, and mouse hovering events. It´s observable in
our mechanism traces that episodes with short duration, less than 5ms, belong to the pointer updating its position
(hovering events). The relevant episodes are the ones with longer duration, they belong to the mouse down event.
Table 2 shows the results grouped in three categories according to their episode duration. What´s important to
note here is how the distribution of the episodes tend to accumulate in the column on the right (50ms - inf.) when
the simulated power policy is applied, even more so when there is background work present. This directly
translates into deteriorated system responsiveness because any episode larger than 50ms won´t be perceived as
instant to the human eye [3].
Even though the experiment is a very simplified scenario we can foresee potential for improvement. Even
worse slowdowns are expected in more complex scenarios such as in multimedia applications. Improving the
treatment of interactive operations in this type of scenario by applying smarter power policies is the focus of our
ongoing research.
5. Conclusions
Enforcing low power policies on interactive operations as if they were no different from background
operations leads to uncomfortable user experiences. We bring forward a mechanism that identifies interactive
operations on runtime and gathers episode duration information from them. Looking at the collected episode data
we gain some insight of the potential for improving user interactiveness when low power policies are applied.
Our future plan is to extend our episode measurement mechanism to include the monitoring of multithreaded
applications. Then we plan to use this tool for our ongoing research that is to implement smarter power and
thermal policies for heterogeneous multicores.
References
[1] Zheng, H., & Nieh, J. (2010, June). RSIO: automatic user interaction detection and scheduling. In ACM
SIGMETRICS Performance Evaluation Review (Vol. 38, No. 1, pp. 263-274). ACM.
[2] Flautner, K., Uhlig, R., Reinhardt, S., & Mudge, T. (2000). Thread-level parallelism and interactive
performance of desktop applications. ACM SIGOPS Operating Systems Review, 34(5), 129-138.
[3] Flautner, K., & Mudge, T. (2002). Vertigo: Automatic performance-setting for linux. ACM SIGOPS
Operating Systems Review, 36(SI), 105-116.
[4] Huh, S., Yoo, J., & Hong, S. (2012, August). Improving Interactivity via VT-CFS and Framework-Assisted
Task Characterization for Linux/Android Smartphones. In Embedded and Real-Time Computing Systems and
Applications (RTCSA), 2012 IEEE 18th International Conference on (pp. 250-259). IEEE.
150 ISET 2014
6
PA-Pfair: A New Pfair Scheduling Policy for Performance
Asymmetric Multiprocessors
Peng Wu, Minsoo Ryu
Hanyang University, Seoul, Republic of Korea
E-mail: {wupeng, msryu}@rtcc.hanyang.ac.kr
Abstract
We propose a PA-Pfair (Performance Asymmetric Pfair) scheduling policy for performance asymmetric
multiprocessors that have identical instruction sets but different processing speeds. PA-Pfair differs from
the original Pfair scheduling in that PA-Pfair is aware of performance asymmetry of underlying processors
during the selection of scheduling parameters such as pseudo-deadlines for subtasks and the choice of
processors for running the highest priority subtasks.
Keywords: Performance Asymmetric Pfair, Scheduling, Multiprocessors.
1. Introduction
Heterogeneous multiprocessor architectures are getting increasingly important since they enable better
performance and energy efficiency. The ARM big.LITTLE architecture is a good example that can
maximize performance at the cost of minimal increase of energy consumption in embedded systems.
In this paper, we propose a PA-Pfair (Performance Asymmetric Pfair) scheduling policy for performance
asymmetric multiprocessors that have identical instruction sets but different processing speeds. PA-Pfair
differs from the original Pfair scheduling in that PA-Pfair is aware of performance asymmetry of underlying
processors during the selection of scheduling parameters such as pseudo-deadlines for subtasks and the
choice of processors for running the highest priority subtasks.
2. System Models and Definitions
Let   {1 ,..., n } be a set of n sporadic tasks. A sporadic task i is defined by (Ci , Di , Ti ) such that
Ci  Di  Ti , where Ci is the worst-case execution time, Di is the relative deadline, and Ti is the minimum interrelease time based on the slowest processor speed. We use  i , j to denote the j th request of task  i . We use Ai , j to
denote the arrival time of  i , j . We refer to the ratio of Ci and Ti as the weight of task denoted by wt ( i ) .
Consider m performance asymmetric multiprocessors and use   {P1 ,..., Pm } to denote a set of such
processors. The processors are labelled in non-decreasing order of processing speed, i.e., Pi is no slower
than Pi 1 .We use si to represent the processing speed of each processor Pi . For national convenience, we
use 1 for the slowest processors speed. Let Yp be the cumulative speed of the first p fastest processors. It
p
is denoted as: Yp   k 1 sk
3. PA-Pfair Scheduling and Schedulability Analysis
The proposed PA-Pfair scheduling divides each task into unit-sized subtasks. PA-Pfair associates each
subtask with a new release time and deadline, called pseudo-release time and pseudo-deadline. At runtime,
it chooses the highest priority subtask and executes it on the fastest processor. Specifically, the PA-Pfair
scheduling algorithm works as follows.
1
151
Subtask size. The length of subtask, i.e., size of scheduling quantum, is defined by
GCD (
L 
s1
s2
 x,
s1
s3
 x , ...,
s1
sm
 x , C1  x , C 2  x , ..., C n  x )
.
(1)
x
th
Execution windows. We denote the j subtask of task  i as  j , where j  1 . Each task can execute
within the execution window specified by its pseudo-release time and deadlines denoted by r (  j ) and
d (  j ) , respectively.
 i

(2)
 wt ( ) * L 
 i

Successor bit. We use b(  j ) to represent whether  j ’s execution window overlaps  j 1 ’s execution
window or not. The successor bit is an important parameter that is used for tie breaking of priority
assignment in case subtasks have the same pseudo-deadlines.
 i 1

*L 
 wt ( i ) 
r (u j )  
b(  ) 
j
and
d (u j ) 
 i
  i

 wt ( ) * L   wt ( ) * L
 i   i 
(3)
Priority assignment and subtask allocation. We assign priorities to subtasks based on EDF (earliest
deadline first). When subtasks have the same deadlines, we compare the successor bits and assign high
priorities to tasks with large successor bit values. If two subtasks have equal deadlines and successor bits,
then their successor subtasks are recursively checked. When allocating subtasks to processors, we always
execute high priority subtasks on fast processors.
Now we describe a sufficient schedulability test for our Pfair scheduling.
Theorem 1: A period task system   {1 ,... n } , is schedulable by fair scheduling on performance
asymmetric multiprocessor platform   {P1 , P2 ,..., Pm } with corresponding processing speed si (0  i  m) ,
if there is no task  i hold the following condition.
Ym Di   ( )Ci  LOAD() Di  Rc
(4)
 ( ) , LOAD() and Rc are defined as following equations:
LOAD()  max t (
  DBF ( i , t )
i
)
t
 t  Di 
  1)Ci )
 Ti 
DBF ( i , t )  max(0, (
Rc  c1  ...ci 1  ci 1 , ...  cn
 ( )  max 0i m
m
j i 1 s j
si
Conclusions
In this paper, we proposed a fair scheduling on performance asymmetric multiprocessors. Also we
develop a sufficient schedulability test for fair scheduling on performance asymmetric multiprocessors.
However, there still remain many issues about fair scheduling upon performance asymmetric
multiprocessors. Our assumption is pessimistic when we obtain our fair schedulability test. In the future
work , we can obtain a more accurate schedulability test for fair scheduling.
Acknowledgement
This work was supported partly by the National Research Foundation of Korea (NRF) grant funded by the Korea
government (MEST) (NRF-2011-0015997), partly by the IT R&D Program of MKE/KEIT [10035708, “The
Development of CPS (Cyber-Physical Systems) Core Technologies for High Confidential Autonomic Control
Software”], and partly by Seoul Creative Human Development Program (HM120006).
References
[1] J. Anderson, Philip Holman and Anand Srinivasan, " Fair Scheduling of Real-time Tasks on
Multiprocessors", Handbook of Scheduling, 2005.
[2] Sanjoy Baruah and Joël Goossens, "The EDF Scheduling of Sporadic Task Systems on Uniform
Multiprocessors", Real-Time Systems Symposium, pp. 367-374, 2008.
152 ISET 2014
2
A Study on Storing Environmental Data on SEDRIS
for Cyber Physical Systems
Hyun Seung Son*, In-geol Chun†, Jae Ho Jeon† , Woo Yeol Kim††, R. Young Chul Kim*
*
†
SE Lab., Deptartment of CIC(Computer and Information Communication)
Hongik University, Sejong, Republic of Korea
E-mail: {son, bob}@selab.hongik.ac.kr
CPS research team, Electronics and Telecommunications Research Institute
Deajeon, Republic of Korea
E-mail: {igchun, jeonjaeho11}@etri.re.kr
††
Department of Computer Education
Daegu National University of Education, Daegu, Republic of Korea
[email protected]
Abstract
To save the data used in simulation of Cyber Physical Systems (CPS), SEDRIS is required. But, SEDRIS
need to define the format of saving environmental data because it supports only the basic data structure to save
environmental data. In this paper, we define the right formats that have 4 types of environmental variables such
as friction wind direction, wind speed, and pressure to save environmental data in simulation of CPS. And we
also confirm the result of environmental data input in SEDRIS. Through this, we can expect to possibly simulate
environmental data in CPS.
Keywords: SEDRIS, Cyber Physical Systems, Modelling & Simulation, Environmental data.
1. Introduction
The existing environment of simulation simulates the one system. But the simulation in Cyber Physical
Systems (CPS) is performed by the combination of factors such as several embedded systems, the physical
condition, and controlled real-time computing. Therefore the CPS requires the integrated management of various
data in simulation and the expression for the synthetic environments. The Sharing Environmental Data
Responsibly with an Interface Specification (SEDRIS) provides the cost-effective technology for the unified
representation and interchange of environmental data, eliminates the expensive and recurrent costs compatible
across domain boundaries, and covers multiple product formats [1]. SEDRIS can also save and manage all
environmental data using in simulation. But SEDRIS need to define a format of inputting the environmental data
because it supports a basic method to save in the database management system. In this paper, we define the
format that have types of environmental variables such as friction wind direction, wind speed, and pressure to
save environmental data in simulation of CPS. In addition, we confirm the result of environmental data input in
SEDRIS.
2. Our defined metrics and input of environmental data in CPS
We define metrics as shown table 1 in order to save 4 types of environmental variables such as friction wind
direction, wind speed, and pressure in the internal SEDRIS, which consists of time and data. The time part
separates the absolute time and relative time. In data part, 4 types of the environmental variables are matched by
the coordinates x, y, h.
1
153
Table 1. The metrics for representation of environmental data in CPS
N
o
Absolute time
(M-D/Y)
Relative time
(D–H:M–S)
x
y
h
1
2
3
4
4-5/2014
4-5/2014
4-5/2014
0-0:0-0
0-1:0-0
0-2:0-0
0
0
0
0
0
0
0
0
0
Environmental data
Friction
Wind direction Wind speed
(Type)
(Radian)
(m/s)
GROUND
1.57
10
GROUND
1.57
10
GROUND
1.74
20
...
Pressure
(Bar)
0.001
0.001
0.001
To save internally data in SEDRIS, it is possible to use the Application Programing Interface (API) of
SEDIRIS Software Development Kit (SDK) [2]. But developers not easily use the low level APIs without
understanding the structures of DRM, SRM, and EDCS. To solve this problem, we propose the SEDRIS Highlevel API (SHA) [3]. In this SHA, we add API for saving environmental data. And we confirm input result using
the additional API as shown figure 1.
Figure 1. The input result of environmental data in SEDRIS
3. Conclusions
SEDRIS require defining a right format to save environmental data because it supports a basic method to save
such as the database management system. Also, developers not easily use the low level APIs without
understanding the structures of DRM, SRM, and EDCS. To solve this problem, we define metrics and add API
for saving environmental data in SEDRIS. We actually input the environmental data with additional API. As a
result, we confirm the inserted data in SEDRIS. Through this, we can expect to be possible the simulation of
environmental data in CPS. Further research will be focused on terrain map of the complex format for additional
environment data such as temperature, and humidity, so on.
Acknowledgments. This work was supported by the IT R&D Program of MKE/KEIT [10035708, "The
Development of CPS(Cyber-Physical Systems) Core Technologies for High Confidential Autonomic Control
Software"]
References
[1] F. Mamaghani, "An Introduction to SEDRIS", 2008, http://www.sedris.org
[2] SEDRIS SDKs, http://www.sedris.org/hdr1trpl.htm
[3] H.S. Son, R. Y.C. Kim, I.G. Chun, J.H. Jeon, W.Y. Kim, "API Development for Efficiently Mapping between
SEDRIS and Simulation Systems", Next Generation Computer and IT Applications, ASTL 27, pp.172-176, 2013.
154 ISET 2014
2
Zero-Copy Load Balancing for OpenCL Platforms on Mobile
Systems with Unified Memory Architecture
Jonghyun Park , Jaemin Hwang, Byeong-Gyu Nam
Dept. of Computer Science and Engineering
Chungnam National University, Daejeon, Republic of Korea
E-mail: {jh.park, jmhwang, bgnam}@cnu.ac.kr
Abstract
A zero-copy load balancing scheme is proposed for OpenCL platforms on mobile systems with unified
memory architecture. Conventional OpenCL load balancing involved memory copy overheads between graphics
memory and system memory due to the separate memories for CPU and GPU. However, it incurs unnecessary
memory copy overheads in mobile systems such as accelerated processing units (APUs) and application
processors (APs) which incorporate the unified memory architecture. In this work, we eliminate the memory
copies associated with the data transfers between CPU and GPU by exploiting the shared memory between them.
Experimental results show 15% performance improvements through the zero-copy scheme.
Keywords: Load balancing, Zero-copy, Unified memory architecture, OpenCL, Heterogeneous computing
1. Introduction
Recently, OpenCL load balancers have been developed to redistribute the workloads between CPU and GPU
on their availabilities to improve the performance of mobile heterogeneous systems [1], [2]. The OpenCL load
balancing requires sharing of OpenCL data between CPU and GPU and therefore, conventional load balancing
schemes used memory copies between CPU and GPU through the bandwidth limited PCI-Express I/O bus,
resulting in performance overhead [1-3]. This approach involves unnecessary memory copies if adopted in the
mobile systems like accelerated processing units (APUs) and application processors (APs) due to the unified
memory architecture (UMA) of CPU and GPU in these systems. In this paper, we eliminate the memory copy
overhead in the load balancing on mobile systems with the UMA by adopting the zero-copy method [4] that uses
the shared system memory between CPU and GPU to transfer OpenCL data to each other. As a result, we achieve
15% performance improvement compared with the prior OpenCL load balancers [1].
2. Zero Memory Copy in OpenCL Load Balancer
Fig. 1 compares non-uniform memory architecture (NUMA) of conventional desktop system and unified
memory architecture (UMA) of APUs and APs. Desktop system has separate graphics and system memories for
GPU and CPU, respectively, and thus conventional OpenCL load balancers involve memory copy overhead
between CPU and GPU to transfer data to each other, as shown in Fig. 1(a). However, in mobile systems with
UMA, this overhead is unnecessary due to the shared memory between CPU and GPU. Hence, we propose a
zero-copy OpenCL load balancing scheme for mobile systems with UMA that share OpenCL data between CPU
and GPU via the shared memory, as illustrated in Fig. 1(b). In conventional load balancers, CPU creates an
OpenCL memory object in the graphics memory using the clCreateBuffer() to transfer OpenCL data to the GPU,
1
155
CPU
Memory
Controller
GPU
PCI-E
CPU
GPU
Memory
GPU
Memory Controller
Copy
System
Memory
Data sharing region
System Memory
(a) Conventional load balancer on NUMA
(b) Zero-copy load balancer on UMA
Figure 1. Comparison of memory architectures between NUMA of desktop systems and UMA of APUs / APs
and GPU accesses the graphics memory to get the OpenCL data sent from the CPU. This process involves data
copy overheads from CPU to GPU through the bandwidth limited PCI-Express I/O bus. However, in our
proposed zero-copy scheme, CPU creates an OpenCL memory object in the system memory by setting the
CL_MEM_USE_HOST_PTR flag in the clCreateBuffer() and sends the memory pointer to GPU so that the
GPU can directly access the CPU memory region using the pointer without incurring any data copy overheads.
3. Evaluation Result
Execution time (ms)
We used the AMD A10-4600M APU that integrates CPU and GPU in a single chip and adopts the unified
memory architecture [5]. Measurement result for dot multiplication shows a 120ms improvement through the
zero-copy method adopted in our load balancer, which converts to a 15% performance improvement from
conventional load balancer as shown in Fig. 2.
800
600
759
15%
639
400
200
0
Conventional
load balancer
Zero-copy
load balancer
Figure 2. Performance comparison
4. Conclusion
A zero-copy load balancing scheme is proposed for the OpenCL platforms on mobile systems with unified
memory architecture. The scheme eliminates data copy overhead by sharing the OpenCL data through the shared
system memory between CPU and GPU. As a result, we achieve a 15% performance improvement compared to
prior OpenCL load balancers.
156 ISET 2014
2
Acknowledgement
This work was supported by the Industrial Convergence Source Technology Development Program (NO.
10041332) through the Ministry of Science, ICT and Future Planning, Korea.
References
[1] M. Boyer et al. "Automatic intra-application load balancing for heterogeneous systems," AMD Fusion R
Developer Summit, 2011.
[2] C.S. de La Lama., et al. "Static multi-device load balancing for opencl," IEEE 10th International
Symposium on Parallel and Distributed Processing with Applications (ISPA), pp. 675-682, 2012.
[3] T. Komoda et al. "Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and
task mapping," IEEE 31st International Conference on Computer Design (ICCD), pp. 349-356, 2013.
[4] P. Boudier and G. Sellers, "Memory system on fusion APUs," AMD Fusion developer summit, 2011.
[5] A. Branover, D. Foley, and M. Steinman, "AMD Fusion APU:Llano," IEEE Micro, vol. 32, no. 2, pp. 28-37,
Mar-Apr. 2012.
3
157
The 9th
Invited Session A: ETRI
09:30-10:50, May 23, 2014
Technology Trends of Scalable Open Platforms
Chair : YungJoon Jung (ETRI, Director)
NO
1
2
3
4
5
Invited Session
Embedded SW Platform Trends........................................................................................................................................161
Young-Chang You(FALinux, CEO)
AR Service Platform Technology Trends.........................................................................................................................163
Chuwhan Kim(Qualcomm Korea, Senior Director)
Open IoT Platform: Mobius................................................................................................................................................165
Jaeho Kim(KETI, Team Manager)
Data-centric Communication Middleware for CPS based on OMG DDS.................................................................167
Soo-Hyung Lee(ETRI, Principal Researcher)
Trend of SW Platform for Heterogeneous Multi-core system and OpenSEED Community Activity ................169
Seung-hwa Song(IDIS Co., Ltd, Open Project Leader)
Embedded SW Platform Trends
Young-Chang You
Falinux Co., Ltd., Seoul, Republic of Korea
Abstract
The appearance of IT devices like wearable device and smart phone has increased the complexity of
embedded software. Plenty of specialized software platforms have been developed and improved to solve the
such complexity. There're also IT trends such as 'cloud', 'Internet of Thing' that had impact on those platforms.
With the advent of HTML5 technology, the embedded devices connected to cloud-based service have been
transplanted and developed on the Web OS platform such as Tizen, Chrome, and Firefox mobile.
The embedded device platforms are laregely classified according to whether they support embedded OS or just
have firmware. The linux kernel is widely used and recognized as de facto standard in the area of embedded
systems apart from aviation, railload, and military industries.
The linux kernel has been actively developed to back up mobile devices. The development of linux embedded
kernel led by communities is now done by the developers of chip vendors. While the ARM processors are mostly
used in the embedded systems, the uses of them have been increasing in the PC-based systems in these days.
The developments of software platforms have necessitated the technologies related to 64-bit, multicores, and
GPU architecture. The 'Open IT' trend spreads drastically in the embedded industry and the most typical area for
it is that of the software platforms for developers. While the traditional developments of embedded tools are
rapidly decreasing, it's a tendency to coalesce into 'Open Source Group'.
As the number of operating devices rapidly increases, the quality control for them is required. A party of
traditional software platforms to address it have been introduced in developemnts of embedded systems. Now the
embedded software platforms aren't only specialized in embedded systems, but being developed with them
intimately connected to other IT areas.
Keywords: Embedded, Software, Platform,Trend
1
161
Embedded
SW Platform Trends
Youngchang You(CEO FALINUX Co., Ltd.)
ISET 2014
Embedded Operating System
 Linux Kernel
 Leading By Chip Vendor
 Big Vs Small
 Real Time Vs General
 Power Of Open Source Group
162 ISET 2014
AR Service Platform Technology Trend
Chuwhan Kim
QUALCOMM KOREA, Inc.
Sr. Director, Business Development
[email protected]
Abstract
Augmented reality (AR) allows computer-generated content to be superimposed over a live camera view of
the real world. In the early days of mobile devices, there were many reasons for the fading interest in AR.
Industry quoted numerous technical challenges with limited computing power for recognition, 3D generation, and
lack of compelling use cases.
However, with wide spread of smart mobile devices, AR is becoming an integral part of new digital
environment where users experience digital contents in more intuitive and interactive way. Especially, visionbased AR provides a greatly enhanced user experience by allowing computer graphics to be tightly aligned with
real world objects. It enables developers to build games, extend print and TV media with interactive 3D content,
and create educational applications that bridge the digital and real worlds.
Embracing the next evolutionary computer vision technologies such as off-target tracking, 3D mapping, 3D
object recognition, and even deep learning, AR is creating unprecedented uses cases in various fields of digital
environment.
QUALCOMM’s Vuforia is an AR software platform for Android and iOS that enables users to see images
from a Vuforia target database on the device or in the cloud. When a target is recognized, the app generates
augmented reality experiences, unlocks new functionality and contents.
Table of Contents:
AR platform & technology trend
Global developer adoption
Commercial app growth trend
Vuforia platform overview
AR app Example
What’s coming next
Keywords: Augmented Reality, Image Classification, Service, Platform, Devices
1
163
AR Service Platform Trend
Chuwhan Kim (김주한)
QUALCOMM
2014. 5. 23
1
2
164 ISET 2014
Open IoT Platform: Mobius
Jaeho Kim
Convergence Emerging Industries R&D Division,
Korea Electronics Technology Institute, Seongnam-si, Republic of Korea
Abstract
The Internet of Things (IoT) is gaining ground in various vertical domains such as healthcare, home
automation and public services. Since IoT connects all smart objects and enables them to communicate with each
other, the intelligent services introduced by IoT will provide a huge impact on our everyday life. Additionally,
IoT is expected to create a new ecosystem involving a wide array of players such as device developers, service
providers, software developers, network operators, and service users. This requires an open platform satisfying
all different needs from various stakeholders and providing standardized mechanisms for managing IoT devices.
In this presentation, we introduce an open service framework for the Internet of Things called Mobius1.0. The
Mobius platform is an open IoT implementation realizing true IoT mass market and establishing a global IoT
ecosystem with the worldwide use of IoT devices and softwares. We believe that the Mobius framework will play
a key role in the widespread adoption of the Internet of Things in our everyday life. We also hope that Mobius
opens up endless opportunities to all related stakeholders as well as various vertical domains in the world of
information and communication technologies.
Keywords: Machine-to-Machine communications, Internet of Things, Open platform.
1
165
ISET 2014
Open IoT Platform: Mobius 1.0
Open IoT Platform: Mobius
2014. 5. 23
Jaeho Kim ([email protected])
Korea Electronics Technology Institute
ISET 2014
Open IoT Platform: Mobius 1.0
Agenda
1
Open IoT Platform Overview
2
Open IoT Platform Ecosystem
3
Open IoT Platform (Mobius, &CUBE) Architecture
4
Open IoT Platform Pilot Services
5
Conclusion
1
166 ISET 2014
Data-Centric Communication Middleware for CPS based on OMG
DDS
Soo-Hyung Lee
Embedded SW Research Department
Abstract
Cyber-Physical System (CPS) is a system of integrating cyber computational elements controlling complex
physical elements. Many example of cyber-physical systems can be found in areas of diverse converging domain
such as defense system, intelligent transportation, energy and future manufacturing system. To make CPS system
work successfully, its reliable and continuous communication capability between the elements is essential. But
the operational environment of CPS is heterogeneous, large-scale because CPS system can be a system of
systems. Date-centric communication middleware based on OMG Data Distribution Service (DDS) can be a
alternative for CPS communication platform. In this presentation, CPS characteristics from the viewpoint of data
exchange will be given. A brief overview of DDS will be presented. Finally we present the current development
status of CPS middleware as a conclusion
Keywords: CPS, DDS, Data-centric, Communication, Middleware
1
167
Contents
Ⅰ
The Introduction to CPS Middleware
Ⅱ
The Overview of DDS Technology
Ⅲ
Current Status of CPS Middleware
2
168 ISET 2014
Trend of SW Platform for Heterogeneous Multi-core system and
OpenSEED Community Activities
Seung-hwa Song
IDIS Co., Ltd
Abstract
Heterogeneous system architecture today is not early technology trend anymore. This architecture is already
accepted widely in various computer industries such as personal computer and mobile device.
Typical single-core architecture faced to limitation of performance growth in the past and multi-core
architecture era had come decades ago. Early multi-core architecture were basically based on homogeneous
system architecture that gain performance by just adding cores. However, even though each core shows high
performance and it is usable for general purpose, many-core architecture is not easily accepted for many domains
except server clustering industry because of its price. Furthermore, end-user devices like PC or mobile phone
require more various particular tasks rather than a few performance-oriented tasks. One of the needs is graphic
processing which drives development of GPU. Many heterogeneous systems utilize CPU and GPU usually on the
same silicon chip.
Multi-core era also saw some interesting developments with advances of GPU. Since GPUs have parallel
vector processing capabilities that enable them to compute large sets of data, people tried to utilize them for
general purpose computation beyond graphic processing. And even parallel processing consumed much lower
power relative to similar works on CPUs. Although GPUs have definite advantages above, vector processing is
not always good answer. CPUs are still better for certain problems and we cannot dump typical abundant
software libraries and solutions. This is because CPU-GPU coupled architecture trend has been risen up.
Heterogeneous system is very sophisticated. Thus software industry faced a truly hard portability issue that
programmers cannot support all different platforms by re-writing code. To overcome this issue, the HSA
Foundation which is open industry standard organization for heterogeneous system was formed. The goal of HSA
is to help system designers integrate different architecture easily and provide advanced approaches and standard
software infrastructure such as compiler and language.
In this presentation, today’s trend of heterogeneous system and its software platform technologies will be
introduced such as CPU-GPU offloading and OpenCL. By these trend changes, there have been many efforts to
improve software platform for heterogeneous system in Korea. Researches driven by the Korean Electronics and
Telecommunications Research Institute, the ETRI, will be introduced. Research works are not only included but
an open source community to try and evaluate software technologies developed by the ETRI also organized and
its activities will be introduced too.
Keywords: Heterogeneous system architecture, CPU-GPU offloading, OpenCL, OpenSEED
1
169
Trend of SW Platform for
Heterogeneous Multi-core system and
OpenSEED Community Activities
Seung-hwa Song
Content
• Era of multi-core system and its advances
• Software platform trend for heterogeneous
system
• CPU-GPU offloading issues and related
researches by ETRI
• OpenSEED activities
170 ISET 2014
The 9th
Invited Session B: DGIST
14:40-16:00, May 23, 2014
CPS & Wellness
Chair : Kyouho Lee (Inje Univ., Professor)
NO
1
2
3
4
Invited Session
Noise induced Tracking Error in Systems with Saturating Actuators. .....................................................................173
Yongsoon Eun(DGIST, Professor)
Networking and Applications for Vehicular Cyber-Physical Systems......................................................................175
Jaehoon (Paul) Jeong(Sungkyunkwan Univ., Professor)
Recent Trends and Issues of Wellness Human-care System.......................................................................................177
Jae Sung Choi(DGIST, Senior Research Engineer)
Wearable Cyber-Physical Systems. ..................................................................................................................................179
Taejoon Park(DGIST, Professor)
Noise Induced Tracking Error in Systems with Saturating Actuators
Yongsoon Eun
Information and Communication Engineering
Daegu Gyeongbuk Institute of Science and Technology
Daegu, Republic of Korea
Abstract
This paper is devoted to a recently discovered phenomenon that takes place in feedback systems with
saturating actuators, proportional-integral control, and anti-windup. Namely, in such systems, measurement noise
induces steady state error in step tracking, which is incompatible with the standard error coefficients. We
quantify this phenomenon using stochastic averaging theory and show that the noise induced loss of tracking
occurs only if anti-windup is present. An indicator that predicts this phenomenon is derived, and a rule-of-thumb,
based on this indicator, is formulated. An illustration using a digital printing device is provided. As control
systems constitute a substantial part of cyber physical systems, the results are expected to benefit analysis and
synthesis of cyber physical systems.
Keywords: control systems, saturating actuators, measurement noise, anti-windup.
1
173
2014 International Symposium on
Embedded Technology (ISET)
Noise Induced Tracking Error in Systems with
Saturating Actuators
2014. 05. 23
Yongsoon Eun
DGIST
Outline
1. Introduction
2. Problem Formulation
3. Analysis
3.1 Application of stochastic averaging
3.2 Analysis of Noise Induced Tracking Errors
4. Indicators for Noise Induced Tracking Error
5. Control Systems Design using Noise Induced Tracking Error Indicator
5.1 Xerographic toner concentration control
5.2 CPU Temperature control
6. Conclusions
2
174 ISET 2014
Networking and Applications for Vehicular Cyber-Physical Systems
Department of Software
Sungkyunkwan University, Suwon, Republic of Korea
Abstract
This paper introduces networking and applications for Vehicular Cyber-Physical Systems (VCPS) for smart
road services. First, this paper defines VCPS as systems that are integrated by Physical Systems in road networks
and Cyber Systems in vehicular cloud via wireless and wired communications. This VCPS can provide drivers
and pedestrians with the following smart road services: (i) Driving safety (e.g., accident avoidance and pedestrian
detection), (ii) Driving efficiency (e.g., intelligent navigation and road condition sharing), and (iii) Data services
(e.g., location-based services and entertainment). Second, this paper introduces mobile applications for VCPS
smart services: (i) Road condition monitoring, (ii) Participatory crowd monitoring, (iii) Smart road-screen service,
(iv) Green vehicle speed control, and (v) Safe-driving assistant. Third, this paper explains mobile networking in
vehicular networks, consisting of Infrastructure-to-Vehicle (I2V) and Vehicle-to-Infrastructure (V2I)
communications. This paper articulates VCPS characteristics for vehicular networking design, such as
predictable vehicle mobility, road network layout, vehicular traffic statistics, and vehicle trajectory. It then
explains research topics in vehicular networks, such as unicast, multicast, and infrastructure deployment. Last,
this paper introduces ongoing VCPS research projects at SKKU CPS laboratory, such as smart navigation system
(i.e., Self-Adaptive Interactive Navigation Tool, SAINT) and vehicular MAC protocol (i.e., Trajectory-based
Media Access Control, TMAC) for the driving efficiency and safety in road networks, respectively.
Keywords: Vehicular Cyber-Physical Systems, Vehicular Networks, Smart Road, Trajectory, Navigation.
1
175
Networking and Applications for
Vehicular Cyber-Physical Systems
[email protected]
CPS Lab: http://cpslab.skku.edu/
Contents
Vehicular Cyber-Physical Systems (VCPS)
 Mobile Applications for VCPS
 Mobile Networking in Vehicular Networks
 VCPS Research Projects at SKKU CPS Lab
 Conclusion

176 ISET 2014
Recent Trends and Issues of Wellness Human-care System
Jae Sung Choi
DGIST
Abstract
Wellness is a continuous process to keep individuals’ physical, spiritual, environmental, occupational, and
emotional health. It is a method of life towards health optimization and optimized well-being status. For better
life for human being, wellness human care monitoring system using wired/wireless sensors is a shapely growing
research application in recent years. Recent technologies already offer the possibility and efficiency in smart
healthcare systems to autonomous monitoring feature of patient’s activity and body signal measurement. This
presentation will address recent trends of Wellness and Healthcare system in EU, North-America, and Korea.
Also I discuss about the necessity and possibility of wellness human care system with several expected issues.
1
177
Recents Trends and Issues of Wellness Human-care System
Daegu Gyeongbuk Institue of Science and Technology
Jae Sung Choi, Ph.D
2015.05.23
Contents
Vehicular Cyber-Physical Systems (VCPS)
 Mobile Applications for VCPS
 Mobile Networking in Vehicular Networks
 VCPS Research Projects at SKKU CPS Lab
 Conclusion

178 ISET 2014
Wearable Cyber-Physical Systems
Taejoon Park
DGIST
Associate Professor, Associate Director of CPS Global Center
Department of Information and Communication Engineering
Abstract
Cyber-physical systems (CPS), often referred to as 21st century embedded systems, are emerging as a new
research field that will play a key role in the creative convergence of computer and network science with such
diverse industries as consumer electronics, communications, healthcare, automotive, transportation systems,
aerospace, energy, manufacturing, national infrastructure, and so on. In this talk, after making a brief introduction
to CPS, we present our ongoing research on wearable CPS, which focuses on how to minimize the energy
consumption for wearable and mobile devices with negligible negative impact on smartness, accuracy, reliability
and safety. We explain what we have done so far and what we are planning to do for the development of, e.g.,
energy-efficient body area networking, approximate computing supporting energy-accuracy tradeoffs, and
wearable applications such as mobile point-of-care testing.
1
179
ISET 2014
Wearable Cyber-Physical
Systems
2014. 5. 23
Taejoon Park
Dept. of Information and Communication Engineering
Contents
1
CPS Overview
2
CPS for Wearable Smart Devices
3
Our Approaches
4
Summary
2
180 ISET 2014
The 9th
Invited Session C: GNU & KAI
14:40-16:00, May 23, 2014
IMA Systems for Next Generation of Aircraft and Its
Applications
NO
Chair : Yong-Kee Jun (Gyeongsang Nat’l Univ., Professor)
Invited Session
1
2
3
4
Design of Software Configuration Tool for Integrated Modular Avionics. .............................................................185
Eu-Teum Choi(Gyeongsang Nat’l Univ., Student)
Design of Development Environment to Support Detecting Races in Airborne Software. ...............................185
Sun-Sook Kim(Suresoft Technologies Inc., Researcher)
Switching Video Technologies for Next Generation of IMA Systems.......................................................................187
Sang-cheul Lee(Intellics Inc., Department Manager)
A Study on Feasible Configuration of AFDX Networks in Avionics Systems..........................................................189
Kyong Hoon Kim(Gyeongsang Nat’l Univ., Professor)
Design of Software Configuration Tool for Integrated Modular
Avionics
Eu-Teum Choi*, OK-Kyoon Ha†, Young-Kee Jun*
*
Department of Informatics
Gyeongsang National University, Republic of Korea
†
Engineering Research Institute
Abstract
ARINC 653 specification has been developed as a standardized interface definition of real-time operating
system to simplify the development of Integrated Modular Avionics (IMA). The ARINC 653 provides a strict
and robust time and space partitioning to guarantee the reliability of avionics by isolating the failures of the
system. Configuration data for the time and space partitions in ARINC 653 can be defined as the XML
configuration file(s) that can be accessed only by system OS. Requirements for an IMA system are integrated to
the configuration data which bases on XML schema of the ARINC 653 standard. However, it is quite tedious
activity to check the syntax errors of XML and the integrity of partition scheduling during the integrating tasks.
Moreover, existing configuration tools, which employ general purpose editing tool, do not provide any function
to verify the static errors of XML and the integrity of input data for partitioning such as the allocation of
resources and the scheduling of applications. In this paper, we present a configuration tool that provides
generating the basic configuration data for IMA based on XML Scheme of the ARINC 653 standard. Our tool
also provides Partition Editor which verifies the integrity of partitioning with graphic user interface (GUI) by
analyzing the input data of partitions.
Keywords: Integrated Modular Avionics, Integrated Development Environment, ARINC 653,
configuration data, verification
References
[1] Airlines electronic engineering committee (AEEC), Avionics Application Software Standard Interface –
ARINC 653-part 1 (Supplement 2 – Required Services), ARINC Inc., 2006.
[2] J. Rufino, S. Filipe, M. Coutinho, S. Santos, and J. Windsor, “ARINC 653 Interface in RTEMS”, In
proceedings of the Data Systems In Aerospace, June, 2007.
[3] P. J. Prisaznuk, “ARINC 653 role in Integrated Modular Avionics (IMA)”, In proceedings of the 27th Digital
Avionics Systems Conference (DASC), pp. 1.E.5-1 - 1.E.5-10, October, 2008.
[4] O.-K. Ha, G. M. Tchamgoue, J. Suh, and Y. Jun, “On-the-fly Healing of Race Conditions in ARINC 653
Flight Software”, In proceedings of the 29th Digital Avionics Conference (DASC), pp. 5.A.6-1 - 5.A.6-11,
October, 2010.
[5] G. M. Tchamgoue, L. Gan, O.-K. Ha, S. Yang, and Y. Jun, “ Visualizing concurrency faults in ARINC 653
Real Time Applications”, In proceedings of the 31st Digital Avionics Systems Conference(DASC), pp. 9E6-1
– 9E6-9, October, 2012.
1
183
•
Federated and Integrated Modular Avionics
Federated
IMA
Advantages
Advantages
• High performance
• Independence of design and
certification
• Well-understood methodology
• Established supply chain
•
•
•
•
Lower SWaP requirements
Better software reuse, refresh
Better portability, modularity
More efficient platform
certification
Challenges
Challenges
• Greater size, weight, and power
(SWaP) requirements
• Less software reuse
• Less portability, less modularity
• Cannot scale into larger platforms
Flight
Control
Radar
Display
Avionics Bus
(MIL STD 1553, ARINC 429, TTEternet…)
• Greater complexity of system
integration
• Greater complexity of design and
certification
• Less experienced supply chain
Flight
Control
Radar
Display
Time and space partitioning
ARINC 653 Operating System
2
184 ISET 2014
Design of Development Environment to Support Detecting Races in
Airborne Software
Sun-Sook Kim*, OK-Kyoon Ha†, Young-Kee Jun‡
*
Suresoft Technologies Inc.
†
Engineering Research Institute
‡
Abstract
There is increasingly need to concurrency programs to improve the performance of software for airborne
systems and equipment, since the high-performance IMA (Integrated Modular Avionics) based on multi-core
architectures was introduced. Data races which are most notorious class of concurrency bugs in parallel programs,
may occur unintended results of applications, and they cause unintended system behavior or system fault.
Therefore, we must verify data races to certify the parallel programs for airborne software which requires the
strict safety and the reliability. Unfortunately, existing IDEs (Integrated Development Environments) does not
verify where the existence of data races ran with an execution of parallel programs. It means that we need
additional tools to verify credibility of a data race free from an execution of parallel programs. This paper
presents an analysis tool that supports detecting data race based on existing IDE for airborne software. We
designed the tool using UML (Unified Modeling Language) as a plug-in for Eclipse IDE which is widely used for
developing airborne software. We verified our design by analyzing four important properties for each state,
termination, precision, effectiveness and I/O. Empirical results show that the run-time overhead of our dynamic
tool is moderate enough for practical use by IDE user.
Keywords: Integrated Modular Avionics, Integrated Development Environment, data races, verification
References
[1] S. Kim, O. Ha, Y. Jun, "Parallel Programming for Multi-core Avionics", In Proceedings of the 2010
International Conference on Advanced Aircraft Technologies (ICAAT 2010), pp. 81-82, 2010.
[2] O. Ha, G. Tchamqoue, J. Suh, and Y. Jun, “On-the-fly Healing of Race Conditions in ARINC-653 Flight
Software”, In Proceedings of Digital Avionics Systems Conference (DASC 2010), pp. 238-246, 2010.
[3] Wind River, Workbench http://www.windriver.com/products/workbench/, 2013.
[4] Green Hills, Multi http://www.ghs.com/products/MULTI_IDE.html/, 2013.
[5] Lynux Works, Luminosity http://www.lynuxworks.com/products/eclipse/luminosity.php/, 2013.
[6] MDS Technology, NEOS IDE http://www.mdstec.com/, 2013.
1
185
Contents
I. Background
I.
Airborne Software and Development Environment
II. Data Races in Airborne Software
III. Problem of Existing IDEs
II.Substance of Research
I. Data Races Detection Environment : SUN-RACE
II. Verification of Design
III. Result of Research
I. Implementation and Experimentation
II. Conclusion
Sun Sook Kim
186 ISET 2014
2
2014-04-28
Switching Video Technologies for Next Generation of IMA System
Sang-cheul Lee
R&D team, Intellics,Inc.
Abstract
The contribution of this paper is to describe switching video technologies in IMA system. Because of growth
up the MFD ability, there is no analog primary indicator. This means that mission computers may connect to
MFD with Level A rather than Level B. Therefore, we have to consider the system safety, such as redundancy,
for any Level A mission computer. This paper gives how to configure the video switching and safety for IMA
systems.
Keywords: IMA, Video switching
1
187
Switching Video Technologies for
Next Generation of IMA System
2014. 05. 23
Contents
•
•
•
•
Traditional Mission Computer
Federated vs. IMA
Switching Video Display Computer
Conclusion
188 ISET 2014
A Study on Feasible Configuration of AFDX Networks in Avionics
Systems
Dongha An, Kyung-Chul Choi, Kyong Hoon Kim, Ki-Il Kim
Gyeongsang National University, Jinju, Republic of Korea
E-mail: {dhan, blank, khkim, kikim}@gnu.ac.kr
Abstract
As recent aircrafts consist of a lot of components or units due to increased requirements and functionalities,
high-speed network systems are also required in aircraft systems. In order to meet both real-time and highbandwidth network capabilities, AFDX (Avionics Full Duplex Switched Ethernet) networks have been proposed
as a Part 7 in ARINC 664 standard. Much recent work has focused on the system analysis of AFDX networks
including end-to-end delays and worst-case latencies by using queuing networks, network calculus, or model
checking. However, only a few studies have been done on the problem of AFDX configuration such as BAG
(Bandwidth Allocation Gap) and MTU (Maximum Transmission Unit). In this work, we define a problem of
feasible configuration of BAG and MTU in a single AFDX switch and provide an algorithm to solve the problem.
The proposed problem can be extended to a problem of configurations of multiple AFDX switches in avionics
systems.
Keywords: Avionics, AFDX, Real-time, Optimal configuration.
1
189
2014 International Symposium on Embedded
Technology (ISET 2014)
A Study on Feasible
Configuration of AFDX Networks
for in Avionics Systems
Dongha An, Kyung-Chul Choi, Kyong Hoon Kim, Ki-Il Kim
Gyeongsang National University
South Korea
Real-Time Systems Laboratory
@
Contents
 Introduction
 Avionics, IMA, AFDX
 Virtual Link in AFDX
 System Model
 Virtual Link Model
 Parameters and Constraints of VLs
 Problem Definition
 The Proposed Solution
 Part 1: Schedulable BAG and MTU Pairs of a VL
 Part 2: Feasible BAG and MTU of VLs
 Performance Evaluation
 Conclusions
A Study on Feasible Configuration of AFDX Networks in Avionics Systems
190 ISET 2014
2
Memo
191
Memo
192 ISET 2014
Memo
193
Memo
194 ISET 2014

Keynote Speech

Transcription

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