Datasheet of HX8340

Transcription

Datasheet of HX8340

DATA SHEET
( DOC No. HX8340-B(N)-DS )
HX8340-B(N)
176RGB x 220 dot, 262k color,
with internal GRAM,
TFT Mobile Single Chip Driver
Preliminary version 01 October, 2007
HX8340-B(N)
176RGB x 220 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Contents
October, 2007
1. General Description..................................................................................................................................... 7
2. Features........................................................................................................................................................ 8
3. Block Diagram............................................................................................................................................ 10
4. Pin Description .......................................................................................................................................... 11
4.1 Pin Description ..................................................................................................................................11
4.2 Pin Assignment ................................................................................................................................ 16
4.3 PAD Coordinates .............................................................................................................................. 17
4.4 Alignment Mark................................................................................................................................. 22
4.5 Bump Size ......................................................................................................................................... 23
5. Interface...................................................................................................................................................... 24
5.1 System Interface Circuit .................................................................................................................. 25
5.1.1 8080-Series Parallel Bus.......................................................................................................... 26
5.1.2 6800-Series Parallel Interface.................................................................................................. 29
5.1.3 Serial Interface ......................................................................................................................... 32
5.1.4 Data Transfer Break and Recovery.......................................................................................... 35
5.1.5 Data Transfer Pause ................................................................................................................ 37
5.1.6 Data Transfer Modes................................................................................................................ 38
5.1.7 MCU Data Color Coding .......................................................................................................... 39
5.1.8 MCU Data Color Coding for RAM data Read .......................................................................... 54
5.1.9 Serial Interface Data Color Coding for RAM data Write........................................................... 59
5.1.10 Color Depth Conversion Look-up Tables ............................................................................... 62
5.2 RGB Interface.................................................................................................................................... 64
5.2.1 Color Order on RGB Interface ................................................................................................. 68
5.2.2 RGB Data Color Coding........................................................................................................... 69
6. Display Data GRAM ................................................................................................................................... 72
6.1 Display Data GRAM Mapping .......................................................................................................... 72
6.2 Address Counter (AC) of GRAM ..................................................................................................... 73
6.2.1 System interface to GRAM Write Direction.............................................................................. 74
6.3 GRAM to Display Address Mapping ............................................................................................... 79
6.3.1 Normal Display On or Partial Mode On, Vertical Scroll Off...................................................... 81
6.3.2 Vertical Scroll Display Mode..................................................................................................... 84
6.3.3 Updating Order on Display Active Area in RGB Interface Mode.............................................. 87
7. Functional Description.............................................................................................................................. 90
7.1 Internal Oscillator............................................................................................................................. 90
7.2 Gamma Characteristic Correction Function.................................................................................. 91
7.3 Tearing Effect Output Line ............................................................................................................ 101
7.3.1 Tearing Effect Line Modes...................................................................................................... 101
7.3.2 Tearing Effect Line Timing...................................................................................................... 102
7.3.3 Example 1: MPU Write is faster than Panel Read ................................................................. 103
7.3.4 Example 2: MPU Write is slower than Panel Read................................................................ 104
7.4 LCD Power Generation Circuit...................................................................................................... 105
7.4.1 Power Supply Circuit.............................................................................................................. 105
7.4.2 LCD Power Generation Scheme............................................................................................ 107
7.5 Power Function............................................................................................................................... 108
7.5.1 System Interface Power On/Off Sequence ............................................................................ 108
7.5.2 RGB Interface Power on/off ....................................................................................................112
7.5.3 Power Levels Definition...........................................................................................................114
7.6 Sleep Out – Command and Self-diagnostic Functions of Display Module ...............................116
7.6.1 Register Loading Detection.....................................................................................................116
7.6.2 Functionality Detection............................................................................................................117
7.7 Input / Output Pin State...................................................................................................................118
7.7.1 Output Pins .............................................................................................................................118
7.7.2 Input Pins ................................................................................................................................118
8. Command Set........................................................................................................................................... 119
8.1 Command Description ................................................................................................................... 124
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.1October, 2007
HX8340-B(N)
List of Contents
October, 2007
8.1.1 NOP........................................................................................................................................ 124
8.1.2 Software Reset (01h) ............................................................................................................. 125
8.1.3 Read Display Identification Information (04h) ........................................................................ 126
8.1.4 Read Display Status (09h) ..................................................................................................... 127
8.1.5 Read Display Power Mode (0Ah)........................................................................................... 131
8.1.6 Read Display MADCTL (0Bh) ................................................................................................ 133
8.1.7 Read Display Pixel Format (0Ch) .......................................................................................... 135
8.1.8 Read Display Image Mode (0Dh)........................................................................................... 137
8.1.9 Read Display Signal Mode (0Eh)........................................................................................... 139
8.1.10 Read Display Self-Diagnostic Result (0Fh).......................................................................... 140
8.1.11 Sleep In (10h) ....................................................................................................................... 141
8.1.12 Sleep Out (11h) .................................................................................................................... 143
8.1.13 Partial Mode On (12h).......................................................................................................... 145
8.1.14 Normal Display Mode On (13h) ........................................................................................... 146
8.1.15 Display Inversion Off (20h)................................................................................................... 147
8.1.16 Display Inversion On (21h) .................................................................................................. 148
8.1.17 Gamma Set (26h)................................................................................................................. 149
8.1.18 Display off (28h) ................................................................................................................... 150
8.1.19 Display on (29h) ................................................................................................................... 151
8.1.20 Column Address Set (2Ah)................................................................................................... 152
8.1.21 Page Address Set (2Bh)....................................................................................................... 154
8.1.22 Memory Write (2Ch)............................................................................................................. 156
8.1.23 Color Setting (2Dh) .............................................................................................................. 157
8.1.24 Memory Read (2Eh)............................................................................................................. 158
8.1.25 Partial Area (30h) ................................................................................................................. 160
8.1.26 Vertical Scrolling Definition (33h) ......................................................................................... 162
8.1.27 Tearing Effect Line Off (34h) ................................................................................................ 166
8.1.28 Tearing Effect Line On (35h) ................................................................................................ 167
8.1.29 Memory Access Control (36h).............................................................................................. 168
8.1.30 Vertical Scrolling Start Address (37h)................................................................................... 170
8.1.31 Idle Mode Off (38h) .............................................................................................................. 172
8.1.32 Idle Mode On (39h) .............................................................................................................. 173
8.1.33 Interface Pixel Format (3Ah) ................................................................................................ 175
8.1.34 Read ID1 (DAh).................................................................................................................... 176
8.1.35 Read ID2 (DBh).................................................................................................................... 177
8.1.36 Read ID3 (DCh) ................................................................................................................... 178
8.1.37 SETOSC: Set Internal Oscillator (B0h) ................................................................................ 179
8.1.38 SETPWCTR1: Set Power Control 1(B1h)............................................................................ 180
8.1.43 SETDISCTRL: Set Display Control (B6h) ............................................................................ 188
8.1.44 SETFRMCTRL: Set Frame Rate Control (B7h)................................................................... 191
8.1.45 SETDISCYCCTRL: Set Display Cycle Control (B8h) .......................................................... 193
8.1.46 SETINVCTRL: Set Display Inversion Control (B9h) ............................................................ 195
8.1.47 RGBBPCTR: Set RGB Interface Blanking Porch (BAh) ...................................................... 196
8.1.48 SETRGBIF: Set RGB Interface Related Register (BBh)...................................................... 197
8.1.49 SETDODC: Set Driver Output Direction Control (BCh) ....................................................... 198
8.1.50 SETINTMODE: Set Interface Mode (BDh)........................................................................... 199
8.1.51 SETPANEL: Set Panel (BEh)............................................................................................... 200
8.1.52 SETOTP: Set OTP Related Setting (RBFh)......................................................................... 201
8.1.53 SETONOFF: Set Chip On/Off (C0h) .................................................................................... 202
8.1.54 SETEXTCOM: Set extended command set (C1h)............................................................... 203
8.1.55 SETGAMMAP: Set “+” polarity Gamma Curve GC0 Related Setting (C2h)........................ 204
Himax Confidential
-P.2October, 2007
HX8340-B(N)
List of Contents
October, 2007
8.1.56 SETGAMMAN: Set “-” polarity Gamma Curve GC0 Related Setting (C3h) ........................ 205
9. Layout Recommendation........................................................................................................................ 206
9.1 Parallel Interface of Command-Parameter Mode ........................................................................ 206
9.2 RGB + SPI Interface of Command-Parameter ............................................................................. 207
10. OTP ......................................................................................................................................................... 208
11. Electrical Characteristic........................................................................................................................ 210
11.1 Absolute Maximum Ratings ........................................................................................................ 210
11.2 ESD Protection Level ................................................................................................................... 210
11.3 Latch-Up Protection Level ........................................................................................................... 210
11.4 Light Sensitivity............................................................................................................................ 210
11.5 Maximum Layout Resistance .......................................................................................................211
11.6 DC Characteristics ....................................................................................................................... 212
11.6.1 Current Consumption ........................................................................................................... 213
11.7 AC CHARACTERISTICS ............................................................................................................... 214
11.7.1 Parallel Interface Characteristics (8080-series MPU) .......................................................... 214
11.7.2 Parallel Interface Characteristics (6800-series MPU) .......................................................... 216
11.7.3 Serial Interface Characteristics ............................................................................................ 217
11.7.4 RGB Interface Characteristics.............................................................................................. 218
11.7.5 Reset Input Timing ............................................................................................................... 220
11.7.6 Measurement Conditions ..................................................................................................... 221
12. Ordering Information............................................................................................................................. 223
13. Revision History .................................................................................................................................... 223
Himax Confidential
-P.3October, 2007
HX8340-B(N)
List of Figures
October, 2007
Figure 5. 1 8080-Series NWR_RNW Protocol .................................................................................. 27
Figure 5. 2 8080-Series parallel bus protocol, Write to register or display RAM .............................. 27
Figure 5. 3 8080-Series NRD Protocol ............................................................................................. 28
Figure 5. 4 8080-Series parallel bus protocol, Read data from register or display RAM.................. 28
Figure 5. 5 6800-Series Write Protocol ............................................................................................. 30
Figure 5. 6 6800-Series parallel bus protocol, Write to register or display RAM .............................. 30
Figure 5. 7 6800-Series Read Protocol............................................................................................. 31
Figure 5. 8 6800-Series parallel bus protocol, Read data from register or display RAM.................. 31
Figure 5. 9 Serial interface data Stream format ................................................................................ 32
Figure 5. 10 Serial interface Write protocol (Write to register with control bit in transmission) ........ 33
Figure 5. 11 Serial interface Read protocol....................................................................................... 34
Figure 5. 12 Serial bus protocol, write mode – interrupted by NRESET .......................................... 35
Figure 5. 13 Serial bus protocol, write mode – interrupted by NCS.................................................. 35
Figure 5. 14 Write interrupts recovery (serial interface).................................................................... 36
Figure 5. 15 Write interrupts recovery (both serial and parallel interface) ........................................ 36
Figure 5. 16 Serial bus protocol, write mode – paused by NSC ....................................................... 37
Figure 5. 17 Parallel bus protocol, write mode – paused by NCS .................................................... 37
Figure 5. 18 Example of I80- / M68- System 8-Bit Parallel Bus Interface ........................................ 40
Figure 5. 19 Example of I80- / M68- System 16-Bit Parallel Bus Interface ...................................... 44
Figure 5. 20 Example of I80- / M68- System 9-Bit Parallel Bus Interface ........................................ 48
Figure 5. 21 Example of I80- / M68- System 18-Bit Parallel Bus Interface ...................................... 50
Figure 5. 22 DOTCLK Cycle ............................................................................................................. 64
Figure 5. 23 RGB Interface Circuit Input Timing Diagram ................................................................ 65
Figure 5. 24 RGB Mode timing Diagram........................................................................................... 66
Figure 6. 2 Image Data Sending Order from the Host ...................................................................... 74
Figure 6. 3 Image Data Writing Control ............................................................................................ 74
Figure 6. 4 Example for rotation with MY, MX and MV – 1............................................................... 77
Figure 6. 5 Example for rotation with MY, MX and MV - 2................................................................ 78
Figure 6. 6 Example of partial mode on (ML=’0’) .............................................................................. 82
Figure 6. 7 Example of partial mode on (ML=’1’) .............................................................................. 82
Figure 6. 8 Vertical Scrolling ............................................................................................................. 84
Figure 6. 9 Memory Map of Vertical Scrolling I ................................................................................. 84
Figure 6. 10 Memory Map of Vertical Scrolling II .............................................................................. 85
Figure 6. 11 Memory Map of Vertical Scrolling III ............................................................................. 85
Figure 6. 12 Vertial scroll example when ML=’0’ .............................................................................. 86
Figure 6. 13 Vertial scroll example when ML=’1’ .............................................................................. 86
Figure 6. 14 Data Streaming Order in RGB I/F................................................................................. 87
Figure 6. 15 Updating order when TB = ‘L’ and RL = ‘L’................................................................... 88
Figure 6. 16 Updating order when TB = ‘L’ and RL = ‘H’ .................................................................. 88
Figure 6. 17 Updating order when TB = ‘H’ and RL = ‘L’ .................................................................. 89
Figure 6. 18 Updating order when TB = ‘H’ and RL = ‘H’ ................................................................. 89
Figure 7. 1 HX8340-B Internal Clock Circuit ..................................................................................... 90
Figure 7. 2 Grayscale Control ........................................................................................................... 91
Figure 7. 3 Structure of Grayscale Voltage Generator...................................................................... 92
Figure 7. 4 Gamma Resister Stream and Gamma Reference Voltage ............................................ 94
Figure 7. 5 Relationship between Source Output and VCOM .......................................................... 99
Figure 7. 6 Relationship between GRAM Data and Output Level (Normal white panel and INVON=“0”)
................................................................................................................................................... 99
Figure 7. 7 Gamma Curve according to the GC0 to GC3 bit .......................................................... 100
Figure 7. 8 TE mode 1 output ......................................................................................................... 101
Figure 7. 9 TE mode 2 output ......................................................................................................... 101
Figure 7. 10 TE output waveform.................................................................................................... 101
Figure 7. 11 Waveform of Tearing Effect Signal ............................................................................. 102
Himax Confidential
-P.4October, 2007
HX8340-B(N)
List of Figures
October, 2007
Figure 7. 12 Timing of Tearing Effect Signal................................................................................... 102
Figure 7. 17 The Block Diagram of HX8340-B Power Circuit ......................................................... 105
Figure 7. 18 LCD Power Generation Scheme ................................................................................ 107
Figure 7. 19 Case 1 – NRESET Line is Held High or Unstable by Host at Power On.................... 109
Figure 7. 20 NRESET Line is Held Low by Host at Power On ........................................................110
Figure 7. 21 Power On Sequence on RGB......................................................................................112
Figure 7. 22 Power OFF Sequence on RGB Mode .........................................................................113
Figure 7. 23 Power Flow Chart for Different Power Modes (RCM[1:0] = ‘0x’) .................................114
Figure 7. 24 Power Flow Chart for Different Power Modes (RCM[1:0] = ‘10’ or ‘11’) ......................115
Figure 7. 25 Register Loading Detection Flow.................................................................................116
Figure 7. 26 Functionality Detection Flow........................................................................................117
Figure 9. 1 Layout Recommendation of System Interface.............................................................. 206
Figure 9. 2 Layout Recommendation of RGB Interface.................................................................. 207
Figure 11. 1 Parallel Interface Characteristics (8080-series MPU)................................................. 214
Figure 11. 2 Chip Select Timing ...................................................................................................... 215
Figure 11. 3 Write to Read and Read to Write Timing .................................................................... 215
Figure 11. 4 Parallel Interface Characteristics (6800-series MPU)................................................. 216
Figure 11. 5 Serial Interface Characteristics ................................................................................... 217
Figure 11. 6 Reset Input Timing ...................................................................................................... 220
Himax Confidential
-P.5October, 2007
HX8340-B(N)
List of Tables
October, 2007
Table 5. 1 Pin connection According to MCU Interface Type Selection ............................................ 25
Table 5. 2 The function of 8080-series parallel interface .................................................................. 26
Table 5. 3 The function of 6800-series parallel interface .................................................................. 29
Table 5. 4 Serial Interface Type Selection......................................................................................... 32
Table 5. 5 8-Bits Parallel Interface Set Table .................................................................................... 39
Table 5. 6 16-Bits Parallel Interface Set Table .................................................................................. 39
Table 5. 8 18-Bits Parallel Interface Set Table .................................................................................. 39
Table 5. 1016-Bits Parallel Interface Set Table ................................................................................. 54
Table 5. 11 9-Bits Parallel Interface Set Table................................................................................... 54
Table 5. 12 18-Bits Parallel Interface Set Table ................................................................................ 54
Table 5. 13 Look-up Tables for 4k color mode .................................................................................. 62
Table 5. 14 Look-up Tables for 65k color mode ................................................................................ 63
Table 5. 16 RGB interface Bus Width Set Table ............................................................................... 67
Table 5. 17 Meaning of the Pixel Information for main colors on RGB Interface .............................. 68
Table 6. 1 GRAM Address for Display Panel Position ...................................................................... 72
Table 6. 2 CASET and PASET Control for Physical Column/Page Pointers .................................... 74
Table 6. 3 Rules for Updating GRAM Order...................................................................................... 75
Table 6. 4 Address Direction Settings ............................................................................................... 76
Table 6. 5 GRAM X Address and Display Panel Position ................................................................. 79
Table 6. 6 GRAM Address and Display Panel Position ( SMY =’L’ ) ................................................. 80
Table 6. 7 GRAM Address and Display Panel Position (SMY =’H’) .................................................. 80
Table 6. 8 ISC[3:0] Bits Definition...................................................................................................... 83
Table 6. 9 Rules for Updating Order On Display Active Area in RGB Interface Display Mode......... 89
Table 7. 1 Gamma-Adjustment Registers ......................................................................................... 93
Table 7. 2 Offset Adjustment 0 Table 7. 3 Offset Adjustment 1 .................................................... 95
Table 7. 4 Gamma Center Resistance Adjustment ........................................................................... 95
Table 7. 5 Output Voltage of 8 to 1 Selector ..................................................................................... 96
Table 7. 6 Gamma Voltage Calculation Formula .............................................................................. 97
Table 7. 7 Voltage Calculation Formula of Grayscale Voltage.......................................................... 98
Table 7. 8 Voltage Calculation Formula of Grayscale Voltage V2~V7 and V56~V61....................... 98
Table 7. 9 AC characteristics of Tearing Effect Signal.................................................................... 102
Table 7. 10 The adoptability of Capacitor........................................................................................ 106
Table 7. 11 The adoptability of Diode .............................................................................................. 106
Table 7. 12 RGB mode Power ON AC Characteristics ....................................................................112
Table 7. 13 RGB mode Power OFF AC Characteristics ..................................................................113
Table 7. 14 Characteristics of Output Pins.......................................................................................118
Table 7. 15 Characteristics of Input Pins..........................................................................................118
P98. Modify Table 7. 16 Voltage Calculation Formula of Grayscale Voltage V2~V7 and V56~V61 223
Table 11. 1 Absolute Maximum Ratings .......................................................................................... 210
Himax Confidential
-P.6October, 2007
HX8340-B(N)
Preliminary Version 01
October, 2007
1. General Description
This document describes HX8340-B 176RGBx220 dots resolution driving controller. The
HX8340-B is designed to provide a single-chip solution that combines a gate driver, a source
driver, power supply circuit for 262,144 colors to drive a TFT panel with 176RGBx220 dots at
maximum.
The HX8340-B can be operated in low-voltage (1.65V) condition for the interface and integrated
internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage
follower circuit for liquid crystal driver. In addition, The HX8340-B also supports various
functions to reduce the power consumption of a LCD system via software control.
The HX8340-B supports three interface groups: Command-Parameter interface group,
Register-Content interface group and RGB interface mode. Command-Parameter interface
mode and Register-Content interface mode are selected by the external pin IFSEL setting, and
RGB interface mode is selected by external RCM[1:0] pins. This manual description focuses on
Command-Parameter interface mode and RGB interface mode, about the Register-Content
interface mode; please refer to the HX8340-B(T) datasheet for detail.
Himax Confidential
-P.7October, 2007
HX8340-B(N)
176RGB x 220 dot, 262K color, TFT Mobile Single Chip Driver
DATA SHEET Preliminary V01
2. Features
l Single chip solution to drive a a-TFT LCD panel
l Display Resolution: 176(H) x RGB(H) x 220(V)
l Display Color modes (Command-Parameter interface mode.( IFSEL= ‘H’ ) and RGB
interface mode)
l Normal Display Mode On
a. System Interface Circuit
i. 4096(R(4),G(4),B(4)) colors
ii.65,536(R(5),G(6),B(5)) colors
iii.262,144(R(6),G(6),B(6)) color
b. RGB Interface Circuit
i. 65,536(R(5),G(6),B(5)) colors
ii. 262,144(R(6),G(6),B(6)) colors
l Idle Mode On
a. 8 (R(1),G(1),B(1)) colors.
l Outputs
l Source outputs: 528 source lines.
l Selectable gate line control signal for glass 220 gate lines
l Adjusted source voltages ( V0p ~V63p, V0n ~V63n)
l Display interface:
— System interface:
a. 8-/9-/16-/18-bit parallel bus system interface
b. 3-wires serial bus system interface
— RGB interface:
a. 6-/16-/18-bit RGB interface
l Internal graphics RAM capacity: 176 x18x220 bit = 696960bits
l Display features
l The vertical scroll display function in line units
l Partial area display mode.
l Software programmable color depth mode
l On chip
l OTP memory to store initialization register settings
l Automatic malfunction recovery for default values (OTP table and other default values
reloading after Sleep Out, HW / SW)
l 4 selectable electro-optical transfer function for all R, G, B data (Gamma)
l Internal oscillator and hardware reset function
l DC/DC converter and charge bump circuit for source, glass gate driving voltage
l Adjust AC VCOM generation
Himax Confidential
-P.8October, 2007
HX8340-B(N)
l LCD Driving Inversion Algorithm
— Frame inversion AC liquid-crystal drive
— 1~7 line inversion AC liquid-crystal drive
l Input power supply
— IOVCC = 1.65 to 3.3V (Logic IO power supply voltage range)
— VCI = 2.5 to 3.3V (Driver power supply voltage range)
l Output voltage levels
— DDVDH = 5.2 V (Power supply for driver circuit range)
— VREG1 = 3.3V to 4.8V (Source output voltage range)
— VGH = +9.0 to +15.6V (Positive Gate output voltage range)
— VGL = -6.0 to -13.5V (Negative Gate output voltage range)
— VCOMH = 2.5V to 5.0V (Common electrode output high voltage)
— VCOML = -2.5V to 0.0V (Common electrode output low voltage)
l
l
l
l
Low power consumption, suitable for battery operated systems
CMOS compatible inputs
Chip on Glass or Chip on Foil
Operating temperature range : -40℃~ 85℃
Himax Confidential
-P.9October, 2007
HX8340-B(N)
3. Block Diagram
S1 ~ S528
IOVCC
Internal
register
IM 3~0, IFSEL0
EXTC
NCS
NRD_E
NWR_RNW
DNC
D17~0
Source
driver
7
MPU IF
18-bit
16-bit
9-bit
8-bit
OTP
D/A Converter
circuit
18
SDI
SDO
Serial IF
GRAM control
RGB IF
18-bit
16-bit
6-bit
GRAM
Data Latch
DE
VS
HS
DOTCLK
NRESET
TEST3~1
Mode
selection
3
V0~63
VREG1
RL
TB
SHUT
REV
IDM
Grayscale voltage
generator
VTEST
VMONI
Timing
Control
VCI
Gamma adjusting circuit
Power
Regulator
Gate
Driver
VDDD
G1~G220
VGH/VGL
OSC
VSSD
Generator Timing
Step Up1
VSSA
Step Up2
Step Up3
VCOM Cricuit
Himax Confidential
-P.10October, 2007
HX8340-B(N)
4. Pin Description
4.1 Pin Description
Signals
I/O
IM3, IM2, IM1, IM0
I
NRESET
I
NCS
I
DNC
I
NRD(E)
I
NWR(RNW)(SCL)
I
SDI
I
SDO
O
DB[17:0]
I/O
VS
I
HS
I
DE
I
DOTCLK
I
TE
O
Interface Logic Pin
Pin
Connected
Description
Number
with
VSSD/
System interface select. Please refer to section 5.1.1 and 5.1.2
4
IOVCC
to detail. If not used, please fix this pin to IOVCC or VSSD level.
Reset pin. Setting either pin low initializes the LSI. Must be
1
MCU
reset after power is supplied.
Chip select input pin.
1
MPU
Low: chip can be accessed;
High: chip cannot be accessed.
Command / parameter or display data selection pin in parallel
1
MCU
bus system interface.
If not used, please fix this pin at IOVCC or GND level.
(NRD) Read enable pin I80 parallel bus system interface.
(E) Read/Write operation enable pin in M68 parallel bus
1
MCU
system interface.
If not used, please fix this pin at IOVCC or GND level
(NWR) Write enable pin I80 parallel bus system interface.
(RNW) Read/Write select pin in M68 parallel bus system
interface.
1
MCU
(SCL) server as serial data clockin serial bus system interface.
Serial data input pin in serial bus system interface. The data is
MCU
1
inputted on the rising edge of the SCL signal.
Serial data output pin in serial bus system interface. The data is
outputted on the falling edge of SCL signal. SDI and SDO pins
MCU
are possible to connect together outside of driver IC as one
1
SDA line.
If not used, please let this pin floating.
Input data bus
18
MCU
If not used, please fix this pin at GND level.
Vertical synchronizing signal in RGB interface. Has to be fixed
1
MCU
to IOVCC level if it is not used.
Horizontal synchronizing signal. Has to be fixed to IOVCC level
1
MCU
if it is not used.
Data enable signal in RGB interface. Has to be fixed to VSSD
1
MCU
level if it is not used.
Pixel clock signal in RGB interface. Has to be fixed to VSSD
1
MCU
level if is not used.
Tearing effect output pin to synchronies MCU to frame writing,
1
MCU
activated by S/W command.
When this pin is not activated (TE function off), this pin is low.
Himax Confidential
-P.11October, 2007
HX8340-B(N)
Signals
I/O
Mode Select Pins
Pin
Connected
Description
Number
with
Interface format select pin
IFSEL
I
1
MPU
EXTC
I
1
MPU
RCM1, RCM0
I
2
MCU
IFSEL
0
1
Interface Format Selection
RCM1, RCM0
0x
10
11
MCU and RGB Interface Mode Select
System Interface (1)
RGB Interface (1) (VS+HS+DE)
RGB Interface (2) (VS+HS)
Register-content interface mode
Command-Parameter interface mode
In this document, the IFSEL has to be connected to IOVCC and
Command-Parameter interface mode is select.
Extended command set access enable bit in
Command-Parameter interface mode.
Low: extended command set can not be accessed.
High: extended command set can be accessed.
Internal pull low.
RGB and System interface mode selection pin.
As internal RCM[1:0] bits are written, the external pin RCM[1:0]
control is invalid, and RGB and System interface mode
selection is controlled by internal RCM[1:0] bits.
If not used, please fix this pin to IOVCC or GND.
RGB direction select H/W pin for Color filter default setting.
SRGB
I
1
MCU
SRGB
0
1
RGB Filter Order for Color Filter Default Setting
S1, S2, S3 filter order = ’B’, ‘G’, ‘R’
S1, S2, S3 filter order = ’R’, ‘G’, ‘B’
Module source output direction H/W select pin.
SMX
I
1
MCU
SMX
0
1
Module Source Output Direction
S528 -> S1
S1 -> S528
Module Gate output direction H/W select pin.
SMY
I
1
MCU
SMY
0
1
Module Gate Output Direction
G1 -> G220
G220 -> G1
Normal mode and Idle mode control pin in RGB I/F.
IDM
0
1
IDM
I
1
MCU
Idle Mode H/W Controller
Normal display (can be changed to Idle mode by S/W)
Into Idle mode
As internal IDMON /IDMOFF commands are written in RGB
interface, the external pin IDM control is invalid, and normal and
idle mode selection is controlled by internal IDMON/IDMOFF
commands.
Chip On/ Off H/W control pin in RGB I/F.
SHUT
I
1
MCU
SHUNT
0
1
Display On/Off in RGB I/F
Display On
Display Off
As internal CSHUT commands be written in RGB interface, the
external pin SHUT control is invalid, and chip on/off selection is
controlled by internal CSHUT commands.
Himax Confidential
-P.12October, 2007
HX8340-B(N)
Signals
RL
TB
REV
I/O
I
I
I
Mode Select Pins
Pin
Connected
Description
Number
with
Source output direction H/W select pin in RGB I/F.
1
1
1
MCU
MCU
MCU
RL
0
1
Normal Direction
Reverse Direction
As internal CRL bit be written in RGB interface, the external pin
RL control is invalid, and CRL is operated based on external pin
SMX setting.
Gate output direction H/W select pin in RGB I/F.
TB
0
1
Normal Direction
Reverse Direction
As internal CTB bit be written in RGB interface, the external pin
TB control is invalid, and CRL is operated based on external pin
SMY setting.
Source output data polarity select H/W pin.
REV
0
1
Source Output Data Polarity
Data not reverse
Data reverse
As internal INVON /INVOFF commands are written, the external
pin REV control is invalid, and INVON /INVOFF commands are
operated based on internal NB bit setting.
Himax Confidential
-P.13October, 2007
HX8340-B(N)
Driver Output Pins
Signals
I/O
Pin
Number
S1~S528
G1~G220
O
O
528
220
IOVCC
VCI
P
P
1
1
VSSD
VSSA
P
P
1
1
VPP_OTP
P
1
C11A,C11B
I/O
2
C12A,C12B
I/O
2
C21A,C21B
C22A,C22B
I/O
4
VDDD
O
1
VREG1
O
1
VCOM
O
1
VCOMH
O
1
VCOML
O
1
VCOMR
I
1
VCL
O
1
DDVDH
O
1
VGH
O
1
VGL
O
1
Connected
with
LCD
LCD
Description
Source driver output pins.
Gate driver output pins.
Power Supply Digital IO Pad power supply. IOVCC = 1.65 ~ 3.3V
Power Supply Analog power supply. VCI = 2.5 ~ 3.3V
Ground
Ground
Digital ground
Analog ground
Power supply pin used in OTP program mode and operates at
Power supply 6.5V ± 0.2.
If not in OTP program mode, please let it open.
Connect to the step-up capacitors for step up circuit 1
Step-up
operation (DDVDH). Leave this pin open if the internal step-up
Capacitor
circuit is not used.
Step-up
operation (VCL). Leave this pin open if the internal step-up
Capacitor
circuit is not used.
Step-up
operation (VGH, VGL). Leave this pin open if the internal
Capacitor
step-up circuit is not used.
Stabilizing Output from internal logic voltage (1.6V). Connect to a
Capacitor stabilizing capacitor
Stabilizing
Internal generated stable power for source driver unit.
Capacitor
The power supply of common voltage in TFT driving. The
TFT common
voltage amplitude between VCOMH and VCOML is output.
electrode
Connect this pin to the common electrode in TFT panel.
Connect this pin to the capacitor for stabilization. This pin
Stabilizing
indicates a high level of VCOM amplitude generated in driving
capacitor
the VCOM alternation.
When the VCOM alternation is driven, this pin indicates a low
Stabilizing
level of VCOM amplitude. Connect this pin to a capacitor for
capacitor
stabilization.
A VCOMH reference voltage input. When adjusting VCOMH
Resistor or externally, set registers to halt the VCOMH internal adjusting
open
circuit and connect a variable resistor between VREG1 and
GND for VCOMH adjusting.
Stabilizing
A negative voltage of VCI x (-1) output for VCOML circuit.
capacitor
A power output from the step-up circuit1.
Stabilizing
Connect to a stabilizing capacitor between GND and DDVDH.
capacitor
DDVDH =5.2V (typ.) when VCI = 2.8V.
A positive power output from the step-up circuit 2 for the gate
line drive circuit.
Stabilizing
The step-up rate is determined by BT3-0 bits. Connect to a
capacitor
stabilizing capacitor between GND and VGH.
VGH=max 15.6V
A negative power output from the step-up circuit 2 for the gate
line drive circuit.
Stabilizing The step-up rate is determined by BT(3-0) bits. Connect to a
capacitor
stabilizing capacitor between GND and VGL, and insert a
schottkey barrier diode between GND and VGL.
VGL=min -13.5V
Himax Confidential
-P.14October, 2007
HX8340-B(N)
Signals
I/O
Pin
Number
OSC
I
1
TEST5-1
REGVDD
VMONI
VTEST
DUMMY1-44
I
I
O
O
-
5
1
1
1
32
Test pin and others
Connected
with
Description
External oscillator clock input with internal pull-low circuit. That
External
input is valid in test mode enable. Left it opens in normal
Clock / Open
operation mode.
GND
Test pin input (Internal pull low)
Open
Test pin. Left it opens in normal operation mode.
Open
A test pin. Disconnect it.
Open
Gamma voltage of Panel test pin output. Must be left open.
Open
Dummy pads, Dummy 18 and Dummy 19 are connection pins
Himax Confidential
-P.15October, 2007
HX8340-B(N)
4.2 Pin Assignment
Himax Confidential
-P.16October, 2007
HX8340-B(N)
4.3 PAD Coordinates
No.
Pad name
X
Y
No.
Pad name
X
Y
No.
Pad name
X
Y
No.
Pad name
X
Y
1
2
DUMMY1
DUMMY2
-6695
-6635
-257
-257
61
62
C11B
C11B
-3095
-3035
-257
-257
121
122
NWR/SCL
DB17
505
565
-257
-257
181
182
VDDD
VDDD
4655
4715
-257
-257
3
VCOM
-6575
-257
63
C11B
-2975
-257
123
DB16
650
-257
183
VDDD
4775
-257
4
5
VCOM
VCOM
-6515
-6455
-257
-257
64
65
C11B
C11B
-2915
-2855
-257
-257
124
125
DB15
DB14
735
820
-257
-257
184
185
VDDD
VDDD
4835
4895
-257
-257
6
VCOM
-6395
-257
66
VPP_OTP
-2795
-257
126
DB13
905
-257
186
VDDD
4955
-257
7
DUMMY3
-6335
-257
67
VPP_OTP
-2735
-257
127
DB12
990
-257
187
VDDD
5015
-257
8
9
VGH
VGH
-6275
-6215
-257
-257
68
69
VPP_OTP
VPP_OTP
-2675
-2615
-257
-257
128
129
DB11
DB10
1075
1160
-257
-257
188
189
VDDD
VDDD
5075
5135
-257
-257
10
VGH
-6155
-257
70
VPP_OTP
-2555
-257
130
DB9
1245
-257
190
IOVCC
5195
-257
11
12
VGH
VGH
-6095
-6035
-257
-257
71
72
VPP_OTP
DUMMY12
-2495
-2435
-257
-257
131
132
DB8
DB7
1330
1415
-257
-257
191
192
IOVCC
IOVCC
5255
5315
-257
-257
13
DUMMY4
-5975
-257
73
DUMMY13
-2375
-257
133
DB6
1500
-257
193
IOVCC
5375
-257
14
VGL
-5915
-257
74
DUMMY14
-2315
-257
134
DB5
1585
-257
194
IOVCC
5435
-257
15
16
VGL
VGL
-5855
-5795
-257
-257
75
76
DUMMY15
DUMMY16
-2255
-2195
-257
-257
135
136
DB4
DB3
1670
1755
-257
-257
195
196
IOVCC
TEST1
5495
5555
-257
-257
17
VGL
-5735
-257
77
DUMMY17
-2135
-257
137
DB2
1840
-257
197
TEST2
5615
-257
18
19
VGL
DUMMY5
-5675
-5615
-257
-257
78
79
C12A
C12A
-2075
-2015
-257
-257
138
139
DB1
DB0
1925
2010
-257
-257
198
199
VREG1
VREG1
5675
5735
-257
-257
20
C22A
-5555
-257
80
C12A
-1955
-257
140
IM3
2095
-257
200
VREG1
5795
-257
21
C22A
-5495
-257
81
C12A
-1895
-257
141
IM2
2155
-257
201
VREG1
5855
-257
22
23
C22A
C22B
-5435
-5375
-257
-257
82
83
C12A
C12B
-1835
-1775
-257
-257
142
143
IM1
IM0
2215
2275
-257
-257
202
203
VCOMH
VCOMH
5915
5975
-257
-257
24
C22B
-5315
-257
84
C12B
-1715
-257
144
SDO
2335
-257
204
VCOML
6035
-257
25
26
C22B
C21A
-5255
-5195
-257
-257
85
86
C12B
C12B
-1655
-1595
-257
-257
145
146
REGVDD
TE
2420
2505
-257
-257
205
206
VCOML
VCOMR
6095
6155
-257
-257
27
C21A
-5135
-257
87
C12B
-1535
-257
147
EXTC
2590
-257
207
Dummy18
6215
-257
28
29
C21A
C21B
-5075
-5015
-257
-257
88
89
DDVDH
DDVDH
-1475
-1415
-257
-257
148
149
SRGB
SMX
2675
2735
-257
-257
208
209
Dummy19
TEST3
6275
6335
-257
-257
30
C21B
-4955
-257
90
DDVDH
-1355
-257
150
SMY
2795
-257
210
VCOM
6395
-257
31
C21B
-4895
-257
91
DDVDH
-1295
-257
151
IFSEL
2855
-257
211
VCOM
6455
-257
32
33
VTEST
VMONI
-4835
-4775
-257
-257
92
93
DDVDH
DDVDH
-1235
-1175
-257
-257
152
153
RCM0
RCM1
2915
2975
-257
-257
212
213
VCOM
VCOM
6515
6575
-257
-257
34
VSSD
-4715
-257
94
DDVDH
-1115
-257
154
IDM
3035
-257
214
TEST4
6635
-257
35
36
VSSD
VSSD
-4655
-4595
-257
-257
95
96
DDVDH
VCI
-1055
-995
-257
-257
155
156
SHUT
RL
3095
3155
-257
-257
215
216
TEST5
Dummy20
6695
6772
-257
236
37
VSSD
-4535
-257
97
VCI
-935
-257
157
TB
3215
-257
217
Dummy21
6756
116
38
VSSD
-4475
-257
98
VCI
-875
-257
158
REV
3275
-257
218
Dummy22
6740
236
39
40
VSSD
VSSD
-4415
-4355
-257
-257
99
100
VCI
VCI
-815
-755
-257
-257
159
160
VSSA
VSSA
3335
3395
-257
-257
219
220
Dummy23
G2
6724
6708
116
236
41
VSSD
-4295
-257
101
VCI
-695
-257
161
VSSA
3455
-257
221
G4
6692
116
42
43
VSSD
VSSD
-4235
-4175
-257
-257
102
103
VCI
VCI
-635
-575
-257
-257
162
163
VSSA
VSSA
3515
3575
-257
-257
222
223
G6
G8
6676
6660
236
116
44
DUMMY6
-4115
-257
104
VCI
-515
-257
164
VSSA
3635
-257
224
G10
6644
236
45
DUMMY7
-4055
-257
105
VCI
-455
-257
165
VSSA
3695
-257
225
G12
6628
116
46
47
DUMMY8
DUMMY9
-3995
-3935
-257
-257
106
107
VCL
VCL
-395
-335
-257
-257
166
167
VSSD
VSSD
3755
3815
-257
-257
226
227
G14
G16
6612
6596
236
116
48
DUMMY10
-3875
-257
108
VCL
-275
-257
168
VSSD
3875
-257
228
G18
6580
236
49
50
DUMMY11
C11A
-3815
-3755
-257
-257
109
110
VCL
VCL
-215
-155
-257
-257
169
170
VSSD
VSSD
3935
3995
-257
-257
229
230
G20
G22
6564
6548
116
236
51
C11A
-3695
-257
111
OSC
-95
-257
171
VSSD
4055
-257
231
G24
6532
116
52
C11A
-3635
-257
112
DNC
-35
-257
172
VSSD
4115
-257
232
G26
6516
236
53
54
C11A
C11A
-3575
-3515
-257
-257
113
114
NCS
VS
25
85
-257
-257
173
174
VSSD
VSSD
4175
4235
-257
-257
233
234
G28
G30
6500
6484
116
236
55
C11A
-3455
-257
115
HS
145
-257
175
VSSD
4295
-257
235
G32
6468
116
56
57
C11A
C11A
-3395
-3335
-257
-257
116
117
DOTCLK
DE
205
265
-257
-257
176
177
VSSD
VSSD
4355
4415
-257
-257
236
237
G34
G36
6452
6436
236
116
58
C11B
-3275
-257
118
NRESET
325
-257
178
VDDD
4475
-257
238
G38
6420
236
59
60
C11B
C11B
-3215
-3155
-257
-257
119
120
SDI
NRD
385
445
-257
-257
179
180
VDDD
VDDD
4535
4595
-257
-257
239
240
G40
G42
6404
6388
116
236
Himax Confidential
-P.17October, 2007
HX8340-B(N)
No.
241
242
Pad name
X
Y
X
Y
X
Y
X
Y
G164
G166
5412
5396
116
236
S506
S505
4452
4436
116
236
No.
421
422
Pad name
116
236
No.
361
362
Pad name
6372
6356
No.
301
302
Pad name
G44
G46
S446
S445
3492
3476
116
236
243
244
G48
G50
6340
6324
116
236
303
304
G168
G170
5380
5364
116
236
363
364
S504
S503
4420
4404
116
236
423
424
S444
S443
3460
3444
116
236
245
G52
6308
116
305
G172
5348
116
365
S502
4388
116
425
S442
3428
116
246
G54
6292
236
306
G174
5332
236
366
S501
4372
236
426
S441
3412
236
247
248
G56
G58
6276
6260
116
236
307
308
G176
G178
5316
5300
116
236
367
368
S500
S499
4356
4340
116
236
427
428
S440
S439
3396
3380
116
236
249
G60
6244
116
309
G180
5284
116
369
S498
4324
116
429
S438
3364
116
250
251
G62
G64
6228
6212
236
116
310
311
G182
G184
5268
5252
236
116
370
371
S497
S496
4308
4292
236
116
430
431
S437
S436
3348
3332
236
116
252
G66
6196
236
312
G186
5236
236
372
S495
4276
236
432
S435
3316
236
253
G68
6180
116
313
G188
5220
116
373
S494
4260
116
433
S434
3300
116
254
255
G70
G72
6164
6148
236
116
314
315
G190
G192
5204
5188
236
116
374
375
S493
S492
4244
4228
236
116
434
435
S433
S432
3284
3268
236
116
256
G74
6132
236
316
G194
5172
236
376
S491
4212
236
436
S431
3252
236
257
258
G76
G78
6116
6100
116
236
317
318
G196
G198
5156
5140
116
236
377
378
S490
S489
4196
4180
116
236
437
438
S430
S429
3236
3220
116
236
259
G80
6084
116
319
G200
5124
116
379
S488
4164
116
439
S428
3204
116
260
261
G82
G84
6068
6052
236
116
320
321
G202
G204
5108
5092
236
116
380
381
S487
S486
4148
4132
236
116
440
441
S427
S426
3188
3172
236
116
262
G86
6036
236
322
G206
5076
236
382
S485
4116
236
442
S425
3156
236
263
G88
6020
116
323
G208
5060
116
383
S484
4100
116
443
S424
3140
116
264
265
G90
G92
6004
5988
236
116
324
325
G210
G212
5044
5028
236
116
384
385
S483
S482
4084
4068
236
116
444
445
S423
S422
3124
3108
236
116
266
G94
5972
236
326
G214
5012
236
386
S481
4052
236
446
S421
3092
236
267
268
G96
G98
5956
5940
116
236
327
328
G216
G218
4996
4980
116
236
387
388
S480
S479
4036
4020
116
236
447
448
S420
S419
3076
3060
116
236
269
G100
5924
116
329
G220
4964
116
389
S478
4004
116
449
S418
3044
116
270
G102
5908
236
330
Dummy24
4948
236
390
S477
3988
236
450
S417
3028
236
271
272
G104
G106
5892
5876
116
236
331
332
Dummy25
Dummy26
4932
4916
116
236
391
392
S476
S475
3972
3956
116
236
451
452
S416
S415
3012
2996
116
236
273
G108
5860
116
333
Dummy27
4900
116
393
S474
3940
116
453
S414
2980
116
274
275
G110
G112
5844
5828
236
116
334
335
Dummy28
Dummy29
4884
4868
236
116
394
395
S473
S472
3924
3908
236
116
454
455
S413
S412
2964
2948
236
116
276
G114
5812
236
336
Dummy30
4852
236
396
S471
3892
236
456
S411
2932
236
277
G116
5796
116
337
Dummy31
4836
116
397
S470
3876
116
457
S410
2916
116
278
279
G118
G120
5780
5764
236
116
338
339
Dummy32
S528
4820
4804
236
116
398
399
S469
S468
3860
3844
236
116
458
459
S409
S408
2900
2884
236
116
280
G122
5748
236
340
S527
4788
236
400
S467
3828
236
460
S407
2868
236
281
282
G124
G126
5732
5716
116
236
341
342
S526
S525
4772
4756
116
236
401
402
S466
S465
3812
3796
116
236
461
462
S406
S405
2852
2836
116
236
283
G128
5700
116
343
S524
4740
116
403
S464
3780
116
463
S404
2820
116
284
G130
5684
236
344
S523
4724
236
404
S463
3764
236
464
S403
2804
236
285
286
G132
G134
5668
5652
116
236
345
346
S522
S521
4708
4692
116
236
405
406
S462
S461
3748
3732
116
236
465
466
S402
S401
2788
2772
116
236
287
G136
5636
116
347
S520
4676
116
407
S460
3716
116
467
S400
2756
116
288
289
G138
G140
5620
5604
236
116
348
349
S519
S518
4660
4644
236
116
408
409
S459
S458
3700
3684
236
116
468
469
S399
S398
2740
2724
236
116
290
G142
5588
236
350
S517
4628
236
410
S457
3668
236
470
S397
2708
236
291
292
G144
G146
5572
5556
116
236
351
352
S516
S515
4612
4596
116
236
411
412
S456
S455
3652
3636
116
236
471
472
S396
S395
2642
2626
116
236
293
G148
5540
116
353
S514
4580
116
413
S454
3620
116
473
S394
2610
116
294
G150
5524
236
354
S513
4564
236
414
S453
3604
236
474
S393
2594
236
295
296
G152
G154
5508
5492
116
236
355
356
S512
S511
4548
4532
116
236
415
416
S452
S451
3588
3572
116
236
475
476
S392
S391
2578
2562
116
236
297
G156
5476
116
357
S510
4516
116
417
S450
3556
116
477
S390
2546
116
298
299
G158
G160
5460
5444
236
116
358
359
S509
S508
4500
4484
236
116
418
419
S449
S448
3540
3524
236
116
478
479
S389
S388
2530
2514
236
116
300
G162
5428
236
360
S507
4468
236
420
S447
3508
236
480
S387
2498
236
Himax Confidential
-P.18October, 2007
HX8340-B(N)
No.
Pad name
X
Y
No.
Pad name
X
Y
No.
Pad name
X
Y
No.
Pad name
X
Y
481
482
483
S386
S385
S384
2482
2466
2450
116
236
116
541
542
543
S326
S325
S324
1522
1506
1490
116
236
116
601
602
603
S266
S265
S264
562
546
-554
116
236
116
661
662
663
S206
S205
S204
-1482
-1498
-1514
116
236
116
484
S383
2434
236
544
S323
1474
236
604
S263
-570
236
664
S203
-1530
236
485
S382
2418
116
545
S322
1458
116
605
S262
-586
116
665
S202
-1546
116
486
487
S381
S380
2402
2386
236
116
546
547
S321
S320
1442
1426
236
116
606
607
S261
S260
-602
-618
236
116
666
667
S201
S200
-1562
-1578
236
116
488
S379
2370
236
548
S319
1410
236
608
S259
-634
236
668
S199
-1594
236
489
490
S378
S377
2354
2338
116
236
549
550
S318
S317
1394
1378
116
236
609
610
S258
S257
-650
-666
116
236
669
670
S198
S197
-1610
-1626
116
236
491
S376
2322
116
551
S316
1362
116
611
S256
-682
116
671
S196
-1642
116
492
493
S375
S374
2306
2290
236
116
552
553
S315
S314
1346
1330
236
116
612
613
S255
S254
-698
-714
236
116
672
673
S195
S194
-1658
-1674
236
116
494
S373
2274
236
554
S313
1314
236
614
S253
-730
236
674
S193
-1690
236
495
S372
2258
116
555
S312
1298
116
615
S252
-746
116
675
S192
-1706
116
496
497
S371
S370
2242
2226
236
116
556
557
S311
S310
1282
1266
236
116
616
617
S251
S250
-762
-778
236
116
676
677
S191
S190
-1722
-1738
236
116
498
S369
2210
236
558
S309
1250
236
618
S249
-794
236
678
S189
-1754
236
499
500
S368
S367
2194
2178
116
236
559
560
S308
S307
1234
1218
116
236
619
620
S248
S247
-810
-826
116
236
679
680
S188
S187
-1770
-1786
116
236
501
S366
2162
116
561
S306
1202
116
621
S246
-842
116
681
S186
-1802
116
502
S365
2146
236
562
S305
1186
236
622
S245
-858
236
682
S185
-1818
236
503
504
S364
S363
2130
2114
116
236
563
564
S304
S303
1170
1154
116
236
623
624
S244
S243
-874
-890
116
236
683
684
S184
S183
-1834
-1850
116
236
505
S362
2098
116
565
S302
1138
116
625
S242
-906
116
685
S182
-1866
116
506
507
S361
S360
2082
2066
236
116
566
567
S301
S300
1122
1106
236
116
626
627
S241
S240
-922
-938
236
116
686
687
S181
S180
-1882
-1898
236
116
508
S359
2050
236
568
S299
1090
236
628
S239
-954
236
688
S179
-1914
236
509
S358
2034
116
569
S298
1074
116
629
S238
-970
116
689
S178
-1930
116
510
511
S357
S356
2018
2002
236
116
570
571
S297
S296
1058
1042
236
116
630
631
S237
S236
-986
-1002
236
116
690
691
S177
S176
-1946
-1962
236
116
512
S355
1986
236
572
S295
1026
236
632
S235
-1018
236
692
S175
-1978
236
513
514
S354
S353
1970
1954
116
236
573
574
S294
S293
1010
994
116
236
633
634
S234
S233
-1034
-1050
116
236
693
694
S174
S173
-1994
-2010
116
236
515
S352
1938
116
575
S292
978
116
635
S232
-1066
116
695
S172
-2026
116
516
S351
1922
236
576
S291
962
236
636
S231
-1082
236
696
S171
-2042
236
517
518
S350
S349
1906
1890
116
236
577
578
S290
S289
946
930
116
236
637
638
S230
S229
-1098
-1114
116
236
697
698
S170
S169
-2058
-2074
116
236
519
S348
1874
116
579
S288
914
116
639
S228
-1130
116
699
S168
-2090
116
520
521
S347
S346
1858
1842
236
116
580
581
S287
S286
898
882
236
116
640
641
S227
S226
-1146
-1162
236
116
700
701
S167
S166
-2106
-2122
236
116
522
S345
1826
236
582
S285
866
236
642
S225
-1178
236
702
S165
-2138
236
523
524
S344
S343
1810
1794
116
236
583
584
S284
S283
850
834
116
236
643
644
S224
S223
-1194
-1210
116
236
703
704
S164
S163
-2154
-2170
116
236
525
S342
1778
116
585
S282
818
116
645
S222
-1226
116
705
S162
-2186
116
526
S341
1762
236
586
S281
802
236
646
S221
-1242
236
706
S161
-2202
236
527
528
S340
S339
1746
1730
116
236
587
588
S280
S279
786
770
116
236
647
648
S220
S219
-1258
-1274
116
236
707
708
S160
S159
-2218
-2234
116
236
529
S338
1714
116
589
S278
754
116
649
S218
-1290
116
709
S158
-2250
116
530
531
S337
S336
1698
1682
236
116
590
591
S277
S276
738
722
236
116
650
651
S217
S216
-1306
-1322
236
116
710
711
S157
S156
-2266
-2282
236
116
532
S335
1666
236
592
S275
706
236
652
S215
-1338
236
712
S155
-2298
236
533
S334
1650
116
593
S274
690
116
653
S214
-1354
116
713
S154
-2314
116
534
535
S333
S332
1634
1618
236
116
594
595
S273
S272
674
658
236
116
654
655
S213
S212
-1370
-1386
236
116
714
715
S153
S152
-2330
-2346
236
116
536
S331
1602
236
596
S271
642
236
656
S211
-1402
236
716
S151
-2362
236
537
538
S330
S329
1586
1570
116
236
597
598
S270
S269
626
610
116
236
657
658
S210
S209
-1418
-1434
116
236
717
718
S150
S149
-2378
-2394
116
236
539
S328
1554
116
599
S268
594
116
659
S208
-1450
116
719
S148
-2410
116
540
S327
1538
236
600
S267
578
236
660
S207
-1466
236
720
S147
-2426
236
Himax Confidential
-P.19October, 2007
HX8340-B(N)
No.
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
Pad name
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133
S132
S116
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
X
-2442
-2458
-2474
-2490
-2506
-2522
-2538
-2554
-2570
-2586
-2602
-2618
-2634
-2650
-2716
-2732
-2748
-2764
-2780
-2796
-2812
-2828
-2844
-2860
-2876
-2892
-2908
-2924
-2940
-2956
-2972
-2988
-3004
-3020
-3036
-3052
-3068
-3084
-3100
-3116
-3132
-3148
-3164
-3180
-3196
-3212
-3228
-3244
-3260
-3276
-3292
-3308
-3324
-3340
-3356
-3372
-3388
-3404
-3420
-3436
Y
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
No.
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
Pad name
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
X
-3452
-3468
-3484
-3500
-3516
-3532
-3548
-3564
-3580
-3596
-3612
-3628
-3644
-3660
-3676
-3692
-3708
-3724
-3740
-3756
-3772
-3788
-3804
-3820
-3836
-3852
-3868
-3884
-3900
-3916
-3932
-3948
-3964
-3980
-3996
-4012
-4028
-4044
-4060
-4076
-4092
-4108
-4124
-4140
-4156
-4172
-4188
-4204
-4220
-4236
-4252
-4268
-4284
-4300
-4316
-4332
-4348
-4364
-4380
-4396
Y
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
No.
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
Pad name
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
Dummy33
Dummy34
Dummy35
Dummy36
Dummy37
Dummy38
Dummy39
Dummy40
G219
G217
G215
G213
G211
G209
G207
G205
G203
G201
G199
G197
G195
G193
G191
G189
G187
G185
G183
G181
G179
G177
G175
G173
G171
G169
X
-4412
-4428
-4444
-4460
-4476
-4492
-4508
-4524
-4540
-4556
-4572
-4588
-4604
-4620
-4636
-4652
-4668
-4684
-4700
-4716
-4732
-4748
-4764
-4780
-4796
-4812
-4828
-4844
-4860
-4876
-4892
-4908
-4924
-4940
-4956
-4972
-4988
-5004
-5020
-5036
-5052
-5068
-5084
-5100
-5116
-5132
-5148
-5164
-5180
-5196
-5212
-5228
-5244
-5260
-5276
-5292
-5308
-5324
-5340
-5356
Y
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
No.
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
Pad name
G167
G165
G163
G161
G159
G157
G155
G153
G151
G149
G147
G145
G143
G141
G139
G137
G135
G133
G116
G129
G127
G125
G123
G121
G119
G117
G115
G113
G111
G109
G107
G105
G103
G101
G99
G97
G95
G93
G91
G89
G87
G85
G83
G81
G79
G77
G75
G73
G71
G69
G67
G65
G63
G61
G59
G57
G55
G53
G51
G49
X
-5372
-5388
-5404
-5420
-5436
-5452
-5468
-5484
-5500
-5516
-5532
-5548
-5564
-5580
-5596
-5612
-5628
-5644
-5660
-5676
-5692
-5708
-5724
-5740
-5756
-5772
-5788
-5804
-5820
-5836
-5852
-5868
-5884
-5900
-5916
-5932
-5948
-5964
-5980
-5996
-6012
-6028
-6044
-6060
-6076
-6092
-6108
-6124
-6140
-6156
-6172
-6188
-6204
-6220
-6236
-6252
-6268
-6284
-6300
-6316
Himax Confidential
Y
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
116
236
-P.20October, 2007
HX8340-B(N)
No.
Pad name
X
Y
961
G47
-6332
116
962
G45
-6348
236
963
G43
-6364
116
964
G41
-6380
236
965
G39
-6396
116
966
G37
-6412
236
967
G35
-6428
116
968
G33
-6444
236
969
G31
-6460
116
970
G29
-6476
236
971
G27
-6492
116
972
G25
-6508
236
973
G23
-6524
116
974
G21
-6540
236
975
G19
-6556
116
976
G17
-6572
236
977
G15
-6588
116
978
G13
-6604
236
979
G11
-6620
116
980
G9
-6636
236
981
G7
-6652
116
982
G5
-6668
236
983
G3
-6684
116
984
G1
-6700
236
985
Dummy41
-6716
116
986
Dummy42
-6732
236
987
Dummy43
-6748
116
988
Dummy44
-6764
236
Alignment mark
X
Y
A1
-6827.5
-219.5
A2
+6827.5
-219.5
Himax Confidential
-P.21October, 2007
HX8340-B(N)
4.4 Alignment Mark
A_MARK (A1)
A_MARK (A2)
Himax Confidential
-P.22October, 2007
HX8340-B(N)
4.5 Bump Size
Input PAD
Output PAD
Himax Confidential
-P.23October, 2007
HX8340-B(N)
5. Interface
The HX8340-B supports two-type interface group: Command-Parameter interface mode,
Register-Content interface mode.
This manual description focuses on Command-Parameter interface mode. About the
Register-Content interface mode, please refer to the HX8340-B (T) datasheet for detail.
In Command-Parameter interface mode (IFSEL0 = ‘H’), the HX8340-B has a system interface
circuit for command/parameter (include display data) transferring, and a RGB interface circuit
for data transferring during animated display. The system interface circuit uses data bus pins
(DB17-0). Since the data bus pins (DB17-0) can be used as input in RGB interface circuit, the
HX8340-B shows animated display with less wiring.
System interface can be used to access internal command and internal 18-bit/pixel GRAM.
The RGB interface is only used to access display data. Please make sure that in RGB
interface mode, the input display data is not written to GRAM and is displayed directly.
Himax Confidential
-P.24October, 2007
HX8340-B(N)
5.1 System Interface Circuit
The command-parameter interface circuit in HX8340-B supports 18-/16-/9-/8-bit bus width
parallel bus system interface for I80 series and M68 series CPU, and a serial bus system
interface for serial data input. When NCS = ‘L’, the parallel and serial bus system interface of the
HX8340-B become active and data transfer through the interface circuit is available. The input
bus width format of system interface circuit is selected by external pins IM3-0 setting. For
selecting the input bus format, please refer to Table 5.1.
In command-parameter interface, it includes command code and the following parameter and
GRAM data. The command code can be written through data bus by setting DNC=’0’. Then the
parameter or GRAM data can be written to register at which that index pointer pointed by setting
DNC =’1’.
IM3 IM2 IM1 IM0
0
0
0
0
1
1
1
1
Interface
NWR_
NRD_
RNW_ DNC
E
SCL
0
0
0 6800 MCU 16-bits Parallel
E
0
0
E
0
1
0 8080 MCU 16-bits Parallel NRD_E
0
1
Note 1
1
- Serial interface
0
0
E
0
0
E
0
1
0
1
Other Setting
Setting Invalid
Note: (1) Can be connected to GND or IOVCC level.
(2) SDI and SDO can be tie together as SDA
RNW
RNW
NWR
NWR
SCL
RNW
RNW
NWR
NWR
DNC
DNC
DNC
DNC
Note 1
DNC
DNC
DNC
DNC
Data Bus use
DB0, DB9: Unused, DB17-B10, DB8-DB1: 16-bit data
DB9- DB0 Unused, DB17-DB10: 8-bits Data
DB0, DB9: Unused, DB17-10, DB8-DB1: 16-bit data
DB9- DB0: Unused, DB17-DB10: 8-bits Data
SDI, SDO
DB17-DB0: 18-bits Data
DB8-DB0: Unused, DB17-DB9: 9-bits Data
DB17-DB0: 18-bits Data
DB8-DB0: Unused, DB17-DB9: 9-bits Data
Table 5. 1 Pin connection According to MCU Interface Type Selection
Himax Confidential
-P.25October, 2007
HX8340-B(N)
5.1.1 8080-Series Parallel Bus
The MCU uses 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or
12-wires 9-data parallel interface. The chip-select NCS (active low) enables and disables the
parallel interface. NRESET (active low) is an external reset signal. NWR_RNW_SCL is the
parallel data write, NRD_E is the parallel data read and DB17-0 is parallel data.
The Graphics Controller Chip reads the data at the rising edge of NWR signal. The DNC is the
data/command flag. When DNC =’1’, DB17-0 bits are display RAM data or command
parameters. When DNC =’0’, DB17-0 bits are commands. The interface function of 8080-series
parallel interface are given in Table 5.2
IM3 IM2 IM1 IM0 Interface DNC
0
0
0
0
1
1
0
1
16-bits
Parallel
8-bits
Parallel
1
0
1
0
18-bits
Parallel
1
0
1
1
9-bits
Parallel
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
NWR_
NRD
RNW_
_E
SCL
1
1
1
↑
↑
1
1
1
↑
↑
1
1
1
↑
↑
1
1
1
↑
↑
↑
↑
↑
1
1
↑
↑
↑
1
1
↑
↑
↑
1
1
↑
↑
↑
1
1
Function
Write 8-bits command (DB8 to DB1)
Write 8-bits parameter (DB8 to DB1)
Write 16-bits display data (DB17 to DB10, DB8 to DB1)
Read 8-bits command (DB8 to DB1)
Read 16-bits display data (DB17 to DB10, DB8 to DB1)
Write 8-bits display data (DB17 to DB10)
Read 8-bits parameter or status (DB17 to DB10)
Read 8-bits display data (DB17 to DB10)
Table 5. 2 The function of 8080-series parallel interface
Himax Confidential
-P.26October, 2007
HX8340-B(N)
Write Cycle Sequence
The write cycle means that the host writes information (command or/and data) to the display
via the interface. Each write cycle (NWR_RNW high-low-high sequence) consists of 3 control
(DNC, NRD_E, and NWR_RNW_SCL) and data signals (DB[B:0]). DNC bits are a control
signal, which tells if the data is a command or a data. The data signals are the command if the
control signal is low (=’0’) and vice versa it is data (=’1’).
NWR_RNW
DB[B:0]
The host starts to control
DB[B:0] lines when
there is a falling edge of
the NWR_RNW
The display reads
D[B:0] lines when
there is a rising edge
of the NWR_RNW
The host stops to
control DB[B:0] lines
Figure 5. 1 8080-Series NWR_RNW Protocol
1-byte command
DB[B:0]
S
CMD
2-byte command
N-byte command (PA=N-1)
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
NRESET ‘1’
NCS
DNC
‘1’
NRD_E
NWR_RNW
DB[B:0]
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Host [17:0]
Host to LCD
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Driver [17:0]
LCD to Host]
Hi-Z
CMD: Write command code
PA: Parameter or RAM data
Signal on DB[B:0], DNC. NWR_RNW,
NRD_E pins during NCS=’1’ are ignored
Figure 5. 2 8080-Series parallel bus protocol, Write to register or display RAM
Himax Confidential
-P.27October, 2007
HX8340-B(N)
Read Cycle Sequence
The read cycle (NRD_E high-low-high sequence) means that the host reads information from
display via interface. The display sends data (DB[B:0]) to the host when there is a falling edge of
NRD_E and the host reads data when there is a rising edge of NRD_E.
NRD_E
DB[B:0]
The display starts to
when there is a falling
edge of the NRD_E
The host reads
DB[B:0] lines when
there is a rising edge
of NRD_E
The display stops to
control DB[B:0]
Figure 5. 3 8080-Series NRD Protocol
Read Parameter
DB[B:0]
Read display RAM data
S
CMD
DM
PA
CMD
DM
data
data
P
DB[B:0]
S
CMD
DM
PA
CMD
DM
data
data
P
Host [17:0]
Host to LCD
S
CMD
Driver [17:0]
LCD to Host]
S
NRESET ‘1’
NCS
DNC
NRD_E
NWR_RNW
Hi-Z
Hi-Z
DM
DM: Dummy
CMD
PA
Hi-Z
Hi-Z
DM
P
data
data
P
Figure 5. 4 8080-Series parallel bus protocol, Read data from register or display RAM
Himax Confidential
-P.28October, 2007
HX8340-B(N)
5.1.2 6800-Series Parallel Interface
The MCU uses an 11-wires 8-data parallel interface or 19-wires 16-data parallel interface or
12-wires 9-data parallel interface. The chip-select NCS(active low) enables and disables the
parallel interface. NRESET (active low) is an external reset signal. The RNW is the Read/Write
flag and DB[B:0] is parallel data.
The Graphics Controller Chip reads the data at the falling edge of NRD_E signal when
NWR_RNW_SCL=’1’ and Writes the data at the falling of the NRD_E signal when
NWR_RNW_SCL=’0’. The DNC is the data/command flag. When DNC=’1’, DB[B:0] bits are
display RAM data or command parameters. When DNC=’0’, DB[B:0] bits are commands.
The 6800-series bi-directional interface can be used for communication between the micro
controller and LCD driver chip. Interface bus width can be selected with IM2, IM1 and IM0. The
interface functions of 6800-series parallel interface are given in Table 5.3.
NWR_
NRD_
IM3 IM2 IM1 IM0 Interface DNC RNW_
E
SCL
0
0
0
0
16-bits
Parallel
0
0
0
1
8-bits
Parallel
1
0
0
0
18-bits
Parallel
1
0
0
1
9-bits
Parallel
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Function
Write 16-bits display data (DB17 to DB10, DB8 to DB1)
Read 16-bits display data (DB17 to DB10, DB8 to DB1)
Table 5. 3 The function of 6800-series parallel interface
Himax Confidential
-P.29October, 2007
HX8340-B(N)
Write Cycle Sequence
The write cycle means that the host writes information (command or/and data) to the display via
the interface. Each write cycle (NRD_E low-high-low sequence) consists of 3 control (DNC,
NRD_E, and NWR_RNW) and data signals (DB[B:0]). DNC bit is a control signal, which tells if
the data is a command or a data. The data signals are the command if the control signal is low
(=’0’) and vice versa it is data (=’1’).
NWR_RNW ‘0’
NRD_E
DB[B:0]
DB[B:0] lines when
there is a rising edge of
the NRD_E
The display writes
The host stops to
DB[B:0] lines when
there is a falling edge
of the NRD_E
Figure 5. 5 6800-Series Write Protocol
1-byte command
DB[B:0]
S
CMD
2-byte command
N-byte command (PA=N-1)
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
NRESET ‘1’
NCS
DNC
NWR_RNW
‘0’
NRD_E
DB[B:0]
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Host [17:0]
Host to LCD
S
CMD
CMD
PA1
CMD
PA1
PAN-2
PAN-1
P
Driver [17:0]
LCD to Host]
Hi-Z
Signal on DN[B:0], DNC. NWR_RNW,
Figure 5. 6 6800-Series parallel bus protocol, Write to register or display RAM
Himax Confidential
-P.30October, 2007
HX8340-B(N)
Read Cycle Sequence
The read cycle means that the host reads information (command or/and data) to the display via
the interface. Each read cycle (NRD_E low-high-low sequence) consists of 3 control (DNC,
NRD_E, and NWR_RNW) and data signals (DB[B:0]). DNC bit is a control signal, which tells if
the data is a command or a data. The data signals are the command if the control signal is low
(=’0’) and vice versa it is data (=’1’).
NWR_RNW
‘1’
NRD_E
DB[B:0]
DB[B:0] lines when
there is a rising edge of
the NRD_E
The display reads
The host stops to
DB[B:0] lines when
there is a falling edge
of the NRD_E
Figure 5. 7 6800-Series Read Protocol
Read Parameter
DB[B:0]
S
CMD
DM
Read display RAM data
PA
CMD
DM
data
data
P
PA
CMD
DM
data
data
P
NRESET ‘1’
NCS
DNC
NWR_RNW
‘1’
‘0’
NRD_E
DB[B:0]
S
CMD
Host [17:0]
Host to LCD
S
CMD
Driver [17:0]
LCD to Host]
S
Hi-Z
DM
Hi-Z
DM
DM: Dummy
CMD
PA
Hi-Z
Hi-Z
DM
P
data
data
P
Figure 5. 8 6800-Series parallel bus protocol, Read data from register or display RAM
Himax Confidential
-P.31October, 2007
HX8340-B(N)
5.1.3 Serial Interface
The HX5340-B uses 3-wires 9-bit serial peripheral interface. The chip select NCS (active low)
enables and disables the serial interface). NRESET (active low) is an external reset signal.
NWR_RNW_SCL is serial data clock and SDI is serial input data signal, SDO is serial output
data signal. Please note that SDI and SDO pins are possible to connect together outside of
driver IC as one SDA line. The selection of this interface is done by IM2. See the Table 5.4.
IM3 IM2 IM1 IM0
‘-‘
‘1’
‘-‘
‘-‘
Interface
3-Pin Serial interface
Table 5. 4 Serial Interface Type Selection
Write Function
The write mode of the interface means the micro controller writes commands and data to the
3-Pin serial data packet contains a control bit DNC and a transmission byte. If DNC is ‘0’, the
transmission byte is interpreted as command byte. If DNC is ‘1’, the transmission byte is stored
in the display data RAM (Memory write command), or command register as parameter.
Any instruction can be sent in any order to the DRIVER. The MSB is transmitted first. The serial
interface is initialized when NCS is high. In this state, SCL clock pulse or SDA data have no
effect. A falling edge on NCS enables the serial interface and indicates the start of data
transmission.
Figure 5. 9 Serial interface data Stream format
Himax Confidential
-P.32October, 2007
HX8340-B(N)
When NCS is high, NWR_RNW _SCL clock is ignored. During the high time of NCS the serial
interface is initialized. At the falling edge of NCS, NWR_RNW _SCL can be high or low (see
Figure 5.10). SDA is sampled at the rising edge of NCS. DNC indicates, whether the byte is
command code (DNC =’0’) or parameter/GRAM data (DNC =’1’). It is sampled when first rising
edge of NWR_RNW _SCL. If NCS stay low after the last bit of command/data byte, the serial
interface expects the DNC bit of the next byte at the next rising edge of SCL.
S
TB
TB
P
NCS
Host
SDA
0
D7
D6
D5
D4
D3
D2
D1
D0
DNC
D7
D6
D5
D4
D3
D2
D1
D0
(MCU to
Driver)
SCL
Command
Command / Parameter
NCS can be ‘H’ between parameter / command and parameter
/command SCL and SDA during NCS=’H’ is invalid
Figure 5. 10 Serial interface Write protocol (Write to register with control bit in transmission)
Himax Confidential
-P.33October, 2007
HX8340-B(N)
Read Functions
The read mode of the interface means that the micro controller reads register value from the
Driver. To do the micro controller first has to send a command (Read ID or register command)
and then the following byte is transmitted in the opposite direction. After the read status
command has been sent, the SDA line must be set to tri-state no later than at the falling edge of
SCL of the last bit.
3 wire Serial Interface Protocol
for RDID1~RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command : 8-bit read
S
TB
TB
P
S
NCS
NWR_RNW
_SCL
SDA(SDI)
DNC
D7
D6
D5
D4
D3
D2
D1
D0
DNC
input
SDA(SDO)
D7
D6
D5
D4
D3
D2
D1
D0
output
for RDID command : 24-bit read
S
TB
TB
P
S
NCS
NWR_RNW
_SCL
SDA(SDI)
DNC
D7
D6
D5
D4
D3
D2
D1
input
D0
DNC
Dummy clock
D23
SDA(SDO)
D22
D21
D2
D1
D0
output
for RDDST command : 32-bit read
S
TB
TB
P
S
NCS
NWR_RNW
_SCL
SDA(SDI)
DNC
D7
D6
D5
D4
D3
input
SDA(SDO)
D2
D1
D0
DNC
Dummy clock
D31
D30
D29
D2
D1
D0
output
Figure 5. 11 Serial interface Read protocol
Himax Confidential
-P.34October, 2007
HX8340-B(N)
5.1.4 Data Transfer Break and Recovery
If there is a break in data transmission by NRESET pulse, while transferring a Command or
Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been
completed, then DRIVER will reject the previous bits and have reset the interface such that it will
be ready to receive command data again when the chip select line (NCS) is next activated after
NRESET have been High state. See the following example
≈
Figure 5. 12 Serial bus protocol, write mode – interrupted by NRESET
If there is a break in data transmission by NCS pulse, while transferring a Command or Frame
Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been
completed, then DRIVER will reject the previous bits and have reset the interface such that it will
be ready to receive the same byte re-transmitted when the chip select line (NCS) is next
activated. See the following example
Figure 5. 13 Serial bus protocol, write mode – interrupted by NCS
Himax Confidential
-P.35October, 2007
HX8340-B(N)
If 1, 2 or more parameter command is being sent and a break occurs while sending any
parameter before the last one and if the host then sends a new command rather than
re-transmitting the parameter that was interrupted, then the parameters that were
successfully sent are stored and the parameter where the break occurred is rejected. The
interface is ready to receive next byte as shown below.
Break
CMD1
PARA11
PARA12
PARA11 is sucessfully sended but PARA12
is breaked and need to be transfered again
CMD2
CMD1
PARA11
PARA12
PARA13
Command1 with 1 st parameter (P ARA11) should
be executed again to write remained parameter
(PA RA12 and PARA13)
Figure 5. 14 Write interrupts recovery (serial interface)
If a 2 or more parameter command is being sent and a break occurs by the other command
before the last one is sent, then the parameters that were successfully sent are stored and the
other parameter of that command remains previous value.
Break
CMD1
PARA11
PARA11 is sucessfully sent but the other parameters
are not sent and break happeds by the other
command.
CMD2
CMD1
PARA11
PARA12
PARA13
Command1 with 1st parameter (PA RA11) should
be executed again to write remained parameter
(PARA12 and PARA13)
Figure 5. 15 Write interrupts recovery (both serial and parallel interface)
Himax Confidential
-P.36October, 2007
HX8340-B(N)
5.1.5 Data Transfer Pause
It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter
Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole
byte of a Frame Memory Data or Multiple Parameter Data has been completed, then DRIVER
will wait and continue the Frame Memory Data or Parameter Data Transmission from the point
where it was paused. If the Chip Select Line is released after a whole byte of a command has
been completed, then the Display Module will receive either the command’s parameters (if
appropriate) or a new command when the Chip Select Line is next enabled as shown below.
This applies to the following 4 conditions:
a. Command-Pause-Command
b. Command-Pause-Parameter
c. Parameter-Pause-Command
d. Parameter-Pause-Parameter
Serial Interface Pause
Figure 5. 16 Serial bus protocol, write mode – paused by NSC
Parallel Interface Pause
Figure 5. 17 Parallel bus protocol, write mode – paused by NCS
Himax Confidential
-P.37October, 2007
HX8340-B(N)
5.1.6 Data Transfer Modes
The Module has three kinds color modes for transferring data to the display RAM. These are
12-bits color per pixel, 16-bits color per pixel and 18-bits color per pixel. The data format is
described for each interface. Data can be downloaded to the Frame Memory by 2 methods.
Method 1
The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame
Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is
written.
Start
Start Frame
Memory
Write
Stop
Image
Data
Frame 1
Image
Data
Frame 2
Image
Data
Frame 3
Any
Command
Method 2
Image Data is sent and at the end of each Frame Memory download, a command is sent to stop
Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is
downloaded.
Start
Start Frame
Memory
Write
Image
Data
Frame 1
Any
Command
Start Frame
Memory
Write
Image
Data
Frame 2
Any
Command
Stop
Any
Command
Note: (1) These apply to all data transfer Color modes on both serial and parallel interfaces.
(2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data
will be stored in the frame memory.
Himax Confidential
-P.38October, 2007
HX8340-B(N)
5.1.7 MCU Data Color Coding
MCU Data Color Coding for RAM data Write
- Parallel 8-Bits Bus Interface
Register
Command
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
3AH
03h
05h
06h
0
R3
B3
G3
R4
G2
R5
G5
B5
0
R2
B2
G2
R3
G1
R4
G4
B4
1
R1
B1
G1
R2
G0
R3
G3
B3
0
1
R0
B0
G0
R1
B4
R2
G2
B2
G3
R3
B3
R0
B3
R1
G1
B1
1
G2
R2
B2
G5
B2
R0
G0
B0
0
G1
R1
B1
G4
B1
x
x
x
0
G0
R0
B0
G3
B0
x
x
x
x
x
x
x
x
x
x
x
x
DB8
x
DB8
x
x
x
x
x
x
x
x
DB7 DB6
x
x
DB7 DB6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Command
2CH
Color
4K-Color
(2-pixels/ 3-byyes)
65K-Color
(1-pixels/ 2-byyes)
262K-Color
(1-pixels/ 3byyes)
Table 5. 5 8-Bits Parallel Interface Set Table
Register
Command
3AH
03h
05h
06h
x
x
R4
R5
B5
G5
x
R3
R4
B4
G4
x
R2
R3
B3
G3
x
R1
R2
B2
G2
R3
R0
R1
B1
G1
R2
G5
R0
B0
G0
R1
G4
x
x
x
R0
G3
x
x
x
x
x
x
x
x
DB8
0
DB7 DB6
0
1
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
0
x
DB8
DB7 DB6
DB5
DB4
DB3
DB2
DB1
DB0
G3
G2
G5
R5
B5
G2
G1
G4
R4
B4
G0
B4
G2
R2
B2
B3
B3
G1
R1
B1
B2
B2
G0
R0
B0
B1
B1
x
x
x
B0
B0
x
x
x
x
x
x
x
x
G1
G0
G3
R3
B3
Command
2CH
Color
4K-Color
65K-Color
262K-Color
(2-pixels/ 3byyes)
Register
Command
3AH
06h
Register
2CH
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Color
R5 R4 R3 R2 R1 R0 G5 G4 G3
x
x
x
x
x
x
x
x
x
262K-Color
(1-pixels/ 2bytes)
G2 G1 G0 B5 B4 B3 B2 B1 B0
x
x
x
x
x
x
x
x
x
0
0
1
0
1
1
0
0
x
DB8
x
DB7 DB6
x
x
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
Register
Command
3AH
03h
05h
06h
x
x
x
R5
x
x
x
R4
x
x
R4
R3
x
x
R3
R2
x
x
R2
R1
x
x
R1
R0
x
R3
R0
G5
x
R2
G5
G4
x
R1
G4
G3
DB8
0
DB7 DB6
0
1
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
0
x
DB8
DB7 DB6
DB5
DB4
DB3
DB2
DB1
DB0
R0
G3
G2
G3
G2
G1
G1
G0
B5
G0
B4
B4
B3
B3
B3
B2
B2
B2
B1
B1
B1
B0
B0
B0
G2
G1
G0
Register
2CH
Color
4K-Color
65K-Color
262K-Color
Himax Confidential
-P.39October, 2007
HX8340-B(N)
Parallel 8-Bits Bus Interface for RAM Data Write
Different display data formats are available for three colors depth supported by listed below.
- 4K-Colors, RGB 4, 4, 4-bits input data. (3AH=”03h”)
Figure 5. 18 Example of I80- / M68- System 8-Bit Parallel Bus Interface
Himax Confidential
-P.40October, 2007
HX8340-B(N)
8-bits data bus for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colors, 3AH= ”03h”
There are 2-pixels (6 sub-pixels) per 3-bytes.
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
8080-Series control pins
RNW
‘0’
E
DB17
0
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
DB16
0
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
DB15
1
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
DB14
0
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
DB13
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
DB12
1
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
DB11
0
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
DB10
0
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
Pixel n
Pixel n+1
12-bits
12-bits
Look-Up Table for 4K-colors or data mapping (12-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note: (1) The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and
Blue data.
(2) 3-times transfer is used to transmit 1 pixel data with the 12-bits color depth information.
(3) ‘-‘ = Don't care - Can be set to IOVCC or VSSD level
Himax Confidential
-P.41October, 2007
HX8340-B(N)
8-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
There is 1-pixel (3 sub-pixels) per 2-bytes.
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
0
R1, Bit 4
G1, Bit 2
R2, Bit 4
G2, Bit 2
DB16
0
R1, Bit 3
G1, Bit 1
R2, Bit 3
G2, Bit 1
DB15
1
R1, Bit 2
G1, Bit 0
R2, Bit 2
G2, Bit 0
DB14
0
R1, Bit 1
B1, Bit 5
R2, Bit 1
B2, Bit 5
DB13
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
DB12
1
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
DB11
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
DB10
0
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n+1
Pixel n
16-bits
16-bits
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note: (1) The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and
MSB=Bit 4, LSB=Bit 0 for Red and Blue data.
(2) 2-times transfer is used to transmit 1 pixel data with the 16-bits color depth information.
(3) ‘-‘ = Don't care - Can be set to IOVCC or VSSD level
Himax Confidential
-P.42October, 2007
HX8340-B(N)
There is 1-pixel (3 sub-pixels) per 3-bytes.
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
0
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
DB16
0
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
DB15
1
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
DB14
0
R1, Bit 2
G1, Bit 2
B1, Bit 2
R2, Bit 2
DB13
1
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
DB12
1
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
DB11
0
-
-
-
-
DB10
0
-
-
-
-
Pixel n+1
Pixel n
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue
data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information.
Note 3. ‘-‘ = Don't care - Can be set to IOVCC or VSSD level
Himax Confidential
-P.43October, 2007
HX8340-B(N)
Himax Confidential
-P.44October, 2007
HX8340-B(N)
There is 1-pixel (3 sub-pixels) per 1-byte
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
-
-
-
-
-
DB16
-
-
-
-
-
DB15
-
-
-
-
-
DB14
-
-
-
-
-
DB13
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
DB12
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
DB11
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
DB10
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
DB8
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
DB7
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
DB6
1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
DB5
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
DB4
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
DB3
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
DB2
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
DB1
0
B1, Bit 0
B2, Bit 0
Pixel n
Pixel n+1
12-bits
B3, Bit 0
Pixel n+2
B4, Bit 0
Pixel n+3
12-bits
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and
Blue data.
Himax Confidential
-P.45October, 2007
HX8340-B(N)
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
-
R1, Bit 4
R2, Bit 4
R3, Bi
R4, Bit 4
DB16
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
DB15
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
DB14
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
DB13
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
DB12
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
DB11
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
DB10
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
DB8
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
DB7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
DB6
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
DB5
0
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
DB4
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
DB3
1
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
DB2
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
DB1
0
B1, Bit 0
Pixel n
B2, Bit 0
Pixel n+1
16-bits
B4, Bit 0
Pixel n+2
Pixel n+3
16-bits
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and
Himax Confidential
-P.46October, 2007
HX8340-B(N)
There are 2-pixels (6 sub-pixels) per 3-bytes
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
-
R1, Bit 5
B1, Bit 5
G2, Bit 5
R3, Bit 5
DB16
-
R1, Bit 4
B1, Bit 4
G2, Bit 4
R3, Bit 4
DB15
-
R1, Bit 3
B1, Bit 3
G2, Bit 3
R3, Bit 3
DB14
-
R1, Bit 2
B1, Bit 2
G2, Bit 2
R3, Bit 2
DB13
-
R1, Bit 1
B1, Bit 1
G2, Bit 1
R3, Bit 1
DB12
-
R1, Bit 0
B1, Bit 0
G2, Bit 0
R3, Bit 0
DB11
-
-
-
-
-
DB10
-
-
-
-
-
DB8
0
G1, Bit 5
R2, Bit 5
B2, Bit 5
G3, Bit 5
DB7
0
G1, Bit 4
R2, Bit 4
B2, Bit 4
G3, Bit 4
DB6
1
G1, Bit 3
R2, Bit 3
B2, Bit 3
G3, Bit 3
DB5
0
G1, Bit 2
R2, Bit 2
B2, Bit 2
G3, Bit 2
DB4
1
G1, Bit 1
R2, Bit 1
B2, Bit 1
G3, Bit 1
DB3
1
G1, Bit 0
R2, Bit 0
B2, Bit 0
G3, Bit 0
DB2
0
-
-
-
-
DB1
0
-
-
-
-
Pixel n
18-bits
Frame
Memory
Pixel n+1
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Blue data.
Himax Confidential
-P.47October, 2007
HX8340-B(N)
Himax Confidential
-P.48October, 2007
HX8340-B(N)
There is 1-pixel (3 sub-pixels) per 2-bytes
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
0
R1, Bit 5
G1, Bit 2
R2, Bit 5
G2, Bit 2
DB16
0
R1, Bit 4
G1, Bit 1
R2, Bit 4
G2, Bit 1
DB15
1
R1, Bit 3
G1, Bit 0
R2, Bit 3
G2, Bit 0
DB14
0
R1, Bit 2
B1, Bit 5
R2, Bit 2
B2, Bit 5
DB13
1
R1, Bit 0
B1, Bit 4
R2, Bit 1
B2, Bit 4
DB12
1
R1, Bit 0
B1, Bit 3
R2, Bit 0
B2, Bit 3
DB11
0
G1, Bit 5
B1, Bit 2
G2, Bit 5
B2, Bit 2
DB10
0
G1, Bit 4
B1, Bit 1
G2, Bit 4
B2, Bit 1
DB9
-
G1, Bit 3
B1, Bit 0
G2, Bit 3
B2, Bit 0
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Himax Confidential
-P.49October, 2007
HX8340-B(N)
Himax Confidential
-P.50October, 2007
HX8340-B(N)
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
-
-
-
-
-
DB16
-
-
-
-
-
DB12
-
-
-
-
-
DB11
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
DB10
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
DB9
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
DB8
0
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
DB7
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
DB6
1
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
DB5
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
DB4
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
DB3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
DB2
0
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
DB1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
DB0
-
B1, Bit 0
B2, Bit 0
Pixel n+1
Pixel n
12-bits
B3, Bit 0
Pixel n+2
B4, Bit 0
Pixel n+3
12-bits
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Blue data.
Himax Confidential
-P.51October, 2007
HX8340-B(N)
There is 1-pixel (3 sub-pixels) per 1-bytes
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
-
-
-
-
-
DB16
-
-
-
-
-
DB15
-
R1, Bit 4
R2, Bit 4
R3, Bi
R4, Bit 4
DB14
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
DB13
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
DB12
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
DB11
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
DB10
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
DB9
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
DB8
0
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
DB7
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
DB6
1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
DB5
0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
DB4
1
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
DB3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
DB2
0
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
DB1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
DB0
-
B1, Bit 0
B2, Bit 0
Pixel n
Pixel n
16-bits
B1, Bit 0
Pixel n
B4, Bit 0
Pixel n
16-bits
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is ad follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and
Himax Confidential
-P.52October, 2007
HX8340-B(N)
NRESET ‘1’
NCS
DNC
NWR
NRD
‘1’
RNW
‘0’
E
DB17
-
R1, Bit 5
R2, Bit 5
R3, Bit5
R4, Bit 5
DB16
-
R1, Bit 4
R2, Bit 4
R3, Bit5
R4, Bit 4
DB15
-
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
DB14
-
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
DB13
-
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
DB12
-
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
DB11
-
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
DB10
-
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
DB9
-
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
DB8
0
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
DB7
0
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
DB6
1
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
DB5
0
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
DB4
1
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
DB3
1
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
DB2
0
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
DB1
0
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B1, Bit 0
B2, Bit 0
B1, Bit 0
B4, Bit 0
DB0
Pixel n
18-bits
Frame
Memory
Pixel n+1
Pixel n+2
Pixel n+3
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Blue data.
Himax Confidential
-P.53October, 2007
HX8340-B(N)
5.1.8 MCU Data Color Coding for RAM data Read
Register
Command
0
0
1
0
1
1
1
0
x
Read
Data Format
x
R5
G5
B5
x
R4
G4
B4
x
R3
G3
B3
x
R2
G2
B2
x
R1
G1
B1
x
R0
G0
B0
x
x
x
x
x
x
x
x
DB8
x
DB8
DB7 DB6
x
x
DB7 DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Command
2EH
Color
Dummy Read
262K-Color
(1-pixels/ 3bytes)
Register
Command
x
x
x
x
x
x
x
x
x
Read
Data Format
R5
B5
G5
x
R4
B4
G4
x
R3
B3
G3
x
R2
B2
G2
x
R1
B1
G1
x
R0
B0
G0
x
x
x
x
x
x
x
x
x
x
x
x
DB8
0
DB7 DB6
0
1
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
0
x
DB8
DB7 DB6
DB5
DB4
DB3
DB2
DB1
DB0
G5
R5
B5
x
G4
R4
B4
x
G2
R2
B2
x
G1
R1
B1
x
G0
R0
B0
x
x
x
x
x
x
x
x
x
x
x
x
x
G3
R3
B3
Command
2EH
Color
Dummy Read
262K-Color
(2-pixels/ 3bytes)
Table 5. 1016-Bits Parallel Interface Set Table
Register
Command
0
0
1
0
1
1
1
0
x
Read
Data Format
x
R5
G2
x
R4
G1
x
R3
G0
x
R2
B5
x
R1
B4
x
R0
B3
x
G5
B2
x
G4
B1
x
G3
B0
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
x
x
x
Register
2EH
Color
Dummy Read
x
x
x
x
x
x
x
x
x
262K-Color
(1-pixels/ 2bytes)
DB8
x
DB8
DB7 DB6
x
x
DB7 DB6
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
Register
Command
x
Read
Data Format
DB8
0
DB8
DB7 DB6
0
1
DB7 DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
1
0
x
DB5
DB4
DB3
DB2
DB1
DB0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Register
2EH
Color
Dummy Read
262K-Color
(1-pixels/ 2bytes)
Himax Confidential
-P.54October, 2007
HX8340-B(N)
Parallel 8-Bits Bus Interface for RAM Data Read
There is 1-pixel (3 sub-pixels) per 3-bytes. (RGB 6-6-6-bits output)
RESET ‘1’
NCS
DNC
NRD
NWR
RNW
‘1’
‘0’
‘1’
E
DB17
0
---
R1, Bit 5
G1, Bit 5
B1, Bit 5
DB16
0
---
R1, Bit 4
G1, Bit 4
B1, Bit 4
DB15
1
---
R1, Bit 3
G1, Bit 3
B1, Bit 3
DB14
0
---
R1, Bit 2
G1, Bit 2
B1, Bit 2
DB13
1
---
R1, Bit 1
G1, Bit 1
B1, Bit 1
DB12
1
---
R1, Bit 0
G1, Bit 0
B1, Bit 0
DB11
1
---
-
-
-
DB10
0
---
-
-
-
Dummy Pixel
n
Pixel n
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
data.
Himax Confidential
-P.55October, 2007
HX8340-B(N)
There are 2 pixel (6 sub-pixels) per 3 bytes (RGB 6-6-6-bits output)
NRESET ‘1’
NCS
DNC
NRD
NWR
RNW
‘1’
‘0’
‘1’
E
DB17
-
---
R1, Bit 5
B1, Bit 5
G2, Bit 5
DB16
-
---
R1, Bit 4
B1, Bit 4
G2, Bit 4
DB15
-
---
R1, Bit 3
B1, Bit 3
G2, Bit 3
DB14
-
---
R1, Bit 2
B1, Bit 2
G2, Bit 2
DB13
-
---
R1, Bit 1
B1, Bit 1
G2, Bit 1
DB12
-
---
R1, Bit 0
B1, Bit 0
G2, Bit 0
DB11
-
---
-
-
-
DB10
-
---
-
-
-
DB8
0
---
G1, Bit 5
R2, Bit 5
B2, Bit 5
DB7
0
---
G1, Bit 4
R2, Bit 4
B2, Bit 4
DB6
1
---
G1, Bit 3
R2, Bit 3
B2, Bit 3
DB5
0
---
G1, Bit 2
R2, Bit 2
B2, Bit 2
DB4
1
---
G1, Bit 1
R2, Bit 1
B2, Bit 1
DB3
1
---
G1, Bit 0
R2, Bit 0
B2, Bit 0
DB2
1
---
-
-
-
DB1
0
---
-
-
-
Dummy Pixel
Pixel n
18-bits
Frame
Memory
Pixel n+1
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Blue data.
Himax Confidential
-P.56October, 2007
HX8340-B(N)
NRESET ‘1’
NCS
DNC
NRD
NWR
RNW
‘1’
‘0’
‘1’
E
DB17
0
---
R1, Bit 5
G1, Bit 2
R2, Bit 5
DB16
0
---
R1, Bit 4
G1, Bit 1
R2, Bit 4
DB15
1
---
R1, Bit 3
G1, Bit 0
R2, Bit 3
DB14
0
---
R1, Bit 2
B1, Bit 5
R2, Bit 2
DB13
1
---
R1, Bit 0
B1, Bit 4
R2, Bit 1
DB12
1
---
R1, Bit 0
B1, Bit 3
R2, Bit 0
DB11
1
---
G1, Bit 5
B1, Bit 2
G2, Bit 5
DB10
0
---
G1, Bit 4
B1, Bit 1
G2, Bit 4
DB9
-
---
G1, Bit 3
B1, Bit 0
G2, Bit 3
Dummy Pixel
Pixel n
Pixel n+1
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
data.
Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Himax Confidential
-P.57October, 2007
HX8340-B(N)
NRESET ‘1’
NCS
DNC
NRD
NWR
RNW
‘1’
‘0’
‘1’
E
DB17
-
---
R1, Bit 5
R2, Bit 5
R3, Bit5
DB16
-
---
R1, Bit 4
R2, Bit 4
R3, Bit5
DB15
-
---
R1, Bit 3
R2, Bit 3
R3, Bit 3
DB14
-
---
R1, Bit 2
R2, Bit 2
R3, Bit 2
DB13
-
---
R1, Bit 1
R2, Bit 1
R3, Bit 1
DB12
-
---
R1, Bit 0
R2, Bit 0
R3, Bit 0
DB11
-
--
G1, Bit 5
G2, Bit 5
G3, Bit 5
DB10
-
---
G1, Bit 4
G2, Bit 4
G3, Bit 4
DB9
-
---
G1, Bit 3
G2, Bit 3
G3, Bit 3
DB8
0
---
G1, Bit 2
G2, Bit 2
G3, Bit 2
DB7
0
---
G1, Bit 1
G2, Bit 1
G3, Bit 1
DB6
1
--
G1, Bit 0
G2, Bit 0
G3, Bit 0
DB5
0
---
B1, Bit 5
B2, Bit 5
B3, Bit 5
DB4
1
---
B1, Bit 4
B2, Bit 4
B3, Bit 4
DB3
1
---
B1, Bit 3
B2, Bit 3
B3, Bit 3
DB2
1
---
B1, Bit 2
B2, Bit 2
B3, Bit 2
DB1
0
---
B1, Bit 1
B2, Bit 1
B3, Bit 1
DB0
-
---
B1, Bit 0
Dummy Pixel
Pixel n
18-bits
Frame
Memory
B2, Bit 0
Pixel n+1
B1, Bit 0
Pixel n+2
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Blue data.
Himax Confidential
-P.58October, 2007
HX8340-B(N)
5.1.9 Serial Interface Data Color Coding for RAM data Write
Different display data formats are available for three colors depth supported by the LCM listed
below.
Write data for 12-bits/pixel (RGB 4-4-4-bits input), 4K-colors, 3AH=”03h”
3 pin serial interface
NRESET
‘1’
NCS
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
Pixel n+1
D1
D0
D8
R13 R12 R11 R10 G13 G12 G11 G10
1
D7
D6
D5
D4
D3
D2
D1
D0
D8
B13 B12 B11 B10 R23 R22 R21 R20
1
D7
D6
D5
D4
D3
D2
D1
D0
G23 G22 G21 G20 B23 B22 B21 B20
SCL
12-bits
12-bits
Look-Up Table for 4K-colors mapping (12-Bits to 18-Bits)
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. Pixel data with the 12-bits color depth information
Note 2. The most significant bits are: Rx3, Gx3 and Bx3
Note 3. The least significant bits are: Rx0, Gx0 and Bx0
Himax Confidential
-P.59October, 2007
HX8340-B(N)
Write data for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 3AH=”05h”
NRESET
‘1’
CSX
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
D1
D0
R14 R13 R12 R11 R10 G15 G14 G13
D8
1
Pixel n+1
D7
D6
D5
D4
D3
D2
D1
D0
D8
G12 G11 G10 B14 B13 B12 B11 B10
1
D7
D6
D5
D4
D3
D2
D1
D0
R24 R23 R22 R21 R20 G25 G24 G23
SCL
16-bits
Look-Up Table for 65k-colors mapping (16-Bits to 18-Bits)
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Himax Confidential
-P.60October, 2007
HX8340-B(N)
Write data for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 3AH= ”06h”
NRESET
‘1’
NCS
Pixel n
D8
SDA
1
D7
D6
D5
D4
D3
D2
D1
D0
D8
-
-
1
R15 R14 R13 R12 R11 R10
D7
D6
D5
D4
D3
D2
G15 G14 G13 G12 G11 G10
D1
D0
D8
-
-
1
D7
D6
D5
D4
D3
D2
D1
D0
-
-
B15 B14 B13 B12 B11 B10
SCL
18-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Himax Confidential
-P.61October, 2007
HX8340-B(N)
5.1.10 Color Depth Conversion Look-up Tables
Look Up Table Outputs
Frame Memory Data
(6-bit)
R005R004 R003 R002 R001 R000
G005G004 G003 G002 G001 G000
B005B004 B003 B002 B001 B000
R105R104 R103 R102 R101 R100
G105G104 G103 G102 G101 G100
B105B104 B103 B102 B101 B100
R205R204 R203 R202 R201 R200
G205G204 G203 G202 G201 G200
B205B204 B203 B202 B201 B200
R305R304 R303 R302 R301 R300
G305G304 G303 G302 G301 G300
B305B304 B303 B302 B301 B300
R405R404 R403 R402 R401 R400
G405G404 G403 G402 G401 G400
B405B404 B403 B402 B401 B400
R505R504 R503 R502 R501 R500
G505G504 G503 G502 G501 G500
B505B504 B503 B502 B501 B500
R605R604 R603 R602 R601 R600
G605G604 G603 G602 G601 G600
B605B604 B603 B602 B601 B600
R705R704 R703 R702 R701 R700
G705G704 G703 G702 G701 G700
B705B704 B703 B702 B701 B700
R805R804 R803 R802 R801 R800
G805G804 G803 G802 G801 G800
B805B804 B803 B802 B801 B800
R905R904 R903 R902 R901 R900
G905G904 G903 G902 G901 G900
B905B904 B903 B902 B901 B900
R105R104 R103 R102 R101 R100
G105G104 G103 G102 G101 G100
B105B104 B103 B102 B101 B100
R115R114 R113 R112 R111 R110
G115G114 G113 G112 G111 G110
B115B114 B113 B112 B111 B110
R125R124 R123 R122 R121 R120
G125G124 G123 G122 G121 G120
B125B124 B123 B122 B121 B120
R135R134 R133 R132 R131 R130
G135G134 G133 G132 G131 G130
B135B134 B133 B132 B131 B130
R145R144 R143 R142 R141 R140
G145G144 G143 G142 G141 G140
B145B144 B143 B142 B141 B140
R155R154 R153 R152 R151 R150
G155G154 G153 G152 G151 G150
B155B154 B153 B152 B151 B150
Default
value
after H/W
Reset
RGBSET
parameter
Look Up Table Input
Data
000000
1
0000
000011
2
0001
000101
3
0010
000111
4
0011
001001
5
0100
001011
6
0101
001101
7
0110
001111
8
0111
010001
9
1000
010011
10
1001
010101
11
1010
010111
12
1011
011001
13
1100
011011
14
1101
011101
15
1110
011111
16
1111
4k Color
Table 5. 13 Look-up Tables for 4k color mode
Himax Confidential
-P.62October, 2007
HX8340-B(N)
Look Up Table Outputs Frame
Memory Data (6-bit)
R005R004 R003 R002 R001 R000
B005B004 B003 B002 B001 B000
R105R104 R103 R102 R101 R100
B105B104 B103 B102 B101 B100
R205R204 R203 R202 R201 R200
B205B204 B203 B202 B201 B200
R305R304 R303 R302 R301 R300
B305B304 B303 B302 B301 B300
R405R404 R403 R402 R401 R400
B405B404 B403 B402 B401 B400
R505R504 R503 R502 R501 R500
B505B504 B503 B502 B501 B500
R605R604 R603 R602 R601 R600
B605B604 B603 B602 B601 B600
R705R704 R703 R702 R701 R700
B705B704 B703 B702 B701 B700
R805R804 R803 R802 R801 R800
B805B804 B803 B802 B801 B800
R905R904 R903 R902 R901 R900
B905B904 B903 B902 B901 B900
R105R104 R103 R102 R101 R100
B105B104 B103 B102 B101 B100
R115R114 R113 R112 R111 R110
B115B114 B113 B112 B111 B110
R125R124 R123 R122 R121 R120
B125B124 B123 B122 B121 B120
R135R134 R133 R132 R131 R130
B135B134 B133 B132 B131 B130
R145R144 R143 R142 R141 R140
B145B144 B143 B142 B141 B140
R155R154 R153 R152 R151 R150
B155B154 B153 B152 B151 B150
R165R164 R163 R162 R161 R160
B165B164 B163 B162 B161 B160
R175R174 R173 R172 R171 R170
B175B174 B173 B172 B171 B170
R185R184 R183 R182 R181 R180
B185B184 B183 B182 B181 B180
R195R194 R193 R192 R191 R190
B195B194 B193 B192 B191 B190
R205R204 R203 R202 R201 R200
B205B204 B203 B202 B201 B200
R215R214 R213 R212 R211 R210
B215B214 B213 B212 B211 B210
R225R224 R223 R222 R221 R220
B225B224 B223 B222 B221 B220
R235R234 R233 R232 R231 R230
B235B234 B233 B232 B231 B230
R245R244 R243 R242 R241 R240
B245B244 B243 B242 B241 B240
R255R254 R253 R252 R251 R250
B255B254 B253 B252 B251 B250
R265R264 R263 R262 R261 R260
B265B264 B263 B262 B261 B260
R275R274 R273 R272 R271 R270
B275B274 B273 B272 B271 B270
R285R284 R283 R282 R281 R280
B285B284 B283 B282 B281 B280
R295R294 R293 R292 R291 R290
B295B294 B293 B292 B291 B290
R305R304 R303 R302 R301 R300
B305B304 B303 B302 B301 B300
R315R314 R313 R312 R311 R310
B315B314 B313 B312 B311 B310
Default
value
after
H/W
Reset
Look Up Table Input
Data
RGBSET
parameter
000000
1
00000
000011
2
00001
000101
3
00010
000111
4
00011
001001
5
00100
001011
6
00101
001101
7
00110
001111
8
00111
010001
9
01000
010011
10
01001
010101
11
01010
010111
12
01011
011001
13
01100
011011
14
01101
011101
15
01110
011111
16
01111
100001
17
10000
100011
18
10001
100101
19
10010
100111
20
10011
101001
21
10100
101011
22
10101
101101
23
10110
101111
24
10111
110001
25
11000
110011
26
11001
110101
27
11010
110111
28
11011
111001
29
11100
111011
30
11101
111101
31
11110
111111
32
11111
65k Color
Note : Green color in 65k color mode is mapping directly.
Table 5. 14 Look-up Tables for 65k color mode
Himax Confidential
-P.63October, 2007
HX8340-B(N)
5.2 RGB Interface
The HX8340-B uses RCM[1:0]=’10’ or ‘11’ hardware setting to select RGB interface. When
after Power on Sequence, the RGB interface is activated. When RCM[1:0]=’10’ use VS, HS, DE,
DOTCLK, DB17-0 parallel lines for the RGB interface (RGB mode 1). When RCM[1:0]=’11’ use
VS, HS, DOTCLK, DB17-0 parallel lines for the RGB interface (RGB mode 2)
Pixel clock (DOTCLK) must be running all the time without stopping and it is used to entering
VS, HS, DE and DB17-0 lines states when there is a rising edge of the DOTCLK.
In RGB interface mode 1, the valid display data is inputted in pixel unit via DB17-0 according to
the high-level(‘H’) of DE signal, and display operations are executed in synchronization with the
frame synchronizing signal (VS), line synchronizing signal (HS) and pixel clock (DOTCLK). In
RGB interface mode 2, the valid display data is inputted in pixel unit via DB17-0 according to
the HBP setting of HS signal, and the VBP setting of VS. In these two RGB interface mode, the
input display data is not written to GRAM and is displayed directly.
Vertical synchronization (VS) signal is used to tell when there is received a new frame of the
display, and this is negative (‘-‘, ‘0’, low) active. Horizontal synchronization signal (HS) is used
to tell when there is received a new line of the frame, and this is negative (‘-‘, ‘0’, low) active.
Data enable (DE) is used to tell when there is received RGB information that should be
transferred on the display, and this is positive (‘+’, ‘1’, high) active. DB17-0 are used to tell what
is the information of the image that is transferred on the display when DE=’H’.
The pixel clock cycle is described in the following figure.
DOTCLK
VS
HS
DE
DB17-0
Figure 5. 22 DOTCLK Cycle
Himax Confidential
-P.64October, 2007
HX8340-B(N)
General timing diagram in RGB interface is as follow:
Figure 5. 23 RGB Interface Circuit Input Timing Diagram
The image information is correct on the display when the timings are in range on the interface.
However, the image information will be incorrect on the display, when timings are out of the
range on the RGB interface and the correct image information will be displayed automatically
(by the display module) on the next frame (vertical sync.), when there is returned from out of the
range to in range RGB interface timings.
Himax Confidential
-P.65October, 2007
HX8340-B(N)
1-Frame (TVP)
V Back Porch (TVBP)
VS
V Front Porch (T VFP)
HS
DE
1-Line (THP)
H Back Porch (THBP)
HS
Valid data area (THDISP )
H Front Porch (T HFP)
DOTCLK
DE
Data Bus
Latch data
In-Valid
In-Valid
D1 D2 D3 D4 D5
D1 D2 D3 D4 D5
In-Valid
Dn
Dn
Note: RGB mode 2 doesn’t need DE signal
Note: EPL=’0’, VSPL=’0’, HSPL=’0’ and DPL=’0’ of SETRGBIF (BBH) command.
Figure 5. 24 RGB Mode timing Diagram
Himax Confidential
-P.66October, 2007
HX8340-B(N)
All 3-kinds of bus width can be available during RGB interface mode (selected by COLMOD
(3AH) command for 6-bits, 16-bits and 18-bits data width)
3AH
50h
60h
3Ah
E0h
D17 D16 D15 D14 D13 D12 D11 D10
R4 R3
R2 R1 R0
x
G5 G4
R5 R4
R3 R2 R1
R0 G5 G4
D17 D16 D15 D14 D13 D12 D11 D10
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D9
G3
G3
D9
x
x
x
D8
G2
G2
D8
x
x
x
D7
G1
G1
D7
R5
G5
B5
D6
G0
G0
D6
R4
G4
B4
D5
B4
B5
D5
R3
G3
B3
D4
B3
B4
D4
R2
G2
B2
D3
B2
B3
D3
R1
G1
B1
D2
B1
B2
D2
R0
G0
B0
D1
B0
B1
D1
x
x
x
D0
x
B0
D0
x
x
x
Bus width
16-bits data
18-bits data
Bus width
6-bits data
Note 1: When 3AH=”E0h”, 6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth
information.
Note 2: Only 3AH= “50h”,”60h”, “E0h” are valid on RGB I/F, Others are invalid.
Note 3. ‘x’ don’t care, but need to set IOVCC or VSSD level.
Table 5. 15 RGB interface Bus Width Set Table
RGB Interface Mode
RGB I/F Mode DOTCLK
RGB Mode 1
RGB Mode 2
Used
Used
DE
VS
HS
Used
Not Used
Used
Used
Used
Used
Video Data bus
DB[B:0]
Used
Used
Register for Blanking
Porch setting
Not Used
Used
There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins.
In RGB Mode 1 (RCM1, RCM0 = “10”), writing data to display is done by DOTCLK and Video
Data Bus (DB[B:0]), when DE is high state. The external synchronization signals (DOTCLK, VS
and HS) are used for internal display signals. So, controller (host) must always transfer
DOTCLK, VS, HS and DE signals to driver.
In RGB Mode 2 (RCM1, RCM0 = “11”), blanking porch setting of VS and HS signals are defined
by RGBBPCTR command. DE pin is not used.
Himax Confidential
-P.67October, 2007
HX8340-B(N)
5.2.1 Color Order on RGB Interface
The meaning of the pixel information, when there are used 3 components/pixel (Red, Green
and Blue) on RGB interface, is describing on the following table:
Pixel Color
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
R Component
All bits are 0
All bits are 0
All bits are 0
All bits are 0
All bits are 1
All bits are 1
All bits are 1
All bits are 1
G Component
All bits are 0
All bits are 0
All bits are 1
All bits are 1
All bits are 0
All bits are 0
All bits are 1
All bits are 1
B Component
All bits are 0
All bits are 1
All bits are 0
All bits are 1
All bits are 0
All bits are 1
All bits are 0
All bits are 1
Note: There are only defined main colors on this table - Not all gray levels of colors.
Table 5. 16 Meaning of the Pixel Information for main colors on RGB Interface
Himax Confidential
-P.68October, 2007
HX8340-B(N)
5.2.2 RGB Data Color Coding
18-bits/pixel Colors Order on 6-bits Data width RGB Interface (RGB 6-6-6-bits input).
There are 1 pixel (3 sub-pixels) per 3 bytes, 262K-colors, 3AH= ”E0h”
NRESET ‘1’
RCM = ‘1’
RCM
VS
‘1’
HS
‘1’
DE
‘1’
DOTCLK
DB17
-
-
-
-
-
DB16
-
-
-
-
-
DB9
-
-
-
-
-
DB8
-
-
-
-
-
DB7
R1, Bit 5
G1, Bit 5
B1, Bit 5
R2, Bit 5
G2, Bit 5
DB6
R1, Bit 4
G1, Bit 4
B1, Bit 4
R2, Bit 4
G2, Bit 4
DB5
R1, Bit 3
G1, Bit 3
B1, Bit 3
R2, Bit 3
G2, Bit 3
DB4
R1, Bit 2
G1, Bit 2
B1, Bit 2
R1, Bit 2
G2, Bit 2
DB3
R1, Bit 1
G1, Bit 1
B1, Bit 1
R2, Bit 1
G2, Bit 1
DB2
R1, Bit 0
G1, Bit 0
B1, Bit 0
R2, Bit 0
G2, Bit 0
DB1
-
-
-
-
-
DB0
-
-
-
-
-
Pixel n
Pixel n+1
6-bits
Frame
Memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit7, LSB=Bit0 for Red, Green and Blue
data. (3-trandfer data one pixel)
Note 2. ‘-’ Don’t care, but need to set IOVCC or VSSD level.
Himax Confidential
-P.69October, 2007
HX8340-B(N)
16-bits/pixel Colors Order on the 16-bits Data width RGB Interface (RGB 5-6-5-bits input).
There are 1 pixel (3 sub-pixels) per 1 bytes, 65K-colors, 3AH= ”50h”
NRESET ‘1’
RCM = ‘1’
RCMx
VS
‘1’
HS
‘1’
DE
‘1’
DOTCLK
DB17, R4
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
R5, Bit 4
DB16, R3
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
R5, Bit 3
DB15, R2
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
R5, Bit 2
DB14, R1
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R5, Bit 1
DB13, R0
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
R5, Bit 0
DB12
-
-
-
-
-
DB11, G5
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G5, Bit 5
DB10,
G4
DB9, G3
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G5, Bit 4
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
G5, Bit 3
DB8, G2
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
G5, Bit 2
DB7, G1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
G5, Bit 1
DB6, G0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
DB5, B4
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
DB4, B3
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
DB3, B2
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
DB2, B1
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
DB1, B0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
DB0
-
-
-
-
-
Pixel n
16-bits
Pixel n+1
16-bits
Pixel n+2
Pixel n+3
Pixel n+4
16-bits
18-bits
Frame
Memory
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and
MSB=Bit4, LSB=Bit0 for Red and Blue data.
Himax Confidential
-P.70October, 2007
HX8340-B(N)
18-bits/pixel Colors Order on the 18-bits Data width RGB Interface (RGB 6-6-6-bits input).
There are 1 pixel (3 sub-pixels) per 1 bytes, 262K-colors, 3AH= ”60h”
NRESET ‘1’
RCM = ‘1’
RCMx
VS
‘1’
HS
‘1’
DE
‘1’
DOTCLK
D17, R5
R1, Bit 5
R2, Bit 5
R3, Bit 5
R4, Bit 5
R5, Bit 5
D16, R4
R1, Bit 4
R2, Bit 4
R3, Bit 4
R4, Bit 4
R5, Bit 4
D15, R3
R1, Bit 3
R2, Bit 3
R3, Bit 3
R4, Bit 3
R5, Bit 3
D14, R2
R1, Bit 2
R2, Bit 2
R3, Bit 2
R4, Bit 2
R5, Bit 2
D13, R1
R1, Bit 1
R2, Bit 1
R3, Bit 1
R4, Bit 1
R5, Bit 1
D12, R0
R1, Bit 0
R2, Bit 0
R3, Bit 0
R4, Bit 0
R5, Bit 0
D11, G5
G1, Bit 5
G2, Bit 5
G3, Bit 5
G4, Bit 5
G5, Bit 5
D10, G4
G1, Bit 4
G2, Bit 4
G3, Bit 4
G4, Bit 4
G5, Bit 4
D9, G3
G1, Bit 3
G2, Bit 3
G3, Bit 3
G4, Bit 3
G5, Bit 3
D8, G2
G1, Bit 2
G2, Bit 2
G3, Bit 2
G4, Bit 2
G5, Bit 2
D7, G1
G1, Bit 1
G2, Bit 1
G3, Bit 1
G4, Bit 1
G5, Bit 1
D6, G0
G1, Bit 0
G2, Bit 0
G3, Bit 0
G4, Bit 0
G5, Bit 0
D5, B5
B1, Bit 5
B2, Bit 5
B3, Bit 5
B4, Bit 5
B5, Bit 5
D4, B4
B1, Bit 4
B2, Bit 4
B3, Bit 4
B4, Bit 4
B5, Bit 4
D3, B3
B1, Bit 3
B2, Bit 3
B3, Bit 3
B4, Bit 3
B5, Bit 3
D2, B2
B1, Bit 2
B2, Bit 2
B3, Bit 2
B4, Bit 2
B5, Bit 2
D1, B1
B1, Bit 1
B2, Bit 1
B3, Bit 1
B4, Bit 1
B5, Bit 1
D0, B0
B1, Bit 0
B2, Bit 0
B3, Bit 0
B4, Bit 0
B5, Bit 0
Pixel n
Pixel n+1
18-bits
Frame
Memory
Pixel n+2
Pixel n+3
Pixel n+4
18-bits
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and
Blue data.
Himax Confidential
-P.71October, 2007
HX8340-B(N)
6. Display Data GRAM
The display data RAM stores display dots and consists of 696960 bits (176x18x220 bits). There
is no restriction on access to the RAM even when the display data on the same address is
loaded to DAC There will be no abnormal visible effect on the display when there is a
simultaneous Panel Read and Interface Read or Write to the same location of the Frame
Memory.
176 x 220 x 18 bit
528
528
528
6.1 Display Data GRAM Mapping
Every pixel (18-bit) data in GRAM is located by a (Page, Column) address (Y, X). By specifying
the arbitrary window address CASET’s SC, EC and PASET’s SP, EP, it is possible to access
the GRAM by setting RAMWR or RAMRD commands from start positions of the window
address.
-------------------------------------------------
(00,AC)H
(01,AC)H
(02,AC)H
(03,AC)H
(04,AC)H
(05,AC)H
(00,AD)H
(01,AD)H
(02,AD)H
(03,AD)H
(04,AD)H
(05,AD)H
(00,AE)H
(01,AE)H
(02,AE)H
(03,AE)H
(04,AE)H
(05,AE)H
--------
---------
--------
--------
--------
(D6,00)H
(D7,00)H
(D8,00)H
(D9,00)H
(DA,00)H
(DB,00)H
(D6,01)H (D6,02)H
--------(D6,AC)H (D6,AD)H (D6,AE)H
(D7,01)H (D7,02)H
--------(D7,AC)H (D7,AD)H (D7,AE)H
(D8,01)H (D8,02)H
--------(D8,AC)H (D8,AD)H (D8,AE)H
(D9,01)H (D9,02)H
--------(D9,AC)H (D9,AD)H (D9,AE)H
(DA,01)H (DA,02)H
--------(DA,AC)H (DA,AD)H (DA,AE)H
(DB,01)H (DB,02)H
--------(DB,AC)H (DB,AD)H (DB,AE)H
Table 6. 1 GRAM Address for Display Panel Position
(00,AF)H
(01,AF)H
(02,AF)H
(03,AF)H
(04,AF)H
(05,AF)H
--------
(00,02)H
(01,02)H
(02,02)H
(03,02)H
(04,02)H
(05,02)H
--------
(00,01)H
(01,01)H
(02,01)H
(03,01)H
(04,01)H
(05,01)H
--------
(00,00)H
(01,00)H
(02,00)H
(03,00)H
(04,00)H
(05,00)H
(D6,AF)H
(D7,AF)H
(D8,AF)H
(D9,AF)H
(DA,AF)H
(DB,AF)H
Himax Confidential
-P.72October, 2007
HX8340-B(N)
6.2 Address Counter (AC) of GRAM
The HX8340-B contains an address counter (AC) which assigns address for writing/reading
pixel data to/from GRAM. The address pointers set the position of GRAM. Every time when a
pixel data is written into the GRAM, the X address or Y address of AC will be automatically
increased by 1 (or decreased by 1), which is decided by the register (MADTCL’s MV(B5),
MX(B6) and MY(B7) bits setting.
To simplify the address control of GRAM access, the window address function allows for writing
data only to a window area of GRAM specified by registers. After data being written to the
GRAM, the AC will be increased or decreased within setting window address-range which is
specified by the CASET (start: SC, end: EC) and the PASET (start: SP, end: EP). Therefore,
the data can be written consecutively without thinking a data wrap by those bit function.
Himax Confidential
-P.73October, 2007
HX8340-B(N)
6.2.1 System interface to GRAM Write Direction
Data stream from MCU is like
this figure
B
E
Figure 6. 1 Image Data Sending Order from the Host
The data is written in the order illustrated above. The counter which dictates where in the
physical memory the data is to be written is controlled by MADTCL’s MV(B5), MX(B6) and
MY(B7) bits setting
CASET
MY
MX
MV
PASET
MADCTL
Virtual to physical Pointer
transtator
Virtual (0,0) when
MV = don't care,
MX = '0', MY = '0'
Physical Column
Pointer
(0,X)
(0,0)
Physical Page
Pointer
Physical
axes
(Y,0)
Virtual (0,0) when
MV = don't care,
MX = '0', MY = '1'
Virtual (0,0) when
MV = don't care,
MX = '1', MY = '0'
X=175d, Y= 219d
(Y,X)
Virtual (0,0) when
MV = don't care,
M X = '1', MY = '1'
Figure 6. 2 Image Data Writing Control
MV
0
0
0
0
1
1
1
1
MX
0
0
1
1
0
0
1
1
MY
CASET
PASET
0
Direct to Physical Column Pointer
Direct to Physical Page Pointer
1
Direct to (Y - Physical Page Pointer)
0
Direct to (X-Physical Column Pointer)
1
Direct to (X - Physical Column Pointer)
0
1
0
Direct to (X-Physical Column Pointer)
1
Direct to (X - Physical Column Pointer)
Table 6. 2 CASET and PASET Control for Physical Column/Page Pointers
Himax Confidential
-P.74October, 2007
HX8340-B(N)
For each image orientation, the controls for the column and page counters apply as below:
Condition
Column Counter
Page Counter
Return to
Return to
When RAMWR/RAMRD command is accepted.
“Start Column”
“Start Page”
Complete Pixel Pair Write/Read action
Increment by 1
No change
Return to
The Column counter value is larger than “End column.”
Increment by 1
“Start Column”
Return to
Return to
The Page counter value is larger than “End page”.
“Start Column”
“Start Page”
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write
Direction set by MADCTL bits B7, B6 and B5.
Table 6. 3 Rules for Updating GRAM Order
Himax Confidential
-P.75October, 2007
HX8340-B(N)
The following figure depicts the GRAM address update method with MV, MX and MY bit setting.
Display
MADCTR
Data
parameter
Direction MV MX MY
Image in the
Host
Image in the Driver (GRAM)
H/W Position (0,0)
B
Normal
0
0
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
B
Y-Invert
0
0
H/W Position (0,0)
1
X,Y address (0,0)
X: CASET
Y: RASET
E
B
E
B
X-Invert
0
1
H/W Position (0,0)
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
H/W Position (0,0)
B
X-Invert
Y-Invert
0
1
E
1
X,Y address (0,0)
X: CASET
Y: RASET
B
E
B
X-Y
Exchange
1
0
H/W Position (0,0)
B
X,Y address (0,0)
X: CASET
Y: RASET
0
E
E
H/W Position (0,0)
B
X-Y
Exchange
X-invert
1
0
1
X,Y address (0,0)
X: CASET
Y: RASET
E
B
X-Y
Exchange
Y-invert
1
1
H /W
Position (0 ,0 )
1
B
X , Y address (0 , 0 )
X : CASET
Y : RASET
E
H/W Position (0,0)
B
1
B
0
E
X-Y
Exchange
X-invert
Y-invert
E
E
1
E
B
X,Y address (0,0)
X: CASET
Y: RASET
Table 6. 4 Address Direction Settings
Himax Confidential
-P.76October, 2007
HX8340-B(N)
Example for rotation with MY, MX and MV
This example is using following values: start page = 0, end page = 40, start column = 0 and end
column = 20 => commands: page address set (0, 40) and column address set (0, 20). The sent
figure is as follows and its sending order is as follows.
Written image and direction from the host to frame memory
Image from the host
Writieg direction
Start page=0
Start
End page=40
End
Start column =0
End column=20
Image position on the frame memory with MY = 0/ 1 , MX = 0 / 1, MV = 0/ 1
Memory
Location
(0,0)
FRAME
MEMORY
MY =0
MX =0
MV =0
Memory
Location
(0,0)
FRAME
MEMORY
MY =0
MX =1
MV =0
FRAME
MEMORY
MY =1
MX =0
MV =0
Memory
Location
(0,0)
Memory
Location
(0,0)
FRAME
MEMORY
MY =1
MX =1
MV =0
Figure 6. 3 Example for rotation with MY, MX and MV – 1
Himax Confidential
-P.77October, 2007
HX8340-B(N)
Written image and direction from the host to frame memory
Image from the host
Writieg direction
Start page=0
Start
End page=40
End
Start column =0
End column=20
Image position on the frame memory with MY = 0/ 1 , MX = 0 / 1, MV = 0/ 1
Memory
Location
(0,0)
FRAME
MEMORY
MY =0
MX =0
MV =1
Memory
Location
(0,0)
MY =1
MX =0
MV =1
Memory
Location
(0,0)
FRAME
MEMORY
MY =0
MX =1
MV =1
FRAME
MEMORY
Memory
Location
(0,0)
FRAME
MEMORY
MY =1
MX =1
MV =1
Figure 6. 4 Example for rotation with MY, MX and MV - 2
Himax Confidential
-P.78October, 2007
HX8340-B(N)
6.3 GRAM to Display Address Mapping
By setting the external SMX pin, the relation between the source output channel and the
GRAM address can be changed as reverse display. By setting the external SMY pin, the
relation between the gate output channel and the GRAM address can be changed as reverse
display. By setting the external SRGB pin, the relation between the source output channel
and the <R>, <G>, <B> dot allocation can be reversed for different LCD color filter
arrangement. Table 6.5, Table 6.6 and Table 6.7 show the relationship among the GRAM
data allocation, the source output channel, and the R, G, B dot allocation.
SRGB = ‘H’
Source SMX = ‘H’ S1
Output SMX = ‘L’ S526
X Address
RGB data
Pixel
R
S2
S527
S3
S528
S4
S523
S5
S524
S6
S525
-------------
S523
S4
“00”h
G
Pixel 1
B
R
“01”h
G
Pixel 2
B
-------------------
R
S2
S527
S1
S526
S6
S525
S5
S524
-------------
S523
S6
S524
S5
S525
S6
“AE”h
G
B
Pixel 175
S526
S1
R
S527
S2
S528
S3
“AF”h
G
B
Pixel 176
SRGB = ‘L’
Source SMX = ‘L’ S3
Output SMX = ‘H’ S528
X Address
Bit Allocation
Pixel
R
S4
S523
S524
S5
S525
S4
“00”h
“01”h
------“AE”h
G
B
R
G
B
------R
G
B
Pixel 1
Pixel 2
------Pixel 175
Table 6. 5 GRAM X Address and Display Panel Position
S526
S3
R
S527
S2
S528
S1
“AF”h
G
B
Pixel 176
Himax Confidential
-P.79October, 2007
HX8340-B(N)
S528
0001h
0101h
0201h
0301h
0401h
0501h
0601h
0701h
0801h
0002h
0102h
0202h
0302h
0402h
0502h
0602h
0702h
0802h
-------------------------------------------------------------------------
-------
-------
---------
-------
-------
-------
-------
00AEh
01AEh
02AEh
03AEh
04AEh
05AEh
06AEh
07AEh
08AEh
S527
S526
S525
0000h
0100h
0200h
0300h
0400h
0500h
0600h
0700h
0800h
-------
00ADh
01ADh
02ADh
03ADh
04ADh
05ADh
06ADh
07ADh
08ADh
S524
S523
S522
S521
G1
G2
G3
G4
G5
G6
G7
G8
G9
-------
00ACh
01ACh
02ACh
03ACh
04ACh
05ACh
06ACh
07ACh
08ACh
S520
S519
S518
---------
S517
S9
S8
S7
S6
S5
S4
S3
S2
S1
S/G pins
00AFh
01AFh
02AFh
03AFh
04AFh
05AFh
06AFh
07AFh
08AFh
G211
G212
G213
G214
G215
G216
G217
G218
G219
G220
D200h
D300h
D400h
D500h
D600h
D700h
D800h
D900h
DA00h
DB00h
D201h
D301h
D401h
D501h
D601h
D701h
D801h
D901h
DA01h
DB01h
D202h
D302h
D402h
D502h
D602h
D702h
D802h
D902h
DA02h
DB02h
---------------------------------------------------------------------------------
D2ACh
D3ACh
D4ACh
D5ACh
D6ACh
D7ACh
D8ACh
D9ACh
DAACh
DBACh
D2ADh
D3ADh
D4ADh
D5ADh
D6ADh
D7ADh
D8ADh
D9ADh
DAADh
DBADh
D2AEh
D3AEh
D4AEh
D5AEh
D6AEh
D7AEh
D8AEh
D9AEh
DAAEh
DBAEh
D2AFh
D3AFh
D4AFh
D5AFh
D6AFh
D7AFh
D8AFh
D9AFh
DAAFh
DBAFh
Table 6. 6 GRAM Address and Display Panel Position ( SMY = ’L’ )
S528
S527
0001h
0101h
0201h
0301h
0401h
0501h
0601h
0701h
0801h
0002h
0102h
0202h
0302h
0402h
0502h
0602h
0702h
0802h
-------------------------------------------------------------------------
-------
-------
---------
-------
-------
-------
-------
00EEh
01EEh
02EEh
03EEh
04EEh
05EEh
06EEh
07EEh
08EEh
S526
S525
0000h
0100h
0200h
0300h
0400h
0500h
0600h
0700h
0800h
-------
00EDh
01EDh
02EDh
03EDh
04EDh
05EDh
06EDh
07EDh
08EDh
S524
S523
S522
S521
G220
G219
G218
G217
G216
G215
G214
G213
G212
-------
00ECh
01ECh
02ECh
03ECh
04ECh
05ECh
06ECh
07ECh
08ECh
S520
S519
S518
---------
S517
S9
S8
S7
S6
S5
S4
S3
S2
S1
S/G pins
00EFh
01EFh
02EFh
03EFh
04EFh
05EFh
06EFh
07EFh
08EFh
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
D200h
D300h
D400h
D500h
D600h
D700h
D800h
D900h
DA00h
DB00h
D201h
D301h
D401h
D501h
D601h
D701h
D801h
D901h
DA01h
DB01h
D202h
D302h
D402h
D502h
D602h
D702h
D802h
D902h
DA02h
DB02h
---------------------------------------------------------------------------------
D2ACh
D3ACh
D4ACh
D5ACh
D6ACh
D7ACh
D8ACh
D9ACh
DAACh
DBACh
D2ADh
D3ADh
D4ADh
D5ADh
D6ADh
D7ADh
D8ADh
D9ADh
DAADh
DBADh
D2AEh
D3AEh
D4AEh
D5AEh
D6AEh
D7AEh
D8AEh
D9AEh
DAAEh
DBAEh
D2AFh
D3AFh
D4AFh
D5AFh
D6AFh
D7AFh
D8AFh
D9AFh
DAAFh
DBAFh
Table 6. 7 GRAM Address and Display Panel Position (SMY = ’H’)
Himax Confidential
-P.80October, 2007
HX8340-B(N)
HX8340-B supports three kinds of display mode: one is Normal Display Mode, one is the other
is Partial Display Mode, and Scrolling Display Mode.
When the NORON(R13h) command is set, HX8340-B will be into Normal Display Mode. When
the PLTON(R12h) command is set, HX8340-B will be into Partial Display Mode.
6.3.1 Normal Display On or Partial Mode On, Vertical Scroll Off
In this mode, content of the frame memory within an area where column pointer is 0000h to
00AFh and page pointer is 0000h to 00DBh is displayed. To display a dot on leftmost top corner,
store the dot data at (column pointer, page pointer) = (0,0) (SMX = ‘L’, SMY = ‘L’).
13
14
20
21
22
23
30
31
32
0Y
0Z
00h
00
01
02
03
04
1W
1X
1Y
1Z
01h
10
11
12
13
14
2X
2Y
2Z
20
21
22
23
3Y
3Z
30
31
32
220 Lines
220 Lines
176 x 220 x 18 bit
Frame Memory
U0
U1
UY
UZ
V0
V1
VY
VZ
WY WZ
W0 W1
X0
X1
X2
Y0
Y1
Y2
Y3
Z0
Z1
Z2
Z3
Z4
Z5
ZV
05
AFh
12
0X
AEh
11
0W
05
AD h
10
0 1h
04
00h
03
AFh
02
AEh
0 1h
01
AD h
00h
00
0W
0X
0Y
0Z
0 0h
1W
1X
1Y
1Z
0 1h
2X
2Y
2Z
3Y
3Z
UY
UZ
VY
VZ
176 x 220
LCD Panel
U0
U1
V0
V1
WY WZ
W0 W1
XX
XY
XZ
X0
X1
X2
YW
YX
YY
YZ
DAh
Y0
Y1
Y2
Y3
ZW
ZX
ZY
ZZ
DBh
Z0
Z1
Z2
Z3
D9h
Z4
Z5
ZV
XX
XY
XZ
D9h
YW
YX
YY
YZ
DAh
ZW
ZX
ZY
ZZ
DBh
176 Columns
Himax Confidential
-P.81October, 2007
HX8340-B(N)
Example:
(1) PLTON command (R12h),
(2) R30h’s SR=11DEC, ER=130DEC, MADCTL’s B4(ML)=’0’ (SMY = ’L’).
Physical 0, 0 Point
ML = '0'
0
*-- 123456789 --*
130
*-- ABCDEFG --*
Panel Scan Direction
11
219
0
0
Non- display Area
*-- 123456789--*
Non- display Area
219
219
Content of GRAM
Display Panel
Figure 6. 5 Example of partial mode on (ML=’0’)
Example:
(1) PLTON command (R12h),
(2) R30h’s SR= 11DEC, ER=130DEC, MADCTL’s B4(ML)=’1’ (SMY = ’L’).
Physical 0, 0 Point
ML = 1
0
130
11
Panel Scan Direction
*-- 123456789 --*
*-- HX8356- A --*
*-- ABCDEFG --*
0
219
Non- display Area
*-- ABCDEFG --*
Non- display Area
219
Content of GRAM
0
219
Display Panel
Figure 6. 6 Example of partial mode on (ML=’1’)
Himax Confidential
-P.82October, 2007
HX8340-B(N)
The refresh gate scan cycle in the rest display area of the screen (non-display area) can be
specified by ISC[3:0] bits. The scan cycle is set to an odd number from 0~13.The polarity is
inverted every scan cycle.
ISC3
ISC2
ISC1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ISC0
Scan Cycle
0
0 frame
1
3 frames
0
5 frames
1
7 frames
0
9 frames
1
11 frames
0
13 frames
1
15 frames
0
17 frames
1
19 frames
0
21 frames
1
23 frames
0
25 frames
1
27 frames
0
29 frames
1
31 frames
Table 6. 8 ISC[3:0] Bits Definition
fFLM = 60Hz
50 ms
84 ms
117 ms
150 ms
184 ms
217 ms
251 ms
284 ms
317 ms
351 ms
384 ms
418 ms
451 ms
484 ms
518 ms
The rest display area (non-display area) will be the white display if the type of LCD is normally
white (NWB = “1”) and will be the black display if the type of LCD is normally black (NWB = “0”)
in refresh gate scan cycle.
Himax Confidential
-P.83October, 2007
HX8340-B(N)
6.3.2 Vertical Scroll Display Mode
The vertical scrolling display is specified by VSCRDEF instruction (R33h) and VSCRSADD
instruction (R37h).
Original
Scrolling
TFA
VSA
BFA
Figure 6. 7 Vertical Scrolling
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=220. In this case, scrolling is
applied as shown below.
Example (1) TFA=’2d’, VSA=’218d’, BFA=’0d’, VSP=’3d’ when MADCTL B4 (ML)=0
(SMX = ‘L’, SMY = ‘L’).
AFh
AEh
ADh
01h
00h
AF h
AEh
ADh
01h
00h
Top f ixed area
00 01
02 03 04 05
0W 0X 0Y 0Z
00h
00 01 02 03 04 05
0W 0X 0Y 0Z
00h
10 11
12 13 14
1W 1X 1Y 1Z
01h
10 11 12 13 14
1W 1X 1Y 1Z
01h
20 21 22 23
2X 2Y 2Z
30 31 32
3Y 3Z
30 31 32 33
40 41 42
Scro ll area
176 x 220 x18bit
Frame memory
U0 U1
UY UZ
V0 V1
V0 V1
VY VZ
W0 W1
W0 W1
WY WZ
X0 X1
X0
X1 X2
Y0 Y1
XX XY XZ
Y2 Y3
Z0 Z1 Z2 Z3 Z4
Z5
4Y 4Z
176 x 220
LCD panel
D9h
Y0 Y1 Y2
YW YX YY YZ
DAh
Z0 Z1 Z2 Z3
ZV ZW ZX ZY ZZ
DBh
20 21 22 23 24 25
VY VZ
WY WZ
XY XZ
YX YY YZ
D9h
ZW ZX ZY ZZ
DAh
2V 2W 2X 2Y 2Z
DBh
Sc r o l l a r e a = 2 1 8 l in e s
Scroll
pointer
=03H
3X 3Y 3Z
Figure 6. 8 Memory Map of Vertical Scrolling I
Himax Confidential
-P.84October, 2007
HX8340-B(N)
(SMX = ‘L’, SMY = ‘L’).
23
30
31
32
Scro ll area
0Y
0Z
1W
1X
1Y
1Z
2X
2Y
2Z
3Y
3Z
UY
0W
0X
0Y
0Z
00h
1W
1X
1Y
1Z
01h
3X
3Y
3Z
4Y
4Z
V1
VY
VZ
W1
WY
WZ
X1
XY
XZ
0 0h
00
01
02
03
04
0 1h
10
11
12
13
14
30
31
32
33
40
41
42
UZ
V0
Scroll
pointer
=03H
176 x 220 x 18bit
Frame memory
U0
176 x 220
LCD panel
U1
V0
V1
VY
VZ
W0
W0
W1
WY
WZ
X0
Bottom fixed area
X0
X1
Y0
Y1
Z0
Z1
X2
Y2
Y3
Z2
Z3
Z4
Z5
ZV
05
22
0X
AFh
21
0W
AEh
20
05
AD h
14
01h
04
13
00h
03
12
AFh
02
11
AEh
01h
01
10
AD h
0 0h
Top f ixed area
00
XX
XY
XZ
D9h
20
21
22
YW
YX
YY
YZ
DAh
Y0
Y1
Y2
Y3
ZW
ZX
ZY
ZZ
DBh
Z0
Z1
Z2
Z3
YW
Z4
Z5
ZV
ZW
2X
2Y
2Z
D9h
YX
YY
YZ
DAh
ZY
ZZ
DBh
ZX
Figure 6. 9 Memory Map of Vertical Scrolling II
(SMX = ‘L’, SMY = ‘L’).
30 31 32
00 01 02 03 04 05
0W 0X 0Y 0Z
00h
10 11 12 13 14
1W
01h
50 51 52 53
3Y 3Z
5X 5Y 5Z
60 61 62
6Y 6Z
4Z
50
5Z
176 x 220
LCD panel
Scroll
pointer
=05H
176 x 220 x 18bit
Frame memory
B o t t o m f ix e d a re a
U0
U1
UY UZ
X0 X1
V0
V1
VY VZ
20 21
W0 W1
WY WZ
30 31
X0 X1 X2
Y0 Y1 Y2 Y3
Z0 Z1 Z2
1X 1Y 1Z
Sc r o l l a r e a
40 41
E Fh
01h
2X 2Y 2Z
EE h
20 21 22 23
00h
ED h
1W 1X 1Y 1Z
01h
0W 0X 0Y 0Z
10 11 12 13 14
00h
EFh
EE h
EDh
01h
00h
T o p f ix e d a r e a
00 01 02 03 04 05
Z3 Z4 Z5
XX XY XZ
13Dh
40 41 42
YW YX YY YZ
13Eh
Y0 Y1 Y2 Y3
13Fh
Z0 Z1 Z2 Z3 Z4 Z5
ZV ZW ZX ZY ZZ
XY XZ
3Y 3Z
4X 4Y 4Z
13Dh
YW YX YY YZ
13Eh
ZV ZW ZX ZY ZZ
13Fh
Figure 6. 10 Memory Map of Vertical Scrolling III
Himax Confidential
-P.85October, 2007
HX8340-B(N)
Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands “Vertical
Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h).
Case 1: TFA + VSA + BFA ≠ ‘220d’
N/A. Do not set TFA + VSA + BFA ≠‘220d’. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA= ‘20d’ (Scrolling)
Example (1) When TFA=’0d’, VSA=’220d’, BFA=’0d’ and VSP=’40d’, MADCTL parameter
B4(ML)=’0’
Figure 6. 11 Vertial scroll example when ML=’0’
Example (2) TFA=’30d’, VSA=’190d’, BFA=’0d’ and VSP=’80d’ ,MADCTRL parameter B4(ML)
= ’1’
Figure 6. 12 Vertial scroll example when ML=’1’
Himax Confidential
-P.86October, 2007
HX8340-B(N)
6.3.3 Updating Order on Display Active Area in RGB Interface Mode
(Normal Mode On + Sleep Out)
There is defined different kind of updating orders for display in RGB interface mode (RCM[1:0]
= ‘10’ or ‘11’). These updating are controlled by external RL pin internal CRL bit based on
external SMX pin setting and external TB pin/ internal CTB bit based on external SMY pin
setting.
Please note that as internal CRL bit be written in RGB interface, the external pin RL control is
invalid, and CRL is operated based on external pin SMX setting. As internal CTB bit be written
in RGB interface, the external pin TB control is invalid, and CRL is operated based on external
pin SMY setting.
Data streaming direction from the host to the display is described in the following figure.
B
Data stream from
RGB Interface
is like in this figure
HX8340-B
E
Figure 6. 13 Data Streaming Order in RGB I/F
Himax Confidential
-P.87October, 2007
HX8340-B(N)
Physical
0,0
Point
Start
Point
0,0
Active area on the LCD
Vertical counter(0-Y)
HX8340-B
Horizontal counter (0-X)
End
Point
Y,X
Figure 6. 14 Updating order when TB = ‘L’ and RL = ‘L’
Physical
0,0
Point
Vertical counter( 0- Y)
End
Point
X, Y
Start
Point
0,0
Horizontal counter (X-0)
Figure 6. 15 Updating order when TB = ‘L’ and RL = ‘H’
Himax Confidential
-P.88October, 2007
HX8340-B(N)
Physical
0, 0
Point
Vertical counter (Y- 0)
Start
Point
0, 0
End
Point
Y, X
Horizontal counter (0-X)
Figure 6. 16 Updating order when TB = ‘H’ and RL = ‘L’
Physical
0,0
Point
End
Point
Y, X
Verti cal counter(Y- 0)
Horizontal counter (X-0)
Start
Point
0, 0
Figure 6. 17 Updating order when TB = ‘H’ and RL = ‘H’
Condition
Horizontal Counter
Vertical Counter
An active VS signal is received
Return to 0
Return to 0
Single Pixel information of the active area is received
Increment by 1
No change
An active HS signal between two active area lines
Return to 0
Increment by 1
The Horizontal counter value is larger than X and the
Return to
Return to
Vertical counter value is larger than Y
“Start Column”
“Start Page”
Note: Pixel order is RGB on the display.
Table 6. 9 Rules for Updating Order on Display Active Area in RGB Interface Display Mode
Himax Confidential
-P.89October, 2007
HX8340-B(N)
7. Functional Description
7.1 Internal Oscillator
The HX8340-B can oscillate an internal R-C oscillator for internal operation. Because the
tolerance of internal oscillator frequency is ±5%, it can be adjusted for initial 2.52MHz internal
clock generation. With other dividers setting, the 2.51MHz internal clock can be used to
generate clock for other part of the chip using.
In RGB interface mode (RCM[1:0] = ‘10’ or ‘11’), external DOTCLK will be replace the internal
clock for other part of the chip using.
RGB Display Mode
DOTCLK
Display
Controller
DIV[1:0]
Internal Display Mode
Oscillator
Clock
2.52MHz
fosc
RADJ[2:0]
Frequency
Divider 1
FS0[2:0]
Step up Circuit 1
( for DDVDH)
Frequency
Divider 2
FS1[2:0]
Step up Circuit 2
( for VGH,VGL)
Step up Circuit 3
( for VCL)
DOTCLK
RGB Display Mode
Figure 7. 1 HX8340-B Internal Clock Circuit
Himax Confidential
-P.90October, 2007
HX8340-B(N)
7.2 Gamma Characteristic Correction Function
The HX8340-B incorporates gamma adjustment function for the 262,144-color display (64
grayscale for each R, G and B color). Gamma adjustment operation is implemented by deciding
the8 grayscale levels firstly in gamma adjustment control registers to match the LCD panel.
These registers are available both for positive polarities and negative polarities.
Graphics
RAM
(GRAM)
MP02 MP01 MP00
Positive
Polarity
Register
R R R R R R GG G G GG B B B B B B
54 3210 5 432 10 54 3210
MP12 MP11 MP10
MP22 MP21 MP20
MP32 MP31 MP30
MP42 MP41 MP40
MP52 MP51 MP50
CP
CP01 CP00
CP
CP
04
03
02
CP13 CP12 CP11 CP10
CP23 CP22 CP21 CP20
CP
CP33 CP32 CP31 CP30
43
6
6
OP04 OP03 OP01 OP00
6
OP13
OP
OP11 OP10
12
CGM CGM CGM CGM
11
V0
6-bit Grayscale
6-bit Grayscale
6-bit Grayscale
D/A Converter
D/A Converter
D/A Converter
Output Driver
Output Driver
Output Driver
V1
Grayscale
Voltage
V63
Generator
Negative
Polarity
Register
10
01
00
MN02 MN01 MN00
MN12 MN11 MN10
MN22 MN21 MN20
MN
MN31 MN30
32
MN
MN41 MN40
42
MN
MN51 MN50
52
CN
CN01 CN00
CN
CN
04
03
02
CN13 CN12 CN11 CN10
CN23 CN22 CN21 CN20
R
G
B
LCD
CN
CN33 CN32 CN31 CN30
43
ON04 ON03 ON01 ON00
ON13 ON
ON11 ON10
12
Figure 7. 2 Grayscale Control
Himax Confidential
-P.91October, 2007
HX8340-B(N)
Structure of Grayscale Voltage Generator
Eight reference gamma voltages (RVP 0, 1, 8, 20, 43, 55, 62 and 63). For positive and negative
polarity are specified by the center adjustment, the micro adjustment and the offset adjustment
registers firstly. With those eight voltages injected into specified node of grayscale voltage
generator, total 64 grayscale voltages (V0-V63) can be generated from grayscale amplifier for
LCD panel used.
Micro Adjust Register ( 6x3 bits)
VREG1
MP/N5 MP/N4 MP/N3 MP/N2
3
3
3
3
MP/N1 MP/N0
3
3
RVP/N0
CP/N0
V0P/N
5
8 to 1
select
RVP/N1
V1P/N
V2P/N
CP/N1
4
8 to 1
select
4
OP/N0
Offset
Adjust
Register
OP/N1
8 to 1
select
CP/N2
4
8 to 1
select
RVP/N43
V20 P/N
V21P/N
Gray Scale
Voltage
Generator
RVP/N55
V43P/N
V44P/N
V55 P/N
V56 P/N
4
8 to 1
select
CP/N4
V8 P/N
V9 P/N
RVP/N20
4
8 to 1
select
CP/N3
RVP/N8
5
RVP/N62
RVP/N63
V62 P/N
V63 P/N
VGS
Figure 7. 3 Structure of Grayscale Voltage Generator
Himax Confidential
-P.92October, 2007
HX8340-B(N)
Gamma-Characteristics Adjustment Register
This HX8343-B has register groups for specifying a series grayscale voltage that meets the
Gamma-characteristics for the LCD panel used. These registers are divided into two groups,
which correspond to the gradient, amplitude, and macro adjustment of the voltage for the
grayscale characteristics.
(1) Offset adjustment registers
The offset adjustment variable registers are used to adjust the amplitude of the grayscale
voltage. This function is implemented by controlling these variable resisters in the top and
bottom of the gamma resister stream for reference gamma voltage generation. These registers
are available for both positive and negative polarities
(2) Gamma center adjustment registers
The gamma center adjustment registers are used to adjust the reference gamma voltage in the
middle level of grayscale without changing the dynamic range. This function is implemented by
choosing one input of 8 to 1 selector in the gamma resister stream for reference gamma
voltage generation. These registers are available for both positive and negative polarities.
(3) Gamma macro adjustment registers
The gamma macro adjustment registers can be used for fine adjustment of the reference
gamma voltage. This function is implemented by controlling the 8-to-1 selectors (MP/N0~5),
each of which has 8 inputs and generate one reference voltage output (RVP/N 0, 1, 8, 20, 44,
56, 63, 64). These registers are available for both positive and negative polarities.
Register
Groups
Center
Adjustment
Macro
Adjustment
Offset
Adjustment
Positive
Polarity
CP/N0 4-0
CP/N1 3-0
CP/N2 3-0
CP/N3 3-0
CP/N4 4-0
MP/N0 2-0
MP/N1 2-0
MP/N2 2-0
MP/N3 2-0
MP/N4 2-0
MP/N5 2-0
OP/N0 3-0
OP/N1 3-0
Description
Variable resistor (VRTP/N) for center adjustment
Variable resistor (VRCP/N0)for center adjustment
Variable resistor (VRMP/N) for center adjustment
Variable resistor (VRCP/N1)for center adjustment
Variable resistor (VRBP/N)for center adjustment
8-to-1 selector (reference voltage level of grayscale 1)
Variable resistor (VROP/N0)for offset adjustment
Variable resistor (VROP/N1)for offset adjustment
Table 7. 1 Gamma-Adjustment Registers
Himax Confidential
-P.93October, 2007
HX8340-B(N)
Gamma resister stream and 8 to 1 Selector
The block consists of two gamma resister streams one is for positive polarity and the other is for
negative polarity, each one including eight gamma reference voltages. (RVP/N 0, 1, 8, 20, 43,
55, 62 63)
VREG1
OP/N0
VP/N0
0-62R
0-30R
VRP/N0 VRTP/N
4R*7
VRCP/N0
0-30R
2R*7
15R
2R*7
VRMP/N
0-30R
2R*7
5R
1R*7
VRCP/N1 0-45R
1R*7
VRP/N1 0-30R
VSS
VgP/N0
Center adjustment CP/N0
V0 P/N
KVP/N1
VP/N1
KVP/N2
VP/N2
KVP/N3
VP/N3
KVP/N4
VP/N4
KVP/N5
VP/N5
KVP/N6
VP/N6
KVP/N7
VP/N7
KVP/N8
VgP/N1
Buffer
KVP/N9
VP/N8
KVP/N10
VP/N9
KVP/N11
VP/N10
KVP/N12
VP/N11
KVP/N13
VP/N12
KVP/N14
VP/N13
KVP/N15
VP/N14
KVP/N16
VP/N15
VgP/N2
V1 P/N
R1
CGM0
0
1
2
3
1R 3R 5R 2R
1R 1.5R 3.33R 1.83R
1R 2R 2.67R1.67R
1R 1R 1R 1.5R
1R 1R 1R 1.33R
1R 1R 1R 1.17R
1R 1R 1R 1R
V2 P/N
R2
V3 P/N
R3
V4 P/N
R4
V5 P/N
R5
V6 P/N
R6
V7 P/N
R7
V8 P/N
R8
Buffer
V9 P/N
R9
V10 P/N
KVP/N17
VP/N16
KVP/N18
VP/N17
KVP/N19
VP/N18
KVP/N20
VP/N19
KVP/N21
VP/N20
KVP/N22
VP/N21
KVP/N23
VP/N22
KVP/N24
VgP/N3
V19 P/N
R19
V20 P/N
R20
Buffer
V21 P/N
R21
V22 P/N
KVP/N25
VP/N23
KVP/N26
VP/N24
KVP/N27
VP/N26
KVP/N28
VP/N27
KVP/N29
VP/N28
KVP/N30
VP/N29
KVP/N31
VP/N30
KVP/N32
VP/N31
V41 P/N
R41
VgP/N4
V42 P/N
V43 P/N
R42
R43
Buffer
V44 P/N
R44
V45 P/N
KVP/N33
VP/N32
KVP/N34
VP/N33
KVP/N35
VP/N34
KVP/N36
VP/N35
KVP/N37
VP/N36
KVP/N38
VP/N37
KVP/N39
VP/N38
KVP/N40
R53
VgP/N5
Buffer
KVP/N41
VP/N39
KVP/N42
VP/N40
KVP/N43
VP/N41
KVP/N44
VP/N42
KVP/N45
VP/N43
KVP/N46
VP/N44
KVP/N47
V54 P/N
R54
VP/N45
VRBP/N 0-124R
KVP/N0
VgP/N6
CGM1
0
1R
1R
1R
1R
1R
1R
1R
1
1R
1R
1R
1R
2R
V55 P/N
R55
2
3
1R 1R
1R 1.17R
1R 1.33R
1R 1.5R
2.67R1.67R
1.5R 3.33R1.83R
3R 5R 2R
V56 P/N
R56
V57 P/N
R57
V58 P/N
R58
V59 P/N
R59
V60 P/N
R60
V61 P/N
R61
V62 P/N
Buffer
KVP/N48
VgP/N7
OP/N1
V63 P/N
Figure 7. 4 Gamma Resister Stream and Gamma Reference Voltage
Himax Confidential
-P.94October, 2007
HX8340-B(N)
Variable resister
There are two types of variable resistors, one is for center adjustment and the other is for offset
adjustment. The resistances are decided by setting values in the center adjustment, offset
adjustment registers. Their relationships are shown below.
Value in Register
OP/N0 3-0
0000
0001
0010
•
•
1101
1110
1111
Resistance
VRP/N0
0R
2R
4R
•
•
26R
28R
30R
Table 7. 2 Offset Adjustment 0
Value in Register
OP/N1 3-0
0000
0001
0010
•
•
1101
1110
1111
Resistance
VRP/N1
0R
2R
4R
•
•
26R
28R
30R
Table 7. 3 Offset Adjustment 1
Value in Register
CP/N0 4-0
Resistance
VRTP/N0
Value in Register
CP/N4 4-0
Resistance
VRBP/N
Value in Register
CP/N1(2) 3-0
00000
00001
00010
•
•
11100
11101
11110
11111
0R
2R
4R
•
•
56R
58R
60R
62R
00000
00001
00010
•
•
11100
11101
11110
11111
0R
4R
8R
•
•
112R
116R
120R
124R
0000
0001
0010
•
•
1100
1101
1110
1111
Value in Register
CP/N3 3-0
0000
0001
0010
•
•
1100
1101
1110
1111
Resistance
VRCP/N0
VRMP/N
0R
2R
4R
•
•
24R
26R
28R
30R
Resistance
VRCP/N1
0R
3R
6R
•
•
36R
39R
42R
45R
Table 7. 4 Gamma Center Resistance Adjustment
Himax Confidential
-P.95October, 2007
HX8340-B(N)
8 to 1 Selector
The 8 to 1 selector has eight input voltages generated by gamma resister stream and outputs
one reference voltages selected from inputs for gamma reference voltage generation by
setting value in macro adjustment register. There are six 8 to 1 selectors and the relationships
are shown below.
Value in
Register
MP/N 2-0
000
001
010
011
100
101
110
111
Voltage level
VgP/N 1
KVP/N1
KVP/N 2
KVP/N3
KVP/N 4
KVP/N 5
KVP/N 6
KVP/N 7
KVP/N 8
VgP/N 2
KVP/N9
KVP/N10
KVP/N11
KVP/N12
KVP/N13
KVP/N14
KVP/N15
KVP/N16
VgP/N 3
KVP/N17
KVP/N18
KVP/N19
KVP/N20
KVP/N21
KVP/N22
KVP/N23
KVP/N24
VgP/N 4
KVP/N25
KVP/N26
KVP/N27
KVP/N28
KVP/N29
KVP/N30
KVP/N31
KVP/N32
VP/N 5
KVP/N33
KVP/N34
KVP/N35
KVP/N36
KVP/N37
KVP/N38
KVP/N39
KVP/N40
VP/N 6
KVP/N41
KVP/N42
KVP/N43
KVP/N44
KVP/N45
KVP/N46
KVP/N47
KVP/N48
Table 7. 5 Output Voltage of 8 to 1 Selector
Himax Confidential
-P.96October, 2007
HX8340-B(N)
The grayscale levels are determined by the following formulas.
Reference
Voltage
VgP/N0
VgP/N1
VgP/N2
VgP/N3
VgP/N4
VgP/N5
VgP/N6
VgP/N7
Formula
---MP/N0 2-0=000
MP/N0 2-0=001
MP/N0 2-0=010
MP/N0 2-0=011
MP/N0 2-0=100
MP/N0 2-0=101
MP/N0 2-0=110
MP/N0 2-0=111
MP/N1 2-0=000
MP/N1 2-0=001
MP/N1 2-0=010
MP/N1 2-0=011
MP/N1 2-0=100
MP/N1 2-0=101
MP/N1 2-0=110
MP/N1 2-0=111
MP/N2 2-0=000
MP/N2 2-0=001
MP/N2 2-0=010
MP/N2 2-0=011
MP/N2 2-0=100
MP/N2 2-0=101
MP/N2 2-0=110
MP/N2 2-0=111
MP/N3 2-0=000
MP/N3 2-0=001
MP/N3 2-0=010
MP/N3 2-0=011
MP/N3 2-0=100
MP/N3 2-0=101
MP/N3 2-0=110
MP/N3 2-0=111
MP/N4 2-0=000
MP/N4 2-0=001
MP/N4 2-0=010
MP/N4 2-0=011
MP/N4 2-0=100
MP/N4 2-0=101
MP/N4 2-0=110
MP/N4 2-0=111
MP/N5 2-0=000
MP/N5 2-0=001
MP/N5 2-0=010
MP/N5 2-0=011
MP/N5 2-0=100
MP/N5 2-0=101
MP/N5 2-0=110
MP/N5 2-0=111
----
Pin
VREG1-VD*VRP/N0 /sumRP/N
VREG1 –VD((VRP/N0+VRTP/N) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +4R) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N +28R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+57R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +71R+VRCP/N0) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N+97R+VRCP/N0 +VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRTP/N+ VRMP/N +98R+VRCP/N0+VRCP/N1) /sumRP/N
VREG1 –VD((VRP/N0+ VRBP/N+ VRTP/N+ VRMP/N +104R+VRCP/N0+VRCP/N1)
/sumRP/N
KVP/N0
KVP/N1
KVP/N2
KVP/N3
KVP/N4
KVP/N5
KVP/N6
KVP/N7
KVP/N8
KVP/N9
KVP/N10
KVP/N11
KVP/N12
KVP/N13
KVP/N14
KVP/N15
KVP/N16
KVP/N17
KVP/N18
KVP/N19
KVP/N20
KVP/N21
KVP/N22
KVP/N23
KVP/N24
KVP/N25
KVP/N26
KVP/N27
KVP/N28
KVP/N29
KVP/N30
KVP/N31
KVP/N32
KVP/N33
KVP/N34
KVP/N35
KVP/N36
KVP/N37
KVP/N38
KVP/N39
KVP/N40
KVP/N41
KVP/N42
KVP/N43
KVP/N44
KVP/N45
KVP/N46
KVP/N47
KVP/N48
KVP/N49
SumRP=104R+VRP0+ VRP1+ VRTP+ VRCP0+VRMP+VRCP1+VRBP
SumRN=104R+ VRP0+ VRP1+ VRTP+ VRCP0+VRMP+VRCP1+VRBP
VD=(VREG1–VSS)
Table 7. 6 Gamma Voltage Calculation Formula
Himax Confidential
-P.97October, 2007
HX8340-B(N)
Grayscale
Formula
Voltage
V0P/N VgP/N0
V1 P/N VgP/N1
V2 P/N VgP/N2+(VgP/N1-VgP/N2)*CT1
V8 P/N VgP/N2
V9 P/N VgP/N3+(VgP/N2-VgP/N3)*(22/24)
V20 P/N VgP/N3
Grayscale
Formula
Voltage
V43 P/N VgP/N4
V55 P/N VgP/N5
V56 P/N VgP/N6+(VgP/N5-VgP/N6)*CB1
V62 P/N VgP/N6
V63 P/N VgP/N7
Table 7. 7 Voltage Calculation Formula of Grayscale Voltage
CGM0[1:0]
“00”
“01”
“10”
“11”
CGM1[1:0]
“00”
“01”
“10”
“11”
CT1
6/7
7.5/10.5 10/15
8.5/10.5
CB1
6/7
9.5/10.5
14/15
9.5/10.5
CT2
5/7
6/10.5 6.67/15 6.67/10.5
CB2
5/7
8.5/10.5
13/15 8.33/10.5
CT3
4/7
4/10.5
4/15
5.0/10.5
CB3
4/7
7.5/10.5
12/15
7.0/10.5
CT4
3/7
3/10.5
3/15
3.5/10.5
CB4
3/7
6.5/10.5
11/15
5.5/10.5
CT5
2/7
2/10.5
2/15
2.17/10.5
CB5
2/7
4.5/10.5 8.33/15 3.83/10.5
CT6
1/7
1/10.5
1/15
1/10.5
CB6
1/7
3.0/10.5
5/15
2.0/10.5
NOTE: Negative gamma don’t have CGM0/CGM1 setting, the ratio V2~V7 and V56~V61 is automatically mapping from
positive side.
Table 7. 8 Voltage Calculation Formula of Grayscale Voltage V2~V7 and V56~V61
Himax Confidential
-P.98October, 2007
HX8340-B(N)
Relationship between GRAM Data and Output Level
Sn
Vcom
Negative polarity
Positive polarity
Figure 7. 5 Relationship between Source Output and VCOM
Figure 7. 6 Relationship between GRAM Data and Output Level (Normal white panel and INVON=“0”)
Himax Confidential
-P.99October, 2007
HX8340-B(N)
Four-Characteristic Gamma Curve Selection
There are four kinds of Gamma Curve which can be selected by GAMSET command. The
parameter GC[7:0] is stored in internal register and used to select one set of gamma
correction register.
Figure 7. 7 Gamma Curve according to the GC0 to GC3 bit
Himax Confidential
-P.100October, 2007
HX8340-B(N)
7.3 Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal
can be enabled or disabled by the Tearing Effect Line off & on commands. The mode of the
Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The
signal can be used by the MPU to synchronize Frame Memory Writing when displaying video
images.
7.3.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
tVdh = The LCD display is not updated from the Frame Memory
tvdl = The LCD display is updated from the Frame Memory (except Invisible Line – see below)
Figure 7. 8 TE mode 1 output
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking
Information, there is one V-sync and 220 H-sync pulses per field.
thdl
thdh
V-Sync
V-Sync
Invisible Line
1st Line
2nd Line
161th Line
162th Line
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Figure 7. 9 TE mode 2 output
Note: During Sleep in Mode, the Tearing Output Pin is active Low
Figure 7. 10 TE output waveform
Himax Confidential
-P.101October, 2007
HX8340-B(N)
7.3.2 Tearing Effect Line Timing
The Tearing Effect signal is described below.
Figure 7. 11 Waveform of Tearing Effect Signal
Symbol
tvdl
tvdh
thdl
thdh
Parameter
Vertical Timing Low Duration
Vertical Timing High Duration
Horizontal Timing Low Duration
Horizontal Timing High Duration
Min.
TBD
BP+FP
TBD
TBD
Idle Mode Off (Frame Rate = TBD Hz)
Max.
Unit
Description
ms
us
us
500
us
-
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
Table 7. 9 AC characteristics of Tearing Effect Signal
Figure 7. 12 Timing of Tearing Effect Signal
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to
avoid Tearing Effect:
Himax Confidential
-P.102October, 2007
HX8340-B(N)
7.3.3 Example 1: MPU Write is faster than Panel Read
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during
the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always
written ahead of the panel scan and each Panel Frame refresh has a complete new image:
Himax Confidential
-P.103October, 2007
HX8340-B(N)
7.3.4 Example 2: MPU Write is slower than Panel Read
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one
horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to
download behind the Panel Read pointer and finishing download during the subsequent Frame
before the Read Pointer “catches” the MPU to Frame memory write position.
Himax Confidential
-P.104October, 2007
HX8340-B(N)
7.4 LCD Power Generation Circuit
7.4.1 Power Supply Circuit
The power circuit of HX8340-B is used to generate supply voltages for LCD panel driving.
C12A
C11A
C9
C1
C12B
C10
C11
Step up
Circuit 3
VCL
C11B
DDVDH
C2
Reference
Voltage
VCOML
Generation
Circuit
VREG1
Reference
Voltage
VCOMH
Generation
Circuit
VCI
VSSA
VSSD
VCI
C12
Step up
Circuit 1
VDDD
C3
C4
DDVDH
Reference
Voltage
Generation
Circuit
C21A
C5
C21B
Step up
Circuit 2
C22A
C6
C22B
VGH
C7
C8
VGL
HX8340-B
D1
Figure 7. 13 The Block Diagram of HX8340-B Power Circuit
Himax Confidential
-P.105October, 2007
HX8340-B(N)
Specification of Connected Passive Component
Capacitor
C1 (C11A/B)
C2 (DDVDH)
C3 (VREG1)
C4(VCOMH)
C5 (C21A/B)
C6 (C22A/B)
C7 (VGH)
C8 (VGL)
C9 (C12A/B)
C10 (VCL)
C11 (VCOML)
C12 (VDDD)
Diode
D1 (VGL-GND)
Recommended voltage
Capacity
6V
1 µF (B characteristics)
10V
10V
10V
10V
10V
25V
16V
6V
6V
6V
6V
Table 7. 10 The adoptability of Capacitor
Feature
Schottkey Diode, VF < 0.4V / 20mA at 25°C, VR ≥30V
Table 7. 11 The adoptability of Diode
Himax Confidential
-P.106October, 2007
HX8340-B(N)
7.4.2 LCD Power Generation Scheme
The boost voltage generated is shown as below.
Figure 7. 14 LCD Power Generation Scheme
Himax Confidential
-P.107October, 2007
HX8340-B(N)
7.5 Power Function
7.5.1 System Interface Power On/Off Sequence
Power source IOVCC, VCI can be applied and powered down in any order.
IOVCC, VCI can be powered down in any order.
During power off, if LCD is in the Sleep Out mode, IOVCC, VCI must be powered down
minimum 120msec after NRESET has been released.
During power off, if LCD is in the Sleep In mode, IOVCC, VCI can be powered down minimum
0msec after NRESET has been released.
NCS can be applied at any timing or can be permanently grounded. NRESET has priority
over NCS.
Note: (1) There will be no damage to the display module if the power sequences are not met.
(2) There will be no abnormal visible effects on the display panel during the Power On/Off
Sequences.
(3) There will be no abnormal visible effects on the display between end of Power on Sequence
and before receiving Sleep Out command. Also between receiving Sleep In command and
Power Off Sequence.
If NRESET line is not held stable by host during Power on Sequence as defined in Sections
7.5.2.1 and 7.5.2.2, then it will be necessary to apply a Hardware Reset (NRESET) after Host
Power on Sequence is complete to ensure correct operation, otherwise correct functionality is
not guaranteed. The power on/off sequence is illustrated as below.
Himax Confidential
-P.108October, 2007
HX8340-B(N)
7.5.1.1 Case 1 – NRESET line is held High or Unstable by Host at Power On
If NRESET line is held high or unstable by the host during Power On, then a Hardware Reset
must be applied after both IOVCC, VCI have been applied, otherwise correct functionality is
not guaranteed. There is no timing restriction upon this hardware reset.
tRPW= +/- no limit
tFPW= +/- no limit
IOVCC
VCI
Time when the latter signal rises up to 90% of its typical .
value
Time when the former signal falls down to 90% of its
Typical value
tRPWNCS = +/- no limit
NCS
tFPWNCS = +/- no limit
H or L
tRPWNRES= + no limit
tFPWNRES1 = min120ms
NRESET
(Power down in
sleep out mode)
tRPWNRES= + no limit
NRESET
( Power down in
sleep in mode)
tFPWNRES2 = min0ns
tFPWNRES1 is applied to NRESET falling in the Sleep Out Mode
tFPWNRES2 is applied to NRESET falling in the Sleep In Mode
Note: Unless otherwise specified
,
timings herein show cross point at 50% of signal/power level
Figure 7. 15 Case 1 – NRESET Line is Held High or Unstable by Host at Power On
Himax Confidential
-P.109October, 2007
HX8340-B(N)
7.5.1.2 Case 2 – NRESET line is held Low by host at Power On
If NRESET line is held Low (and stable) by the host during Power On, then the
NRESET must be held low for minimum 10μsec after VCI have been applied.
tRPW= +/- no limit
tFPW= +/- no limit
IOVCC
VCI
Time when the latter signal rises up to 90% of its typical value
Time when the former signal falls down to 90% of its Typical
value
tRPWNCS= +/- no limit
tRPWNCS= +/- no limit
NCS
.
H or L
tFPWNRES1 = min120ms
tRPWNRES = min10us
NRESET
( Power down in
Sleep Out mode)
tRPWNRES= min10us
NRESET
tFPWNRES 2 = min0 ns
( Power down in
Sleep In mode )
tFPWNRES1 is applied to NREST falling in the Sleep Out Mode
tFPWNRES2 is applied to NREST falling in the Sleep In Mode
Note: Unless otherwise specified timings herein show cross point at 50% of signal/power level
Figure 7. 16 NRESET Line is Held Low by Host at Power On
Himax Confidential
-P.110October, 2007
HX8340-B(N)
Power ON/OFF Sequence
Power on Flow
Power off Flow
VCI/IOVCC
Power On
Sleep Out
NRESET = 'L'
Auto-Reload OTP
Parameter to Register
Min. 5ms
Auto-in Sleep In
Mode
Sleep In Command
Min. 5ms
VCI/IOVCC
Power off
SLPOUT Command
DISPON Command
Himax Confidential
-P.111October, 2007
HX8340-B(N)
7.5.2 RGB Interface Power on/off
RGB mode Power on/off can be controlled by external pin SHUT or by internal CSHUT bit. As
the internal CSHUT bit be written in RGB interface, the external pin SHUT control will be
invalid
Power on Sequence
The Driver operates power up and display ON by IOVCC, VCII, SHUT, VS, HS, DE, DOTCLK on
RGB mode as show as following figure.
IOVCC
T VCI - IOVCC
VCI
TRS-SH
NRESET
SHUT
TVCI-SH
CSHUT
DOTCLK
CSHUT CMD
T CLK- Reset
HS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VS
Host
Driver IC
Display ON
Display OFF TSH-ON
Display
Normal Display
Normal Display
Source Output
Blanking Display (Over 1 frame display)
VCOM Output
Normal Display
Gate Output
Figure 7. 17 Power On Sequence on RGB
Characteristics
IOVCC On to VCI On
IOVCC/VCI on to falling edge of SHUT
RESX to falling of SHUT
DOTCLK to NRESET
Falling edge of SHUT to Display start
Symbol
TIOVCC-VCI
TVCI-SH
TRS-SH
T CLK-Nreset
TSH-ON
Min
0
2
1
20
Typ
Max
10
2
20
6
Unit
ns
ms
ms
DOTCLK
VS
Remark
Note1
Note 1: TIOVCC-VCI can be <=0ns, >0ns. In any case, IOVCC and VCI power up sequence should not have any impact on
the driver / display functionalities / performance.
Note 2:EPL=’0’, VSPL=’0’, HSPL=’0’ and DPL=’0’ of SETRGBIF (BBH) command.
Table 7. 12 RGB mode Power ON AC Characteristics
Himax Confidential
-P.112October, 2007
HX8340-B(N)
Power OFF Sequence Operate
The Driver operates power off and display OFF by VCI, IOVCC, SHUT, VS, HS and DE on RGB mode 2 as
show as following figure.
IOVCC
TVCI -IOVCC
VCI
NRESET
SHUT
TOFF-VCI
CSHUT
C-SHUT CMD
DOTCLK
HS
TSH-OFF
VS
Host
Driver IC
Display High
Voltage
Display ON
Display OFF
Display
Normal Display
Source Output
Normal Display
0V
VCOM Output
Normal Display
0V
Blanking Display (Over 1 frame display)
Gate Output
Figure 7. 18 Power OFF Sequence on RGB Mode
Characteristics
IOVCC On to VCI On
Signals input to IOVCC/VCI off
Rising edge of SHUT to Display off
Symbol
Tiovcc-vci
TSH-OFF
TSH-OFF
Min
0
1
2
Typ
Max
Unit
ns
us
VS
Remark
Note1
Note2
Note 1: TIOVCC-VCI can be <=0ns, >0ns. In any case, IOVCC and VCI power up sequence should not have any impact on
the driver / display functionalities / performance.
Note 2: Signals mean VS, HS, and DOTCLK signal.
Note 3: EPL=’0’, VSPL=’0’, HSPL=’0’ and DPL=’0’ of SETRGBIF (BBH) command.
Table 7. 13 RGB mode Power OFF AC Characteristics
Himax Confidential
-P.113October, 2007
HX8340-B(N)
7.5.3 Power Levels Definition
7.5.3.1 General Definition for Power Levels on System Interface (RCM[1:0] = ‘0x’)
Figure 7. 19 Power Flow Chart for Different Power Modes (RCM[1:0] = ‘0x’)
Himax Confidential
-P.114October, 2007
HX8340-B(N)
7.5.3.2 General Definition for Power Levels on RGB Interface (RCM[1:0] = ‘10’ or ‘11’)
Figure 7. 20 Power Flow Chart for Different Power Modes (RCM[1:0] = ‘10’ or ‘11’)
Himax Confidential
-P.115October, 2007
HX8340-B(N)
7.6 Sleep Out – Command and Self-diagnostic Functions of Display Module
7.6.1 Register Loading Detection
Sleep Out-command (See section 8.1.12 “Sleep Out (11h)”) is a trigger for an internal function
of the display module, which indicates, if the display module loading function of factory default
values from EEPROM (or similar device) to registers of the display controller is working
properly.
There are compared factory values of the EEPROM and register values of the display controller
by the display controller. If those both values (EEPROM and register values) are the same,
there is an inverted (=increased by 1) bit, which is defined in section 8.1.10 “Read Display
Self-Diagnostic Result (0Fh)” (=RDDSDR) (The bit used for this command is D7). If those both
values are not the same, this bit (D7) is not inverted (= increased by 1). The flow chart for this
internal function is shown as below.
Note: There is not compared and loaded register values, which can be changed by User (User area
commands: 00h to AFh and DAh to DDh), by the display module.
Figure 7. 21 Register Loading Detection Flow
Himax Confidential
-P.116October, 2007
HX8340-B(N)
7.6.2 Functionality Detection
Sleep Out-command (See section 8.1.12 “Sleep Out (11h)”) is a trigger for an internal
function of the display module, which indicates, if the display module is still running and
meets functionality requirements.
The internal function (= the display controller) is comparing, if the display module is still
meeting functionality requirements (e.g. booster voltage levels, timings, etc.) If functionality
requirement is met, there is an inverted (= increased by 1) bit, which defined in section 8.1.10
“Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is
D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1).
The flow chart for this internal function is shown as below.
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In –mode to Sleep Out
-mode, before there is possible to check if User’s functionality requirements are met and a value of RDDSDR’s D6 is valid.
Otherwise, there is 5msec delay for D6’s value, when Sleep Out –command is sent in Sleep out -mode.
Figure 7. 22 Functionality Detection Flow
Himax Confidential
-P.117October, 2007
HX8340-B(N)
7.7 Input / Output Pin State
7.7.1 Output Pins
Output or Bi-directional pins
After Power On
After Hardware Reset
DB17 to DB0
High-Z (Inactive)
High-Z (Inactive)
(Output driver)
SDO
High-Z (Inactive)
High-Z (Inactive)
TE
Low
Low
Table 7. 14 Characteristics of Output Pins
7.7.2 Input Pins
Input pins
NRESET
NCS
NWR_RNW_SCL
NRD_E
DNC
SDI
VS
HS
DE
DOTCLK
DB[17:0]
OSC, M3, IM2,
IM1,IM0,
EXTC
During Power
On Process
Section 7.5.1
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
After
Power On
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
After Hardware
Reset
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
Input valid
During Power
Off Process
Section 7.5.1
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input invalid
Input valid
Input valid
Input invalid
Input invalid
Input valid
Input valid
Table 7. 15 Characteristics of Input Pins
Input invalid
Himax Confidential
-P.118October, 2007
HX8340-B(N)
8. Command Set
(Hex)
00
01
04
09
0A
0B
0C
0D
0E
0F
Operation
Code
NOP
SWRESET
RDDIDIF
RDDST
RDDPM
RDDMADCTL
RDDCOLMOD
RDDIM
RDDSM
0
0
↑
↑
1
1
D8~D
15
---
0
↑
1
--
0
0
0
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
------
-
-
-
B7
B6
B5
0
↑
1
--
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
------
D31
0
D15
D7
D30
D22
0
D6
D29
D21
D13
D5
D28
D20
0
D4
D27
D19
0
D3
D26
D18
D10
D2
D25
D17
D9
D1
0
D16
D8
0
0
↑
1
--
0
0
0
0
1
0
1
0
1
1
1
1
↑
↑
---
D7
D6
D5
D4
D3
D2
0
0
0
↑
1
--
0
0
0
0
1
0
1
1
1
1
1
1
↑
↑
---
D7
D6
D5
D4
D3
D2
0
0
0
↑
1
--
0
0
0
0
1
1
0
0
1
1
1
1
↑
↑
---
D7
D6
D5
D4
0
D2
D1
D0
0
↑
1
--
0
0
0
0
1
1
0
1
1
1
1
1
↑
↑
---
D7
0
D5
0
0
D2
D1
D0
0
↑
1
--
0
0
0
0
1
1
1
0
1
1
1
1
↑
↑
---
D7
D6
D5
D4
D3
D2
0
0
0
↑
1
--
0
0
0
0
1
1
1
1
1
1
1
1
↑
↑
---
D7
D6
0
0
0
0
0
0
D/NC
NWR NRD
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Software reset
0
0
1
0
0
-
-
-
B2
B1
B0
ID1[7:0]
ID2[7:0]
ID3[7:0]
B4
B3
RDDSDR
10
SLPIN
0
↑
1
--
0
0
0
1
0
0
0
0
11
SLPOUT
0
↑
1
--
0
0
0
1
0
0
0
1
12
PTLON
0
↑
1
--
0
0
0
1
0
0
1
0
13
NORON
0
↑
1
--
0
0
0
1
0
0
1
1
20
INVOFF
0
↑
1
--
0
0
1
0
0
0
0
0
21
INVON
0
↑
1
--
0
0
1
0
0
0
0
1
Himax Confidential
No operation
Read display
identification
information
Dummy read
ID1 read
ID2 read
ID3 read
Read display
status
Dummy read
Read display
power mode
Dummy read
Read display
MADCTL
Dummy read
Read display
pixel format
Dummy read
Read display
image mode
Dummy read
Read display
signal mode
Dummy read
Read display
self-diagnosti
c result
Dummy read
Sleep in and
charge-pump
off
Sleep out and
charge-pump
on
Partial mode
on
Normal
display mode
on
Display
inversion off
Display
inversion on
-P.119October, 2007
HX8340-B(N)
(Hex)
Operation
Code
26
GAMSET
28
29
DISPOFF
DISPON
2A
2B
CASET
PASET
2C
RAMWR
2E
RAMRD
2D
30
33
RGBSET
PLTAR
0
1
0
0
↑
↑
↑
↑
1
1
1
1
D8~
D15
-----
0
↑
1
--
1
↑
1
--
SC[15:8]
1
↑
1
--
SC[7:0]
1
↑
1
--
EC[15:8]
1
↑
1
--
EC[7:0]
0
↑
1
--
1
↑
1
--
SP[15:8]
1
↑
1
--
SP[7:0]
1
↑
1
--
EP[15:8]
1
↑
1
--
EP[7:0]
0
1
0
1
1
↑
↑
↑
↑
1
1
1
1
1
↑
------
0
0
1
0
0
-
0
-
1
-
0
-
0
↑
1
--
0
0
1
0
1
1
1
1
1
1
1
1
1
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
----------
0
↑
1
--
1
1
1
1
↑
↑
↑
↑
1
1
1
1
-----
0
↑
1
--
1
1
↑
↑
1
1
---
TFA[15:8]
TFA[7:0]
1
↑
1
--
VSA[15:8]
1
↑
1
--
VSA[7:0]
1
↑
1
--
BFA[15:8]
1
↑
1
--
BFA[7:0]
D/NC
NWR NRD
D7
D6
D5
0
0
1
0
0
0
0
0
0
0
0
D2
D1
D0
1
1
0
Gamma set
1
1
0
0
GC[7:0]
0
1
0
1
0
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
Display off
Display on
Column
address set
Column
address start
Column
address start
Column
address end
Column
address end
Row address
set
Row address
start
Row address
start
Row address
end
Row address
end
Memory write
1
-
0
-
Memory read
Dummy read
0
1
LUT
parameter
1
D4
0
D3
1
1
1
1
Write data
1
1
Read data
1
1
Function
RGB 007 RGB 006 RGB 005 RGB 004 RGB 003 RGB 002 RGB 001 RGB 000
RGB nn7 RGB nn6 RGB nn5 RGB nn4 RGB nn3 RGB nn2 RGB nn1 RGB nn0
RB167
RB166
RB165
RB164
RB163
RB162
RB161
RB160
RBnn7
RBnn6
RBnn5
RBnn4
RBnn3
RBnn2
RBnn1
RBnn0
RB317
RB316
RB315
RB314
RB313
RB312
RB311
RB310
RGB nn7 RGB nn6 RGB nn5 RGB nn4 RGB nn3 RGB nn2 RGB nn1 RGB nn0
0
0
1
1
0
0
0
0
0
1
1
SR[15:8]
SR[7:0]
ER[15:8]
ER[7:0]
0
0
1
1
0
VSCRDEF
Himax Confidential
Partial start
end address
set
Start row
Start row
End row
End row
Vertical
scrolling
definition
Top fixed area
Top fixed area
Height of the
vertical
scrolling area
Height of the
vertical
scrolling area
Bottom fixed
area
Bottom fixed
area
-P.120October, 2007
HX8340-B(N)
(Hex)
Operation
Code
34
TEOFF
35
TEON
36
37
MADCTL
D/NC
NWR NRD
D8~
D15
D7
D6
D5
D4
D3
D2
D1
D0
0
↑
1
--
0
0
1
1
0
1
0
0
0
↑
1
--
0
0
1
1
0
1
0
1
1
↑
1
--
-
-
-
-
-
-
-
M
0
↑
1
--
0
0
1
1
0
1
1
0
1
↑
1
--
B7
B6
B5
B4
B3
B2
X
X
0
↑
1
--
0
0
1
1
0
1
1
1
1
1
0
0
↑
↑
↑
↑
1
1
1
1
-----
0
0
0
0
1
1
0
0
0
0
0
1
0
↑
1
--
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
↑
↑
1
1
↑
1
1
↑
1
1
1
1
↑
↑
1
↑
↑
1
↑
↑
-----------
VSCRSADD
38
39
IDMOFF
IDMON
3A
COLMOD
DA
RDID1
DB
RDID2
DC
RDID3
1
1
1
-
VSP[15:8]
VSP[7:0]
1
1
1
1
1
1
CSEL[3:0]
IFPF[2:0]
1
0
1
1
0
1
module’s manufacturer[7:0]
1
0
1
1
0
1
LCD module/driver version [7:0]
1
0
1
1
1
0
LCD module/driver ID [7:0]
Function
Tearing effect
line off
Tearing effect
line on
Memory
access control
Vertical
scrolling start
address
Idle mode off
Idle mode on
Interface pixel
format
0
-
Read ID1
Dummy read
1
-
Read ID2
Dummy read
0
-
Read ID3
Dummy read
Himax Confidential
-P.121October, 2007
HX8340-B(N)
Extended Command Set
(Hex)
B0
Operation
Code
SETOSC
B1
SETPWCTR1
B2
SETPWCTR2
B3
SETPWCTR3
B4
SETPWCTR4
B5
SETPWCTR5
B6
SETDISCTRL
B7
SETFRMCTRL
B8
SETDISCYCC
TRL
B9
SETINVCTRL
BA
RGBBPCTR
BB
SETRGBIF
BC
SETDODC
BD
SETINTMODE
BE
SETPANEL
C7
SETOTP
0
↑
1
D8~
D15
--
1
↑
1
--
--
1
↑
1
--
--
0
↑
1
--
1
0
1
1
0
1
↑
1
--
--
--
--
--
--
0
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
1
0
1
1
0
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
---------------------------------
1
--1
--
1
↑
1
--
0
↑
1
--
1
↑
1
--
0
↑
1
--
1
0
1
1
1
1
1
↑
1
--
--
--
--
--
--
--
0
1
↑
↑
1
1
---
1
--
0
--
1
--
1
--
1
--
0
↑
1
--
1
1
0
0
0
1
↑
1
--
1
↑
1
--
D/NC
NWR NRD
D7
D6
D5
D4
D3
D2
D1
1
0
1
1
0
0
0
--
--
--
--
--
--
I/PI_ I/PI_ I/PI_
RADJ2 RADJ1 RADJ0
--
D0
Function
0
OSC_ Set Internal
EN Oscillator
N/P_ N/P_ N/P_
RADJ2 RADJ1 RADJ0
0
0
1
VCO
PON DK
MG
0
1
0
N/P_FS0[2:0]
N/P_FS1[2:0]
0
1
1
AP2 AP1 AP0
Set power
control 1
0
1
1
0
Set power
I/PI_FS0[2:0]
-control 2
I/PI_FS1[2:0]
-0
1
1
0
Set power
----control 3
N/P_SAP[7:0]
I/PI_SAP[7:0]
1
0
1
1
0
1
0
0
Set power
---- VRH4 VRH3 VRH2 VRH1 VRH0
control 4
-----BT2 BT1 BT0
1
0
1
1
0
1
0
1
-- VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0 Set power
-- VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0 control 5
-- VML6 VML5 VML4 VML3 VML2 VML1 VML0
1
0
1
1
0
1
1
0
Set display
PT1 PT0 GON DTE D1
D0
0
0
control
REF PTV1 PTV0 PTG ISC3 ISC2 ISC1 ISC0
1
0
1
1
0
1
1
1
--- I/PI_DIV[1:0] --- N/P_DIV[1:0]
Set frame rate
I/PI_RTN[3:0]
N/P_RTN[3:0]
control
N/P_DUM[7:0]
I/PI_DUM[7:0]
1
0
1
1
1
0
0
0
SON[7:0]
Set display
cycle control
GDON[7:0]
GDOF[7:0]
1
0
1
1
1
0
0
1 Set Display
Cycle Control
-I/PI_NW[2:0]
-N/P_NW[2:0]
1
0
1
1
1
0
1
0 Set RGB
--- HBP5 HBP4 HBP3 HBP2 HBP1 HBP0 interface
VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0 blanking porch
1
0
1
1
1
0
1
1 Set RGB
interface
----DPL HSPL VSPL EPL
related register
1
0
1
1
1
1
0
0 Set Driver
--
--
--
OTP_
OTP_ OTP_
VARD
PTM1 PTM0
J1
OTP_ OTP_
-XA2 XA1
--
--
--
CTB
0
RCM1 RCM0 mode
1
-
-1
Output Direction
CRL Control
1 Set interface
1
-1
OTP_
OTP_ OTP_
OTP_
VARD
OTPE PPR
POR
J0
N
OG
OTP_
OTP_ OTP_
-XA0
YA2 YA1
0
Set panel
NWB
1
OTP_
PWE Set OTP
OTP_
YA0
Himax Confidential
-P.122October, 2007
HX8340-B(N)
(Hex)
Operation
Code
C0
SETONOFF
C1
SETEXTCMD
C2
SETGAMMAP
C3
SETGAMMAN
D/NC
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
NWR NRD
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D8~
D15
--------------------------
D7
D6
D5
D4
1
-1
1
1
0
1
----CP23
--OP13
-1
----CN23
--ON13
1
-1
1
0
1
1
MP12
MP32
MP52
-CP22
--OP12
-1
MN12
MN32
MN52
-CN22
--ON12
0
-0
1
0
0
0
MP11
MP31
MP51
-CP21
--OP11
-0
MN11
MN31
MN51
-CN21
--ON11
0
-0
1
0
0
0
MP10
MP30
MP50
CP04
CP20
-CP44
OP10
-0
MN10
MN30
MN50
CN04
CN20
-CN44
ON10
D3
D2
0
0
--0
0
1
1
0
0
0
0
0
0
-- MP02
-- MP22
-- MP42
CP03 CP02
CP13 CP12
CP33 CP32
CP43 CP42
OP03 OP02
CGM1[1:0]
0
0
-- MN02
-- MN22
-- MN42
CN03 CN02
CN13 CN12
CN33 CN32
CN43 CN42
ON03 ON02
D1
D0
Function
0
0 Set chip on/off
-- CSHUT
0
1
1
1 Set extended
1
1 command set
0
0
1
0
MP01 MP00
MP21 MP20
( Set “+”
MP41 MP40
polarity
CP01 CP00
Gamma Curve
CP11 CP10
GC0 Related
CP31 CP30
Setting
CP41 CP40
OP01 OP00
CGM0[1:0]
1
1
MN01 MN00
MN21 MN20 ( Set “-”
MN41 MN40 polarity
CN01 CN00 Gamma Curve
CN11 CN10 GC0 Related
CN31 CN30 Setting
CN41 CN40
ON01 ON00
Himax Confidential
-P.123October, 2007
HX8340-B(N)
8.1 Command Description
8.1.1 NOP
00 H
Command
Parameter
Description
NOP (No Operation)
DNC NWR NRD D17-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
0
↑
1
-0
0
0
0
0
0
0
0
00
NO PARAMETER
This command is an empty command; it does not have any effect on the display module.
However it can be used to terminate Frame Memory Write as described in RAMWR (Memory
Write) or RAMRD (Memory Read) command.
Restriction
Register
Availability
Status
Normal Mode On, Idle Mode Off, Sleep Out
Normal Mode On, Idle Mode On, Sleep Out
Partial Mode On, Idle Mode Off, Sleep Out
Partial Mode On, Idle Mode On, Sleep Out
Sleep In or Booster Off
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
N/A
N/A
N/A
Default
Flow Chart
Himax Confidential
-P.124October, 2007
HX8340-B(N)
8.1.2 Software Reset (01h)
01 H
Command
Parameter
Description
Restriction
Register
Availability
SWRESET (Software Reset)
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
-0
0
0
0
0
0
0
1
01
NO PARAMETER
When the Software Reset command is written, it causes a software reset. It resets the
commands and parameters to their S/W Reset default values. (See default tables in each
command description.)
The display is blank immediately.
Note: The GRAM contents are unaffected by this command.
It will be necessary to wait 5msec before sending new command following software reset.
The display module loads all display supplier’s factory default values to the registers during
this 5m sec.
If SW Reset is applied during Sleep Out mode, it will be necessary to wait 120 msec before
sending Sleep Out command.
SW Reset command cannot be sent during Sleep Out sequence.
Status
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
N/A
N/A
N/A
Default
Flow Chart
Himax Confidential
-P.125October, 2007
HX8340-B(N)
8.1.3 Read Display Identification Information (04h)
04 H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
Description
RDDIDIF (Read Display Identification Information)
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
-0
0
0
0
0
1
0
0
04
1
1
↑
----------1
1
↑
-ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
-1
1
↑
-1
ID26 ID25 ID24 ID23 ID22 ID21 ID20
-1
1
↑
xx
This read byte returns 24-bit display identification information.
The 1st parameter is dummy data.
The 2nd parameter: LCD module’s manufacturer ID.
The 3rd parameter: LCD module/driver version ID.
The 4th parameter: LCD module/driver ID.
Note: Commands RDID1/2/3(DAh, DBh and DCh) read data correspond to the parameters
2, 3, 4 of the command 04h, respectively.
Restriction
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
TBD
TBD
TBD
Flow Chart
Himax Confidential
-P.126October, 2007
HX8340-B(N)
8.1.4 Read Display Status (09h)
09 H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
5th parameter
Description
RDDST (Read Display Status)
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
-0
0
0
0
1
0
0
1
09
1
1
↑
----------1
1
↑
-D31 D30 D29 D28 D27 D26 D25
0
1
1
↑
-0
D22 D21 D20 D19 D18 D17 D16
1
1
↑
-D15
0
D13
0
0
D10 D9
D8
1
1
↑
-D7
D6
D5
D4
D3
D2
D1
0
This command indicates the current status of the display as described in the table below:
Bit
Description
D31
Booster Voltage Status
D30
Page Address Order (MY)
D29
Column Address Order (MX)
D28
Page/Column Order (MV)
D27
Line Address Order (ML)
D26
RGB/BGR Order
D25
Display Data Latch Order
D24
Switching between Segment outputs and RAM
D23
Switching between Common outputs and RAM
D22
Interface Color Pixel Format Definition
D21
D20
D19
Idle Mode On/Off
D18
Partial Mode On/Off
D17
Sleep In/Out
D16
Display Normal Mode On/Off
D15
Vertical Scrolling Status
D14
Horizontal Scrolling Status
D13
Inversion Status
D12
All Pixels On
D11
All Pixels Off
D10
Display On/Off
D9
Tearing Effect Line On/Off
D8
Gamma Curve Selection
D7
D6
D5
Tearing Effect Output Line Mode
D4
Horizontal Sync. (HS, RGB I/F)
D3
Vertical Sync. (VS,RGB I/F)
D2
Pixel Clock (DOTCLK,RRGB I/F))
D1
Data Enable (DE,RGB I/F)
D0
Bit Values are explained overleaf.
Bit D31 – Booster Voltage Status
‘0’ = Booster Off or has a fault.
‘1’ = Booster On and working OK.
Bit D30 – Page Address Order
‘0’ = Top to Bottom (When MADCTL B7(MY) = ’0’).
‘1’ = Bottom to Top (When MADCTL B7(MY) =’1’).
Bit D29 – Column Address Order
‘0’ = Left to Right (When MADCTL B6(MX) = ’0’).
‘1’ = Right to Left (When MADCTL B6(MX) = ’1’).
Bit D28 –Page / Column Order
‘0’ = Normal Mode (When MADCTL B5(MV) = ’0’).
Comment
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Set to ‘0’
Himax Confidential
-P.127October, 2007
HX8340-B(N)
Bit D27 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4(ML) = ’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4(ML) = ’1’).
Bit D26 – RGB/BGR Order
‘0’ = RGB (When MADCTL B3 = ’0’).
‘1’ = BGR (When MADCTL B3 = ’1’).
Bit D25 – Display Data Latch Order
‘0’ = LCD Refresh Left to Right (When MADCTL B2 = ’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2 = ’1’).
Note : For bits D27, D26 and D25 also refer to 8.1.29 Memory Access Control (R36h)
Bit D24 – Switching Between Segment Outputs and RAM
This bit is not applicable for this project, so it is set to ‘0’.
Bit D23 – Switching Between Common Outputs and RAM
Bits D22, D21, D20 –Interface Color Pixel Format Definition
Interface Format
D22
D21
D20
Not Defined
0
0
0
Not Defined
0
0
1
Not Defined
0
1
0
12 bit/pixel
0
1
1
Not Defined
1
0
0
16 bit/pixel
1
0
1
18 bit/pixel
1
1
0
Not Defined
1
1
1
Bit D19 – Idle Mode On/Off
‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D18 – Partial Mode On/Off
‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
Bit D17 – Sleep In/Out
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D16 – Display Normal Mode On/Off
‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D15 – Vertical Scrolling On/Off
‘0’ = Vertical Scrolling is Off.
‘1’ = Vertical Scrolling is On.
Bit D14 – Horizontal Scrolling Status
Bit D13 – Inversion On/Off
‘0’ = Inversion is Off.
‘1’ = Inversion is On.
Bit D12 – All Pixels On
This bit is not applicable for this project, so it is set to ‘0’.
Bit D11 – All Pixels Off
Bit D10 – Display On/Off
‘0’ = Display is Off.
‘1’ = Display is On.
Bit D9 – Tearing Effect Line On/Off
‘0’ =Tearing Effect Line Off.
‘1’ = Tearing Effect On.
Himax Confidential
-P.128October, 2007
HX8340-B(N)
Bits D8, D7, D6 – Gamma Curve Selection
Gamma Curve Selected B8 B7 B6
Gamma Curve 1
0
0
0
Gamma Curve 2
0
0
1
Gamma Curve 3
0
1
0
Gamma Curve 4
0
1
1
Not Defined
1
0
0
Not Defined
1
0
1
Not Defined
1
1
0
Not Defined
1
1
1
Gamma Set (26h) Parameter
GC0 (Gamma 2.2)
GC1 (Gamma 1.8)
GC2 (Gamma 2.5)
GC3 (Gamma 1)
Not Defined
Not Defined
Not Defined
Not Defined
Bit D5 – Tearing Effect Line Output Mode.
‘0’ = Mode 1, V-Blanking only.
‘1’ = Mode 2, both H-Blanking and V-Blanking.
Bit D4 – Horizontal Sync. (HS) RGB I/F On/Off, Note
‘0’ = Horizontal Sync. line is Off (“Low”).
‘1’ = Horizontal Sync. line is On (“High”).
Bit D3 – Vertical Sync. (VS) RGB I/F On/Off, Note
‘0’ = Vertical Sync. line is Off (“Low”).
‘1’ = Vertical Sync. line is On (“High”).
Bit D2 – Pixel Clock (DOTCLK) RGB I/F On/Off, Note
‘0’ = DCK line is Off (“Low”).
‘1’ = DCK line is On (“High”).
Bit D1 – Data Enable (DE) RGB I/F On/Off, Note
‘0’ = ENABLE line is Off (“Low”).
‘1’ = ENABLE line is On (“High”).
Bit D0 – Parity Error
This bit is not applicable for this project, so it is set to ‘0’
Restriction
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00000000, 01100001, 00000000, 00000000
0xxxxx00, 0xxx0001, 00000000, 00000000
00000000, 01100001, 00000000, 00000000
Himax Confidential
-P.129October, 2007
HX8340-B(N)
Flow Chart
Himax Confidential
-P.130October, 2007
HX8340-B(N)
8.1.5 Read Display Power Mode (0Ah)
0A H
Command
1st parameter
2nd parameter
Description
RDDPM (Read Display Power Mode)
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
-0
0
0
0
1
0
1
0
0A
1
1
↑
----------1
1
↑
-D7
D6
D5
D4
D3
D2
0
0
xx
Bit
Description
Comment
D7
Booster Voltage Status
D6
Idle Mode On/Off
D5
Partial Mode On/Off
D4
Sleep In/Out
D3
Display Normal Mode On/Off
D2
Display On/Off
D1
Not Defined
Set to ‘0’
D0
Not Defined
Set to ‘0’
Bit D7 – Booster Voltage Status
‘0’ = Booster Off or has a fault.
‘1’ = Booster On and working OK (Meets display supplier’s optical requirements).
Bit D6 – Idle Mode On/Off
‘0’ = Idle Mode Off.
‘1’ = Idle Mode On.
Bit D5 – Partial Display Mode On/Off
‘0’ = Partial Mode Off.
‘1’ = Partial Mode On.
Bit D4 – Sleep In/Out
‘0’ = Sleep In Mode.
‘1’ = Sleep Out Mode.
Bit D3 – Normal Display Mode On/Off
‘0’ = Display Normal Mode Off.
‘1’ = Display Normal Mode On.
Bit D2 – Display On/Off
‘0’ = Display is Off.
‘1’ = Display is On.
Bit D1 – Not Defined
Bit D0 – Not Defined
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
08h
08h
08h
Himax Confidential
-P.131October, 2007
HX8340-B(N)
Flow Chart
Himax Confidential
-P.132October, 2007
HX8340-B(N)
8.1.6 Read Display MADCTL (0Bh)
0B H
Command
1st parameter
2nd parameter
RDDMADCTL (Read Display MADCTL)
D6
D5
D4
D3
D2
D1
D0
0
↑
1
-0
0
0
0
1
0
1
1
1
1
↑
---------1
1
↑
-D7
D6
D5
D4
D3
D2
0
0
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Description
Description
Page Address Order (MX)
Column Address Order (MY)
Page/Column Order (MV)
Line Address Order (ML)
RGB/BGR Order
Display Data Latch Order
Switching between Segment outputs and RAM
Switching between Common outputs and RAM
HEX
0B
-xx
Comment
Set to ‘0’
Set to ‘0’
Bit D7 – Page Address Order
‘0’ = Top to Bottom (When MADCTL B7(MY) = ’0’).
‘1’ = Bottom to Top (When MADCTL B7(MY) =’1’).
Bit D6 – Column Address Order
‘0’ = Left to Right (When MADCTL B6(MX) = ’0’).
‘1’ = Right to Left (When MADCTL B6(MX) = ’1’).
Bit D5 –Page / Column Order
‘0’ = Normal Mode (When MADCTL B5(MV) = ’0’).
‘1’ = Reverse Mode (When MADCTL B5(MV) = ’1’).
Bit D4 – Line Address Order
‘0’ = LCD Refresh Top to Bottom (When MADCTL B4(ML) = ’0’).
‘1’ = LCD Refresh Bottom to Top (When MADCTL B4(ML) = ’1’).
Bit D3 – RGB/BGR Order
‘0’ = RGB (When MADCTL B3 = ’0’).
‘1’ = BGR (When MADCTL B3 = ’1’).
Bit D2 – Display Data Latch Order
‘0’ = LCD Refresh Left to Right (When MADCTL B2 = ’0’).
‘1’ = LCD Refresh Right to Left (When MADCTL B2 = ’1’).
Note : For bits D4, D3 and D2 also refer to 8.1.29 Memory Access Control (R36h)
Bit D1 – Switching Between Segment Outputs and RAM
Bit D0 – Switching Between Common Outputs and RAM
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
No Change
00h
Himax Confidential
-P.133October, 2007
HX8340-B(N)
Flow Chart
Himax Confidential
-P.134October, 2007
HX8340-B(N)
8.1.7 Read Display Pixel Format (0Ch)
0C H
Command
1st parameter
2nd parameter
DNC
0
1
1
NWR
↑
1
1
RDDCOLMOD (Read Display COLMOD)
NRD D17-8 D7
D6
D5
D4
D3
D2
1
-0
0
0
0
1
1
↑
-------↑
-D7
D6
D5
D4
0
D2
D1
0
-D1
D0
0
-D0
HEX
0C
-xx
Bit
Description
Comment
D7
D6
RGB Interface Color Format
D5
D4
D3
Set to ‘0’
D2
System Interface Color Format
D1
D0
.
Bits D7,D6, D5, D4 – RGB Interface Color Pixel Format Definition
See section 8.1.33 Interface Pixel Format (R3Ah).
Description
RGB Interface Format
16 bit/pixel
18 bit/pixel
6 bit/pixel
The others
D7
0
0
1
D6
D5
1
0
1
1
1
1
Not Defined
D4
1
0
0
Bit D3 – System Interface Color Format Selection
Bit D2, D1, D0 – Control Interface Color Pixel Format Definition.
See section 8.1.33 Interface Pixel Format (R3Ah).
.
System Interface Color Format
Not Defined
Not Defined
Not Defined
12 bit/pixel
Not Defined
16 bit/pixel
18 bit/pixel
Restrictions
Register
Availability
D2
0
0
0
0
1
1
1
When RCM[1:0] = ‘0x’, D4, D5, D6, D7 = ‘0’
When RCM[1:0] = ‘10’ or ‘11’ D2, D1, D0 = ‘0’
Status
D1
0
0
1
1
0
0
1
D0
0
1
0
1
0
1
0
Availability
Yes
Yes
Yes
Yes
Himax Confidential
-P.135October, 2007
HX8340-B(N)
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
66h (18-bit/pixel)
No Change
66h (18-bit/pixel)
Flow Chart
Himax Confidential
-P.136October, 2007
HX8340-B(N)
8.1.8 Read Display Image Mode (0Dh)
0D H
Command
1st parameter
2nd parameter
Description
DNC
0
1
1
NWR
↑
1
1
RDDIM (Read Display Image Mode)
NRD D17-8 D7
D6
D5
D4
D3
1
-0
0
0
0
1
↑
------↑
-D7
0
D5
0
0
D2
1
-D2
D1
0
-D1
D0
1
-D0
HEX
0D
-xx
Bit D7 – Vertical Scrolling On/Off
‘0’ = Vertical Scrolling is Off.
‘1’ = Vertical Scrolling is On.
Bit D6 – Horizontal Scrolling Status
Bit D5 – Inversion On/Off
‘0’ = Inversion is Off.
‘1’ = Inversion is On.
Bit D4 – All Pixels On
Bit D3 – All Pixels Off
Bits D2, D1, D0 – Gamma Curve Selection
Gamma Curve Selected D2 D1 D0 Gamma Set (R26h) Parameter
Gamma Curve 1
0
0
0
GC0
Gamma Curve 2
0
0
1
GC1
Gamma Curve 3
0
1
0
GC2
Gamma Curve 4
0
1
1
GC3
Not Defined
1
0
0
Not Defined
Not Defined
1
0
1
Not Defined
Not Defined
1
1
0
Not Defined
Not Defined
1
1
1
Not Defined
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
00h
00h
Himax Confidential
-P.137October, 2007
HX8340-B(N)
Flow Chart
Himax Confidential
-P.138October, 2007
HX8340-B(N)
8.1.9 Read Display Signal Mode (0Eh)
0E H
Command
1st parameter
2nd parameter
Description
RDDSM (Read Display Signal Mode)
D6
D5
D4
D3
D2
D1
D0
HEX
0
↑
1
-0
0
0
0
1
1
1
0
0E
1
1
↑
----------1
1
↑
-D7
D6
D5
D4
D3
D2
0
0
xx
Bit D7 – Tearing Effect Line On/Off
‘0’ = Tearing Effect Line Off.
‘1’ = Tearing Effect On.
Bit D6 – Tearing Effect Line Output Mode, see section 7.3.1 for mode definitions.
‘0’ = Mode 1.
‘1’ = Mode 2.
Bit D5 – Horizontal Sync. (RGB I/F) On/Off
‘0’ = Horizontal Sync Bit / Line Off. (“Low”)
‘1’ = Horizontal Sync Bit / Line On. (“High”)
Bit D4 – Vertical Sync. (RGB I/F) On/Off
‘0’ = Vertical Sync Bit / Line Off.(“Low”)
‘1’ = Vertical Sync Bit / Line On.(“High”)
Bit D3 – Pixel Clock (PCLK, RGB I/F) On/Off
Bit D2 – Data Enable (DE, RGB I/F)) On/Off
D1 are D0 - are for future use and are set to ‘0’.
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
00h
00h
00h
Flow Chart
Himax Confidential
-P.139October, 2007
HX8340-B(N)
8.1.10 Read Display Self-Diagnostic Result (0Fh)
0F H
Command
1st parameter
2nd parameter
Description
RDDSDR (Read Display Self-Diagnostic Result)
D6
D5
D4
D3
D2
D1
0
↑
1
-0
0
0
0
1
1
1
1
1
↑
--------1
1
↑
-D7
D6
0
0
0
0
0
This command indicates the status of the display self-diagnostic results after
Sleep Out -command as described in the table below:
Bit D7 – Register Loading Detection
See section 7.6.2.
Bit D6 – Functionality Detection
See section 7.6.2.
Bit D5 – Chip Attachment Detection
Set bit D5 to ‘0’, if this function is not implemented.
Bit D4 – Display Glass Break Detection
Set bit D4 to ‘0’, if this function is not implemented.
Bits D3, D2, D1 and D0 are for future use and are set to ‘0’.
D0
1
-0
HEX
0F
---
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
00h
00h
Flow Chart
Himax Confidential
-P.140October, 2007
HX8340-B(N)
8.1.11 Sleep In (10h)
10 H
Command
Parameter
SLPIN (Sleep In)
D7
D6
D5
D4
0
0
0
1
DNC NWR NRD D17-8
D3
D2
D1
D0 HEX
↑
0
1
-0
0
0
0
10
NO PARAMETER
This command causes the LCD module to enter the minimum power consumption mode.
In this mode the DC/DC converter is stopped, Internal oscillator is stopped, and panel
scanning is stopped.
Description
Restriction
Register
Availability
MCU interface and memory are still working and the memory keeps its contents.
1. This command has no effect when module is already in sleep in mode. Sleep In Mode
can only be left by the Sleep Out Command (11h).
It will be necessary to wait 5msec before sending next command, this is to allow time
for the supply voltages and clock circuits to stabilize.
It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep
In Mode) before Sleep In command can be sent.
2. This command has no effect in RGB interface mode (RCM[1:0] = ‘10’ or ‘11’).
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Sleep In Mode
Sleep In Mode
Sleep In Mode
Himax Confidential
-P.141October, 2007
HX8340-B(N)
It takes 120msec to get into Sleep In mode after SLPIN command issued.
Flow Chart
Himax Confidential
-P.142October, 2007
HX8340-B(N)
8.1.12 Sleep Out (11h)
11 H
Command
Parameter
SLPOUT (Sleep Out)
D6
D5
D4
D3
D2
D1
D0 HEX
0
0
1
0
0
0
1
11
NO PARAMETER
This command turns off sleep mode.
In this mode the DC/DC converter is enabled, Internal oscillator is started, and panel
scanning is started.
DNC NWR NRD D17-8
↑
1
-0
D7
0
Output[1:320]
STOP
Blank
Memory Contents
(If DISPON 29h is set)
VST etc.(V scanner control logic)
CHARGH
DC charge in the capacitor
0V
DC/DC Converter
0V
DC/DC Converter
0V
DC/DC Converter
0V
Description
RESET
Reset pulse for circuit inside panel
START
Internal Oscillator
STOP
See also section -----.
Restriction
Register
Availability
1. This command has no effect when module is already in sleep out mode. Sleep Out
Mode can only be left by the Sleep In Command (10h).
It will be necessary to wait 5msec before sending next command; this is to allow time for
the supply voltages and clock circuits to stabilize.
The display module loads all display supplier’s factory default values to the registers
during this 5msec and there cannot be any abnormal visual effect on the display image if
factory default and register values are same when this load is done and when the display
module is already Sleep Out –mode.
The display module is doing self-diagnostic functions during this 5msec.
It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out
mode) before Sleep Out command can be sent.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Sleep In Mode
Sleep In Mode
Sleep In Mode
Himax Confidential
-P.143October, 2007
HX8340-B(N)
It takes 120msec to become Sleep Out mode after SLPOUT command issued.
Flow Chart
Himax Confidential
-P.144October, 2007
HX8340-B(N)
8.1.13 Partial Mode On (12h)
12 H
Command
Parameter
Description
Restrictions
Register
Availability
PTLON (Partial Mode On)
D6
D5
D4
D3
D2
D1
D0 HEX
↑
1
-0
0
0
1
0
0
1
0
12
0
NO PARAMETER
This command turns on partial mode The partial mode window is described by the Partial
Area command (30H). To leave Partial mode, the Normal Display Mode On command
(13H) should be written.
See also section 6.3.1
1. This command has no effect when Partial mode is active.
Status
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Normal Display Mode On
See Partial Area (30h)
Himax Confidential
-P.145October, 2007
HX8340-B(N)
8.1.14 Normal Display Mode On (13h)
13 H
Command
Parameter
Description
Restriction
Register
Availability
NORON (Normal Display Mode On)
D6
D5
D4
D3
D2
D1
D0 HEX
↑
1
-0
0
0
1
0
0
1
1
13
0
NO PARAMETER
This command returns the display to normal mode. Normal display mode on means
Partial mode off, Scroll mode Off.
1. This command has no effect when Normal mode is active.
Status
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this
command.
Himax Confidential
-P.146October, 2007
HX8340-B(N)
8.1.15 Display Inversion Off (20h)
20 H
Command
Parameter
INVOFF (Display Inversion Off)
DN
NRD NWR D17-8 D7
D6
D5
D4
D3
D2
C
0
1
↑
-0
0
1
0
0
0
NO PARAMETER
This command is used to recover from display inversion mode.
This command makes no change of contents of frame memory.
This command does not change any other status.
D1
D0
HEX
0
0
20
(Example)
memory
Description
display
Restriction
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Inversion Off
Flow Chart
Himax Confidential
-P.147October, 2007
HX8340-B(N)
8.1.16 Display Inversion On (21h)
21 H
Command
Parameter
INVON (Display Inversion On)
DN
NRD NWR D17-8 D7
D6
D5
D4
D3
D2
D1
D0 HEX
C
0
1
↑
-0
0
1
0
0
0
0
1
21
NO PARAMETER
This command is used to enter into display inversion mode.
This command makes no change of contents of frame memory. Every bit is inverted
from the frame memory to the display.
(Example)
memory
Description
display
Restriction
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Flow Chart
Himax Confidential
-P.148October, 2007
HX8340-B(N)
8.1.17 Gamma Set (26h)
26 H
Command
Parameter
Description
Restriction
Register
Availability
GAMSET (Gamma Set)
D6
D5
D4
D3
D2
D1
D0 HEX
↑
1
-0
0
1
0
0
1
1
0
26
0
↑
1
-GC7 GC6 GC5 GC4 GC3 GC2 GC1 GC0
1
01
This command is used to select the desired Gamma curve for the current display. A
maximum of 4 fixed gamma curves can be selected. The curve is selected by setting the
appropriate bit in the parameter as described in the table:
GC[7..0]
Parameter
Curve Selected
01h
GC0
Gamma Curve 1
02h
GC1
Gamma Curve 2
04h
GC2
Gamma Curve 3
08h
GC3
Gamma Curve 4
Note: All other values are undefined.
Values of GC[7..0] not shown in table above are invalid and will not change the
current selected Gamma curve until valid value is received.
Status
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
01h
01h
01h
Default
Flow Chart
Himax Confidential
-P.149October, 2007
HX8340-B(N)
8.1.18 Display off (28h)
28 H
Command
Parameter
DISPOFF (Display Off)
D6
D5
D4
D3
D2
D1
D0 HEX
↑
0
1
-0
0
1
0
1
0
0
0
28
NO PARAMETER
This command is used to enter into DISPLAY OFF mode. In this mode, the output from
Frame Memory is disabled and blank page inserted.
There will be no abnormal visible effect on the display.
(Example)
memory
Description
Restriction
Register
Availability
display
1. This command has no effect when module is already in display off mode.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Off
Display Off
Display Off
Legend
Display On
Mode
Command
Parameter
Display
Flow Chart
DISPOFF
Action
Mode
Display Off
Mode
Sequential
transfer
Himax Confidential
-P.150October, 2007
HX8340-B(N)
8.1.19 Display on (29h)
29 H
Command
Parameter
DISPON (Display On)
D7
D6
D5
D4
D3
0
1
0
1
0
D2
D1
D0 HEX
DNC NWR NRD D17-8
↑
0
0
0
1
29
1
-NO PARAMETER
This command is used to recover from DISPLAY OFF mode. Output from the Frame
Memory is enabled.
(Example)
memory
Description
Restriction
Register
Availability
display
1. This command has no effect when module is already in display on mode.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Display Off
Display Off
Display Off
Flow Chart
Himax Confidential
-P.151October, 2007
HX8340-B(N)
8.1.20 Column Address Set (2Ah)
2A H
CASET (Column Address Set)
D6
D5
D4
D3
↑
Command
0
0
1
0
1
1
-0
1st parameter
1
↑
1
-SC15 SC14 SC13 SC12 SC11
↑
1
-2nd parameter 1
SC7 SC6 SC5 SC4 SC3
3rd parameter 1
↑
1
-EC15 EC14 EC13 EC12 EC11
↑
1
-4th parameter 1
EC7 EC6 EC5 EC4 EC3
D2
0
SC10
SC2
EC10
EC2
D1
1
SC9
SC1
EC9
EC1
D0
0
SC8
SC0
EC8
EC0
HEX
2A
This command is used to define area of frame memory where MCU can access.
This command makes no change on the other driver status.
The values of SC[15:0] and EC[15:0] are referred when RAMWR command comes. Each
value represents one column line in the Frame Memory.
Description
Restriction
Register
Availability
SC[15:0] always must be equal to or less than EC[15:0]
When SC[15:0] or EC[15:0] is greater than maximum row address like below, data of out of
range will be ignored.
0000h<=SC[15:0]<=EC[15:0]<=00AFh (When MADCTL’s B5(MV)=0)
0000h<=SC[15:0]<=EC[15:0]<=00DBh (When MADCTL’s B5(MV)=1)
Status
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SC[15:0]=0000h
EC[15:0]=00AFh
When MADCTL’s B5(MV) = 0:
SC[15:0]=0000h
EC[15:0]=0AFh
SC[15:0]=0000h
EC[15:0]=00DBh
SC[15:0]=0000h
EC[15:0]=00AFh
Himax Confidential
-P.152October, 2007
HX8340-B(N)
Flow Chart
Himax Confidential
-P.153October, 2007
HX8340-B(N)
8.1.21 Page Address Set (2Bh)
2B H
PASET (Page Address Set)
D6
D5
D4
D3
D2
D1
D0
HEX
↑
Command
0
0
1
0
1
0
1
1
2B
1
-0
1st parameter 1
↑
1
-SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8
↑
1
-2nd parameter 1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
3rd parameter 1
↑
1
-EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8
↑
1
-4th parameter 1
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
This command is used to define area of frame memory where MCU can access.
The values of SP[15:0] and EP[15:0] are referred when RAMWR command comes.
Each value represents one Page line in the Frame Memory.
Description
Restriction
Register
Availability
SP[15:0] always must be equal to or less than EP[15:0]
When SP[15:0] or EP[15:0] is greater than maximum row address like below, data of out of
range will be ignored.
0000h<=SP[15:0]<=EP[15:0]<=00DBh (When MADCTL’s B5(MV)=0)
0000h<=SP[15:0]<=EP[15:0]<=00AFh (When MADCTL’s B5(MV)=1)
Status
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
SP[15:0]=0000h
EP[15:0]=00DBh
SP[15:0]=0000h
EP[15:0]=0DBh
SP[15:0]=0000h
EP[15:0]=00AFh
SP[15:0]=0000h
EP[15:0]=00DBh
Himax Confidential
-P.154October, 2007
HX8340-B(N)
Flow Chart
Himax Confidential
-P.155October, 2007
HX8340-B(N)
8.1.22 Memory Write (2Ch)
2C H
Command
1st parameter
:
nth parameter
DNC NWR NRD D17-8
↑
0
1
-1
1
1
↑
1
↑
↑
1
1
RAMWR (Memory Write)
D7
D6
D5
D4
D3
0
1
0
1
0
D1[15:0]
Dx[15:0]
Dn[15:0]
D2
1
D1
0
D0
0
HEX
2C
00..FF
00..FF
00..FF
Description
This command is used to transfer data from MCU to frame memory.
This command makes no change to the other driver status.
When this command is accepted, the column register and the page register are reset to the
Start Column/Start Page positions.
The Start Column/Start Page positions are different in accordance with MADCTL setting.
(See 6.1)
Then D[17:0] is stored in frame memory and the column register and the page register
incremented.
Sending any other command can stop frame Write.
Restriction
1. In all color modes, there is no restriction on length of parameters.
Register
Availability
Status
Status
Power On Sequence
S/W Reset
H/W Reset
Default
RAMWR
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Contents of memory is set randomly
Contents of memory is not cleared
Legend
Command
Parameter
Flow Chart
Image Data
D1[17:0],D2[17:0],
...,Dn[17:0]
Display
Action
Mode
Any Command
Sequential
transfer
Himax Confidential
-P.156October, 2007
HX8340-B(N)
8.1.23 Color Setting (2Dh)
2D H
Command
1st parameter
:
th
16 parameter
17th parameter
:
th
32 parameter
Description
Restriction
Register
Availability
RGBSET (Color Setting)
D6
D5
D4
D3
D2
D1
D0
HEX
↑
0
0
1
0
1
1
0
1
2D
1
-0
RGB RGB RGB RGB RGB RGB RGB RGB
1
↑
1
-00..FF
007 006 005 004 003 002 001 000
1
↑
1
-00..FF
nn7 nn6 nn5 nn4 nn3 nn2 nn1 nn0
1
↑
1
-00..FF
157 156 155 154 153 152 151 150
1
↑
1
-- RB167 RB166 RB165 RB164 RB163 RB162 RB161 RB160 00..FF
↑
1
-- RBnn7 RBnn6 RBnn5 RBnn4 RBnn3 RBnn2 RBnn1 RBnn0 00..FF
1
1
↑
1
-- RB317 RB316 RB315 RB314 RB313 RB312 RB311 RB310 00..FF
This command is used to define the LUT for 12bit to 18bit / 16bit-to-18bit, color depth
conversions. 80 bytes must be written to the LUT regardless of the color mode. Only the
values in section 5.1.10 are referred.
In this condition, 4K-color (4-4-4), and 65K-color(5-6-5) data input are transferred
6(R)-6(G)-6(B) through RGB LUT table.
This command has no effect on other commands/parameters and Contents of frame
memory.
Visible change takes effect next time the Frame Memory is written to.
Do not send any command before the last data is sent or LUT is not defined correctly.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Random values
Contents of the look-up table protected
Random values
Flow Chart
Himax Confidential
-P.157October, 2007
HX8340-B(N)
8.1.24 Memory Read (2Eh)
2E H
Command
1st parameter
2nd parameter
:
(n+1)th parameter
Description
RAMRD (Memory Read)
D6
D5
D4
D3
D2
D1
D0 HEX
0
1
0
1
1
1
0
2E
--------1
↑
1
D1[17:0]
00..FF
1
↑
1
Dx[17:0]
00..FF
↑
1
1
Dn[17:0]
00..FF
This command is used to transfer data from frame memory to MCU. This command makes
no change to the other driver status.
When this command is accepted, the column register and the page register are reset to the
Start Column/Start Page positions.
The Start Column/Start Page positions are different in accordance with MADCTL setting.
(See 6.1)
Then D[7:0] is read back from the frame memory and the column register and the page
register incremented
Frame read can be stopped by sending any other command.
1. In all color modes, the Frame Read is always like figure below. There is no restriction on
length of parameters. Note – Memory Read is only possible via the Parallel Interface.
Example: Read memory data form I80-8bit interface
DNC NWR NRD D17-8
↑
0
1
-1
↑
1
--
D7
0
--
NCS
NRESET
DNC
NWR_RNW
NRD_E
D7
0
X
R1
Bit5
G1
Bit5
B1
Bit5
R2
Bit5
D6
0
X
R1
Bit4
G1
Bit4
B1
Bit4
R2
Bit4
D5
1
X
R1
Bit3
G1
Bit3
B1
Bit3
R2
Bit3
D4
0
X
R1
Bit2
G1
Bit2
B1
Bit2
R2
Bit2
D3
1
X
R1
Bit1
G1
Bit1
B1
Bit1
R2
Bit1
D2
1
X
R1
Bit0
G1
Bit0
B1
Bit0
R2
Bit0
D1
1
X
X
X
X
D0
0
X
X
X
X
Restriction
Register
Availability
Status
X
X
Availability
Yes
Yes
Yes
Yes
Yes
Himax Confidential
-P.158October, 2007
HX8340-B(N)
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
Contents of memory is set randomly
RAMRD
Legend
Command
Dummy
Parameter
Flow Chart
Display
Image Data
D1[17:0],D2[17:0],Dn[17:0]
Action
Mode
Sequential
transfer
Any Command
Himax Confidential
-P.159October, 2007
HX8340-B(N)
8.1.25 Partial Area (30h)
30 H
PLTAR (Partial Area)
D6
D5
D4
D3
D2
D1
D0
HEX
↑
Command
0
0
1
1
0
0
0
0
30
1
-0
1st parameter 1
↑
1
-SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8
0000
↑
1
-2nd parameter 1
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
3rd parameter 1
↑
1
-ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8
00DB
↑
1
-4th parameter 1
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
This command defines the partial mode’s display area. There are 4 parameters associated
with this command, the first defines the Start Row (SR) and the second the End Row (ER),
as illustrated in the figures below. SR and ER refer to the Frame Memory Line Pointer.
If End Row > Start Row when MADCTL B4(ML) = 0:
Start Row
SR[15:0]
Partial Area
ER[15:0]
End Row
If End Row > Start Row when MADCTL B4(ML) = 1:
End Row
Description
ER[15:0]
Partial Area
SR[15:0]
Start Row
If End Row<Start Row when MADCTL’s B4(ML) = 0:
End Row
ER[15:0]
Partial Area
SR[15:0]
Start Row
If End Row = Start Row then the Partial Area will be one row deep.
Restriction
Register
Availability
1. SR[15:0] and ER[15:0] cannot be exceed than 00DBh.
Status
Availability
Yes
Yes
Yes
Yes
Yes
Himax Confidential
-P.160October, 2007
HX8340-B(N)
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Default Value
SR[15:0]=0000h
ER[15:0]=00DBh
SR[15:0]=0000h
ER[15:0]=00DBh
SR[15:0]=0000h
ER[15:0]=00DBh
1. To Enter Partial Display Mode:
PLTAR
Legend
Command
SR[15:0]
Parameter
Display
ER[15:0]
Action
PTLON
Partial M ode
Flow Chart
Mode
Sequential
transfer
2. To Leave Partial Display Mode
Partial Mode
DISPOFF
(Optional)
To prevent
Tearing Effect
Image displayed
NORON
Partial Mode OFF
RAMRW
Image Data
DISPON
Himax Confidential
-P.161October, 2007
HX8340-B(N)
8.1.26 Vertical Scrolling Definition (33h)
33 H
VSCRDEF (Vertical Scrolling Definition)
D6
D5
D4
D3
D2
D1
D0
↑
Command
0
0
1
1
0
0
1
1
1
-0
1st parameter
TFA TFA TFA TFA TFA TFA TFA TFA
1
↑
1
-15
14
13
12
11
10
9
8
↑
1
-TFA 7 TFA 6 TFA 5 TFA 4 TFA 3 TFA 2 TFA 1 TFA 0
2nd parameter 1
3rd parameter
VSA VSA VSA VSA VSA VSA VSA VSA
1
↑
1
-15
14
13
12
11
10
9
8
4th parameter
1
↑
1
--
VSA
7
VSA
6
VSA
5
VSA
4
VSA
3
VSA
2
VSA
1
VSA
0
5th parameter
1
↑
1
--
BFA
15
BFA
14
BFA
13
BFA
12
BFA
11
BFA
10
BFA
9
BFA
8
6th parameter
1
↑
1
--
HEX
33
0000
00DC
0000
BFA 7 BFA 6 BFA 5 BFA 4 BFA 3 BFA 2 BFA 1 BFA 0
This command defines the Vertical Scrolling Area of the display.
When MADCTL B4(ML) = ‘0’,
--The 1st & 2nd parameter TFA[15:0] describes the Top Fixed Area (in No. of lines from top
of the Frame Memory and Display).
--The 3rd & 4th parameter VSA[15:0] describes the height of the Vertical Scrolling Area (in
No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start
Address).
--The first line read from Frame Memory appears immediately after the bottom most line of
the Top Fixed Area. The 5th & 6th parameter BFA[15:0] describes the Bottom Fixed Area
(in No. of lines from Bottom of the Frame Memory and Display).
--TFA, VSA and BFA refer to the Frame Memory Line Pointer.
Description
When MADCTL B4(ML) = ‘1’
st
nd
--The 1 & 2 parameter TFA[15:0] describes the Top Fixed Area (in No. of lines from
bottom of the Frame Memory and Display).
rd
th
--The 3 & 4 parameter VSA[15:0] describes the height of the Vertical Scrolling Area (in
No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start
Address).
--The first line read from Frame Memory appears immediately after the top most line of the
Top Fixed Area.
--The 5th & 6th parameter BFA[15:0] describes the Bottom Fixed Area (in No. of lines from
Top of the Frame Memory and Display).
See Section 6.3 for details of the Memory to Display Mapping.
Himax Confidential
-P.162October, 2007
HX8340-B(N)
Restriction
The condition is (TFA+VSA+BFA)=220 in 176RGB x 220
, otherwise Scrolling mode is undefined.
In Vertical Scroll Mode, MADCTL B5(MV) should be set to ‘0’ – this only affects the Frame
Memory Write.
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
TFA[15:0]=0000
TFA[15:0]=0000
TFA[15:0]=0000
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VSA[15:0]=00DCh
VSA[15:0]=00DCh
VSA[15:0]=00DCh
BFA[15:0]=0000
BFA[15:0]=0000
BFA[15:0]=0000
Himax Confidential
-P.163October, 2007
HX8340-B(N)
1. To enter Vertical Scroll Mode:
Normal Mode
Legend
Command
VSCRDEF
Parameter
1st & 2nd Parameter TFA[15...0]
Display
3rd & 4th Parameter VSA[15...0]
Action
5th & 6th Parameter BFA[15...0]
Mode
CASET
Sequential
transfer
1st & 2nd Parameter SC[15...0]
3rd & 4th Parameter EC[15...0]
PASET
Only
required
for nonrolling
scrolling
Redefines the Frame
Memory Window that
the scroll data will be
written to.
See Note 1
1st & 2nd Parameter SP[15...0]
3rd & 4th Parameter EP[15..0]
MADCTL
Parameter
Optional – It may be
necessary to redefine
the Frame Memory
Write Direction.
RAMRW
Flow Charts
Scroll Image
Data
VSCRSADD
1st & 2nd Parameter VSP[15...0]
Scroll Mode
Note: The Frame Memory Window size must be defined correctly otherwise undesirable image
will be displayed.
Himax Confidential
-P.164October, 2007
HX8340-B(N)
2. Continuous Scroll:
Legend
Scroll Mode
CASET
1st & 2nd Parameter SC[15..0]
Command
Parameter
Display
Action
3rd & 4th Parameter EC[15..0]
Mode
PASET
1st & 2nd Parameter SP[15..0]
Sequential
transfer
3rd & 4th Parameter EP[15..0]
RAMRW
Scroll Image
Data
VSCRSADD
1st & 2nd Parameter VSP[15..0]
3. To Leave Vertical Scroll Mode:
Scroll Mode
DISPOFF
(Optional)
To prevent
Tearing Effect
Image displayed
NORON/PTLON
Scroll Mode OFF
RAMRW
Image Data
D1[15:0], D2[15:0],
…., Dn[15:0]
DISPON
Note: Scroll Mode can be left by both the Normal Display Mode On (13h) and Partial Mode On
(12h) commands.
Himax Confidential
-P.165October, 2007
HX8340-B(N)
8.1.27 Tearing Effect Line Off (34h)
34 H
Command
Parameter
DNC NWR NRD D17-8
↑
0
1
-No Parameter
TEOFF (Tearing Effect Line OFF)
D7
D6
D5
D4
D3
0
1
1
0
0
D2
1
D1
0
D0
0
HEX
34
Description
This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE
signal line.
Restriction
1. This command has no effect when Tearing Effect output is already OFF.
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Off
Off
Off
Flow Chart
Himax Confidential
-P.166October, 2007
HX8340-B(N)
8.1.28 Tearing Effect Line On (35h)
35 H
Command
1st
parameter
DNC NWR NRD D17-8
↑
0
1
-1
↑
1
--
TEON (Tearing Effect Line ON)
D7
D6
D5
D4
D3
0
1
1
0
0
--
--
--
--
--
D2
1
D1
0
D0
1
HEX
35
--
--
M
00h
This command is used to turn ON the Tearing Effect output signal from the TE signal
line. This output is not affected by changing MADCTL bit B4.
The Tearing Effect Line On has one parameter which describes the mode of the
Tearing Effect Output Line. (X=Don’t Care).
When M=0:
The Tearing Effect Output line consists of V-Blanking information only:
tvdl
tvdh
Vertical Time
Scale
Description
When M=1:
The Tearing Effect Output Line consists of both V-Blanking and H-Blanking
information:
tvdl
tvdh
Vertical Time
Scale
Restriction
Register
Availability
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin
will be active Low.
1. This command has no effect when Tearing Effect output is already ON.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Off
Off
Off
Legend
TE Line Output OFF
Command
Parameter
TEON
Flow Chart
M
Display
Action
Mode
TE Line Output ON
Sequential
transfer
Himax Confidential
-P.167October, 2007
HX8340-B(N)
8.1.29 Memory Access Control (36h)
MADCTL (Memory Access Control)
D6
D5
D4
D3
D2
↑
Command
0
1
-0
0
1
1
0
1
↑
1st parameter
1
MX
MV
ML BGR
SS
1
-MY
This command defines read/write scanning direction of frame memory.
Bit Assignment
36 H
Description
Bit
MY
MX
Name
PAGE ADDRESS ORDER
COLUMN ADDRESS ORDER
MV
PAGE/COLUMN SELECTION
ML
Vertical ORDER
BGR
RGB-BGR ORDER
MH
Horizontal ORDER
D1
1
--
D0
0
--
HEX
36
--
Description
These 3 bits controls MCU to
memory write/read direction. See
Section 6.2.1 MCU to memory
write/read direction”
LCD vertical refresh direction
control
Color selector switch control
(0=RGB color filter panel, 1=BGR
color filter panel)
LCD horizontal refresh direction
control
ML- Vertical Updating order
ML="1"
ML="0"
Top-Left(0,0)
Top- Left ( 0,0)
Memory
Top- Left ( 0,0)
Top-Left(0,0)
Memory
Display
Display
Sent last
Sent First
Sent 2nd
Sent 3rd
Sent 3rd
Sent 2nd
Sent First
Sent last
BGR-RGB-RBG Order
BGR="0"
RG B
BGR="1"
RG B
RG B
SIG1
Driver IC
SIG2
SIG132
SIG1
Driver IC
SIG2
SIG132
SIG1
SIG2
SIG132
SIG1
SIG2
SIG132
RG B
RG B
BGR B GR
RG B RG B
RG B RG B
LCD Panel
BGR B GR
RG B
BG R
BG R
LCD Panel
Himax Confidential
-P.168October, 2007
HX8340-B(N)
SS- Horizontal Updating order
SS="0"
SS="1"
Top-Left (0,0)
Top-Left (0,0)
Display
Display
Sent 3rd
Top-Left( 0,0)
Memory
Memory
Sent First
Sent 2nd
Sent 3rd
Sent last
Register
Availability
Sent last
Sent 3rd
Sent 2nd
Sent First
Restriction
Top- Left( 0,0)
Note: Top-Left (0,0) means a physical memory location.
D1 and D0 are set to ‘00’ internally. D2 is implemented if the LCD is updating pixel-by pixel.
D2 is set to ‘0’ internally if the LCD is updating line-by-line.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
00h
No Change
00h
Flow Chart
Himax Confidential
-P.169October, 2007
HX8340-B(N)
8.1.30 Vertical Scrolling Start Address (37h)
37 H
Command
1st parameter
2nd parameter
VSCRSADD (Vertical Scrolling Start Address)
DNC NRD NWR D17-8
D7
D6
D5
D4
D3
D2
D1 D0
HEX
0
1
↑
--0
0
1
1
0
1
1
1
37
VSP VSP VSP VSP VSP VSP VSP VSP
1
1
↑
15
14
13
12
11
10
9
8
0000
VSP VSP VSP VSP VSP VSP VSP VSP
1
1
↑
7
6
5
4
3
2
1
0
This command is used together with Vertical Scrolling Definition (33h). These two
commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start
Address command has one parameter which describes the address of the line in the
Frame Memory that will be written as the first line after the last line of the Top Fixed Area
on the display as illustrated below:
When MADCTL B4(ML)=’0’
Example:
When Top Fixed Area TFA = ‘00d’, Bottom Fixed Area BFA = ‘02’d, Vertical Scrolling Area
VSA = ‘218'd’ and VSP = ‘3d’
(Example)
(0,0)
Memory
B4 = 0
Display
Pointer
0
1
2
3
:
:
:
:
218
219
Line Pointer
VSP[15:0]
(0,219)
When MADCTL B4(ML)=’1’
Example:
When Top Fixed Area TFA = ‘00d’, Bottom Fixed Area BFA = ‘02d, Vertical Scrolling Area
VSA = ‘218d’ and VSP = ‘3d’
(Example)
(0,0)
Line Pointer
VSP[15:0]
Memory
B4 =1
Display
Pointer
219
218
:
:
:
:
3
2
1
0
(0,219)
Restriction
When new Pointer position and Picture Data are sent, the result on the display will happen
at the next Panel Scan to avoid tearing effect. VSP refers to the Frame Memory line
Pointer.
1. Since the value of the Vertical Scrolling Start Address is absolute (with reference to the
Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition
(33h) – otherwise undesirable image will be displayed on the Panel.
Himax Confidential
-P.170October, 2007
HX8340-B(N)
Register
Availability
Status
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Flow Chart
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
0000h
0000h
0000h
See Vertical Scrolling Definition (33h) description.
Himax Confidential
-P.171October, 2007
HX8340-B(N)
8.1.31 Idle Mode Off (38h)
38 H
Command
Parameter
DNC
0
NWR
↑
NRD
1
D17-8
--
IDMOFF (Idle Mode Off)
D7
D6
D5
D4
0
0
1
1
NO PARAMETER
D3
1
D2
0
D1
0
D0
0
HEX
38
This command is used to recover from Idle mode on.
Description In the idle off mode, LCD can display maximum 262,144 colors.
X = don’t care.
Restriction
Register
Availability
This command has no effect when module is already in idle off mode.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
Flow Chart
Himax Confidential
-P.172October, 2007
HX8340-B(N)
8.1.32 Idle Mode On (39h)
39 H
Command
Parameter
DNC
0
NWR
↑
NRD
1
D17-8
--
IDMON (Idle Mode On)
D7
D6
D5
D4
0
0
1
1
NO PARAMETER
D3
1
D2
0
D1
0
D0
1
HEX
39
This command is used to enter into Idle mode on.
In the idle on mode, colour expression is reduced. The primary and the secondary colours
using MSB of each R, G and B in the Frame Memory, 8 colour depth data is displayed.
Description
Memory contents vs. Display Colour
R6R5 R4 R3 R2 R1 R0
G6G5 G4 G3 G2 G1 G0
Black
0X X XX X X
0X X XX X X
Blue
0X X XX X X
0X X XX X X
Red
1X X XX X X
0X X XX X X
Magenta
1X X XX X X
0X X XX X X
Green
0X X XX X X
1X X XX X X
Cyan
0X X XX X X
1X X XX X X
Yellow
1X X XX X X
1X X XX X X
White
1X X XX X X
1X X XX X X
B 6B 5 B 4 B 3 B 2 B 1 B 0
0X X XX X X
1X X XX X X
0X X XX X X
1X X XX X X
0X X XX X X
1X X XX X X
0X X XX X X
1X X XX X X
X = don’t care.
Restriction
Register
Availability
This command has no effect when module is already in idle off mode.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
Idle Mode Off
Idle Mode Off
Idle Mode Off
Himax Confidential
-P.173October, 2007
HX8340-B(N)
Flow Chart
Himax Confidential
-P.174October, 2007
HX8340-B(N)
8.1.33 Interface Pixel Format (3Ah)
3A H
Command
1st parameter
Description
DNC NWR NRD D17-8
↑
1
-0
↑
1
1
--
COLMOD (Interface Pixel Format)
D7
D6
D5
D4
D3
D2
0
0
1
1
1
0
CS
CS
CS
IFP
-EL2 EL1 EL0
F2
D1
1
IFP
F1
D0
0
IFP
F0
HEX
3A
66
This command is used to define the format of RGB picture data, which is to be transfer via
the system and RGB interface. The formats are shown in the table:
System interface
Interface Format
IFPF2
IFPF1
IFPF0
Not Defined
0
0
0
Not Defined
0
0
1
Not Defined
0
1
0
12 Bit/Pixel
0
1
1
Not Defined
1
0
0
16 Bit/Pixel
1
0
1
18 Bit/Pixel
1
1
0
Not Defined
1
1
1
RGB interface
Interface Format
16 Bit/Pixel
18 Bit/Pixel
6 Bit/Pixel
Not Defined
CSEL3
0
0
1
CSEL2
CSEL1
1
0
1
1
1
1
The Other Setting
CSEL0
1
0
0
Restriction
Register
Availability
Status
Status
Power On Sequence
S/W Reset
H/W Reset
Default
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
66h (18-bit/pixel)
No Change
66h (18-bit/pixel)
Example:
16Bit/Pixel Mode
Legend
Command
Parameter
Flow Chart
COLMOD
Display
Action
D2:0] = ‘110’
18 Bit/Pixel Mode
Mode
Sequential
transfer
Himax Confidential
-P.175October, 2007
HX8340-B(N)
8.1.34 Read ID1 (DAh)
DA H
RDID1 (Read ID1)
NRD
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
DNC NWR
↑
Command
0
1
-1
1
0
1
1
0
1
0
1st parameter
↑
1
1
---------2nd parameter
↑
1
1
This read byte returns 8-bit LCD module’s manufacturer ID
The 1st parameter is dummy data
Description
The 2nd parameter (ID17 to ID10): LCD module’s manufacturer ID.
NOTE: See command RDDID (04h), 2nd parameter.
Restriction
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
HEX
DA
--
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
TBD
TBD
TBD
Flow Chart
Himax Confidential
-P.176October, 2007
HX8340-B(N)
8.1.35 Read ID2 (DBh)
DB H
RDID2 (Read ID2)
D6
D5
D4
D3
D2
↑
1
-1
1
0
1
1
0
Command
0
↑
-------1st parameter
1
1
↑
-1
ID26 ID25 ID24 ID23 ID22
2nd parameter
1
1
This read byte returns 8-bit LCD module/driver version ID
The 2nd parameter (ID26 to ID20): LCD module/driver version ID
Parameter Range: ID=80h to FFh
Description
ID Byte Value
80h
81h
82h
83h
84h
85h
Version
TBD
TBD
TBD
TBD
TBD
TBD
D1
1
-ID21
D0
1
-ID20
HEX
DB
---
Changes
TBD
TBD
TBD
TBD
TBD
TBD
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
TBD
TBD
TBD
Flow Chart
Himax Confidential
-P.177October, 2007
HX8340-B(N)
8.1.36 Read ID3 (DCh)
DC H
RDID3 (Read ID3)
D6
D5
D4
D3
D2
D1
D0
↑
1
-1
1
0
1
1
1
0
0
Command
0
↑
---------1st parameter 1
1
nd
↑
2 parameter 1
1
This read byte returns 8-bit LCD module/driver ID
The 2nd parameter (ID37 to ID30): LCD module/driver ID
Description
Parameter Range: ID=80h to FFh
NOTE: See command RDDID (04h), 4th parameter.
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
HEX
DC
---
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
TBD
TBD
TBD
Flow Chart
Himax Confidential
-P.178October, 2007
HX8340-B(N)
8.1.37 SETOSC: Set Internal Oscillator (B0h)
B0 H
DNC NWR NRD D17-8
SETOSC( Set Internal Oscillator)
D7
D6
D5
D4
D3
Command
1st parameter
0
↑
1
--
1
1
↑
1
--
--
2nd parameter
1
↑
1
--
--
0
1
1
---I/PI_
I/PI_
I/PI_
RADJ2 RADJ1 RADJ0
0
---
D2
D1
D0
0
0
0
HEX
B0
--OSC_EN
N/P_
N/P_
N/P_
RADJ2 RADJ1 RADJ0
01
54
These command is used to set internal oscillator related setting
OSC_EN: Enable internal oscillator, OSC_EN = ‘1’, internal oscillator start to oscillate.
OSC_EN = ‘0’, internal oscillator stop. In RGB interface mode (RCM[1:0] = ‘10’ or ‘11’),
internal oscillator will be stop to oscillate and OSC_EN bit control is invalid.
N/P_RADJ[2:0]: Internal oscillator frequency adjusts in Normal / Partial mode.
I/PI_RADJ[2:0]: Internal oscillator frequency adjusts in Idle(8-color) / Partial Idle mode.
For details, please refer to “7.1 Internal Oscillator” section.
Description
Restrictions
Register
Availability
Default
RADJ2
0
0
0
0
1
1
1
1
RADJ1
0
0
1
1
0
0
1
1
RADJ0
0
1
0
1
0
1
0
1
Internal Oscillator Frequency
133% x 2.52MHz
125% x 2.52MHz
117% x 2.52MHz
108% x 2.52MHz
100% x 2.52MHz
85% x 2.52MHz
75% x 2.52MHz
50% x 2.52MHz
1. EXTC should be high to enable this command
2. In RGB interface mode (RCM[1:0] = ‘10’ or ‘11’), oscillator will be stop and these bits
control are invalid.
Status
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OSC_EN=0, N/P_RADJ[2:0]=4’b100, I/PI_RADJ[2:0]=4’b101.
Flow Chart
Himax Confidential
-P.179October, 2007
HX8340-B(N)
8.1.38 SETPWCTR1: Set Power Control 1(B1h)
B1 H
DNC NWR NRD D17-8
↑
1
-Command
0
↑
1
-1st parameter
1
SETPWCTRL1 (Set power control 1)
D7
D6
D5
D4
D3
D2
D1
1
0
1
1
0
0
0
------ VCOMG PON
D0
1
DK
HEX
B1
01
DK: Specify on/off control of step-up circuit 1 for DDVDH voltage generation. For detail, see
the Power Supply Setting Sequence.
DK
Operation of step-up circuit 1
0
1
ON
OFF
PON: Specify on/off control of step-up circuit 2 for VGH, VGL voltage generation.
For detail, see the Power Supply Setting Sequence.
Description
PON
0
1
OFF
ON
VCOMG: Specify on/off control of step-up circuit 3 for VCL voltage generation. For detail,
see the Power Supply Setting Sequence. When VCOMG = ‘0’, VCOML = GND.
VCOMG
0
1
OFF
ON
Restrictions
EXTC should be high to enable this command
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
PON=1’b0, DK=1’b1, VCOMG=1’b0.
Flow Chart
Himax Confidential
-P.180October, 2007
HX8340-B(N)
B2 H
SETPWCTRL 2 (Set power control 2)
D6
D5
D4
D3
D2
D1
D0
HEX
↑
1
-1
0
1
1
0
0
1
0
B2
Command
0
↑
1
--I/PI_FS0[2:0]
-N/P_FS0[2:0]
44
1st parameter
1
↑
1
--I/PI_FS1[2:0]
-N/P_FS1[2:0]
22
2ndparameter 1
N/P_FS0[2:0]: Set the operating frequency of the step-up circuit 1 and extra step-up circuit 1
for DDVDH voltage generation in Normal / Partial mode.
I/PI_FS0[2:0]: Set the operating frequency of the step-up circuit 1 and extra step-up circuit 1
for DDVDH voltage generation in Idle(8-color) / Partial Idle mode.
Description
FS02
FS01
FS00
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Operation Frequency of Step-up Circuit 1
and Extra Step-up circuit 1
¼ x H Line Frequency
½ x H Line Frequency
1 x H Line Frequency
1.5 x H Line Frequency
N/P_FS1[2:0]: Set the operating frequency of the step-up circuit 2 and 3 for VGH, VGL and
VCL voltage generation in Normal / Partial mode.
I/PI_FS1[2:0]: Set the operating frequency of the step-up circuit 2 and 3 for VGH, VGL and
VCL voltage generation in Idle(8-color) / Partial Idle mode.
FS12
FS11
FS10
Operation Frequency of Step-up Circuit 2 ,
Step-up Circuit 3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
¼ x H Line Frequency
½ x H Line Frequency
1.5 x H Line Frequency
Note: Ensure that the operation frequency of step-up circuit 1 ≧ step-up circuit 2
Restrictions
Register
Availability
Status
Availability
Yes
Yes
Yes
Yes
Yes
Himax Confidential
-P.181October, 2007
HX8340-B(N)
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Default Value
N/P_FS0[2:0]=3’b100, I/PI_FS0[2:0]=3’b100,
N/P_FS1[2:0]=3’b010, I/PI_FS1[2:0]=3’b010.
N/P_FS0[2:0]=3’b100, I/PI_FS0[2:0]=3’b100,
N/P_FS1[2:0]=3’b010, I/PI_FS1[2:0]=3’b010.
N/P_FS0[2:0]=3’b100, I/PI_FS0[2:0]=3’b100,
N/P_FS1[2:0]=3’b010, I/PI_FS1[2:0]=3’b010.
Flow Chart
Himax Confidential
-P.182October, 2007
HX8340-B(N)
B3 H
SETPWCTRL 3 (Set power control 3)
D6
D5
D4
D3
D2
D1
D0
HEX
↑
1
-1
0
1
1
0
0
1
1
B3
Command
0
↑
1
------AP2 AP1 AP0
1st parameter
1
03
↑
1
-N/P_SAP[7:0]
32
2ndparameter 1
↑
1
-I/PI_SAP[7:0]
32
3rdparameter
1
AP[2:0]: Adjust the amount of current driving for the operational amplifier in the power supply
circuit. When the amount of fixed current is increased, the LCD driving capacity and the
display quality are high, but the current consumption is increased. Adjust the fixed current by
considering both the display quality and the current consumption.
AP2
0
0
0
0
1
1
1
1
Description
AP1
0
0
1
1
0
0
1
1
AP0
0
1
0
1
0
1
0
1
Constant Current of Operational Amplifier
Operation of the operational amplifier stops
Small
Medium Low
Medium
Medium High
Large
Setting Inhibited
Setting Inhibited
N/P_SAP[7:0]: Internal use, not open.
I/PI_SAP[7:0]: Internal use, not open.
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
AP[2:0]=3’b011, N/P_SAP[7:0]=8’h32, I/PI_SAP[7:0]=8’h32.
Flow Chart
Himax Confidential
-P.183October, 2007
HX8340-B(N)
B4 H
Command
1st parameter
2nd parameter
SETPWCTRL4 ( Set power control 4)
D6
D5
D4
D3
D2
D1
D0
HEX
↑
1
-1
0
1
1
0
1
0
0
B4
0
↑
1
----VRH4 VRH3 VRH2 VRH1 VRH0 03
1
↑
1
------BT2 BT1 BT0
1
00
VRH[4:0]: Specify the VREG1 voltage adjusting. VREG1 voltage is for gamma voltage
setting.
Description
VRH4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VRH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VRH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VRH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VRH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
VREG1
4.80
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
3.95
3.90
3.85
3.80
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.30
Internal circuit operations
stop. The gamma voltage
can be adjusted from
external VREG1 input.
Himax Confidential
-P.184October, 2007
HX8340-B(N)
BT[2:0]: Switch the output factor of step-up circuit 2 for VGH and VGL voltage generation. The
LCD drive voltage level can be selected according to the characteristic of liquid crystal
which panel used. Lower amplification of the step-up circuit consumes less current
and then the power consumption can be reduced.
BT2 BT1 BT0 DDVDH
VCL
VGH
VGL
0
0
0
5.2V
2.65V
3DDVDH
-VCI-2DDVDH
0
0
1
5.2V
2.65V
3DDVDH
-2DDVDH
0
1
0
5.2V
2.65V
3DDVDH
-VCI-DDVDH
0
1
1
5.2V
2.65V
VCI + 2DDVDH -VCI-2DDVDH
1
0
0
5.2V
2.65V
VCI + 2DDVDH
1
0
1
5.2V
2.65V
VCI + 2DDVDH -VCI-DDVDH
1
1
0
5.2V
2.65V
2DDVDH
-2DDVDH
1
1
1
5.2V
2.65V
2DDVDH
-VCI-DDVDH
-2DDVDH
Note: When VCI = 2.8V
Restrictions
Register
Availability
Default
Status
Availability
Yes
Yes
Yes
Yes
Yes
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
BT[2:0]=3’b000, VRH[4:0]=5’b00011.
BT[2:0]=3’b000, VRH[4:0]=5’b00011.
BT[2:0]=3’b000, VRH[4:0]=5’b00011.
Flow Chart
Himax Confidential
-P.185October, 2007
HX8340-B(N)
B5 H
Command
1st parameter
2nd parameter
3rd parameter
DNC NWR
↑
0
SETPWCTRL5 ( Set power control 5)
NRD D17-8
D7
D6
D5
D4
D3
1
-1
0
1
1
0
D2
1
D1
0
D0
1
HEX
B5
↑
1
1
--VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0
↑
1
1
--VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0
↑
1
1
--VML6 VML5 VML4 VML3 VML2 VML1 VML0
This command is used to set VCOM Voltage include VCOM Low and VCOM High Voltage
40
1C
34
VMH[6:0]: Set the VCOMH voltage (High level voltage of VCOM). The default value is
1Ch(28x0.025+2.5=3.2V)
VMH6
0
0
0
0
0
0
Description
VMH5
0
0
0
0
0
0
VMH4
0
0
0
0
0
0
VMH3
0
0
0
0
0
0
VMH2
0
0
0
0
1
1
VMH1
0
0
1
1
0
0
VMH0
0
1
0
1
0
1
VCOMH
2.500
2.525
2.550
2.575
2.600
2.625
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3.925
3.950
3.975
4.000
4.025
4.050
4.075
4.100
4.125
4.150
4.175
4.200
:
:
:
:
:
:
:
:
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
4700
4725
4750
4775
4800
4800
4800
VCOMH can be
adjusted from VCOMR
with a external VR
(variable resister)
:
:
:
:
:
:
:
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Himax Confidential
-P.186October, 2007
HX8340-B(N)
VML[6:0]: Set the VCOML voltage (Low level voltage of VCOM). The default value is
34h(52x0.025-2.5=-1.2V)
VML6
0
0
0
0
0
0
VML5
0
0
0
0
0
0
VML4
0
0
0
0
0
0
VML3
0
0
0
0
0
0
VML2
0
0
0
0
1
1
VML1
0
0
1
1
0
0
VML0
0
1
0
1
0
1
VCOML
-2.500
-2.475
-2.450
-2.425
-2.400
-2.375
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
-0.125
-0.100
-0.075
-0.050
-0.025
0.000
Setting inhibit
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
Setting inhibit
VMF[6:0]: Set the VCOM offset voltage. VMH+1d/VML+1d means VMH/VML from
original setting move up one step (25mV). VMH-1d/VML-1d means VMH/VML
from original setting move down one step (25mV)
Restrictions
Register
Availability
VMF[6:0]
VCOMH
0
“VMH” – 64d
1
“VMH” – 63d
2
“VMH” – 62d
3
“VMH” – 61d
:
:
62
“VMH” – 2d
63
“VMH” – 1d
64
“VMH”
65
“VMH” + 1d
66
“VMH” + 2d
:
:
126
“VMH” + 62d
127
“VMH” + 63d
Status
Status
Power On Sequence
Default
S/W Reset
H/W Reset
VCOML
“VMH” – 64d
“VMH” – 63d
“VMH” – 62d
“VMH” – 61d
:
“VMH” – 2d
“VMH” – 1d
“VML”
“VMH” + 1d
“VMH” + 2d
:
“VMH” + 62d
“VMH” + 63d
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
VMF[6:0]=8’h40,VMH[6:0]=8’h1C,
VML[6:0]=8’h34.
VMF[6:0]=8’h40,VMH[6:0]=8’h1C,
VML[6:0]=8’h34.
VMF[6:0]=8’h40,VMH[6:0]=8’h1C,
VML[6:0]=8’h34.
Flow Chart
Himax Confidential
-P.187October, 2007
HX8340-B(N)
8.1.43 SETDISCTRL: Set Display Control (B6h)
B6 H
SETDISCTRL ( Set display control )
D6
D5
D4
D3
D2
↑
1
-1
0
1
1
0
1
Command
0
↑
1
-PT1 PT0 GON DTE
1st parameter
1
D1
D0
↑
1
-REF PTV1 PTV0 PTG ISC3 ISC2
2nd parameter 1
D1
1
0
ISC1
D0
0
0
ISC0
HEX
B6
A0
B3
This command is used to set display related register
D[1:0]: When D1 = ‘1’, display is on; when D1 = ‘0’, display is off. When display is off, the
display data is retained in the GRAM and the entire source outputs are set to the VSSD
level.
When D[1:0]= ‘01’, the internal display of the HX8340-B is performed although the actual
display is off. When D[1:0]= ‘00’, the internal display operation halts and the display is off.
D1
D0
Source Output
0
0
1
1
0
1
0
1
VSSD
VSSD
=PT(0,0)
Display
HX8340-B Internal Display
Gate-Driver Control Signals
Operations
Halt
Halt
Operate
Operate
Operate
Operate
Operate
Operate
GON, DTE:
GON
0
1
1
Description
DTE
X
0
1
Gate Output
Fixed to VGH
Fixed to VGL
Normal Operation (VGH/VGL)
PT[1:0] : Specify the Non-display area source output in partial display mode.
Source Output Level
Non-display Area
NB
Display area
GRAM
Data
0
18’h00000
(Normally
.
Black Panel) 18’h3FFFF
1
18’h00000
(Normally
.
White Panel) 18’h3FFFF
PT1-0=(0,*)
PT1-0=(1,0)
PT1-0=(1,1)
VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOM
= “L” = “H” = “L” = “H” = “L” = “H” = “L” = “H”
V63P
V0N
.
.
V63P
V0N
GND GND
Hi-z
Hi-z
V0P
V63N
V0P
V63N
.
.
V63P
V0N
GND GND
Hi-z
Hi-z
V63P
V0N
REF: Refresh display in non-display area in Partial mode enable bit.
REF = ‘0’: Refresh display operation is disabling.
REF = ‘1’: Refresh display operation is enable.
PTG: Specify the scan mode of gate driver in non-display area.
PTG
0
1
Gate Outputs in Non-display Area
Normal Drive
Fixed VGL
Himax Confidential
-P.188October, 2007
HX8340-B(N)
PTV[1:0]: Specify the scan mode of VCOM in non-display area.
PTV1
0
0
1
1
PTV0
0
1
0
1
VCOM Outputs in Non-display Area
Normal Drive
Fixed to VCOML
Fixed to GND
Setting Inhibited
ISC[3:0]: Specify the scan cycle of gate driver when REF = ‘1’ in non-display area. Then
scan cycle is set to an odd number from 0~31.The polarity is inverted every scan cycle.
ISC3
ISC2
ISC1
ISC0
Scan Cycle
fFLM = 60Hz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 frame
3 frames
5 frames
7 frames
9 frames
11 frames
13 frames
15 frames
17 frames
19 frames
21 frames
23 frames
25 frames
27 frames
29 frames
31 frames
50 ms
84 ms
117 ms
150 ms
184 ms
217 ms
251 ms
284 ms
317 ms
351 ms
384 ms
418 ms
451 ms
484 ms
518 ms
PT1
0
1
PT0 REF
x
0
x
--
0
-Non-refresh cycle
1
0
1
1
ISC[3:0]
1
Refresh cycle
-Non-refresh cycle
Refresh cycle
Source Output
Black Display ( NB = ‘0’)
White Display ( NB = ‘1’)
GND
GND
Hi-z
Hi-z
Restrictions
EXTC should be high to enable this command.
Register
Availability
Status
VCOM Output
Gate Output
Normal Driving
Normal Driving
PTV[1:0]
PTV[1:0]
PTG
PTG
Normal Driving
Normal Driving
PTV[1:0]
PTV[1:0]
PTG
PTG
Normal Driving
Normal Driving
Availability
Yes
Yes
Yes
Yes
Yes
Himax Confidential
-P.189October, 2007
HX8340-B(N)
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Default Value
D1-0=2’b00, GON=1, DTE=0, PT[1:0]=2’b10, REF=1, PTG=1,
PTV[1:0] = 2’b01, ISC[3:0]=4’b011.
PTV[1:0] = 2’b01, ISC[3:0]=4’b011.
PTV[1:0] = 2’b01, ISC[3:0]=4’b011.
Flow Chart
Himax Confidential
-P.190October, 2007
HX8340-B(N)
8.1.44 SETFRMCTRL: Set Frame Rate Control (B7h)
B7 H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
SETFRMCTRL ( Set frame rate control)
D6
D5
D4
D3
D2
D1
D0
↑
1
-1
0
1
1
0
1
1
1
0
↑
1
---I/PI_DIV[1:0]
1
--N/P_DIV[1:0]
↑
1
-I/PI_RTN[3:0]
N/P_RTN[3:0]
1
↑
1
-N/P_DUM[7:0]
1
↑
1
1
-I/PI_DUM[7:0]
HEX
B7
00
88
08
08
N/P_DIV[1:0]: Specify the division ratio of internal clocks in Normal / Partial mode for
internal operation. When used internal clock for the display operation, frame frequency can
be adjusted with the N/P_RTN[3:0] bits (1H period clock cycle), N/P_DIV[1:0], and
N/P_DUM[7:0] bits.
I/PI_DIV[1:0]: Specify the division ratio of internal clocks in Idle (8-color) / Partial Idle mode
for internal operation. When used internal clock for the display operation, frame frequency
can be adjusted with the I/PI_RTN[3:0] bits(1H period clock cycle), I/PI_DIV[1:0], and
I/PI_DUM[7:0] bits.
DIV1
DIV0
Division Ratio
0
0
1
1
0
1
0
1
1
2
4
8
fosc = R-C oscillation frequency
Internal Display Operation Clock
Frequency
fosc / 1
fosc / 2
fosc / 4
fosc / 8
Description
N/P_RTN[3:0]: Specify clock number of one line period in Normal / Partial mode for internal
operation.
I/PI_ RTN[3:0]: Specify clock number of one line period in Idle (8-color) / Partial Idle mode
for internal operation.
RTN[3:0]
4’b0000
4’b0001
4’b0010
4’b0011
4’b0100
Clock cycles=1/internal operation clock frequency(fosc)
Clock number per Line
Setting Inhibited
Setting Inhibited
Setting Inhibited
Setting Inhibited
180
:
:
4’b1110
4’b1111
190
191
Himax Confidential
-P.191October, 2007
HX8340-B(N)
N/P_DUM[7:0]: Specify dummy line number in blanking area of one frame in Normal /
Partial mode for internal operation.
I/PI_DUM[7:0]: Specify dummy line number in blanking area of one frame in Idle (8-color) /
Partial Idle mode for internal operation.
DUM[7:0]
000d
001d
002d
003d
004d
:
254d
255d
Line number in blanking period
Setting Inhibited
Setting Inhibited
2
3
4
:
254
255
Formula for the Frame Frequency during internal display mode:
Frame frequency = fosc/( RTN × DIV × (220+DUM) ) [Hz]
fosc: RC oscillation frequency
Restrictions
Register
Availability
Status
Status
Power On Sequence
Default
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
N/P_DIV[1:0]=2’b00, I/PI_DIV[1:0]=2’b00,
N/P_RTN[3:0]=4’b1000, I/PI_ RTN[3:0]=4’b1000,
N/P_DUM[6:0]=7’b0001000, I/PI_ DUM[6:0]=7’b0001000.
N/P_DIV[1:0]=2’b00, I/PI_DIV[1:0]=2’b00,
N/P_RTN[3:0]=4’b1000, I/PI_ RTN[3:0]=4’b1000,
N/P_DUM[6:0]=7’b0001000, I/PI_ DUM[6:0]=7’b0001000.
N/P_DIV[1:0]=2’b00, I/PI_DIV[1:0]=2’b00,
N/P_RTN[3:0]=4’b1000, I/PI_ RTN[3:0]=4’b1000,
N/P_DUM[6:0]=7’b0001000, I/PI_ DUM[6:0]=7’b0001000.
Flow Chart
Himax Confidential
-P.192October, 2007
HX8340-B(N)
8.1.45 SETDISCYCCTRL: Set Display Cycle Control (B8h)
B8 H
Command
1st parameter
2nd parameter
3rd parameter
SETDISCYCCTRL (Set Display Cycle Control )
D6
D5
D4
D3
D2
↑
1
-1
0
1
1
1
0
0
↑
1
-SON[7:0]
1
↑
1
-GDON[7:0]
1
↑
1
1
-GDOF[7:0]
D1
0
D0
0
HEX
B8
38
0F
A8
The HX8340-B can control the display operation period time for LCD panel driving as follow:
1- Line Period
SON
S 1 – S528
Source Output Period
GDON
GDOF
Gate Output Period
VCOM
G(N)
Nth Gate Output Period
G(N+1)
N+1 th Gate Output Period
Description
SON[7:0]: Specify the valid source output start time in 1-line driving period. The period time
value is defined as SYSCLK number in internal clock display mode. The period
time value is defined as DOTCLK number in 18/16-bit bus width RGB display
mode and is defined as DOTCLK/3 number in 6-bit bus width RGB display mode.
(Please note that the setting “00h” and “01h” is inhibited).
GDON[7:0]: Specify the valid gate output start time in 1-line driving period. The period time
value is defined as SYSCLK number in internal clock display mode. The period
time value is defined as DOTCLK number in 18/16-bit bus width RGB display
mode and is defined as DOTCLK/3 number in 6-bit bus width RGB display mode.
(Please note that the setting “00h”, “01h”, “02h” is inhibited).
GDOF[7:0]: Specify the gate output end time in 1-line driving period. The period time value is
defined as SYSCLK number in internal clock display mode. The period time value is
defined as DOTCLK number in 18/16-bit bus width RGB display mode and is defined
as DOTCLK/3 number in 6-bit bus width RGB display mode. (Please note that the
GDON[7:0] + 1≤ GDOF[7:0] ≤ RTN-1).
Restrictions
Register
Availability
Status
Availability
Yes
Yes
Yes
Yes
Yes
Himax Confidential
-P.193October, 2007
HX8340-B(N)
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Default Value
SON[7:0]=8’h38, GDON7:0]=8’h0F, GDOF[7:0]=8’hA8.
Flow Chart
Himax Confidential
-P.194October, 2007
HX8340-B(N)
8.1.46 SETINVCTRL: Set Display Inversion Control (B9h)
B9 H
SETINVCTRL (Set Display Cycle Control )
D6
D5
D4
D3
D2
D1
D0
↑
1
-1
0
1
1
1
0
0
1
Command
0
↑
1
--I/PI_NW[2:0]
-N/P_NW[2:0]
1st parameter
1
This command is used to set display inversion control
HEX
B9
11
N/P_ NW[2:0]: Specify LCD driving inversion type in Normal/ Partial mode.
I/PI_ NW[2:0]: Specify LCD driving inversion type in Idle / Partial Idle mode.
NW[2:0]
0d
1d
2d
3d
:
6d
7d
Restrictions
Register
Availability
Default
LCD driving Inversion Type
Frame inversion
1-line inversion
2-line inversion
3-line inversion
:
6-line inversion
7-line inversion
Status
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
N/P_NW[2:0] = 3’b001, I/PI_N/W[2:0] = 3’b001.
N/P_NW[2:0] = 3’b001, I/PI_N/W[2:0] = 3’b001.
N/P_NW[2:0] = 3’b001, I/PI_N/W[2:0] = 3’b001.
Flow Chart
Himax Confidential
-P.195October, 2007
HX8340-B(N)
8.1.47 RGBBPCTR: Set RGB Interface Blanking Porch (BAh)
BA H
Command
1st parameter
2nd parameter
RGBBPCTR ( Set RGB interface blanking porch)
D6
D5
D4
D3
D2
D1
D0
↑
1
-1
0
1
1
1
0
1
0
0
↑
1
---HBP5 HBP4 HBP3 HBP2 HBP1 HBP0
1
↑
1
-VBP7 VBP6 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0
1
HEX
BA
06
06
This command is used to set vertical and horizontal back porch control in RGB I/F mode
(RCM[1:0]= ‘11’)
HBP[5:0]: Set the delay period from falling edge of HSYNC signal to first valid data in RGB I/F
mode 2
HBP[5:0]
00d
01d
02d
03d
04d
:
61d
62d
63d
Description
No. of clock cycle of DOTCLK
Setting Inhibited
Setting Inhibited
2
3
4
:
61
62
63
VBP[7:0]: Set the delay period from falling edge of VSYNC signal to first valid line in RGB
I/F mode 2
VBP[7:0]
00d
01d
02d
03d
04d
:
253d
254d
255d
No. of clock cycle of HSYNC
Setting Inhibited
Setting Inhibited
2
3
4
:
253
254
255
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
HBP[5:0] = 6’b000110, VBP[7:0] = 8’b00000110.
HBP[5:0] = 6’b000110, VBP[7:0] = 8’b00000110.
HBP[5:0] = 6’b000110, VBP[7:0] = 8’b00000110.
Flow Chart
Himax Confidential
-P.196October, 2007
HX8340-B(N)
8.1.48 SETRGBIF: Set RGB Interface Related Register (BBh)
BB H
SETRGBIF( Set RGB interface related register)
D6
D5
D4
D3
D2
D1
D0
↑
1
-1
0
1
1
1
0
1
1
Command
0
↑
1
-----DPL HSPL VSPL EPL
1st parameter
1
This command is used to set RGB interface related register
HEX
BB
00
EPL: Specify the polarity of Enable pin in RGB interface mode.
EPL
ENABLE pin
Display image
Operation
0
High
Enable
Write data to DB17-0
0
Low
Disable
Disable
1
High
Disable
Disable
1
Low
Enable
Write data to DB17-0
Description
VSPL: The polarity of VSYNC pin. When VSPL=0, the VSYNC pin is Low active. When
VSPL=1, the VSYNC pin is High active.
HSPL: The polarity of HSYNC pin. When HSPL=0, the HSYNC pin is Low active. When
HSPL=1, the HSYNC pin is High active.
DPL: The polarity of DOTCLK pin. When DPL=0, the data is read on the rising edge of
DOTCLK signal. When DPL=1, the data is read on the falling edge of DOTCLK signal.
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
DPL=1’b0, HSPL=1’b0, VSPL=1’b0, EPL=1’b0
Flow Chart
Himax Confidential
-P.197October, 2007
HX8340-B(N)
8.1.49 SETDODC: Set Driver Output Direction Control (BCh)
BC H
SETDODC(Set Driver Output Direction Control)
D6
D5
D4
D3
D2
D1
↑
1
-1
0
1
1
1
1
0
Command
0
↑
1
-------CTB
1st parameter
1
This command is used to set driver output direction control in RGB interface.
D0
0
CRL
HEX
BC
00
CRL: Source output direction select register in RGB interface.
CRL
0
1
Description
CTB: Gate output direction select register in RGB interface.
CTB
0
1
Restrictions
Register
Availability
Normal Direction
Reverse Direction
Normal Direction
Reverse Direction
Note: 1. As CRL bit be written in RGB interface, the external pin RL control is invalid, CRL is
operated based on external pin SMX setting.
2. As CTB bit be written in RGB interface, the external pin TB control is invalid, CTB is
operated based on external pin SMY setting.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
CRL=1’b0, CTB=1’b0.
No Change
CRL=1’b0, CTB=1’b0.
Flow Chart
Himax Confidential
-P.198October, 2007
HX8340-B(N)
8.1.50 SETINTMODE: Set Interface Mode (BDh)
BD H
SETINTMODE ( Set interface mode)
D6
D5
D4
D3
↑
1
-1
0
1
1
1
Command
0
↑
1
------1st parameter
1
This command is used to set interface mode.
D2
1
--
D1
D0
HEX
0
1
BD
RCM1 RCM0 00
RCM[1:0]: RGB and MCU interface select.
RCM1
0
1
1
Description
Restrictions
Register
Availability
RCM0
x
0
1
Interface Select
System Interface (1)
RGB Interface (1) (VS+HS+DE)
RGB Interface (2) (VS+HS)
Note: 1. As RCM[1:0] bit be written, the external pin RCM[1:0] control is invalid.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
RCM[1:0]=2’b00.
No Change
RCM[1:0]=2’b00.
Flow Chart
Himax Confidential
-P.199October, 2007
HX8340-B(N)
8.1.51 SETPANEL: Set Panel (BEh)
BE H
SETPANEL ( Set panel)
D6
D5
D4
D3
↑
1
-1
0
1
1
1
Command
0
↑
1
------1st parameter
1
This command is used to set the characteristic of used panel.
D2
1
--
D1
1
--
D0
0
NWB
HEX
BE
00
NWB: RGB and MCU interface select.
Description
Restrictions
Register
Availability
NWB
Panel Type
Normally White Panel Used
0
Normally Black Panel Used
1
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
NWB = 1’b0.
NWB = 1’b0.
NWB = 1’b0.
Flow Chart
Himax Confidential
-P.200October, 2007
HX8340-B(N)
8.1.52 SETOTP: Set OTP Related Setting (RC7h)
C7 H
Command
1st parameter
2nd parameter
Description
DNC NWR NRD D17-8
↑
0
1
-↑
1
1
--
SETOTP ( Set OTP related setting)
D7
D6
D5
D4
D3
1
1
0
0
0
OTP
OTP_PTM[ OTP_VRAD _PO
1:0]
J[1:0]
R
↑
1
1
--OTP_XA[2:0]
-This command is used to set the OTP related setting.
OTP_POR: for OTP read/write timing control
OTP_OTPEN: 1’b1 to select 6.5V for OTP write operation.
OTP_PPROG : 1’b1 to turn on OTP write mode.
OTP_PWE : 1’b1 to write OTP.
OTP_XA[2:0]: OTP_YA[2:0] : Select OTP write address
OTP_TM[1:0] : OTP Test mode register, In-house use.
OTP_VRADJ[1:0] : OTP VPP2 adjust register, In-house use.
Restrictions
Register
Availability
Status
Status
Power On Sequence
Default
S/W Reset
H/W Reset
D2
1
OTP
_OT
PEN
D1
D0
1
1
OTP OTP
_PP _PW
RO
E
G
OTP_YA[2:0]
HEX
C7
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
OPT_POR= 1’b0, OTP_OTPEN= 1’b0, OTP_PPROG= 1’b0,
OTP_PWE=1’b0
OTP_XA[2:0]=3’b000, OTP_YA[2:0]=3’b000
OTP_VRADJ[1:0]=2’b00 ,OTP_PTM[1:0]=2’b00
OTP_PWE=1’b0
OTP_XA[2:0]=3’b000, OTP_YA[2:0]=3’b000
OTP_PWE=1’b0
OTP_XA[2:0]=3’b000, OTP_YA[2:0]=3’b000
Flow Chart
Himax Confidential
-P.201October, 2007
HX8340-B(N)
8.1.53 SETONOFF: Set Chip On/Off (C0h)
C0 H
SETONOFF( Set chip on / off)
D6
D5
D4
D3
↑
1
-1
1
0
0
0
Command
0
↑
1
------1st parameter
1
This command is used to set chip On/ Off control bit in RGB I/F.
Description
Restrictions
Register
Availability
CSHUT
0
1
D2
0
--
D1
D0
HEX
0
0
C0
-- CSHUT 01
Chip On/Off in RGB I/F
Chip On
Chip Off
As CSHUT command bit be written in RGB interface, the external pin SHUT control is invalid,
and chip on/off selection is controlled by internal CSHUT command bit.
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
CSHUT = 1’b1.
CSHUT = 1’b1.
CSHUT = 1’b1.
Flow Chart
Himax Confidential
-P.202October, 2007
HX8340-B(N)
8.1.54 SETEXTCOM: Set extended command set (C1h)
C1 H
SETEXTCOM ( Set extended command set)
D6
D5
D4
D3
D2
↑
1
-1
1
0
0
0
0
Command
0
↑
1
-1
1
1
1
1
1
1st parameter
1
↑
1
-1
0
0
0
0
0
2nd parameter
1
↑
1
-0
1
0
0
0
0
3rd parameter
1
This command is used to set extended command set access enable.
Extend cmd
Enable
Description
Disable(default)
D1
0
1
1
0
D0
1
1
1
0
HEX
C1
FF
83
40
Command description
After command (C1h), must write 3 parameters
(ffh,83h,40h) by order
After command(C1h), write 3 parameters (xxh,xxh,xxh)
any value is all right, but can not be (ffh,83h,40h)
As CEXTC command bit be written, the external pin EXTC control is invalid, and Extended
command set access enable selection is controlled by internal CEXTC command bit.
Restrictions
Register
Availability
Status
Availability
Yes
Yes
Yes
Yes
Yes
Himax Confidential
-P.203October, 2007
HX8340-B(N)
8.1.55 SETGAMMAP: Set “+” polarity Gamma Curve GC0 Related Setting (C2h)
C2H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
5th parameter
6th parameter
7th parameter
8th parameter
9th parameter
SETGAMMAP ( Set “+” polarity Gamma Curve Related Setting)
D6
D5
D4
D3
D2
↑
0
1
-1
1
0
0
0
0
↑
1
1
--MP12 MP11 MP10
-MP02
↑
1
1
--MP32 MP31 MP30
-MP22
↑
1
-MP42
1
--MP52 MP51 MP50
↑
1
1
----CP04 CP03 CP02
↑
1
1
-CP23 CP22 CP21 CP20 CP13 CP12
↑
1
1
-----CP33 CP32
↑
1
1
----CP44 CP43 CP42
↑
1
-OP13 OP12 OP11 OP10 OP03 OP02
1
↑
1
1
---CGM1[1:0]
Description
This command is used for Gamma Curve related Setting.
For details, please refer to 7.2 Gamma resister stream and 8 to 1 Selector.
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
D1
D0
1
0
MP01 MP00
MP21 MP20
MP41 MP40
CP01 CP00
CP11 CP10
CP31 CP30
CP41 CP40
OP01 OP00
CGM0[1:0]
HEX
C2
---------
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
TBD
No change
TBD
Flow Chart
Himax Confidential
-P.204October, 2007
HX8340-B(N)
8.1.56 SETGAMMAN: Set “-” polarity Gamma Curve GC0 Related Setting (C3h)
C3H
Command
1st parameter
2nd parameter
3rd parameter
4th parameter
5th parameter
6th parameter
7th parameter
8th parameter
SETGAMMAN ( Set “-” polarity Gamma Curve Related Setting)
D6
D5
D4
D3
↑
0
1
-1
1
0
0
0
↑
1
1
--MN12 MN11 MN10
-↑
1
1
--MN32 MN31 MN30
-↑
1
-1
--MN52 MN51 MN50
↑
1
1
----CN04 CN03
↑
1
1
-CN23 CN22 CN21 CN20 CN13
↑
1
1
-----CN33
↑
1
1
----CN44 CN43
↑
1
-ON13 ON12 ON11 ON10 ON03
1
D2
0
MN02
MN22
MN42
CN02
CN12
CN32
CN42
ON02
Description
This command is used for “-” polarity Gamma Curve GC0 related Setting.
For details, please refer to 7.2 Gamma resister stream and 8 to 1 Selector.
Restrictions
Register
Availability
Status
Default
Status
Power On Sequence
S/W Reset
H/W Reset
D1
1
MN01
MN21
MN41
CN01
CN11
CN31
CN41
ON01
D0
1
MN00
MN20
MN40
CN00
CN10
CN30
CN40
ON00
HEX
C3
---------
Availability
Yes
Yes
Yes
Yes
Yes
Default Value
TBD
No change
TBD
Flow Chart
Himax Confidential
-P.205October, 2007
HX8340-B(N)
9. Layout Recommendation
9.1 Parallel Interface of Command-Parameter Mode
G6
G4
G2
DUMM Y23
G220
G218
S526
S527
S528
DUMM Y24
S262
S263
S361
S265
S266
S267
S1
S2
S3
G215
G217
G219
DUMMY
C11B
2
C11AB1
0603/1u/6.3V
C12B
C3
0603/1u/16V
C4
0603/1u/10V
3
C5
0603/1.0u/6.3V
1
C12A
HX8340-B (BUMP UP)
VREG1
VCOMH
VCOML
VCOMR
IOVCC
TE
EXT C
C1
0603/1u/6.3V
C2
0603/1u/25V
U1
VSSA
VSSD
VDDD
IOVCC
C22AB1
0603/1u/10V
C11A
NRESET
SDI
NRD_E
NW R_RNW_SCL
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
IM3
IM2
IM1
IM0
SDO
D3
RB521S-30
C11A
C11B
VPP_OTP
C12A
C12B
DDVDH
VCI
VCL
OSC
DNC
NCS
C21AB1
0603/1u/10V
C22B
VSSD
C21B
C22A
VGL
C21A
VGH
C22A
C22B
C21A
C21B
VCOM
VGH
VGL
C22A
C22B
C21A
C21B
VTEST
VMONI
VSSD
C11A
C11B
VPP_OT P
C12A
C12B
DDVDH
VCI
VCL
OSC
DNC
NCS
VS
HS
DOT CLK
DE
NRESET
SDI
NRD
NW R
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
IM3
IM2
IM1
IM0
SDO
REGVDD
TE
EXT C
SRGB
SMX
SMY
IF SEL
RCM0
RCM1
IDM
SHUT
RL
TB
REV
VSSA
VSSD
VDDD
IOVCC
T EST 1
T EST 2
VREG1
VCOMH
VCOML
VCOMR
T EST 3
VCOM
T EST 4
T EST 5
DUMM Y27
G1
G3
G5
176RGB x 220 TFT Panel
C12AB1
0603/1u/6.3V
VR1
10K(OPEN)
C7
0603/1u/10V
C8
0603/1.0u/6.3V
C6
0603/1u/6.3V
IM3
IM2
IM1
IM0
0
0
0
0
68-system, 16-bit bus interface
0
0
0
1
0
0
1
0
0
0
1
1
-
1
-
-
SERIAL INTERFACE
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
Interface mode
C9
0603/1u/10V
C10
0603/1u/6.3V
IM3
IM 2
IM 1
IM 0
IOVCC1
IOVCC
VDDD1 DDVDH1 VCL1
VDDD
DDVDH VCL
VGH1
VGH
VGL1 VREG1
VGL VREG1
VPP_OTP1
VPP_OTP
VCOM1 VCOMR1 VCOMH1 VCOML1
VCOM VCOMR VCOMH VCOML
R1
0603/0R
VSSD
R2
0603/0R
GND
IM4
IM0
TE1
TE
OSC1
OSC
IM0
TE
OSC
VCOML
VCOMH
VCOMR
IM3
IM1
IM1
VCOM
VPP_OTP
IM2
IM2
IM3
DBS1 IM1
DBS IM3
IM2
VREG1
NCS1
NCS
DBS
VGL
VGH
DNC
NWR_RNW
NWR_RNW1 DNC1
NWR_RNW DNC
NCS
VCL
DDVDH
VDDD
IOVCC
NRESET1 NRD_E1
NRESET NRD_E
NRD_E
1. VCI, IOVCC are separated from different power source
to get better display quality.
2. SDO pin is output pin. SDO pin must be left floating when no use.
3. The input pin must be fixed IOVCC or GND when no use. Refer to "Pin Description".
GND1 GND2
GND GND
NRESET
VCI
VCI
GND
VCC
IOVCC
nRESET
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
nRD_E
NWR_RNW
DNC
nCS
FLM
GND
PWM_OUT
VSYNC
HSYNC
DOT CLK
ENABLE
SDO
SDI
NC
NC
NC
NC
NC
NC
NC
NC
EXT C
DBS
IM3
IM2
IM1
IM0
GND
BL+/NC
BL_GND/NC
J1
VSSA
VCI
EXT C
SDO
SDI
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NRD_E
NW R_RNW_SCL
DNC
NCS
TE
GND
NRESET
VCI1
VCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
GND
VCI
IOVCC
IFSEL="1" COMMAND-PARAMETER MODE
RCM[1:0]="0x" MPU I/F
F PC60-0.5-4.0L
Figure 9. 1 Layout Recommendation of System Interface
Himax Confidential
-P.206October, 2007
HX8340-B(N)
9.2 RGB + SPI Interface of Command-Parameter
G6
G4
G2
DUMMY23
G220
G218
S526
S527
S528
DUMMY24
S262
S263
S361
S265
S266
S267
S1
S2
S3
G215
G217
G219
DUMMY
C11B
2
C11AB2
0603/1u/6.3V
C12B
C20
0603/1u/16V
C14
0603/1u/10V
3
C11
0603/1u/6.3V
1
C12A
HX8340-B(BUMP UP)
VREG1
VCOMH
VCOML
VCOMR
IOVCC
RCM0
RCM1
IDM
SHUT
RL
TB
REV
EXTC
IM3
IM2
IM1
IM0
SDO
C12
0603/1u/6.3V
C18
0603/1u/25V
U2
VSSA
VSSD
VDDD
IOVCC
C22AB2
0603/1u/10V
C11A
DNC
NCS
VS
HS
DOTCLK
DE
NRESET
SDI
NRD_E
NWR__SCL
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DDVDH
VCI
VCL
OSC
D2
RB521S-30
VSSD
C21AB2
0603/1u/10V
C22B
VGH
C21B
C22A
VGL
C21A
C11A
C11B
VPP_OTP
C12A
C12B
C22A
C22B
C21A
C21B
VCOM
VGH
VGL
C22A
C22B
C21A
C21B
VT EST
VMONI
VSSD
C11A
C11B
VPP_OTP
C12A
C12B
DDVDH
VCI
VCL
OSC
DNC
NCS
VS
HS
DOTCLK
DE
NRESET
SDI
NRD
NWR
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
IM3
IM2
IM1
IM0
SDO
REGVDD
TE
EXTC
SRGB
SMX
SMY
IFSEL
RCM0
RCM1
IDM
SHUT
RL
TB
REV
VSSA
VSSD
VDDD
IOVCC
TEST1
TEST2
VREG1
VCOMH
VCOML
VCOMR
TEST3
VCOM
TEST4
TEST5
DUMMY27
G1
G3
G5
176RGB x 220 TFT Panel
C12AB2
0603/1u/6.3V
VR2
10K(OPEN)
C16
0603/1u/10V
C13
0603/1u/6.3V
C15
0603/1.0u/6.3V
C17
0603/1u/10V
C19
0603/1u/6.3V
IOVCC2
IOVCC
VDDD2 DDVDH2 VCL2
VDDD
DDVDH VCL
VGH2
VGH
VGL2 VREG2
VGL VREG1
VPP_OTP2
VPP_OTP
VCOM2 VCOMR2 VCOMH2 VCOML2
VCOM VCOMR VCOMH VCOML
R4
0603/0R
VSSD
R3
0603/0R
GND
VCOML
VCOMH
VCOMR
VCOM
VPP_OTP
VREG1
VGL
VGH
VCL
DDVDH
VDDD
IOVCC
NCS2
NCS
DBS2 IM7
DBS IM3
IM6
IM2
IM5
IM1
IM8
IM0
TE2
TE
OSC2
OSC
IM1
IM0
TE
OSC
NWR_RNW2 DNC2
NWR_RNW DNC
IM2
NRESET2 NRD_E2
NRESET NRD_E
DBS
VSY NC HSY NC DOTCLK ENABLE
VSY NC HSY NC DOTCLK ENABLE
GND3 GND4
GND GND
NCS
VCI
VCI
GND
VCC
IOVCC
nRESET
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
nRD_E
NWR_RNW
DNC
nCS
FLM
GND
PWM_OUT
VSYNC
HSYNC
DOTCLK
ENABLE
SDO
SDI
NC
SHUT
RL
TB
IDM
REV
RCM0
RCM1
EXTC
DBS
IM3
IM2
IM1
IM0
GND
BL+/NC
BL_GND/NC
J2
VSSA
VCI
SHUT
RL
TB
IDM
REV
RCM0
RCM1
GND
NCS
NWR__SCL
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NRESET
VCI2
VCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
GND
VCI
IOVCC
VS
HS
DOTCLK
DE
SDO
SDI
RCM[1:0]="10" RGB MODE1 (HS+VS+DE)
RCM[1:0]="11" RGB MODE2 (HS+VS)
IFSEL="1" COMMAND-PARAMETER MODE
DE
DOTCLK
HS
VS
IM3
DNC
NWR_RNW
NRD_E
1. VCI, IOVC C are separated from different power sou rce
to g et better disp lay q uality.
2. SDO pin is output pin. SDO pin must be left floatin g when no use.
3. T he input p in must be fixed IOVCC or GN D when no use. Refer to "Pin D escription ".
NRESET
F PC60-0.5-4.0L
Figure 9. 2 Layout Recommendation of RGB Interface
Himax Confidential
-P.207October, 2007
HX8340-B(N)
10. OTP
YA[2:0]=
111
XA[2:0]=000 ID17
XA[2:0]=001 1
XA[2:0]=010 ID37
XA[2:0]=011
YA[2:0]=
110
ID16
ID26
ID36
VMF6
YA[2:0]= YA[2:0]= YA[2:0]= YA[2:0]= YA[2:0]=
101
100
011
010
001
ID15
ID14
ID13
ID12
ID11
ID25
ID24
ID23
ID22
ID21
ID35
ID34
ID33
ID32
ID31
VMF5
VMF4
VMF3
VMF2
VMF1
Table 10.1 OTP ADDRESS MAPPING
YA[2:0]=
000
ID10
ID20
ID30
VMF0
Non-Program
00h
00h
00h
00h
OTP Programming Flow
Found optimized value
and record them
(Only ‘1’ need to be
programmed)
Set OTP_OTPEN=’1’
(0xC7=0x04)
Wait 1us
Apply external Voltage
to VPP 6.5V
Wait 1us
Set OTP_PPRog=’1’
(0xC7=0x06)
Floating external
Voltage 6.5V
Wait 1us
(0xC7=0x00)
Wait 1us
Re-Power on
Wait 1us
Set related Address to
XA[2:0] & YA[2:0]
Wait 1us
Set OTP_PWE=’1’
(0xBF=0x07)
Wait 600us
Set OTP_PWE=’0’
(0xC7=0x06)
Wait 1us
(0xC7=0x04)
Wait 1us
Himax Confidential
-P.208October, 2007
HX8340-B(N)
OTP Programming Example (VMF=15h)
15h=8’b00010101
only YA=000,010 and
100 need program
(RC7h,PA1=04h)
Wait 1us
Set OTP_PWE=’1’
(RC7h,PA1=07h)
Wait 600us
Wait 1us
Apply external Voltage
to VPP 6.5V
Wait 1us
(RC7h,PA1=06h)
Wait 1us
Set related Address to XA & YA
(RC7h,PA1=04h,PA2=30h)
Set OTP_PWE=’0’
(RC7h,PA1=06h)
Wait 1us
Wait 1us
Set OTP_PWE=’1’
(RC7h,PA1=07h)
Wait 1us
Set OTP_PWE=’1’
(RC7h,PA1=07h)
Wait 600us
Wait 600us
Set OTP_PWE=’0’
(RC7h,PA1=06h)
Wait 1us
Set OTP_PWE=’0’
(RC7h,PA1=06h)
Wait 1us
(RC7h,PA1=04h)
Wait 1us
Floating external
Voltage 6.5V
Wait 1us
(RC7h,PA1=00h)
Wait 1us
Re-Power on
Himax Confidential
-P.209October, 2007
HX8340-B(N)
11. Electrical Characteristic
11.1 Absolute Maximum Ratings
Item
Logic Supply voltage
Power Supply voltage
Logic input voltage range
Logic Output voltage range
Operating Temperature Range
Storage Temperature Range
Symbol
IOVCC
VCI
Vin
Vo
TOPR
TSTG
Value
-0.3~+3.6
-0.3~+4.2
-0.3~IOVCC+0.5
-0.3~IOVCC+0.5
-20~+70
-40~+125
(VSS = 0V)
Unit
V
V
V
V
°C
°C
Note: (1) IOVCC, VSSD must be maintained.
(2) To make sure IOVCC ≥ VSSD.
(3) To make sure VCI ≥ VSSA.
Table 11. 1 Absolute Maximum Ratings
11.2 ESD Protection Level
Mode
Human Body Model
Machine Model
Test Condition
C = 100 pF, R = 1.5 kΩ
C = 200 pF, R = 0.0 Ω
Protection Level
±2.5K
±250
Unit
V
V
11.3 Latch-Up Protection Level
T.B.D
11.4 Light Sensitivity
T.B.D
Himax Confidential
-P.210October, 2007
HX8340-B(N)
11.5 Maximum Layout Resistance
Name
Maximum
Resistance
Type
Unit
IOVCC
Power supply
10
Ω
VCI
Power supply
10
Ω
VPP_OTP
Power supply
10
Ω
VSSA
Power supply
10
Ω
VSSD
Power supply
10
Ω
OSC
Input
100
Ω
DBS,IM[3:0], EXTC, IFSEL0,RCM[1:0]
Input
100
Ω
NRD_E, NWR_RNW_SCL, DNC, NCS, SDI Input
100
Ω
NRESET,SMX,SMY,SRGB,
Input
100
Ω
IDM,SHUT,RL,TB,REV
Input
100
Ω
DB[17:0], DOTCLK, DE, VS, HS
Input
100
Ω
VGH
Capacitor connection 10
Ω
VGL
Ω
VCL
Ω
DDVDH
Ω
VDDD
Ω
VREG1
Ω
VCOMH, VCOML
Ω
C11A, C11B,
Ω
C12A, C12B
Ω
C21A, C21B
Ω
C22A, C22B
Ω
VCOMR
Input
100
Ω
SDO, TE,
Output
100
Ω
Himax Confidential
-P.211October, 2007
HX8340-B(N)
11.6 DC Characteristics
Parameter
Symbol
Power & Operating Voltages
IO Operating voltage
IOVCC
Driver Operating voltage
VCI
Source Drive Voltage
VREG1
Gate Drive High Voltage
VGH
Gate Drive Low Voltage
VGL
Drive Supply Voltage
|VGH-VGL|
Input / Output
High level input voltage
VIH
Low level input voltage
VIL
High level output voltage
VOH
Low level output voltage
VOL
Input leakage high current IIH
Input leakage current
IIL
Oscillator frequency
fOSC
Booster
AVDD boost voltage1
DDVDH
VCL boost voltage
VCL
VREG1 output voltage
VREG1
VCOM Generator
VCOM amplitude
VCOM
VCOM high level
VCOMH
VCOM low level
VCOML
Source Driver
Output voltage deviation
Output voltage range
Output offset voltage
DVOS
VOS
Voff
Conditions
MIN
TYP
MAX
Unit
1.65
2.5
TBD
TBD
TBD
TBD
1.8
2.8
TBD
TBD
TBD
TBD
3.3
3.3
TBD
TBD
TBD
TBD
V
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
IAVDD=1mA,
ICL=-300uA
No load
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
V
No load
No load
No load
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
V
V
V
TBD
TBD
TBD
mV
TBD
TBD
TBD
mV
TBD
TBD
TBD
V
I/O supply voltage
Operation voltage
IOH = -1.0mA
IOL = +1.0mA
-
VSSD+1.0 ~
VREG1-1.0
VSSD+0.1V ~
VSSD+1.0
VREG1-1.0 ~
VREG1-0.1V
-
Himax Confidential
V
µA
µA
kHz
-P.212October, 2007
HX8340-B(N)
11.6.1 Current Consumption
Host
I/F
Mode of operation
Host interface NOT active
- Normal Mode On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
- Normal Mode On
- Partial Mode Off
- Idle Mode On
- Sleep Out Mode
- Normal Mode Off
- Partial Mode On
(32 lines)
- Idle Mode Off
- Sleep Out Mode
- Normal Mode Off
- Partial Mode On
(32 lines)
- Idle Mode On
- Sleep Out Mode
- Sleep In Mode
Frame
Frequency
Inversion
Mode
Image
Memory Data
Access
Control
(MY:MX:MV)
60Hz
TBD
TBD
TBD
TBD
TBD
Note 1
Note 2
Note 3
Note 4
Note 5
X;X;X
X;X;X
X;X;X
X;X;X
X;X;X
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
60Hz
TBD
Note 5
X;X;X
TBD
TBD
60Hz
TBD
Grey
Levels
X;X;X
TBD
TBD
TBD
Note 6
X;X;X
TBD
TBD
TBD
Note 7
X;X;X
TBD
TBD
N/A
N/A
X;X;X
0;0;0
0;0;1
0;1;0
0;1;1
1;0;0
1;0;1
1;1;0
1;1;1
0;0;0
0;0;1
0;1;0
0;1;1
1;0;0
1;0;1
1;1;0
1;1;1
0.002
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.010
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
60Hz
N/A
Host interface active
262k Colors
NOTE 8
- Normal Mode On
- Partial Mode Off
- Idle Mode Off
- Sleep Out Mode
Current consumption
Typical
Worst case
VCI
VCI
(mA)
(mA)
CPU Access
@ 15fps
60Hz
TBD
262k Colors
NOTE 8
CPU Access
@ 25fps
Typical Case:
TA = 25oC
IOVCC=1.8V
VCI = 2.8V
Note: X Do not care
Worst Case:
TA = -30 to70oC
IOVCC = 1.65V to 1.95V
VCI = 2.5V to 3.3V
Includes Process Variance.
1. All pixels black
2. Checker board one by one
3. Checker board 4 by 4
4. Grey-scale from top to bottom
5. 20% Black, 80%White
6. Black & White Checker board 8 by 8.
7. Absolute Worst Case Patterns: Defined by Display Supplier
8. Absolute Worst Case Patterns and Sequences: Defined by Display Supplier
9. Absolute worst case VCI current is less than TBD mA in the case of CPU access is inactive, Normal Mode On,
Partial Mode Off, Idle Mode Off, Sleep Out mode.
10. Absolute worst case IOVCC current is less than TBD mA in the case of CPU access is inactive, Normal Mode
On, Partial Mode Off, Idle Mode Off, Sleep Out mode.
11. Inrush currents are not included in current consumption values
Himax Confidential
-P.213October, 2007
HX8340-B(N)
11.7 AC CHARACTERISTICS
11.7.1 Parallel Interface Characteristics (8080-series MPU)
Figure 11. 1 Parallel Interface Characteristics (8080-series MPU)
(VSSA=0V, IOVCC=1.65V to 1.95V, VCI=2.5V to 3.3V,Ta = -30 to 70°C)
Signal
Symbol
Parameter
MIN
MAX
Unit
tAST
Address setup time
0
DNC
ns
tAHT
Address hold time (Write/Read)
10
0
Chip select “H” pulse width
tCHW
15
Chip select setup time (Write)
tCS
45
Chip select setup time (Read ID)
tRCS
ns
NCS
355
Chip select setup time (Read FM)
tRCSFM
10
Chip select wait time (Write/Read)
tCSF
10
Chip select hold time
tCSH
tWC
Write cycle
66
NWR_RNW
tWRH
Control pulse “H” duration
15
ns
tWRL
Control pulse “L” duration
15
tRC
Read cycle (ID)
160
NRD_E (ID)
tRDH
Control pulse “H” duration (ID)
90
ns
tRDL
Control pulse “L” duration (ID)
45
tRCFM
Read cycle (FM)
450
NRD_E (FM)
ns
tRDHFM
Control pulse “H” duration (FM)
90
tRDLFM
Control pulse “L” duration (FM)
355
tDST
Data setup time
10
tDHT
Data hold time
10
40
ns
D15 to D0
tRAT
Read access time (ID)
Read access time (FM)
340
tRATFM
80
tODH
Output disable time
20
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOVCC for Input signals.
Description
-
-
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
Himax Confidential
-P.214October, 2007
HX8340-B(N)
Figure 11. 2 Chip Select Timing
Figure 11. 3 Write to Read and Read to Write Timing
Himax Confidential
-P.215October, 2007
HX8340-B
176RGB x 220 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver
11.7.2 Parallel Interface Characteristics (6800-series MPU)
Figure 11. 4 Parallel Interface Characteristics (6800-series MPU)
(VSSA=0V, IOVCC=1.65V to 1.95V, VCI=2.5V to 2.9V,Ta = -30 to 70°C)
Signal
Symbol
Parameter
Min.
Max.
Unit
tAST
Address setup time
0
DNC
ns
tAHT
Address hold time (Write/Read)
10
tCHW
Chip select “H” pulse width
0
tCS
Chip select setup time (Write)
15
tRCS
Chip select setup time (Read ID)
45
ns
NCS
tRCSFM
Chip select setup time (Read FM)
355
tCSF
Chip select wait time (Write/Read)
10
tCSH
10
tWC
Write cycle
66
NWR_RNW
tWRH
Control pulse “H” duration
15
ns
tWRL
Control pulse “L” duration
15
tRC
Read cycle (ID)
160
NRD_E (ID)
tRDH
Control pulse “H” duration (ID)
90
ns
tRDL
Control pulse “L” duration (ID)
45
tRCFM
Read cycle (FM)
450
NRD_E (FM)
tRDHFM
Control pulse “H” duration (FM)
90
ns
tRDLFM
Control pulse “L” duration (FM)
355
Tdst
Data setup time
10
Data hold time
10
tDHT
Read access time (ID)
40
ns
D17 to D0
tRAT
tRATFM
Read access time (FM)
340
tODH
Output disable time
20
80
Description
-
-
-
When read ID data
When read from frame
memory
For maximum CL=30pF
For minimum CL=8pF
Himax Confidential
-P.216October, 2007
HX8340-B(N)
11.7.3 Serial Interface Characteristics
NCS
t CSS
t CHW
t CSH
tSCYCW/tSCYCR
t SCC
tSLW/tSLR
SCL
V IH
VIL t
t SDS
tSHW/tSHR
t SDH
tf
SDIO
(Write data)
tr
tACC
SDIO
(Read data)
t OH
Figure 11. 5 Serial Interface Characteristics
Parameter
Serial clock cycle (Write)
SCL ”H” pulse width (Write)
SCL ”L” pulse width (Write)
Data setup time (Write)
Data hold time (Write)
Serial clock cycle (Read)
SCL ”H” pulse width (Read)
SCL ”L” pulse width (Read)
Symbol
tSCYCW
tSHW
tSLW
tSDS
tSDH
tSCYCR
tSHR
tSLR
Access Time
tACC
Output disable time
tOH
Conditions
SCL
SDIO
SCL
SDI for maximum CL=30pF
For minimum CL=8pF
SDO For maximum CL=30pF
For minimum CL=8pF
SCL, NCS
NCS
Min.
66
15
15
10
10
150
60
60
Typ.
Max.
-
Unit
10
50
ns
15
50
ns
SCL to Chip select
tSCC
20
NCS “H” pulse width
tCHW
40
Chip select setup time
tCSS
15
NCS
tCSH
15
Himax Confidential
ns
ns
ns
ns
ns
-
ns
-P.217October, 2007
HX8340-B(N)
11.7.4 RGB Interface Characteristics
TVSST
VIH
VS
HS
TVSHT
VIL
THSST
Thv
TPCLKCYC
DOTCLK
THSHT
TPCLKHT
TPCLKLT
VIH
VIL
TDST/TDEST
DB[B:0]
DE
TDHT/TDEHT
VIH
VIL
Item
Symbol
Condition
Pixel low pulse width
Pixel high pulse width
Vertical Sync. set-up time
Vertical Sync. hold time
Horizontal Sync. set-up time
Horizontal Sync. hold time
Data Enable set-up time
Data Enable hold time
Data set-up time
Data hold time
Phase difference of sync signal
falling edge
TCLKLT
TCLKHT
TVSST
TVSSHT
THSST
TVSSHT
TDEST
TDEHT
TDST
TDHT
Min
15
15
15
15
15
15
15
15
15
15
Thv
0
Specification
Type.
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
176
Dotclk
Note: 1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Himax Confidential
-P.218October, 2007
HX8340-B(N)
Item
Vertical Timing
Vertical cycle period
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical blanking period
Symbol
TVP
TVS
TVFP
TVBP
TVBL
Vertical active area
TVDISP
Vertical refresh rate
Horizontal Timing
Horizontal cycle period
Horizontal low pulse width
Horizontal front porch
Horizontal back porch
Horizontal blanking period
Horizontal active area
Pixel clock cycle
TVRR=60Hz
TVRR
THP
THS
THFP
THBP
THBL
THDISP
fCLKCYC
Condition
TVBP + TVFP
Min
Specification
Type.
224
2
2
2
4
228
2
2
6
8
Unit
Max
511
HS
HS
HS
HS
HS
HS
HS
HS
Hz
255
220
Frame rate
50
60
80
184
2
2
6
8
176
255
THBP + THFP
180
2
2
2
4
2.0
2.52
10.0
63
DOTCLK
DOTCLK
DOTCLK
DOTCLK
DOTCLK
DOTCLK
MHz
Note 1. IOVCC=1.6 to 3.3V, VCI=2.5 to 3.3V, VSSA=VSSD=0V, Ta=-30 to 70℃ (to +85℃ no damage)
Note 2. Data lines can be set to “High” or “Low” during blanking time – Don’t care.
Note 3. HP is multiples of DOTCLK.
Himax Confidential
-P.219October, 2007
HX8340-B(N)
11.7.5 Reset Input Timing
Shorter than 5μs
tRESW
NRESET
tREST
Internal Status
Normal Operation
Initial Condition
(Default for H/W reset)
Resetting
Figure 11. 6 Reset Input Timing
Symbol
tRESW
Parameter
*1) Reset low pulse width
Related Pins
NRESET
tREST
Min.
10
Typ.
-
Max.
-
-
-
5
-
120
*2) Reset complete time
-
Note
Unit
µs
When reset applied during
Sleep In mode
When reset applied during
Sleep Out mode
ms
ms
Note:
1. Spike due to an electrostatic discharge on !RES line does not cause irregular system reset according to the
following table.
NRESET Pulse
Shorter than 5 µ
Longer than 10 µs
Between 5 µs and 10 µs
Action
Reset Rejected
Reset
Reset Start
2. During the resetting period, the display will be blanked (The display is entering blanking sequence, which
maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in
Sleep In –mode) and then return to Default condition for H/W reset.
3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this
period. This loading is done every time when there is H/W reset complete time (tREST) within 5ms after a
rising edge of RESET.
4. Spike Rejection also applies during a valid reset pulse as shown as below:
5. It is necessary to wait 5msec after releasing RESET before sending commands. Also Sleep Out command
cannot be sent for 120msec.
Himax Confidential
-P.220October, 2007
HX8340-B(N)
11.7.6 Measurement Conditions
11.7.6.1 tACC, tOH Measurement Condition
Measurement Condition Set-up
Oscilloscope
See “NOTE”
Data Generator
Connector
LCD Panel
FPC
External components for test condition
(pull-down and pull-up cases) which are
removed after test:
Resistor: 3kOhm ± 5%
Capacitor: 8 or 30pF ± 10%
Connector Pin / Measurement Point
See “NOTE”
Note: Capacitances and resistances of the oscilloscope’s probe must be included externals components in these
measurements
Minimum Value Measurement
Himax Confidential
-P.221October, 2007
HX8340-B(N)
Maximum Value Measurement
Himax Confidential
-P.222October, 2007
HX8340-B(N)
12. Ordering Information
Part No.
Package
HX8340-B000 PDxxx
PD : mean COG
xxx : mean chip thickness (µm), (default: 300 µm)
13. Revision History
Version
Date
01
2007/10/05
2007/10/16
Description of Changes
New setup
P12. Change SMX and SRGB direction
P14. Modify IOVCC=1.65~3.3V
P15. Modify Dummy pins, change Dummy 14 and
Dummy15 become connection pins.
P39. Modify Table 5.8 GRAM write 18-Bits Parallel
Interface Set Table
P54. Modify Table 5.12 GRAM read 18-Bits Parallel
Interface Set Table
P79. Modify Table 6. 10 GRAM X Address and Display
Panel Position
P83. Modify Table 6. 11 ISC[3:0] Bits Definition
P92. Modify Figure 7. 1HX8340-B Internal Clock Circuit
P98. Modify Table 7. 16 Voltage Calculation Formula of
Grayscale Voltage V2~V7 and V56~V61
P196. Modify 8.1.47 RGBBPCTR: Set RGB Interface
Blanking Porch (BAh)
P122. Remove Extend command C4h~C9h
P203. Add GCS[1:0] bits for C2h gamma setting.
Himax Confidential
-P.223October, 2007
HX8340-B(N)
2007/11/01
P8 Modify IFSEL= ‘H’ for Command-paremeter interface
P9 Modify IOVCC =1.65~3.3V, VGH=+9.0~+15.6V
P10 Modify Block Diagram add RL,TB,SHUT,REV,IDM
pins
P11~12 Modify DNC ,NWR and IFSEL pin description.
P14 Modify VGH max voltage =15.6V
P26 Modify Table 5.2 Read 8-bits parameter or status
(DB8 to DB1)
P29 Modify Table 5.3 Read 8-bits parameter or status
(DB8 to DB1)
P48 Modify Figure 5.20 Example of I80- / M68- System
9-Bit Parallel Bus Interface
P66 Add note for Figure 5. 25 RGB Mode timing Diagram
P94. Modify Figure 7. 23 Gamma Resister Stream and
Gamma Reference Voltage
P95 Modify Table 7.4 Center Adjustment Resistance
P97Modify Table 7.6 Voltage Calculation Formula
P98 Add note to Table 7.8Voltage Calculation Formula of
Grayscale Voltage V2~V7 and V56~V61
P112. Add note to Table 7.12 Power ON AC
Characteristics
P113 add note to Table 7.13 Power OFF AC
Characteristics
P122 Update command RBFh SETOTP related register.
P123 Update RC2h GAMMA positive related setting.
P181 Add SLP bit to RB1h power control.
P183 Modify RB3h AP[2:0] default value 0x03.
P184 Modify RB4h VRH[4:0] default value, change to 0x03
P185 Add description at RB5h VCOM related setting.
P196 Modify RBAH RGBBPCTR setting, only valid at RGB
mode 2
P198 Modify RBCH command; after software reset the
setting doesn’t change.
P199 Modify RBDH command; after software reset the
setting doesn’t change.
P201 Update command RBFh SETOTP related register.
P203 Remove GCS[1:0] bits for C2h gamma setting.
P206~207 Modify Layout Recommendation
P208 Update OTP table and OTP programming flow.
Himax Confidential
-P.224October, 2007
HX8340-B(N)
2007/12/03
P12. Modify SHUT Pin description.
P95. Modify table 7.4 Gamma Center Resistance Adjustment
P97. Modify table 7.6 Gamma Voltage Calculation Formula
P112. Modify RGB mode Power on AC timing
P122. Modify OTP command tabe, change to C7h
P180.Remove SLP bit from RB1h power control command.
P209. Add OTP programming example.
Himax Confidential
-P.225October, 2007

Datasheet of HX8340

Transcription

Similar documents

HX8357-D00/D01

ILI9327 - Crystalfontz

datasheet search site | www.alldatasheet.com

ILI9163 - Rockbox

TM 9-2320-209-20-2-2 - Roscommon Equipment Center

ILI9328 - Adafruit

Renesas R61523_101_091225

使用说明文件

lcd module specification

Discovery kit with STM32F429ZI MCU