AN 696: Using the JESD204B MegaCore Function in Arria V Devices

Transcription

2013-12-02
AN-696
AN 696: Using the JESD204B MegaCore Function in Arria
V Devices
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The JESD204B standard provides a serial data link interface between converters and FPGAs. The JESD204B
®
MegaCore function intellectual property (IP) for Altera FPGAs allows you to transmit and receive data on
the FPGA fabric interface by utilizing the Avalon-Streaming (Avalon-ST) source and sink interfaces, with
unidirectional flow of data. The JESD204B MegaCore function has been hardware-tested with a number of
selected JESD204B-compliant ADC (analog-to-digital converter) device.
This reference design highlights the performance and interoperability of the JESD204B MegaCore function.
®
The design uses an Arria V GT FPGA Development Kit as well as the Analog Devices Inc. (ADI) AD9250
converter daughter card (evaluation module) connected to the development board.
Related Information
• JESD204B MegaCore Function User Guide
• Arria V GT FPGA Development Kit User Guide
• Arria V GT FPGA Development Board Reference Manual
• JESD204B MegaCore Function Hardware Checkout Report
• ADI AD9250 Datasheet
JESD204B MegaCore Function Reference Design
The reference design contains a pregenerated JESD204B design example and peripherals like the SYSREF
generator.
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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Figure 1: System Diagram
The system-level diagram shows how the different modules connect in this reference design.
In this setup where LMF = 222, the data rate of the both transceiver lanes is 4.915 Gbps. The AD9517 clock
generator provides 122.88 MHz clock to the FPGA and 245.76 MHz sampling clock to both AD9250 devices.
The transceiver CDR PLL input reference clock (pll_ref_clk) uses the FPGA clock to generate the frame
clock and link clock.
jesd204b_ed_top.v
Arria V FPGA #2
Oscillator
100 MHz
jesd204b_ed.v
(Example Design)
mgmt_clk
ISSP
LED
x8
FMC AD9250-FMC-250EBZ
global_reset
rx_seriallpbken
Qsys System
JTAG to Avalon
Master Bridge
Avalon-MM
Slave Translator
sclk, ss_n[0],
miso, mosi
4-Wire
device_clk
(122.88 MHz)
link_clk
(122.88 MHz)
SYSREF sysref_out
Generator
Avalon-MM
Interface
Signals
SPI
Slave
CPLD
ADC
3- or 4-Wire
SPI
AD9517
Clock
Generator
Single-Ended
to Differential
Distribution
AD9250
ADC#1
CLK and
SYNC
3-Wire
SPI
SPI
Slave
rx_dev_sync_n
JESD204B IP
(Duplex)
L = 2, M = 2, F = 2
ADC
AD9250
ADC#2
L0
rx_serial_data[0]
(4.915 Gbps)
rx_serial_data[1]
(4.915 Gbps)
ADC
L1
ADC#2 clk
(245.76 MHz)
sysref
sync_n
CLK and
SYNC
ADC
The reference design consists of the following modules:
• JESD204B MegaCore function design example
•
•
•
•
•
•
•
Duplex JESD204B MegaCore function
TX & RX transport layer
core PLL
transceiver reconfiguration controller
transceiver reset controllers
control unit
SPI master
• SYSREF generator
• In-System Sources and Probes (ISSP)
• Qsys System
The design example also contains a parallel pseudorandom-binary-sequence (PRBS) data generator and
checker. The data generator generates a PRBS9 data pattern and the data checker verifies the PRBS9 data
received. The checker flags an error when it finds a mismatch of data sample. You can monitor the data
checker's error flag using the status LED on the development board or the Signal Tap II Logic Analyzer tool.
The reference design implements the JESD204B MegaCore function with the following parameter configuration.
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Table 1: JESD204B MegaCore Function Parameter Settings
Parameter
Value
Description
Subclass
1
Subclass mode
L
2
Number of lanes per converter device
M
2
Number of converters per device
F
2
Number of octets per frame
S
1
Number of transmitted samples per converter per frame
N
14
Number of conversion bits per converter
N'
16
Number of transmitted bits per sample (JESD204 word size, which is in
nibble group)
K
32
Number of frames per multiframe
CS
0
Number of control bits per conversion sample
CF
0
Number of control words per frame clock period per link
HD
0
High Density user data format
SCR
On
Enable scramble
FRAMECLK_DIV
1
The divider ratio of the frame_clk
You need to configure both the AD9517 clock generator and AD9250 ADC module for normal operation.
Between the FPGA and CPLD (on the AD9250 module), a 4-wire SPI configures the clock generator and
ADC. The CPLD, which acts as an SPI slave, uses the first 8-bits of the 32-bits SPI transaction as the
preselection bits to configure the clock generator, converter 1 (ADC #1), or converter 2 (ADC #2). The
remaining 24-bits follow the SPI interface timing requirements as listed in the AD9517 and AD9250 datasheet.
Table 2: AD9517 clock generator and AD9250 ADC Configuration
Module
Description
Preselection Byte
AD9250
ADC #1
0x80
AD9250
ADC #2
0x81
AD9517
Clock generator
0x84
The FPGA, which acts as an SPI master, writes the SPI instruction and register data following the sequence
and content in ROM-1 port of the memory initialization file (MIF). Figure 2 shows a timing diagram for
the correlation between the bit settings in MIF and the write instruction.
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SYSREF Generator
Figure 2: Write Instruction to AD9517/AD9250 Registers Timing Diagram
N_CS
SCLK
SDIO
P7 P6 P5 P4 P3 P2 P1 P0 R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Binary
8- Bit Pre-Selection
16-Bit Instruction
8-Bit Register Data
10000001
0000000001101110
10000001
0x81
0x6E
0x81
Preselection Byte for ADC#2
204B Parameters SCR/L Register Address
Bit[7]: Scambling Enabled
Hexadecimal
Description
Bit[0]: 1 = 2 Lanes
Related Information
JESD204B MegaCore Function User Guide
More information on specific MegaCore function modules as well as the steps to generate the JESD204B
MegaCore function and design example.
SYSREF Generator
The SYSREF generator uses the link clock as a reference clock and generates SYSREF pulses with periodic
gaps for the JESD204B MegaCore function and the ADC module.
The generator generates the pulses with a frequency of (4 × link clock) / (F × K).
In-System Sources and Probes (ISSP)
The ISSP is instantiated to control the global reset and to enable serial loopback.
Table 3: ISSP Control Ports in the Reference Design
Bit
ISSP
Description
[0]
global_reset
Global reset. Assert high to reset and low to release the reset.
[1]
rx_seriallpbken
Enables the serial loopback of the transceiver channel. Assert
high to enable or low to disable the serial loopback feature.
Qsys System
The reference design uses a simple Qsys system that consists of two components: the JTAG to Avalon Master
Bridge and the Avalon-Memory Mapped (Avalon-MM) Slave Translator.
Follow the steps below to examine the Qsys system:
1.
2.
3.
4.
Launch the Quartus II software.
On the File menu, click Open.
Browse and select the jesd204b_avmm_interface.qsys file located in the project directory.
Click Open.
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File Directory and Content
5
The Qsys system consists of the following components:
• JTAG to Avalon Master Bridge—acts as the Avalon-MM master in the reference design, This component
is the main communication channel between the System Console tool and the Avalon-MM slave translator
in the design. The System Console tool accesses the RX registers of the JESD204B MegaCore function.
• Avalon-MM Slave Translator—exports all required Avalon signals to the top-level design. With the
Avalon signals exported, the Qsys system can interface with any Avalon-compliant component that
resides outside of the Qsys component library.
Figure 3: Component Map of the Qsys System
For this reference design, the JESD204B MegaCore function is an Avalon-compliant component. Therefore,
the Avalon-MM Slave Translator component must connect to the JTAG to Avalon Master Bridge component.
Table 4: Memory Map of the Qsys System
Memory map of the Qsys system for the Avalon-MM Slave Translator in this reference design.
Name
merlin_slave_translator_0
Component Name
Avalon-MM Slave
Translator
Base Address
0x000
Description
Exports Avalon-MM signals to
interface with the JESD204B
MegaCore function.
File Directory and Content
The reference design comes with a ZIP file that includes a Quartus II Archive File (.qar) that contains the
project's design files, source files, and ancillary files, as well as system libraries. Once you restore the archive
file using the Quartus II software, a destination folder is created to store all the reference design files.
Table 5: Reference Design Files
This list contains only certain folders and contents in the project directory which you may need to edit.
Folder Name
Content
altera_jesd204
JESD204B MegaCore function configured in duplex mode.
control unit
• MIF file for AD9250
• Control unit
• ROM:1-Port—single-port ROM
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Reference Design Initialization Sequence
Folder Name
Content
issp
Signal source and probe module.
jesd204b_avmm_interface
Qsys Avalon-MM component for interfacing between the JESD204B
MegaCore function and System Console.
output_files
• Quartus II-generated SRAM Object File (.sof)
• Quartus II software compilation report files
pattern
PRBS data generator and checker module.
spi
SPI master module.
transport_layer
Transport layer assembler (TX) and deassembler (RX) module.
xcvr_reset_control_module
Transceiver reset controller module.
Related Information
Internal Memory (RAM and ROM) User Guide
Reference Design Initialization Sequence
The following list describes the initialization sequence of the reference design:
1.
2.
3.
4.
5.
6.
Read the MIF content from the FPGA ROM.
Configure AD9517 clock generator.
Configure ADC #2.
Deassert the Avalon-MM reset after the transceiver is out of reset.
Deassert the link and frame reset.
Link layer state machine goes through code group synchronization (CGS), initial lane synchronization
(ILAS), and user data phase.
7. Upon successfully entering the user data phase, the PRBS checker is enabled.
Hardware and Software Requirements
The reference design requires the following hardware and software tools:
•
•
•
•
Arria V GT FPGA Development Kit with 19 V power adaptor
ADI AD9250 Evaluation Module (EVM) AD-FMCJESDADC1-EBZ
Mini-USB cable
®
Quartus II software
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Hardware Setup
7
Hardware Setup
You need to set up the development board before running the reference design.
Figure 4: Hardware Setup
• The AD9250 module derives power from the FMC connector on the development board.
• The AD9250 module supplies the device clock to FPGA 2.
• For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the
AD9250 module.
FPGA 1
FPGA 2
Status LED
Transceiver Lanes
Device Clock
SYSREF
rx_dev_sync_n
SPI
Power
Arria V GT FPGA Development Board
ADI AD9250 Module
To set up the board connections, perform the following steps:
1. Install the ADI AD9250 daughter card module to the FMC port (J9) on the development board as shown
in Figure 4.
2. Connect the mini-USB cable to the mini USB connector (J7) on development board.
3. Connect the power adapter shipped with the development board to the power supply jack (J6).
4. Turn on the power.
You are now ready to download the .sof file and program the FPGA device on the development board.
FPGA Pin Assignments
The table below lists the top level signals with its corresponding FPGA pin assignments on the Arria V GT
FPGA Development Kit.
Table 6: FPGA 2 Pin Assignments
Top Level Signal Name
FPGA 2 Pin Number
I/O Standard
Direction
device_clk
AB9
1.5-V PCML
Input
device_clk_n
AB8
1.5-V PCML
Input
clkintopb_p0
C34
LVDS
Input
clkintopb_p0_n
D34
LVDS
Input
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Status LED
Top Level Signal Name
FPGA 2 Pin Number
I/O Standard
Direction
rx_dev_sync_n
AD25
2.5-V
Output
sysref_out
AC24
2.5-V
Output
mosi
AD24
2.5-V
Output
sclk
AH27
2.5-V
Output
ss_n[0]
AG27
2.5-V
Output
rx_serial_data[0]
U1
1.5-V PCML
Input
rx_serial_data_n[0]
U2
1.5-V PCML
Input
rx_serial_data[1]
R1
1.5-V PCML
Input
rx_serial_data_n[1]
R2
1.5-V PCML
Input
Status LED
The table below lists the status LEDs on the Arria V GT FPGA Development Kit and its function.
Note: If you utilize the Signal Tap II Logic Analyzer tool to pole the status of these signals, use the
rxframe_clk signal as the sampling clock.
Table 7: Status LEDs
LED Board Reference
Signal Name
Description
D26
data_error [1:0]
Single AND-ed error status signal for the PRBS checkers from
both lane 0 & lane 1. The LED illuminates to indicate a data
error.
D27
jesd204_tx_int
Link layer TX interrupt signal. Applicable only when internal
serial loopback is enabled. The LED illuminates to indicate
a TX interrupt.
D28
jesd204_rx_int
Link layer RX interrupt signal. The LED illuminates to
indicate a RX interrupt.
D29
rx_dev_sync_n
SYNC~ signal to the transmitter. The LED illuminates to
indicate that the transmitter has received K28.5 characters.
D30
dev_lane_aligned
RX path lane alignment status signal for the device. The LED
illuminates to indicate that lane alignment is achieved.
D31
avs_rst_n
Link layer CSR Avalon-MM reset signal. The LED illuminates
to indicate that the Avalon-MM interface is out of reset.
D32
link_rst_n
Link layer reset signal. The LED illuminates to indicate that
the link layer is out of reset.
D33
frame_rst_n
Transport layer reset signal. The LED illuminates to indicate
that the transport layer is out of reset.
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Using the Reference Design
9
Using the Reference Design
This section describes a high-level flow of how to use the reference design files in the Quartus II software.
To use the reference design files, perform the these steps:
1.
2.
3.
4.
Extract the reference design's archive file from avgt_jesd204b_ad9250_ed.zip.
Launch the Quartus II software.
On the File menu, click Open.
Navigate to your project directory and select the avgt_jesd204b_ad9250_ed_<Quartus II version>.qar
file. Click Open.
5. In the Restore Archived Project window, set the archive file name and destination folder. Click OK.
6. To download the .sof file and program the FPGA device on the development board, perform the following
steps:
a. On the Tools menu, click Programmer.
b. Click Add File.
c. Navigate to <project directory>\<output_files>\jesd204b_ed_golden.sof and click Open.
d. Click Start to download the file into the FPGA device on the development board.
7. Use the System Console tool to reset the system and trigger an initialization for the JESD204B MegaCore
function link.
Optionally, if you want to edit the JESD204B MegaCore function parameters and recompile the reference
design, refer to the section on Editing and Recompiling the Reference Design.
Related Information
• Using the System Console Tool to Execute Commands on page 9
Using the System Console Tool to Execute Commands
With the Avalon to JTAG Master Bridge, the System Console tool can access the RX registers of the JESD204B
MegaCore function. The System Console tool issues commands to reset and initiate the JESD204B MegaCore
function link in the reference design.
This design example uses a Tcl script called main.tcl that consists of several different procedures with
different functionality.
Note: Program the Arria V GT device with the .sof file generated in the previous section before launching
the System Console. Having both the programmer and System Console open simultaneously can
cause programming errors.
To launch the System Console, perform the following steps:
1. Launch the Quartus II software.
2. On the Tools menu, select System Console and click System Console.
3. Ensure that the present working directory contains main.tcl
The following table lists the procedures in main.tcl. You can type in a procedure name and its value to
execute the commands.
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Table 8: Description of Procedures in main.tcl
Command Name
read_rxstatus3
Description
Read JESD204 RX status 3 register (read back data in hexadecimal value). This signal
is asserted to indicate:
• RX CDR PLL is locked to the RX data.
• RX CDR transits from LTR to LTD mode for each lane.
read_rxstatus4
is asserted to indicate the current state of RX DLL code group synchronization state
machine for each lane.
read_rxstatus5
is asserted to indicate the current state of RX DLL frame synchronization state machine
for each lane.
read_rxstatus7
is asserted to indicate the status of RX DLL user data phase for each lane.
read_ilas_octet0
Read ILAS octet 0 register (read back data in hexadecimal value). This signal links
the control configuration fields in octets for configuration checking.
read_ilas_octet1
read_ilas_octet2
read_ilas_octet3
read_rx_err0
Read JESD204 RX error status 0 register (read back data in hexadecimal value). This
signal indicates the error status in the MegaCore's RX path.
read_rx_err1
Read JESD204 RX error status 1 register (read back data in hexadecimal value). This
signal indicates the error status in the MegaCore's RX path.
reset
Global reset.
sloopback 1
Enable serial loopback.
sloopback 0
Disable serial loopback.
The following example shows the execution of the above commands in the Tcl Console.
source main.tcl
sloopback 0
>> Disable serial loopback
reset
>> Reset the whole reference design system after disabling serial
loopback
>> Reset Done!
read_rxstatus3
>> Performing a read on rxstatus3 register...
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>> The rxstatus3 is 0x00000003
>> Info: Closed JTAG Master Service
read_rxstatus4
>> The rxstatus4 is 0x0000000a
read_rxstatus5
>> The rxstatus5 is 0x0000000a
read_rxstatus7
>> The rxstatus7 is 0x00030003
read_ilas_octet0
>> Performing a read on ilas_octet0 register...
>> The ilas_octet0 is 0x810000b9
read_ilas_octet1
>> The ilas_octet1 is 0x0d011f01
read_ilas_octet2
>> The ilas_octet2 is 0x0000202f
read_ilas_octet3
>> The ilas_octet3 is 0x0000fa00
read_rx_err0
>> Performing a read on rx_err0 register...
>> The rx_err0 is 0x00000000
read_rx_err1
>> Performing a read on rx_err1 register...
>> The rx_err1 is 0x00000000
These commands allow the System Console to communicate directly with the JESD204B MegaCore function
via the Avalon to JTAG Bridge Master.
Related Information
Analyzing and Debugging Designs with the System Console
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JESD204B MegaCore Function Link initialization Sequences
JESD204B MegaCore Function Link initialization Sequences
Upon device power up, assert reset using Tcl command in the System Console tool to trigger an initialization
for the JESD204B MegaCore function link in the reference design.
The following list describes the link initialization sequence.
Table 9: Link initialization Sequences and Observation
Sequence
Description
Activity
1
The input of the link
layer or the output of the
PCS (jesd204_rx_pcs_
data[63:0]) receives 0xBC
or K28.5 (/K/) characters.
Check both the lane1_cs_
state and lane0_cs_
state register identifiers by
executing read_rxstatus4
command in the System
Console tool to read the
JESD204 RX status register.
0x02 is asserted at both lane1_cs_
state[3:2] for lane 1 and lane0_
cs_state[1:0] for lane 0, which
indicates that code group synchronization (CGS) phase is detected. The
receiver deasserts the synchronization
request signal upon receiving four
consecutive K28.5 characters. Then, the
rx_dev_sync_n signal will be
deasserted.
2
When 0x1C or K28.0 (/
R/) character is received,
the ILAS phase is
detected.
Check both the lane1_cs_
state and lane0_cs_
state register identifiers by
0x02 is asserted at both lane1_cs_
state[3:2] for lane 1 and lane0_
cs_state[1:0] for lane 0. The ILAS
consists of four multiframes. The 1st,
3rd, and 4th multiframes begin with /R/
character and end with 0x7C or K28.3
(/A/) character. On the 2nd multiframe,
the ADC transmits the JESD204B link
configuration information to the
receiver. The 2nd multiframe begins
with /R/ character, followed by 0x9C
or K28.4 (/Q/) character and ends with
/A/ character.
3
User data phase enters Check both the lane1_dll_
after four multiframes of user_data_phase and
ILAS.
lane0_dll_user_data_
phase register identifiers by
Both lane1_dll_user_data_
phase1 of lane 1 & lane0_dll_
user_data_phase0 of lane 0 are
asserted. In this phase, the ADC
transmits PRBS data to the FPGA.
4
All lanes are aligned,
The link layer begins
indicated by the assertion transmitting data to the
transport layer.
of the dev_lane_
aligned signal.
LED D29 illuminates to indicate that
lane alignment is achieved.
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Editing and Recompiling the Reference Design
Sequence
5
Description
Link initialization
successful. Monitor the
data integrity through
the PRBS checker.
Activity
13
Observation
The PRBS checker receives data • LED D33 is off to indicate no data
from the transport layer and
error.
checks the received data against • LED D31 and D32 are off to indicate
the internally generated PRBS
that no interrupt signal is asserted
polynomial data. The
because there is no error condition
polynomial length and feedback
or a synchronization request.
tap position must be the same
for both the ADC PRBS
generator and the FPGA PRBS
checker. The AD9250 module
is set to output PRBS-9 data,
with feedback tap of 5.
Editing and Recompiling the Reference Design
This section describes some editable parameters when interoperating with the AD9250 module. When you
make modification to the JESD204B MegaCore function in the Quartus II software, you must make
corresponding changes to the AD9250 configuration file.
The example below demonstrates the following parameter modification:
• Subclass 1 to 0
• K from 32 to 16
• Disable the scrambler
To edit the JESD204B MegaCore function parameters and recompile the reference design, perform the
following steps:
1. On the Tools menu, click MegaWizard Plug-In Manager.
2. Select Edit an existing custom megafunction variation, then click Next.
3. Select the existing megafunction variation file (.v/.vhd/.vhdl) for the altera_jesd204 component, then
click Next
4. Edit the MegaCore parameters, then click Finish to close the parameter editor and generate the MegaCore.
5. Open the jesd204b_ed_top.v file and change the localparam K value from 32 to 16.
6. Use the text editor to change the following bit settings in the AD9250 module configuration file located
in the /control_unit/ad9250_222.mif directory:
• At content line 22,
change register 0x6E bit[7] from 1 to 0 to disable scrambling:
10000001000000000110111000000001;
change register 0x70 bit[4] from 1 to 0 to set K = 16 (0x0F + 1):
10000001000000000111000000001111;
change register 0x73 bit[5] from 1 to 0 for subclass 0:
10000001000000000111001100001111;
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Document Revision History
change register 0x3A bit [2:0] from “111” to “000” to turn off
SYSREF detection:
10000001000000000011101000000000;
7. Optionally, if you want to rename the MIF, change the pointer to the MIF located in
control_unit/control_unit.v.
rom_1port #(
.INIT_FILE ("./control_unit/<renamed MIF file>.mif"),
) u_rom0 (
.clock
(clk),
.clken
(rom_clken),
.address (rom_addr_ptr),
.q
(rom0_data_out)
);
8. On the Processing menu, click Start Compilation.
Document Revision History
Table 10: Document Revision History
Date
December 2013
Version
2013.12.02
Changes
Initial release.
How to Contact Altera
Table 11: How to Contact Altera
To locate the most up-to-date information about Altera products, refer to this table. You can also contact your local
Altera sales office or sales representative.
Contact
Technical support
Contact Method
Address
Website
www.altera.com/support
Website
www.altera.com/training
Email
[email protected]
Product literature
Website
www.altera.com/literature
Nontechnical support: general
Email
[email protected]
Nontechnical support: software
licensing
Email
[email protected]
Technical training
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AN 696: Using the JESD204B MegaCore Function in Arria V Devices

Transcription

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